Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: providing a substrate, including a first region for forming a first device and a second region for forming a second device, the first device having a higher working voltage than the second device, the substrate having a high-k gate dielectric layer, a metal barrier layer and a polysilicon gate sequentially stacked from bottom to top and extending along a first direction, and source / drain doped regions formed in the substrate on both sides of the polysilicon gate; forming an interlayer dielectric layer on the substrate on the side of the polysilicon gate; forming a first trench in the polysilicon gate of the first region, including a vertical trench extending along the first direction and a horizontal trench connected to the end of the vertical trench, the horizontal trench extending along a second direction; removing the polysilicon gate of the second region to form a gate opening in the interlayer dielectric layer; and forming a metal gate in the first trench and the gate opening. The application reduces the gate resistance of the first device, thereby improving the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the existing semiconductor device, different working voltage devices are usually formed on a substrate, such as a low voltage (LV) device, a high voltage (HV) device and a medium voltage (MV) device.

[0003] With the development of semiconductor manufacturing technology, the critical dimension of the semiconductor device is continuously reduced, which leads to more and more serious gate depletion effect. In order to better overcome the problem of gate depletion effect, the high-k last metal gate last process and the replacement gate process have become the commonly used processes.

[0004] Among them, compared with the low voltage device, the working voltage of the high voltage device and the medium voltage device is higher, and the size of the high voltage device and the medium voltage device is correspondingly larger, so the high voltage device and the medium voltage device still use the polysilicon gate, and the low voltage device uses the metal gate. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which improves the performance of the semiconductor structure.

[0006] To solve the above problem, embodiments of the present application provide a forming method of a semiconductor structure, comprising: providing a substrate, including a first region for forming a first device and a second region for forming a second device, the working voltage of the first device is greater than the working voltage of the second device, the substrate of the first region and the second region is formed with a high-k gate dielectric layer, a metal barrier layer and a polysilicon gate which are stacked in turn from bottom to top and extend along a first direction, and a source / drain doped region is formed in the substrate on both sides of the polysilicon gate; forming an interlayer dielectric layer on the substrate of the side of the polysilicon gate, the interlayer dielectric layer covers the sidewall of the polysilicon gate; forming a first trench in the polysilicon gate of the first region, the first trench includes a vertical trench extending along the first direction, and a horizontal trench communicating with the end of the vertical trench, the horizontal trench extends along a second direction, the second direction is perpendicular to the first direction; removing the polysilicon gate of the second region to form a gate opening in the interlayer dielectric layer; forming a metal gate in the first trench and the gate opening.

[0007] Correspondingly, the embodiment of the present application also provides a semiconductor structure, comprising: a substrate, comprising a first region for forming a first device and a second region for forming a second device, wherein the working voltage of the first device is greater than the working voltage of the second device; a high-k gate dielectric layer on the substrate of the first region and the second region, wherein the high-k gate dielectric layer extends along a first direction; a metal barrier layer on the high-k gate dielectric layer; a polysilicon gate on the metal barrier layer of the first region; a metal gate on the metal barrier layer of the second region and in the polysilicon gate, wherein in the first region, the metal gate comprises a vertical metal gate extending along the first direction and a horizontal metal gate connected to the end of the vertical metal gate, wherein the horizontal metal gate extends along a second direction, and the second direction is perpendicular to the first direction; and source-drain doped regions in the substrate on both sides of the polysilicon gate and on both sides of the metal gate of the second region.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] In the forming method provided by the embodiment of the present application, the substrate comprises a first region for forming a first device and a second region for forming a second device, the working voltage of the first device is greater than the working voltage of the second device, and a first trench is formed in the polysilicon gate of the first region, wherein the first trench comprises a vertical trench extending along a first direction and a horizontal trench connected to the end of the vertical trench, and the horizontal trench extends along a second direction, and the second direction is perpendicular to the first direction. Therefore, after the metal gate is formed in the first trench, the metal gate of the first region is not only formed in the horizontal trench, but also formed in the vertical trench. Compared with the scheme that only a metal gate extending along the channel length direction (i.e. the second direction) is formed in the polysilicon gate of the first region, the embodiment of the present application further forms a metal gate extending along the channel width direction (i.e. the first direction) in the polysilicon gate of the first region, thereby increasing the cross-sectional area of the metal gate of the first region, and further reducing the gate resistance of the first device, and accordingly, the performance of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a top view of a semiconductor structure;

[0011] Figures 2 to 14 is a structure diagram corresponding to each step in the forming method of the semiconductor structure of the embodiment of the present application. DETAILED DESCRIPTION

[0012] As can be seen from the background art, currently, high-voltage devices and medium-voltage devices adopt polysilicon gates, while low-voltage devices adopt metal gates. However, the performance of the semiconductor structure is poor.

[0013] The reasons why the performance of the semiconductor structure needs to be improved will be analyzed in combination with a semiconductor structure. Figure 1 Fig. 1 shows a top view of a semiconductor structure.

[0014] Taking the semiconductor structure as a high-voltage device for example, the semiconductor structure comprises: a substrate (not shown) comprising an active area (AA) 10; a high-k gate dielectric layer (not shown in the figure) located on the substrate of the active area 10, the high-k gate dielectric layer also extending to cover part of the isolation structure (STI) 50, the extension direction of the high-k gate dielectric layer being a first direction (as shown in the y direction in Fig. 1), and the direction perpendicular to the first direction being a second direction (as shown in the x direction in Fig. 1); a metal barrier layer (not shown in the figure) located on the high-k gate dielectric layer; a polysilicon gate 20 located on the metal barrier layer; source / drain doped regions 30 located in the substrate on both sides of the polysilicon gate 20; and a metal gate 40 penetrating the polysilicon gate 20 above the isolation structure 50, the metal gate 40 extending along the second direction. Figure 1 Figure 1 The high-k gate dielectric layer, the metal barrier layer (for example, a titanium nitride layer), and the polysilicon gate 20 are stacked in order from bottom to top.

[0015] The medium-voltage device has a structure similar to that of the high-voltage device. In order to realize the electrical connection between the gate of the high-voltage device and the medium-voltage device and the external circuit, when the metal gate of the low-voltage device is formed, the metal gate is also formed in the polysilicon gate of the high-voltage device and the medium-voltage device, so that the high-voltage device and the medium-voltage device realize electrical connection with the gate plug through the metal gate, and then the gate plug realizes electrical connection with the metal barrier layer. The metal barrier layer has conductivity, and when the high-voltage device or the medium-voltage device is working, the opening or closing of the channel is controlled through the metal barrier layer.

[0016] However, since the above scheme controls the opening or closing of the channel through the metal barrier layer, compared with the traditional metal gate or the traditional polysilicon gate, the above scheme will cause the gate resistance of the high-voltage device or the medium-voltage device to be high.

[0017] Moreover, the substrate comprises the active area 10, and the remaining area on the substrate serves as an isolation area. In the high-voltage device and the medium-voltage device, the metal gate is usually located in the isolation area and extends along the second direction, which is the same as the channel length direction. However, as the critical dimension of the semiconductor device is continuously reduced, the channel length is also becoming smaller and smaller, thereby causing the gate resistance to further increase.

[0018] Moreover, the substrate comprises the active area 10, and the remaining area on the substrate serves as an isolation area. In the high-voltage device and the medium-voltage device, the metal gate is usually located in the isolation area and extends along the second direction, which is the same as the channel length direction. However, as the critical dimension of the semiconductor device is continuously reduced, the channel length is also becoming smaller and smaller, thereby causing the gate resistance to further increase. ​

[0019] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, comprising the following steps: providing a substrate, including a first region for forming a first device and a second region for forming a second device, the working voltage of the first device is greater than the working voltage of the second device, and the substrate of the first region and the second region is provided with a high-k gate dielectric layer, a metal barrier layer and a polysilicon gate which are sequentially stacked from bottom to top and extend along a first direction; source-drain doped regions are formed in the substrate on both sides of the polysilicon gate; an interlayer dielectric layer is formed on the substrate on the side of the polysilicon gate, and the interlayer dielectric layer covers the sidewall of the polysilicon gate; a first trench is formed in the polysilicon gate of the first region, the first trench comprises a vertical trench extending along the first direction and a horizontal trench connected with the end of the vertical trench, and the horizontal trench extends along a second direction which is perpendicular to the first direction; the polysilicon gate of the second region is removed to form a gate opening in the interlayer dielectric layer; and a metal gate is formed in the first trench and the gate opening.

[0020] In the forming method provided by the embodiment of the present application, the metal gate of the first region is not only formed in the horizontal trench, but also formed in the vertical trench, compared with the scheme that the metal gate is only formed in the polysilicon gate of the first region and extends along the length direction of the channel (i.e. the second direction), the metal gate extending along the width direction of the channel (i.e. the first direction) is further formed in the polysilicon gate of the first region, so that the sectional area of the metal gate of the first region is increased, and then the gate resistance of the first device is reduced, and accordingly the performance of the semiconductor structure is improved.

[0021] In order to make the above object, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0022] Figures 2 to 14 is a structure diagram corresponding to each step in the forming method of the semiconductor structure of the embodiment of the present application.

[0023] Combined with reference Figure 2 and Figure 3 , Figure 2 is a sectional view, Figure 3 is a partial top view of the high-voltage device region, the substrate 100 is provided, including a first region 100K for forming a first device and a second region 100L for forming a second device, the working voltage of the first device is greater than the working voltage of the second device, and the substrate 100 of the first region 100K and the second region 100L is provided with a high-k gate dielectric layer, a metal barrier layer and a polysilicon gate which are sequentially stacked from bottom to top and extend along a first direction (such as the horizontal direction in the figure, for example, the horizontal direction of the substrate 100 in the figure is the first direction, and the vertical direction of the substrate 100 in the figure is the second direction). Figure 3The high-k gate dielectric layer 230, the metal barrier layer 220 and the polysilicon gate 210 are sequentially stacked from bottom to top, and the source-drain doped regions 240 are formed in the substrate 100 on both sides of the polysilicon gate 210.

[0024] For ease of illustration, Figure 3 Only the polysilicon gate 210, the source-drain doped regions 240, the second isolation structure 102 and the contact region 250 in the high-voltage device region 100H are shown.

[0025] The top view of the medium-voltage device region 100M is similar to the top view of the high-voltage device region 100H, and the top view of the medium-voltage device region 100M is not shown in this embodiment.

[0026] The substrate 100 is used to provide a process platform for subsequent process procedures. In this embodiment, the substrate 100 is taken as an example for forming a planar field effect transistor, and the substrate 100 is a planar substrate. In other embodiments, the substrate is used to form a fin field effect transistor (FinFET), and accordingly, the substrate includes a substrate and a fin portion protruding from the substrate.

[0027] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the material of the substrate can be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0028] In this embodiment, the substrate is a P-type substrate (Psub), that is, the substrate is doped with P-type ions, and the P-type ions are B ions, Ga ions or In ions.

[0029] In this embodiment, the substrate 100 includes a first region 100K for forming a first device and a second region 100L for forming a second device, and the working voltage of the first device is greater than the working voltage of the second device.

[0030] As an example, the first region 100K includes a medium-voltage device region 100M for forming a medium-voltage device and a high-voltage device region 100H for forming a high-voltage device, and the second region 100L is a low-voltage device region for forming a low-voltage device. The working voltages of the low-voltage device, the medium-voltage device and the high-voltage device are sequentially increased.

[0031] For example, the working voltage of the low-voltage device is less than 3V, the working voltage of the medium-voltage device is 3V to 10V, and the working voltage of the high-voltage device is greater than 10V.

[0032] In the embodiment, the deep N-type well (DNW) region 120 is formed in the substrate 100 of the second region 100L (i.e. the low voltage device region) and the medium voltage device region 100M, and the high voltage well (HV Well) region 110 is formed in the substrate 100 of the high voltage device region 100H.

[0033] In the embodiment, the low voltage well (LV Well) region 130 is formed in the deep N-type well region 120 of the second region 100L, and the medium voltage well (MV Well) region 140 is formed in the deep N-type well region 120 of the medium voltage device region 100M. The deep N-type well region 120 is used to isolate the low voltage well (LV Well) region 130 and the medium voltage well (MV Well) region 140 from the P-type substrate, so as to reduce the substrate coupling noise.

[0034] The type of the doping ions in the well region is opposite to the channel conduction type of the corresponding MOS device. For example, when the high voltage device is an NMOS device, the doping ions in the high voltage well region 110 are P-type ions, and when the high voltage device is a PMOS device, the doping ions in the high voltage well region 110 are N-type ions.

[0035] In the embodiment, the first isolation structure 101 is also formed in the substrate 100.

[0036] Specifically, the first isolation structure 101 is formed in the substrate 100 at the boundary between the second region 100L and the medium voltage device region 100M, and at the boundary between the medium voltage device region 100M and the high voltage device region 100H.

[0037] The first isolation structure 101 is used to isolate the adjacent devices. In the embodiment, the first isolation structure 101 is a shallow trench isolation (STI), so that the first isolation structure 101 has a good isolation effect. In the embodiment, the exposed substrate 100 of the first isolation structure 101 is used as an active region, and the region where the first isolation structure 101 is located is an isolation region. For example, as shown in FIG. 1B, the dashed box in FIG. 1B is used to represent the position of the active region. Figure 3 Figure 3

[0038] In the embodiment, the material of the isolation structure 101 is an insulating material, and the insulating material includes silicon oxide.

[0039] It should be noted that, in the process of forming the first isolation structure 101, the second isolation structure 102 is also formed in part of the substrate 100 of the high voltage device region 100H, so as to divide the substrate 100 of the high voltage device region 100H into multiple active regions. ​​

[0040] Specifically, shallow trenches are formed in the substrate 100 first, and then the shallow trenches are filled to form the first isolation structure 101 and the second isolation structure 102 in the shallow trenches.

[0041] The substrate 100 of the first region 100K and the second region 100L is formed with a high-k gate dielectric layer 230, a metal barrier layer 220 and a polysilicon gate 210 stacked in sequence from bottom to top and extending along the first direction.

[0042] In this embodiment, the polysilicon gate 210 covers the substrate 100 of the active region. The polysilicon gate 210 of the second region 100L is used to occupy a space position for the subsequent formation of a metal gate. The first region 100K is used to form a first device, which has a relatively high working voltage and a relatively large size. Therefore, the polysilicon gate 210 of the first region 100K is retained subsequently, so as to avoid the problem of top surface sagging of the metal gate caused by the relatively large size.

[0043] Specifically, in the high-voltage device region 100H, the polysilicon gate 210 and the metal barrier layer 220 also extend to cover part of the second isolation structure 102, that is, the polysilicon gate 210 and the metal barrier layer 220 also extend to cover part of the isolation region, so as to facilitate the subsequent formation of a metal gate above the isolation structure 102 in the high-voltage device region 100H.

[0044] Similarly, in the medium-voltage device region 100M, the end of the polysilicon gate 210 also extends into part of the isolation region.

[0045] In this embodiment, the material of the polysilicon gate 210 is polysilicon.

[0046] In this embodiment, the metal gate is formed by using a high-K first process in a gate last process. Therefore, the high-k gate dielectric layer 230 and the metal barrier layer 220 on the high-k gate dielectric layer 230 are formed on the substrate 100 first.

[0047] The high-k gate dielectric layer 230 is used to constitute a gate dielectric layer of a transistor, that is, the gate dielectric layer of the transistor includes the high-k gate dielectric layer 230.

[0048] The material of the high-k gate dielectric layer 230 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 230 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 230 is HfO2.

[0049] The metal barrier layer 220 is used to isolate the high-k gate dielectric layer 230 and the polysilicon gate 210, to protect the high-k gate dielectric layer 230, and to act as an etching stop layer during the subsequent etching of the polysilicon gate 210, thereby reducing the probability of damage to the high-k gate dielectric layer 230. Furthermore, the metal barrier layer 220 is also used to block the diffusion of easily diffusing ions (e.g., aluminum ions) in the metal gate into the high-k gate dielectric layer 230 after the subsequent formation of the metal gate. In addition, the metal barrier layer 220 is used to control the on or off of the device channel, and thus the metal barrier layer 220 is a conductive material.

[0050] Specifically, the material of the metal barrier layer 220 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 220 is titanium nitride. The metal barrier layer 220 also has a certain effect on the gate work function of the transistor.

[0051] In actual process, by setting the thickness of the metal barrier layer 220, the metal barrier layer 220 can act as an etching stop layer during the subsequent etching of the polysilicon gate 210, and the metal barrier layer 220 has a good blocking effect on the easily diffusing ions in the metal gate.

[0052] The source / drain doped region 240 is used as a source region or a drain region of the formed transistor. When an NMOS transistor is formed, the doped ions in the source / drain doped region 240 are N-type ions, and the N-type ions are P ions, As ions or Sb ions. When a PMOS transistor is formed, the doped ions in the source / drain doped region 240 are P-type ions, and the P-type ions are B ions, Ga ions or In ions.

[0053] In this embodiment, in the high-voltage device region 100H, the polysilicon gate 210 and the source / drain doped region 240 are isolated by the second isolation structure 102.

[0054] In this embodiment, in the high-voltage device region 100H, a pickup 250 is also formed in the substrate 100 on both sides of the polysilicon gate 210, the pickup 250 surrounds the second isolation structure 102, the source / drain doped region 240 and the polysilicon gate 210, and the pickup 250 and the source / drain doped region 240 are isolated by the second isolation structure 102.

[0055] In this embodiment, a first hard mask layer 215 is formed on the top of the polysilicon gate 210.

[0056] The first hard mask layer 215 is used as an etching mask when the polysilicon gate 210 is formed. As an example, the material of the first hard mask layer 215 is silicon nitride.

[0057] In the embodiment, the sidewall of the polysilicon gate 210 is formed with a side wall 260. The side wall 260 is used to protect the sidewall of the polysilicon gate 210 and to define the forming position of the source-drain doped region 240.

[0058] The side wall 260 can be a single-layer structure or a stacked structure, and the material of the side wall 260 can include one or more of silicon oxide, silicon nitride, silicon oxynitride, boron nitride, aluminum oxide and aluminum nitride. In the embodiment, the side wall 260 is a single-layer structure, and the material of the side wall 260 is silicon nitride.

[0059] Specifically, the side wall 260 also covers the sidewall of the high-k gate dielectric layer 230, the metal barrier layer 220 and the first hard mask layer 215.

[0060] Continuing to refer to Figure 2 , a salicide block (SAB) layer 300 is formed to conformally cover the substrate 100, the source-drain doped region 240, the polysilicon gate 210 and the first hard mask layer 215. In the first region 100K, the salicide block layer 300 and the first hard mask layer 215 located above the top of the polysilicon gate 210 serve as a protection layer 400.

[0061] Subsequently, the salicide block layer 300 is patterned by photolithography and etching techniques to expose the area for forming a salicide layer.

[0062] Moreover, the protection layer 400 covers the top of the polysilicon gate 210 in the first region 100K, and the protection layer 400 is used to protect the top of the polysilicon gate 210 in the first region 100K in the subsequent process of forming an interlayer dielectric layer, thereby reducing the probability of top surface sagging of the polysilicon gate 210 in the first region 100K.

[0063] The material of the salicide block layer 300 includes one or more of silicon nitride, silicon oxide and silicon oxynitride. In the embodiment, the material of the salicide block layer 300 is silicon nitride. In the embodiment, the salicide block layer 300 is formed by using an atomic layer deposition process or a chemical vapor deposition process.

[0064] It should be noted that the thickness of the salicide block layer 300 should not be too small or too large. If the thickness of the salicide block layer 300 is too small, the thickness of the protection layer 400 will be correspondingly small, thereby reducing the protection of the protection layer 400 to the polysilicon gate 210 in the first region 100K; if the thickness of the salicide block layer 300 is too large, the difficulty of subsequent etching of the salicide block layer 300 will be correspondingly increased. Therefore, in the embodiment, the thickness of the salicide block layer 300 is to For example, the thickness of the silicide blocking layer 300 is or

[0065] Referring to Figure 4 In the first region 100K, a pattern layer 310 is formed on the protective layer 400.

[0066] The pattern layer 310 is used as a mask for etching the silicide blocking layer 300, so that the remaining silicide blocking layer 300 is exposed to form a region of the silicide layer.

[0067] In this embodiment, an interlayer dielectric layer is formed on the substrate 100 at the side of the polysilicon gate 210, the interlayer dielectric layer covers the sidewall of the polysilicon gate 210 and exposes the top of the polysilicon gate 210 in the second region 100L, so as to prepare for removing the polysilicon gate 210 in the second region 100L. The process of forming the interlayer dielectric layer includes a planarization process (for example, a chemical mechanical polishing process) after a deposition process, in order to expose the top of the polysilicon gate 210 in the second region 100L, over polishing is usually performed to remove the first hard mask layer 215 on the top of the polysilicon gate 210.

[0068] However, since the working voltage of the first device is greater than that of the second device, the thickness of the gate dielectric layer in the first region 100K is greater than that in the second region 100L, so that the top surface of the polysilicon gate 210 in the first region 100K is usually higher than that in the second region 100L. Therefore, in the process of forming the interlayer dielectric layer, the polysilicon gate 210 in the first region 100K is exposed in advance, which easily leads to the problem of over polishing of the polysilicon gate 210 in the first region 100K, and further leads to the problem of the top surface flatness of the polysilicon gate 210 in the first region 100K, for example, the problem of top surface dishing. Moreover, since the working voltage of the first device is greater than that of the second device, the width dimension of the polysilicon gate 210 in the first region 100K is correspondingly larger, which worsens the problem of top surface dishing of the polysilicon gate 210 in the first region 100K.

[0069] To this end, in this embodiment, by forming the pattern layer 310 on the protective layer 400, the silicide barrier layer 300 above the polysilicon gate 210 in the first region 100K is reserved after etching the silicide barrier layer 300, that is, the protective layer 400 can be reserved, and the probability of damage to the protective layer 400 is reduced, so that the protective layer 400 can protect the top of the polysilicon gate 210 in the first region 100K in the subsequent process of forming the interlayer dielectric layer, thereby improving the top surface flatness of the polysilicon gate 210 in the first region 100K.

[0070] As an example, the pattern layer 310 is photoresist, and the pattern layer 310 is formed by photolithography such as exposure, development, etc.

[0071] Reference Figure 5 The silicide barrier layer 300 on the substrate 100, the source-drain doped region 240, and the first hard mask layer 215 is etched and removed using the pattern layer 310 as a mask.

[0072] After etching the silicide barrier layer 300, the remaining silicide barrier layer 300 exposes the source-drain doped region 240, thereby preparing for the subsequent formation of a silicide layer on the surface of the source-drain doped region 240.

[0073] In this embodiment, after etching the silicide barrier layer 300, the first hard mask layer 215 remains on the top of the polysilicon gate 210 in the second region 100L. In other embodiments, the first hard mask layer on the top of the polysilicon gate in the second region can also be removed according to actual conditions.

[0074] In this embodiment, after etching the silicide barrier layer 300, the forming method further includes removing the pattern layer 310. As an example, the material of the pattern layer 310 is photoresist, and therefore, a gray etching process is used to remove the pattern layer 310.

[0075] In this embodiment, after etching the silicide barrier layer 300, the remaining silicide barrier layer 300 on the sidewall of the polysilicon gate 210 and the sidewall 260 serve as a sidewall structure 410.

[0076] Therefore, in combination with reference Figure 6 After removing the pattern layer 310, the forming method further includes using an anisotropic etching process to etch the sidewall structure 410 to perform a thinning process on the sidewall of the sidewall structure 410.

[0077] A contact etch stop layer (CESL) is further formed on the sidewall of the sidewall structure 410 and the substrate 100, which is also used as a stress layer in Stress Memorization Technology (SMT) to induce corresponding stress in the channel. Therefore, the thickness of the sidewall structure 410 is reduced by thinning the sidewall of the sidewall structure 410, so that the CESL is closer to the channel, and the effect of the stress generated by the CESL on the channel is enhanced.

[0078] The thickness of the sidewall structure 410 refers to the dimension of the sidewall structure 410 along a direction parallel to the substrate 100 and perpendicular to the sidewall of the polysilicon gate 210.

[0079] Specifically, the sidewall structure 410 is etched along a direction perpendicular to the top surface of the polysilicon gate 210 by using an anisotropic etching process, so as to thin the sidewall of the sidewall structure 410.

[0080] Correspondingly, the protection layer 400 is etched during the thinning process, so as to easily affect the thickness of the protection layer 400.

[0081] Therefore, after the thinning process of the sidewall structure 410, the thickness of the protection layer 400 should not be too small or too large. If the thickness of the protection layer 400 is too small, the protection of the polysilicon gate 210 in the first region 100K by the protection layer 400 is reduced. If the thickness of the protection layer 400 is too large, the etching amount of the thinning process is correspondingly small, so that the distance between the CESL and the channel is large. In the embodiment, the thickness of the protection layer 400 is to For example, after the thinning process of the sidewall structure 410, the thickness of the protection layer 400 is

[0082] As an example, during the thinning process, part of the silicide barrier layer 300 is removed.

[0083] In the embodiment, during the thinning process, the remaining first hard mask layer 215 on the top of the polysilicon gate 210 in the second region 100L is removed.

[0084] After the interlayer dielectric layer is formed, the top of the polysilicon gate 210 in the second region 100L is exposed, and the hardness of the first hard mask layer 215 is generally greater than the hardness of the interlayer dielectric layer. Therefore, by removing the first hard mask layer 215 in the second region 100L first, the process difficulty of forming the interlayer dielectric layer later is reduced.

[0085] Reference Figure 7 An interlayer dielectric (ILD) layer 340 is formed on the substrate of the side of the polysilicon gate 210, and the interlayer dielectric layer 340 covers the sidewall of the polysilicon gate 210.

[0086] The interlayer dielectric layer 340 is used to isolate adjacent devices.

[0087] The material of the interlayer dielectric layer 340 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 340 is silicon oxide.

[0088] Specifically, the interlayer dielectric layer 340 is formed by a deposition and planarization process (for example, a chemical mechanical polishing process), so that the interlayer dielectric layer 340 exposes the top of the polysilicon gate 210 in the second region 100L and the top of the protective layer 400.

[0089] By exposing the top of the polysilicon gate 210 in the second region 100L by the interlayer dielectric layer 340, the polysilicon gate 210 is prepared for subsequent removal. By exposing the top of the protective layer 400 by the interlayer dielectric layer 340, the protective layer 400 is prepared for subsequent etching.

[0090] Moreover, in the first region 100K, the top of the polysilicon gate 210 is formed with the protective layer 400, so that the protective layer 400 can protect the top of the polysilicon gate 210 in the first region 100K during the formation of the interlayer dielectric layer 340. After the interlayer dielectric layer 340 is formed, the top surface of the polysilicon gate 210 still has high flatness.

[0091] In which the subsequent process further includes forming a first trench in the polysilicon gate 210 in the first region 100K. By having high flatness of the top surface of the polysilicon gate 210, the appearance quality of the first trench is improved.

[0092] It should be noted that the planarization process is likely to cause damage to the protective layer 400, so that the thickness of the protective layer 400 is reduced after the interlayer dielectric layer 340 is formed.

[0093] However, after the interlayer dielectric layer 340 is formed, the thickness of the protective layer 400 should not be too small or too large. If the thickness of the protective layer 400 is too small, the process time of the planarization process is relatively long, and the polysilicon gate 210 and the sidewall structure 410 of the second region 100L are easily damaged, which results in that the height of the polysilicon gate 210 and the sidewall structure 410 of the second region 100L is too small, and further results in that the height of the metal gate of the second region 100L is too small, which will adversely affect the performance of the semiconductor structure. If the thickness of the protective layer 400 is too large, it is difficult to ensure that the interlayer dielectric layer 340 can expose the top of the polysilicon gate 210 of the second region 100L, and it is also easy to increase the process difficulty when the protective layer 400 is etched. Therefore, in the embodiment, after the interlayer dielectric layer 340 is formed, the thickness of the protective layer 400 is to For example, the thickness of the protective layer 400 is or

[0094] In the embodiment, after the interlayer dielectric layer 340 is formed, the top of the interlayer dielectric layer 340 is lower than the top of the protective layer 400.

[0095] It should be noted that before the interlayer dielectric layer 340 is formed, the forming method further includes: forming a contact hole etching stop layer 330, and the contact hole etching stop layer 330 conformally covers the silicide barrier layer 300, the sidewall 260, the polysilicon gate 210 and the substrate 100.

[0096] In the planarization process of forming the interlayer dielectric layer 340, the contact hole etching stop layer 330 higher than the top of the polysilicon gate 210 and the top of the protective layer 400 is removed, and correspondingly, the contact hole etching stop layer 330 covers the sidewall of the silicide barrier layer 300 and the substrate 100.

[0097] The contact hole etching stop layer 330 is used to induce stress in the channel to achieve SMT. Moreover, in the process of subsequently forming a source / drain plug penetrating through the interlayer dielectric layer 340 and contacting the source / drain doped region 240, the contact hole etching stop layer 330 is used to define the etching stop position in the process of etching through the interlayer dielectric layer 340, so as to avoid over-etching of the source / drain doped region 240.

[0098] As an example, the material of the contact hole etching stop layer 330 is silicon nitride.

[0099] For reference Figure 8 and Figure 9 , Figure 8 is a sectional view, Figure 9 is a partial top view of the high-voltage device region, and the forming method further includes: forming a protective layer 400 on the first region 100K (such as the first region 100K shown in FIG. 1) and the second region 100L (such as the second region 100L shown in FIG. 1), and the protective layer 400 covers the sidewall 260, the polysilicon gate 210 and the substrate 100 of the first region 100K and the second region 100L.Figure 7 The second trench 360 is formed in the high-voltage device region 100H, and includes vertical mask trenches 360W extending along the first direction (as indicated by the Y direction in FIG. 6) and lateral mask trenches 360L communicating with the ends of the vertical mask trenches 360W, the lateral mask trenches 360L extending along the second direction (as indicated by the X direction in FIG. 6). Figure 9 The second trench 360 is formed in the high-voltage device region 100H, and includes vertical mask trenches 360W extending along the first direction (as indicated by the Y direction in FIG. 6) and lateral mask trenches 360L communicating with the ends of the vertical mask trenches 360W, the lateral mask trenches 360L extending along the second direction (as indicated by the X direction in FIG. 6). Figure 9 The second trench 360 is formed in the high-voltage device region 100H, and includes vertical mask trenches 360W extending along the first direction (as indicated by the Y direction in FIG. 6) and lateral mask trenches 360L communicating with the ends of the vertical mask trenches 360W, the lateral mask trenches 360L extending along the second direction (as indicated by the X direction in FIG. 6).

[0100] For ease of illustration, Figure 9 Only the polysilicon gate 210, the pattern layer 350 and the second trench 360 in the high-voltage device region 100H are shown.

[0101] The second trench 360 is used as a mask for etching the polysilicon gate 210 in the first region 100K to form a first trench. The second trench 360 exposes the polysilicon gate 210, thereby preparing for subsequent etching of the polysilicon gate 210 in the first region 100K.

[0102] The first trench is subsequently formed in the polysilicon gate 210 exposed by the second trench 360, and includes vertical trenches extending along the first direction and lateral trenches communicating with the ends of the vertical trenches, the lateral trenches extending along the second direction. The lateral mask trenches 360L are used to define the positions of the lateral trenches, and the vertical mask trenches 360W are used to define the positions of the vertical trenches.

[0103] In this embodiment, the lateral mask trenches 360L communicate with the ends of the vertical mask trenches 360W, and the second trench 360 is T-shaped. In the direction parallel to the substrate 100 and perpendicular to the sidewall of the polysilicon gate 210, the width of the vertical trench is less than the width of the vertical mask trench 360W.

[0104] By first forming the vertical mask trench 360W with a larger width, the problem of sidewall sagging of the vertical trench caused by lateral etching can be significantly alleviated in the process of subsequently etching the polysilicon gate 210 to form the first trench. Accordingly, after the metal gate is subsequently formed in the first trench, the probability of forming a hole between the metal gate and the polysilicon gate 210 is relatively low.

[0105] It should be noted that, in the direction parallel to the substrate 100 and perpendicular to the sidewall of the polysilicon gate 210, the width difference between the vertical mask trench 360W and the subsequently formed vertical trench should not be too small. If the width difference is too small, after the first trench is subsequently formed, the probability of the sidewall of the vertical trench sagging is relatively large, and the sagging degree is relatively large. Therefore, in this embodiment, the width difference between the vertical mask trench 360W and the subsequently formed vertical trench is at least 100 nanometers.

[0106] In this embodiment, the width difference between the second trench 360 and the subsequently formed vertical trench is 100-300 nm, according to the width of the polysilicon gate 210.

[0107] Specifically, the second trench 360 is formed by using the first pattern layer 310 as a first pattern layer, including: forming a second pattern layer 350 on the interlayer dielectric layer 340, the second pattern layer 350 covering the top of the silicide barrier layer 300, and exposing the region of the protective layer 400 to be etched; etching the protective layer 400 using the second pattern layer 350 as a mask, to form the second trench 360 exposing the top of the polysilicon gate 210; and removing the second pattern layer 350 after forming the second trench 360.

[0108] In this embodiment, the anisotropic etching process is used to etch the protective layer 400 in the first region 100K to form the second trench 360.

[0109] The anisotropic etching process has the characteristic of anisotropic etching, i.e., the longitudinal etching rate of the etching process is greater than the lateral etching rate, thereby facilitating the improvement of the profile control of the second trench 360, and the dry etching process has higher controllability.

[0110] For specific description of the second pattern layer 350, refer to the corresponding description of the first pattern layer (i.e., the pattern layer 310) as described above, which is not repeated here.

[0111] In combination with reference to Figure 10 and Figure 11 , Figure 10 is a sectional view, Figure 11 is a partial top view of the high-voltage device region, a T-shaped first trench 212 is formed in the polysilicon gate 210 of the first region 100K, the first trench 212 includes a vertical trench 212W extending along the first direction (as indicated by the Y direction in Figure 11 , and a lateral trench 212L (as indicated by the arrow in Figure 11 ) connected to the end of the vertical trench 212W, the lateral trench 212L extends along the second direction (as indicated by the X direction in Figure 11 , which is perpendicular to the first direction. Figure 11

[0112] For ease of illustration, Figure 11 only the polysilicon gate 210, the source / drain doped region 240, the second isolation structure 102, the contact region 250, the first trench 212, and the metal barrier layer 220 in the high-voltage device region 100H are shown.

[0113] ​The first trench 212 is used to provide a spatial position for forming a metal gate in the first region 100K later.

[0114] Specifically, the lateral trench 212L is located at an end position of the polysilicon gate 210, that is, the lateral trench 212L is located at an isolation region (not labeled).

[0115] After the metal gate is formed in the first trench 212 later, the metal gate of the first region 100K is not only formed in the lateral trench 212L, but also formed in the vertical trench 212W. Compared with the scheme that only the metal gate extending along the channel length direction (i.e., the second direction) is formed in the polysilicon gate of the first region, the metal gate extending along the channel width direction (i.e., the first direction) is also formed in the polysilicon gate 210 of the first region 100K in the embodiment, thereby increasing the cross-sectional area of the metal gate of the first region 100K, and further reducing the gate resistance of the first device, which is beneficial to improve the performance of the semiconductor structure. Moreover, the length of the polysilicon gate 210 along the first direction is generally greater than the width along the second direction, so that the effect of increasing the cross-sectional area of the metal gate of the first region 100K is better.

[0116] In the embodiment, the polysilicon gate 210 is a long strip, and the polysilicon gate 210 has two end faces along the first direction. In order to significantly increase the cross-sectional area of the metal gate, in the first direction, the side wall of the vertical trench 212W away from the vertical trench 212W is flush with one end face of the polysilicon gate 210 before etching, and the end face of the vertical trench 212W is flush with the other end face of the polysilicon gate 210, that is, the first trench 212 penetrates through the entire polysilicon gate 210 along the first direction.

[0117] In the embodiment, an anisotropic etching process is used to etch the polysilicon gate 210 of the first region 100K to form the first trench 212.

[0118] The anisotropic etching process has the characteristic of anisotropic etching, that is, the longitudinal etching rate of the etching process is greater than the lateral etching rate, thereby being beneficial to improve the profile control of the first trench 212, and the controllability of the dry etching process is higher.

[0119] It should be noted that the width of the vertical trench 212W along the second direction should not be too small or too large. If the width of the vertical trench 212W is too small, it is easy to cause the depth-width ratio of the vertical trench 212W to be too large, thereby increasing the difficulty of forming the metal gate in the vertical trench 212W later; if the width of the vertical trench 212W is too large, the vertical mask trench 360W (such as the vertical mask trench 360W shown in FIG. 3) is not easy to form, and the etching process is not easy to control. Figure 9As shown in FIG. 6, the width of the vertical trench 212W along the second direction is too small, and the width difference between the first trench 212 and the vertical trench 212W is too small. In the formation of the first trench 212, the probability of the vertical trench 212W sidewall recessing is still high, and the recessing degree of the vertical trench 212W sidewall is still serious. Therefore, in the embodiment, the width of the vertical trench 212W along the second direction is 100 nm to 300 nm. For example, the width of the vertical trench 212W along the second direction is 150 nm, 200 nm, or 250 nm.

[0120] In addition, the greater the width of the vertical trench 212W along the second direction, the greater the cross-sectional area of the metal gate. Therefore, by setting the width of the vertical trench 212W within the reasonable range, the gate resistance of the first device can be significantly reduced.

[0121] In the embodiment, the forming method further includes: removing the polysilicon gate 210 of the second region 100L to form a gate opening 211 in the interlayer dielectric layer 340 (as shown in FIG. 6). Figure 10

[0122] The gate opening 211 is used to provide a spatial position for the subsequent formation of the metal gate in the second region 100L.

[0123] In the embodiment, the first trench 212 and the gate opening 211 are formed in the same step, thereby simplifying the process steps.

[0124] In the embodiment, before the formation of the first trench 212 and the gate opening 211, the forming method further includes: forming a second hard mask layer 370 on the interlayer dielectric layer 340, and the second hard mask layer 370 exposes the polysilicon gate 210 in the second region 100L and part of the polysilicon gate 210 in the first region 100K.

[0125] The second hard mask layer 370 is used as a mask for etching the polysilicon gate 210. In the embodiment, the material of the second hard mask layer 370 is titanium nitride.

[0126] Titanium nitride has high hardness, and therefore, a thinner second hard mask layer 370 can be formed, that is, the second hard mask layer 370 can be used as a mask for etching the polysilicon gate 210, thereby reducing the aspect ratio of the mask opening formed in the second hard mask layer 370, and further improving the etching effect on the polysilicon gate 210. In other embodiments, the second hard mask layer can also be selected from other metal hard mask layer materials.

[0127] The thickness of the second hard mask layer 370 is small, and therefore, after etching the polysilicon gate 210 with the second hard mask layer 370 as a mask, the recessing problem of the vertical trench 212W sidewall can be improved, and the probability of the vertical trench 212W sidewall recessing is also lower. ​

[0128] Correspondingly, the step of forming the first trench 212 and the gate opening 211 comprises: etching the polysilicon gate 210 with the second hard mask layer 370 as a mask.

[0129] With reference to Figures 12 to 14 , Figure 12 and Figure 13 is a sectional view, Figure 14 is a partial plan view of the high-voltage device region, and the metal gate 390 is formed in the first trench 212 (as shown in Figure 10 ) and the gate opening 211 (as shown in Figure 10 ).

[0130] In order to facilitate illustration, Figure 14 only the polysilicon gate 210, the source-drain doped region 240, the second isolation structure 102, the contact region 250 and the metal gate 390 in the high-voltage device region 100H are shown.

[0131] In the first region 100K, the doping concentration in the polysilicon gate 210 is low, or the polysilicon gate 210 is not doped with ions, and the polysilicon gate 210 is in a high-resistance state, and the device responds to high-frequency signals at a slower speed. Therefore, the potential is loaded onto the metal barrier layer 220 through the metal gate 390, and the cross-sectional area of the metal gate in the first region 100K is increased to reduce the gate resistance of the first device, thereby improving the response speed of the high-frequency signal.

[0132] In the embodiment, the first trench 212 comprises a vertical trench 212W (as shown in Figure 11 ) extending along a first direction (as shown in the Y direction in Figure 11 ), and a horizontal trench 212L (as shown in Figure 11 ) connected to the end of the vertical trench 212W, the horizontal trench 212L extending along a second direction (as shown in the X direction in Figure 11 ), and the second direction is perpendicular to the first direction; therefore, after the metal gate 390 is formed in the first trench 212, the metal gate 390 comprises a vertical metal gate 392 (as shown in Figure 14 ) located in the vertical trench 212W, and a horizontal metal gate 391 (as shown in Figure 14 ) located in the horizontal trench 212L.

[0133] By forming the vertical metal gate 392, the cross-sectional area of the metal gate 390 in the first region 100K is increased, and the gate resistance of the first device is reduced.

[0134] In this embodiment, the metal gate 390 includes a work function layer (not shown in the figure) covering the first trench 212 and the bottom and sidewall of the gate opening 211, and a gate electrode layer (not shown in the figure) covering the work function layer and filling in the first trench 212 and the gate opening 211.

[0135] The work function layer is used to adjust the threshold voltage of the formed transistor. When a PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN; when an NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.

[0136] The gate electrode layer is used to lead out the electrical property of the metal gate 390. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti or W.

[0137] Specifically, as shown in Figure 12 the step of forming the metal gate 390 in the first trench 212 and the gate opening 211 includes: forming a metal gate material layer 380 in the first trench 212 and the gate opening 211, the metal gate material layer 380 covering the second hard mask layer 370; as shown in Figure 13 performing a planarization treatment on the metal gate material layer 380 to expose the top surface of the interlayer dielectric layer 340 of the second region 100L, after the planarization treatment, the remaining metal gate material layer 380 in the first trench 212 and the gate opening 211 serves as the metal gate 390, and in the process of the planarization treatment, the second hard mask layer 370 is removed.

[0138] Correspondingly, the metal gate material layer 380 includes a work function material layer (not shown in the figure) for forming the work function layer, and a gate electrode material layer (not shown in the figure) for forming the gate electrode layer.

[0139] In this embodiment, the planarization treatment is performed by using a chemical mechanical polishing process.

[0140] It should be noted that the material of the second hard mask layer 370 is titanium nitride, and the material of the second hard mask layer 370 is the same as or close to the material of the work function material layer, so that the second hard mask layer 370 can be removed in the process of the planarization treatment.

[0141] It should also be noted that in the process of the planarization treatment, the sidewall 260 higher than the top surface of the polysilicon gate 210, the silicide barrier layer 300 and the contact hole etching stop layer 330 are also removed.

[0142] Accordingly, the present invention also provides a semiconductor structure. Continuing with the references... Figure 13 and Figure 14 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 13 It is a sectional view. Figure 14 This is a partial top view of the high-voltage device area, and for ease of illustration, Figure 14 Only the polysilicon gate 210, source / drain doped region 240, second isolation structure 102, contact region 250 and metal gate 390 in the high voltage device region 100H are shown.

[0143] The semiconductor structure includes: a substrate 100, including a first region 100K for forming a first device and a second region 100L for forming a second device, wherein the operating voltage of the first device is greater than the operating voltage of the second device; and a high-k gate dielectric layer 230, located on the substrate 100 of the first region 100K and the second region 100L, wherein the high-k gate dielectric layer 230 is oriented along a first direction (e.g., ...). Figure 14 (As shown in the Y direction); a metal barrier layer 220 is located on the high-k gate dielectric layer 230; a polysilicon gate 210 is located on the metal barrier layer 220 in the first region 100K; a metal gate 390 is located on the metal barrier layer 220 in the second region 100L and in the polysilicon gate 210. In the first region 100K, the metal gate 390 includes a vertical metal gate 392 extending along the first direction and a horizontal metal gate 391 connected to the end of the vertical metal gate 392. The horizontal metal gate 391 extends along the second direction (as shown in the Y direction). Figure 14 Extending in the X direction, the second direction is perpendicular to the first direction; the source and drain doped regions 240 are located on both sides of the polysilicon gate 210 and on both sides of the metal gate 390 of the second region 100L in the substrate 100.

[0144] Compared to schemes where the metal gate only includes a lateral metal gate, in this embodiment, the metal gate 390 in the first region 100K is T-shaped, and a vertical metal gate 392 extending along the channel width direction (i.e., the first direction) is also formed in the polysilicon gate 210. The vertical metal gate 392 increases the cross-sectional area of ​​the metal gate 390 in the first region 100K, thereby reducing the gate resistance of the first device and correspondingly improving the performance of the semiconductor structure. Furthermore, the length of the polysilicon gate 210 along the first direction is typically greater than its width along the second direction; therefore, increasing the cross-sectional area of ​​the metal gate 390 in the first region 100K is more effective.

[0145] In this embodiment, taking a planar field-effect transistor as an example, the substrate 100 is a planar substrate. In other embodiments, the semiconductor structure is a fin field-effect transistor, and correspondingly, the substrate includes a substrate and fins protruding from the substrate.

[0146] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate can also be a substrate of other material types. For example, the material of the substrate can be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0147] In this embodiment, the substrate is a P-type substrate, i.e., the substrate is doped with P-type ions, which are B ions, Ga ions, or In ions.

[0148] In this embodiment, the substrate 100 includes a first region 100K for forming a first device and a second region 100L for forming a second device, and the working voltage of the first device is greater than that of the second device.

[0149] As an example, the first region 100K includes a medium-voltage device region 100M for forming a medium-voltage device and a high-voltage device region 100H for forming a high-voltage device, and the second region 100L is a low-voltage device region for forming a low-voltage device. The working voltages of the low-voltage device, the medium-voltage device, and the high-voltage device increase in turn.

[0150] In this embodiment, the substrate 100 of the second region 100L (i.e., the low-voltage device region) and the medium-voltage device region 100M is formed with a deep N-type well region 120, and the substrate 100 of the high-voltage device region 100H is formed with a high-voltage well region 110.

[0151] The deep N-type well region 120 of the second region 100L is formed with a low-voltage well region 130, and the deep N-type well region 120 of the medium-voltage device region 100M is formed with a medium-voltage well region 140.

[0152] The type of doping ions in the well region is opposite to the conductivity type of the corresponding MOS device. Specifically, taking the high-voltage device as an example, when the high-voltage device is an NMOS device, the doping ions in the high-voltage well region 110 are P-type ions, and when the high-voltage device is a PMOS device, the doping ions in the high-voltage well region 110 are N-type ions.

[0153] In this embodiment, the semiconductor structure further includes a first isolation structure 101 in the substrate 100. Specifically, the first isolation structure 101 is in the substrate 100 at the boundary between the second region 100L and the medium-voltage device region 100M, and in the substrate 100 at the boundary between the medium-voltage device region 100M and the high-voltage device region 100H.

[0154] The first isolation structure 101 is used to realize isolation between adjacent devices. In this embodiment, the first isolation structure 101 is a shallow trench isolation, so that the first isolation structure 101 has a good isolation effect. The substrate 100 exposed by the first isolation structure 101 is used as an active region, and the region where the first isolation structure 101 is located is an isolation region. For example, as shown in the dashed box in FIG. 1, the active region is located in the high-voltage device region 100H. Figure 14 Figure 14 Figure 14 The dashed box in FIG. 1 is used to represent the position of the active region.

[0155] In this embodiment, the material of the first isolation structure 101 is an insulating material, and the insulating material includes silicon oxide.

[0156] It should be noted that the semiconductor structure further includes a second isolation structure 102 located in part of the substrate 100 in the high-voltage device region 100H. The substrate 100 in the high-voltage device region 100H is divided into a plurality of active regions by the second isolation structure 102. The material of the second isolation structure 102 is the same as that of the first isolation structure 101.

[0157] The high-k gate dielectric layer 230 is used to form a gate dielectric layer of a transistor, that is, the gate dielectric layer of the transistor includes the high-k gate dielectric layer 230. The material of the high-k gate dielectric layer 230 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 230 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 230 is HfO2.

[0158] The metal barrier layer 220 is used to isolate the high-k gate dielectric layer 230 and the polysilicon gate 210, and to protect the high-k gate dielectric layer 230. In the process of forming the semiconductor structure, the metal barrier layer 220 is used as an etching stop layer in the process of etching the polysilicon gate 210, so as to reduce the probability of damage to the high-k gate dielectric layer 230. The metal barrier layer 220 is also used to block the diffusion of easily diffusing ions (for example: aluminum ions) in the metal gate 390 into the high-k gate dielectric layer 230. In addition, the metal barrier layer 220 is used to control the opening or closing of the channel.

[0159] The material of the metal barrier layer 220 includes one or both of titanium nitride and silicon-doped titanium nitride. In this embodiment, the material of the metal barrier layer 220 is titanium nitride. The metal barrier layer 220 also has a certain effect on the gate work function of the transistor.

[0160] ​By setting the thickness of the metal barrier layer 220 reasonably, the metal barrier layer 220 can be used as an etching stop layer in the subsequent etching of the polysilicon gate 210, and the metal barrier layer 220 has better blocking effect on the diffusible ions in the metal gate.

[0161] In the embodiment, the polysilicon gate 210 covers the substrate 100 of the active region. The first region 100K is used to form a first device, and the working voltage of the first device is higher, and the size of the first device is larger. Therefore, in the semiconductor structure, the polysilicon gate 210 is formed in the first region 100K to meet the performance requirements of the semiconductor structure.

[0162] Specifically, in the high-voltage device region 100H, the polysilicon gate 210 also extends to cover part of the second isolation structure 102. In the embodiment, the material of the polysilicon gate 210 is polysilicon.

[0163] The source-drain doped region 240 is used as a source region or a drain region of the formed transistor. When an NMOS transistor is formed, the doped ions in the source-drain doped region 240 are N-type ions, and the N-type ions are P ions, As ions or Sb ions. When a PMOS transistor is formed, the doped ions in the source-drain doped region 240 are P-type ions, and the P-type ions are B ions, Ga ions or In ions.

[0164] In the embodiment, in the high-voltage device region 100H, the polysilicon gate 210 and the source-drain doped region 240 are isolated by the second isolation structure 102.

[0165] In the embodiment, the semiconductor structure further includes a contact region 250 located in the high-voltage device region 100H and in the substrate 100 on both sides of the polysilicon gate 210. The contact region 250 surrounds the second isolation structure 102, the source-drain doped region 240 and the polysilicon gate 210, and the contact region 250 and the source-drain doped region 240 are isolated by the second isolation structure 102.

[0166] In the first region 100K, the doping concentration in the polysilicon gate 210 is low, or the polysilicon gate 210 is not doped with ions, and the polysilicon gate 210 is in a high resistance state, and the device responds to high-frequency signals at a slower speed. Therefore, the potential is loaded to the metal barrier layer 220 by the metal gate 390, and the cross-sectional area of the metal gate 390 in the first region 100K is increased to reduce the gate resistance of the first device, thereby improving the response speed of the high-frequency signal.

[0167] In this embodiment, the polysilicon gate 210 is long strip-shaped, and has two end faces along the first direction. In order to significantly increase the cross-sectional area of the metal gate 390, in the first direction, the sidewall of the lateral metal gate 391 is in contact with one end face of the polysilicon gate 210, and the end face of the vertical metal gate 392 is flush with the other end face of the polysilicon gate 210, that is, the metal gate 390 of the first region 100K penetrates through the entire polysilicon gate 210 along the first direction.

[0168] It should be noted that the width of the vertical metal gate 392 along the second direction should not be too small or too large.

[0169] In the forming process of the semiconductor structure, the metal gate 390 is formed in the first trench, the first trench is T-shaped, and the first trench includes a vertical trench extending along the first direction and a lateral trench in communication with the end of the vertical trench, the lateral trench extending along the second direction, the second direction being perpendicular to the first direction, wherein the metal gate in the vertical trench is the vertical metal gate 392, and the metal gate in the lateral trench is the lateral metal gate 391; therefore, the vertical metal gate 392 is formed in the vertical trench, and if the width of the vertical metal gate 392 is too small, the width of the vertical trench is correspondingly too small, which easily leads to the depth-width ratio of the vertical trench being too large, thereby increasing the difficulty of forming the metal gate 390 in the vertical trench.

[0170] Moreover, in the forming process of the semiconductor structure, before the vertical trench is formed, in the first region 100K, the top of the polysilicon gate 210 is formed with a hard mask layer and a silicide barrier layer on the hard mask layer, the hard mask layer and the silicide barrier layer constituting a protection layer, and a T-shaped second trench extending along the first direction is first formed in the protection layer of the first region 100K to expose part of the polysilicon gate 210, and then a T-shaped first trench is formed in the exposed polysilicon gate 210.

[0171] The second trench includes a vertical mask trench extending along the first direction and a lateral mask trench in communication with the end of the vertical mask trench, the lateral mask trench extending along the second direction. In the direction parallel to the substrate 100 and perpendicular to the sidewall of the polysilicon gate 210, the width of the vertical trench is smaller than the width of the vertical mask trench, so that in the process of etching the polysilicon gate 210 to form the first trench, the problem of the sidewall of the vertical trench being recessed due to lateral etching can be significantly alleviated, thereby reducing the probability of forming a hole between the metal gate 390 and the polysilicon gate 210.

[0172] Therefore, if the width of the vertical metal gate 392 is too large, which results in the width of the vertical trench being too large, the difference between the width of the vertical mask trench and the vertical trench is too small, and the probability of the vertical trench sidewall being recessed is still high when the first trench is formed, and the degree of recess of the vertical trench sidewall is still serious.

[0173] In summary, in this embodiment, the width of the vertical metal gate 392 along the second direction is 100-300 nm. For example, the width of the vertical metal gate 392 along the second direction is 150 nm, 200 nm, or 250 nm.

[0174] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 340 on the substrate 100 on the side of the polysilicon gate 210 and the metal gate 390, and the interlayer dielectric layer 340 covers the sidewall of the polysilicon gate 210 in the first region 100K and the sidewall of the metal gate 390 in the second region 100L.

[0175] The interlayer dielectric layer 340 is used to isolate adjacent devices. The material of the interlayer dielectric layer 340 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the material of the interlayer dielectric layer 340 is silicon oxide.

[0176] In this embodiment, the top of the interlayer dielectric layer 340 is flush with the top of the polysilicon gate 210 and the metal gate 390.

[0177] In this embodiment, the semiconductor structure further includes a sidewall 260 covering the sidewall of the polysilicon gate 210 in the first region 100K and the sidewall of the metal gate 390 in the second region 100L. The sidewall 260 is used to protect the sidewall of the polysilicon gate 210 and the metal gate 390, and is also used to define the formation position of the source / drain doped region 240.

[0178] The sidewall 260 can be a single-layer structure or a stacked structure, and the material of the sidewall 260 can include one or more of silicon oxide, silicon nitride, silicon oxynitride, boron nitride, aluminum oxide, and aluminum nitride. In this embodiment, the sidewall 260 is a single-layer structure, and the material of the sidewall 260 is silicon nitride.

[0179] In this embodiment, the semiconductor structure further includes a silicide blocking layer 300 covering the sidewall of the sidewall 260. The silicide blocking layer 300 is used to define the formation area of the silicide layer.

[0180] The material of the silicide blocking layer 300 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the silicide blocking layer 300 is silicon nitride.

[0181] In the embodiment, the semiconductor structure further comprises a contact hole etching stop layer 330 between the sidewall of the silicide blocking layer 300 and the interlayer dielectric layer 340, and between the interlayer dielectric layer 340 and the substrate 100.

[0182] The contact hole etching stop layer 330 is used to induce stress in the channel, so as to realize SMT. Moreover, in the process of subsequently forming the source / drain plug penetrating through the interlayer dielectric layer 340 and contacting the source / drain doped region 240, the contact hole etching stop layer 330 is used to define the position of etching stop in the process of etching through the interlayer dielectric layer 340, so as to avoid over-etching of the source / drain doped region 240. As an example, the material of the contact hole etching stop layer 330 is silicon nitride.

[0183] The semiconductor structure can be formed by the forming method described in the foregoing embodiments, or can be formed by other forming methods. For the specific description of the semiconductor structure in the embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be described herein again.

[0184] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, which comprises a first region for forming a first device and a second region for forming a second device, the working voltage of the first device being greater than that of the second device, a high-k gate dielectric layer, a metal barrier layer and a polysilicon gate being sequentially stacked from bottom to top on the substrate of the first region and the second region, and source-drain doped regions being formed in the substrate on both sides of the polysilicon gate; forming an interlayer dielectric layer on the substrate on both sides of the polysilicon gate, the interlayer dielectric layer covering the sidewall of the polysilicon gate; forming a first trench in the polysilicon gate of the first region, the first trench comprising a vertical trench extending along the first direction and a horizontal trench communicating with the end of the vertical trench, the horizontal trench extending along the second direction which is perpendicular to the first direction; removing the polysilicon gate of the second region to form a gate opening in the interlayer dielectric layer; forming a metal gate in the first trench and the gate opening; the metal gate is formed not only in the horizontal trench but also in the vertical trench.

2. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, a first hard mask layer is formed on the top of the polysilicon gate; Before forming the interlayer dielectric layer, the method further comprises: forming a silicide barrier layer conformally covering the substrate, the source-drain doped regions, the polysilicon gate and the first hard mask layer, in the first region, the silicide barrier layer and the first hard mask layer above the top of the polysilicon gate serving as a protection layer; forming a pattern layer on the protection layer in the first region; etching to remove the silicide barrier layer on the substrate, the source-drain doped regions and the first hard mask layer with the pattern layer as a mask; removing the pattern layer; In the step of forming the interlayer dielectric layer, the interlayer dielectric layer exposes the top of the protection layer and the top of the polysilicon gate in the second region.

3. The method of forming a semiconductor structure of claim 2, wherein, In the step of forming the interlayer After the dielectric layer, the thickness of the protective layer is to 4. The method of forming a semiconductor structure of claim 2, wherein, In the step of providing the substrate, a sidewall is formed on the sidewall of the polysilicon gate; After etching to remove the silicide barrier layer on the substrate, the source-drain doped regions and the first hard mask layer, the remaining silicide barrier layer on the sidewall of the polysilicon gate and the sidewall serve as a sidewall structure; After removing the pattern layer, the method further comprises: etching the sidewall structure by using an anisotropic etching process to perform thinning treatment on the sidewall of the sidewall structure.

5. The method of forming a semiconductor structure of claim 4, wherein During the thinning treatment, the remaining first hard mask layer on the top of the polysilicon gate in the second region is removed.

6. The method of forming a semiconductor structure of claim 4, wherein, After thinning the sidewall of the sidewall structure, the thickness of the protective layer is to 7. The method of forming a semiconductor structure of claim 2, wherein, After forming the interlayer dielectric layer, before forming the first trench in the polysilicon gate of the first region, the The method further comprises: forming a second trench in the protection layer of the first region, the second trench comprising a vertical mask trench extending along the first direction and a horizontal mask trench communicating with the end of the vertical mask trench, the horizontal mask trench extending along the second direction. The step of forming the first trench comprises forming a first trench in the polysilicon gate exposed by the second trench, wherein the vertical trench has a width less than the width of the vertical mask trench in a direction parallel to the substrate and perpendicular to the sidewall of the polysilicon gate.

8. The method of forming a semiconductor structure of claim 7, wherein, The width difference between the vertical mask trench and the vertical trench in a direction parallel to the substrate and perpendicular to the sidewall of the polysilicon gate is 100-300 nm.

9. The method of forming a semiconductor structure of claim 7, wherein, The first region of the protective layer is etched by using an anisotropic etching process to form the second trench.

10. The method of forming a semiconductor structure of claim 1, wherein, The first trench and the gate opening are formed in the same step.

11. The method of forming a semiconductor structure of claim 10, wherein, Before forming the first trench and the gate opening, the forming method further comprises forming a second hard mask layer on the interlayer dielectric layer, the second hard mask layer exposing the polysilicon gate in the second region and part of the polysilicon gate in the first region. The step of forming the first trench and the gate opening comprises etching the polysilicon gate by using the second hard mask layer as a mask.

12. The method of forming a semiconductor structure of claim 11, wherein, The step of forming the metal gate in the first trench and the gate opening comprises forming a metal gate material layer in the first trench and the gate opening, the metal gate material layer covering the second hard mask layer. The metal gate material layer is subjected to a planarization treatment to expose the top surface of the interlayer dielectric layer in the second region, after the planarization treatment, the remaining metal gate material layer in the first trench and the gate opening serves as the metal gate, and in the process of the planarization treatment, the second hard mask layer is removed.

13. The method of forming a semiconductor structure of claim 11, wherein, The material of the second hard mask layer comprises titanium nitride.

14. The method of forming a semiconductor structure of claim 1, wherein, The material of the metal barrier layer comprises one or both of titanium nitride and silicon-doped titanium nitride.

15. The method of forming a semiconductor structure of claim 2, wherein, The material of the silicide barrier layer comprises one or more of silicon nitride, silicon oxide and silicon oxynitride.

16. The method of forming a semiconductor structure of claim 1, wherein, The width of the vertical trench along the second direction is 100-300 nm.

17. The method of forming a semiconductor structure of claim 1, wherein, The polysilicon gate in the first region is etched by using an anisotropic etching process to form the first trench.

18. A semiconductor structure, characterized by Comprise: a substrate comprising a first region for forming a first device and a second region for forming a second device, the working voltage of the first device being greater than that of the second device; a high-k gate dielectric layer on the substrate in the first region and the second region, the high-k gate dielectric layer extending in a first direction; a metal barrier layer on the high-k gate dielectric layer; a polysilicon gate on the metal barrier layer in the first region; a metal gate on the metal barrier layer in the second region and in the polysilicon gate, in the first region, the metal gate comprises a vertical metal gate extending in the first direction and a horizontal metal gate connected to the end of the vertical metal gate, the horizontal metal gate extending in a second direction perpendicular to the first direction; a source / drain doped region in the substrate on both sides of the polysilicon gate and on both sides of the metal gate in the second region.

19. The semiconductor structure of claim 18, wherein, The material of the metal barrier layer comprises one or both of titanium nitride and silicon-doped titanium nitride.

20. The semiconductor structure of claim 18, wherein, A width of the vertical metal gate along the second direction is 100 nm to 300 nm.

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