Semiconductor structure and method of forming the same, and transistor

Abstract

A semiconductor structure, a method for forming the semiconductor structure, and a transistor, the semiconductor structure comprising: a channel structure layer located on and spaced apart from a protrusion, the channel structure layer comprising one or more spaced apart channel layers; an isolation structure located on a semiconductor substrate and surrounding the protrusion, a top surface of the isolation structure being higher than a top surface of the protrusion and lower than a bottom surface of the channel structure layer, the isolation structure and the protrusion forming a bottom trench, and the bottom trench being located below the channel structure layer; a gate structure crossing the channel structure layer and surrounding the channel layers and filling the bottom trench; the gate structure comprising a gate dielectric layer surrounding surfaces of the channel layers and located on a bottom and sidewalls of the bottom trench, and a gate electrode layer located on the gate dielectric layer; and source / drain doped layers located on both sides of the gate structure and in contact with end portions of the channel structure layer. The bottom trench is provided in the embodiment of the application, so that the gate dielectric layer is located on the sidewalls and the bottom of the bottom trench, which is beneficial to reducing the leakage current of the device and optimizing the performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure, a method for forming the same, and a transistor. BACKGROUND

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration, and the semiconductor process node is following the development trend of Moore's law and is continuously decreasing. As the most basic semiconductor device, transistors are currently widely used. Therefore, as the element density and integration of semiconductor devices increase, in order to adapt to the decrease of the process node, the channel length of the transistor must be shortened.

[0003] In order to better adapt to the requirement of device size scaling, semiconductor technology gradually begins to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In the gate-all-around transistor, the gate surrounds the area where the channel is located from all around. Compared with planar transistors, the gate-all-around transistor has stronger control ability of the gate to the channel, and can better suppress the short channel effect.

[0004] However, the performance of the current device still needs to be improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure, a method for forming the same, and a transistor, which reduces the leakage current of the device, improves the process compatibility, and optimizes the performance of the semiconductor structure.

[0006] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a semiconductor substrate, the semiconductor substrate has a plurality of discrete protrusions; a channel structure layer located on the protrusions and spaced apart from the protrusions, the channel structure layer comprises one or more channel layers arranged in sequence and spaced apart; an isolation structure located on the semiconductor substrate and surrounding the protrusions, the top surface of the isolation structure is higher than the top surface of the protrusions and lower than the bottom surface of the channel structure layer; a bottom groove surrounded by the isolation structure and the protrusions, and the bottom groove is located below the channel structure layer; a gate structure located on the isolation structure and the protrusions, the gate structure spans the channel structure layer and surrounds the channel layer and fills the bottom groove; the gate structure comprises a gate dielectric layer surrounding the surface of the channel layer and located at the bottom and sidewall of the bottom groove, and a gate electrode layer located on the gate dielectric layer; a gate sidewall located on both sides of the gate structure and exposing the end of the channel structure layer extending direction; a source / drain doped layer located on the protrusions on both sides of the gate structure and gate sidewall and in contact with the end of the channel structure layer.

[0007] Accordingly, the embodiment of the present application also provides a transistor, comprising: a semiconductor substrate, wherein a plurality of discrete protrusions are formed on the semiconductor substrate; an isolation structure, which is located on the semiconductor substrate and covers the sidewalls and part of the top surface of the protrusions; a channel structure layer, which is located above the protrusions and is spaced apart from the protrusions and the isolation structure, and the channel structure layer comprises one or more channel layers which are sequentially and spaced apart; a bottom trench, which is surrounded by the protrusions and the isolation structure, and the bottom trench exposes part of the sidewalls of the isolation structure; a gate structure, which is located on the isolation structure and the protrusions, and the gate structure spans the channel structure layer and surrounds the channel layers and fills the bottom trench; the gate structure comprises a gate dielectric layer which surrounds the surfaces of the channel layers and is located on the top surface of the protrusions and the sidewalls and top surface of the isolation structure, and a gate electrode layer which is located on the gate dielectric layer; a gate sidewall, which is located on both sides of the gate structure and exposes the ends of the channel structure layer in the extension direction of the channel structure layer; and source / drain doped layers, which are located on the protrusions on both sides of the gate structure and the gate sidewall and are in contact with the ends of the channel structure layer.

[0008] Accordingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a semiconductor substrate, wherein a plurality of discrete protrusions are formed on the semiconductor substrate, and one or more channel stacks which are sequentially and stacked from bottom to top are formed on the protrusions, and each channel stack comprises a sacrificial layer and a channel layer which is located on the sacrificial layer; forming an isolation structure on the semiconductor substrate exposed by the channel stack, wherein the isolation structure also covers part of the sidewalls of the sacrificial layer which is in contact with the protrusions; forming a pseudo gate structure which spans the channel stack on the isolation structure; forming source / drain doped layers in the channel stack on both sides of the pseudo gate structure, which are in contact with the protrusions; removing the pseudo gate structure to form a gate opening and expose the channel stack; removing the sacrificial layer in the channel stack to form a through trench, and the through trench comprises a first through trench which is surrounded by the protrusions and the channel layer adjacent to the protrusions; wherein the first through trench comprises a bottom trench which is surrounded by the protrusions and the isolation structure, and a top trench which is located on the bottom trench and is in communication with the bottom trench; and filling a gate structure in the gate opening and the through trench, wherein the gate structure comprises a gate dielectric layer which surrounds the surfaces of the channel layers and is located on the bottom of the bottom trench and the sidewalls of the bottom trench, and a gate electrode layer which is located on the gate dielectric layer and fills at least the gate opening and the top trench.

[0009] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0010] The semiconductor structure provided by the embodiment of the present application is characterized in that the top surface of the isolation structure is higher than the top surface of the protruding part and lower than the bottom surface of the channel structure layer, the isolation structure and the protruding part enclose a bottom groove, and the bottom groove is located below the channel structure layer; in the gate structure, the gate dielectric layer is also located at the bottom and the sidewall of the bottom groove; when the gate dielectric layer does not fill the bottom groove and the gate electrode layer also fills the bottom groove, the gate dielectric layer is located at the sidewall of the bottom groove, so that the width of the gate electrode layer in the bottom groove is small, and the effective width of the parasitic channel in the protruding part below the bottom groove is correspondingly small, thereby reducing the leakage current in the parasitic channel; when the gate dielectric layer fills the bottom groove, the distance between the gate electrode layer and the protruding part below the bottom groove can be increased, that is, the parasitic gate dielectric layer of the parasitic device composed of the gate electrode layer, the protruding part below the bottom groove and the source / drain doped layer is thick, which correspondingly increases the difficulty of opening the parasitic device and is beneficial to reducing the leakage current in the parasitic channel; and the source / drain doped layer is in contact with the protruding part, and the source / drain doped layer is usually formed by an epitaxial process, compared with the scheme of reducing the leakage current by arranging an isolation material between the source / drain doped layer and the protruding part, the embodiment of the present application is beneficial to ensuring the epitaxial growth quality of the source / drain doped layer; in summary, the embodiment of the present application is beneficial to reducing the leakage current of the device, and is also beneficial to improving the process compatibility and the film formation quality of the source / drain doped layer, and optimizes the performance of the semiconductor structure.

[0011] In the transistor provided by the embodiment of the present application, the leakage current in the parasitic channel is reduced, the epitaxial quality of the source / drain doped layer is high, and the performance of the transistor is improved.

[0012] In the method for forming the semiconductor structure, the isolation structure further covers a part of the sidewall of the sacrificial layer in contact with the protruding portion. In the step of removing the sacrificial layer to form a through slot, the through slot includes a first through slot surrounded by the protruding portion and the channel layer adjacent to the protruding portion, and the first through slot includes a bottom groove surrounded by the isolation structure and the protruding portion. In the step of forming a gate structure, the gate dielectric layer can be formed on the bottom and the sidewall of the bottom groove. When the gate dielectric layer does not fill the bottom groove, the gate electrode layer also fills the bottom groove. Due to the gate dielectric layer on the sidewall of the bottom groove, the width of the gate electrode layer in the bottom groove is small, and the effective width of the parasitic channel in the protruding portion below the bottom groove is small, which is beneficial to reduce the leakage current in the parasitic channel. When the gate dielectric layer fills the bottom groove, the distance between the gate electrode layer and the protruding portion below the bottom groove can be increased, that is, the parasitic gate dielectric layer of the parasitic device formed by the gate electrode layer, the protruding portion below the bottom groove and the source / drain doped layer is thick, which increases the difficulty of opening the parasitic device and is beneficial to reduce the leakage current in the parasitic channel. In addition, the forming height of the isolation structure is adjusted to form the bottom groove, and the existing process is slightly changed, which is beneficial to simplify the process and improve the process compatibility. In summary, the embodiment is beneficial to reduce the leakage current of the device, improve the process compatibility and optimize the performance of the semiconductor structure.

[0013] In addition, the source / drain doped layer is usually formed by an epitaxial process. Compared with the scheme of reducing the leakage current by arranging an isolation material between the source / drain doped layer and the substrate, the source / drain doped layer in the embodiment is formed on the protruding portion on both sides of the gate structure and in contact with the protruding portion, so that the process of forming the source / drain doped layer is slightly affected, which is beneficial to improve the process compatibility and ensure the epitaxial growth quality of the source / drain doped layer. Therefore, the embodiment is beneficial to improve the process compatibility and reduce the leakage current of the device. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a structural schematic diagram of a semiconductor structure;

[0015] Figure 2 is a structural schematic diagram of another semiconductor structure;

[0016] Figures 3-4 is a structural schematic diagram of an embodiment of the semiconductor structure of the application;

[0017] Figures 5-6 is a structural schematic diagram of another embodiment of the semiconductor structure of the application;

[0018] Figures 7-28 is a structural schematic diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the application;

[0019] Figures 29-30 is a structure diagram of a semiconductor structure corresponding to each step in another embodiment of the forming method of the semiconductor structure. DETAILED DESCRIPTION

[0020] As known from the background, the performance of the device needs to be improved.

[0021] Specifically, taking a fully surrounded gate transistor as an example, the fully surrounded gate transistor generally comprises: a substrate, comprising a substrate and a plurality of protrusions separated on the substrate; a channel structure layer, located on the protrusions and spaced apart from the protrusions, the channel structure layer comprising one or more spaced apart channel layers; a gate structure, spanning the channel structure layer, and also located between adjacent channel layers or between a protrusion and a channel layer adjacent to the protrusion, the gate structure surrounding the channel layer; a source-drain doped layer, located on both sides of the gate structure and covering the sidewall of the channel structure layer.

[0022] Wherein, the source-drain doped layer is located on the protrusions and also in contact with the protrusions, which results in the formation of a parasitic device in the protrusions below the channel structure layer, causing a leakage current in the protrusions below the channel structure layer. Especially, when the source-drain doped layer is also embedded in the protrusions, a protruding protrusion structure will be formed between the source-drain doped layers located on both sides of the gate structure, resulting in the formation of a parasitic channel in the protrusion structure, and the leakage current of the device is more serious. When the source-drain doped layer is embedded in the protrusions to a greater depth, the leakage current of the device is more serious.

[0023] There are two methods to try to reduce the leakage current of the fully surrounded gate transistor.

[0024] REFERENCE Figure 1 is a structure diagram of a semiconductor structure, comprising: a substrate 10, a plurality of discrete protrusions 16 are formed on the substrate 10; a channel structure layer 11, located on the protrusions 16 and spaced apart from the protrusions 16, the channel structure layer 11 comprising one or more spaced apart channel layers 12; a gate structure 13, spanning the channel structure layer 11, and also located between adjacent channel layers 12 or between a protrusion 16 and a channel layer 12 adjacent to the protrusion 16, the gate structure 20 surrounding the channel layer 12; a source-drain doped layer 14, located on both sides of the gate structure 13 and covering the sidewall of the channel structure layer 11; an isolation layer 15, located between the protrusions 16 and the source-drain doped layer 14.

[0025] The isolation layer 15 is arranged between the source-drain doped layer 14 and the protruding part 16 to isolate the source-drain doped layer 14 from the protruding part 16, so that the source-drain doped layer 14 cannot contact the protruding part 16, thereby reducing the leakage current generated in the protruding part 16 under the channel structure layer 11.

[0026] However, the source-drain doped layer 14 is usually formed by an epitaxial process, and arranging the isolation layer 15 between the bottom of the source-drain doped layer 14 and the protruding part 16 will greatly affect the epitaxial process of forming the source-drain doped layer 14, thereby causing poor formation quality of the source-drain doped layer 14 and poor performance of the semiconductor structure.

[0027] Reference Figure 2 is a structural schematic diagram of another semiconductor structure, which comprises a substrate 20, a plurality of discrete protruding parts 26 formed on the substrate 20, an isolation layer 25 arranged on the protruding part 26, a channel structure layer 21 arranged on the isolation layer 25 and spaced apart from the isolation layer 25, the channel structure layer 21 comprising one or more channel layers 22 arranged at intervals, a gate structure 23 crossing the channel structure layer 21 and also arranged between adjacent channel layers 22 or between the isolation layer 25 and the channel layer 22 adjacent to the isolation layer 25, the gate structure 23 surrounding the channel layer 22, and a source-drain doped layer 24 arranged on the isolation layer 25 on both sides of the gate structure 23 and covering the sidewall of the channel structure layer 21.

[0028] In the semiconductor structure, the isolation layer 25 is arranged below the channel structure layer 21, the gate structure 23 and the source-drain doped layer 24, so that the entire device is isolated from the protruding part 26 by the isolation layer 25, thereby reducing the leakage current generated in the protruding part 26.

[0029] In the semiconductor structure, the isolation layer 25 is arranged between the bottom of the source-drain doped layer 24 and the protruding part 26, which will also affect the epitaxial process of forming the source-drain doped layer 24, thereby causing poor formation quality of the source-drain doped layer 24 and poor performance of the semiconductor structure. Moreover, there is no specific method for forming the isolation layer 25 disclosed at present.

[0030] To solve the technical problem, the embodiment of the present application provides a semiconductor structure, a top surface of the isolation structure is higher than a top surface of the protruding part and lower than a bottom surface of the channel structure layer, the isolation structure and the protruding part form a bottom trench, and the bottom trench is located below the channel structure layer; in the gate structure, the gate dielectric layer is also located at the bottom and the sidewall of the bottom trench; when the gate dielectric layer does not fill the bottom trench and the gate electrode layer also fills the bottom trench, because the gate dielectric layer is located at the sidewall of the bottom trench, the width of the gate electrode layer in the bottom trench is small, and the effective width of the parasitic channel in the protruding part below the bottom trench is also small, thereby reducing the leakage current in the parasitic channel; when the gate dielectric layer fills the bottom trench, the distance between the gate electrode layer and the protruding part below the bottom trench can be increased, that is, the parasitic gate dielectric layer of the parasitic device formed by the gate electrode layer, the protruding part below the bottom trench and the source / drain doped layer is thick, and the difficulty of opening the parasitic device is increased, which is beneficial to reducing the leakage current in the parasitic channel; and the source / drain doped layer is in contact with the protruding part, and the source / drain doped layer is usually formed by an epitaxial process, compared with the scheme of reducing the leakage current by setting an isolation material between the source / drain doped layer and the protruding part, the embodiment of the present application is beneficial to ensuring the epitaxial growth quality of the source / drain doped layer; in summary, the embodiment of the present application is beneficial to reducing the leakage current of the device, and is also beneficial to improving the process compatibility and the film formation quality of the source / drain doped layer, and optimizes the performance of the semiconductor structure.

[0031] To solve the technical problem, the embodiment of the present application also provides a transistor, the leakage current in the parasitic channel is reduced, the epitaxial quality of the source / drain doped layer is high, and the performance of the transistor is improved.

[0032] To solve the technical problem, the embodiment of the present application also provides a forming method of a semiconductor structure, wherein the isolation structure also covers a part of the side wall of the sacrificial layer in contact with the protruding part, in the step of removing the sacrificial layer to form a through slot, the through slot comprises a first through slot surrounded by the protruding part and the channel layer adjacent to the protruding part, and the first through slot comprises a bottom groove surrounded by the isolation structure and the protruding part; accordingly, in the step of forming a gate structure, the gate dielectric layer can be formed on the bottom and the side wall of the bottom groove; when the gate dielectric layer does not fill the bottom groove, and the gate electrode layer also fills the bottom groove, the gate dielectric layer is located on the side wall of the bottom groove, so that the width of the gate electrode layer in the bottom groove is small, and the effective width of the parasitic channel in the protruding part below the bottom groove is also small, which is beneficial to reduce the leakage current in the parasitic channel; when the gate dielectric layer fills the bottom groove, the distance between the gate electrode layer and the protruding part below the bottom groove can be increased, that is, the parasitic gate dielectric layer of the parasitic device composed of the gate electrode layer, the protruding part below the bottom groove and the source / drain doped layer is thick, which is beneficial to increase the difficulty of opening the parasitic device and reduce the leakage current in the parasitic channel; and the embodiment of the present application only adjusts the forming height of the isolation structure to form the bottom groove, which has small changes to the existing process, is beneficial to simplify the process and improve the process compatibility; in summary, the embodiment of the present application is beneficial to reduce the leakage current of the device, improve the process compatibility and optimize the performance of the semiconductor structure.

[0033] In addition, the source / drain doped layer is usually formed by an epitaxial process, and compared with the scheme of reducing the leakage current by arranging an isolation material between the source / drain doped layer and the protruding part, the source / drain doped layer in the embodiment of the present application is formed on the protruding part on both sides of the gate structure and in contact with the substrate, so that the process of forming the source / drain doped layer is less affected, which is beneficial to improve the process compatibility, guarantee the epitaxial growth quality of the source / drain doped layer, and further reduce the leakage current of the device while improving the process compatibility.

[0034] In order to make the above-mentioned purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0035] For the convenience of illustration and description, the semiconductor structure provided by the embodiment of the present application will be described in detail first.

[0036] Reference Figure 3 and Figure 4 , which shows a structure schematic diagram of an embodiment of the semiconductor structure of the present application. Figure 3 is a sectional view along the direction perpendicular to the extension direction of the channel layer at the position of the channel layer, Figure 4 is Figure 3 a sectional view along the A-A1 direction.

[0037] like Figure 3 and Figure 4 As shown, in this embodiment, the semiconductor structure includes: a semiconductor substrate 110 with a plurality of discrete protrusions 120; a channel structure layer 200 located above and spaced apart from the protrusions 120, the channel structure layer 200 including one or more channel layers 40 arranged sequentially at intervals; an isolation structure 150 located on the semiconductor substrate 110 and surrounding the protrusions 120, the top surface of the isolation structure 150 being higher than the top surface of the protrusions 120 and lower than the bottom surface of the channel structure layer 200; a bottom trench 70 formed by the isolation structure 150 and the protrusions 120, and the bottom trench 70 being located below the channel structure layer 200; and a gate. Structure 300 is located on the isolation structure 150 and the protrusion 120. The gate structure 300 spans the channel structure layer 200, surrounds the channel layer 40, and fills the bottom trench 70. The gate structure 300 includes a gate dielectric layer 310 surrounding the surface of the channel layer 40 and located at the bottom and sidewalls of the bottom trench 70, and a gate electrode layer 320 located on the gate dielectric layer 310. Gate sidewalls 165 are located on both sides of the gate structure 300 and expose the ends of the channel structure layer 200 extending in the direction of extension. Source and drain doped layers 170 are located on the protrusions 120 on both sides of the gate structure 300 and the gate sidewalls 165 and are in contact with the ends of the channel structure layer 200.

[0038] The semiconductor substrate 110 is used to provide a process platform for the formation of semiconductor structures.

[0039] In this embodiment, a gate-all-around (GAA) transistor is used as an example of semiconductor structure. In other embodiments, the semiconductor structure may also be formed as a forksheet transistor or a complementary field-effect transistor (CFET).

[0040] In this embodiment, the semiconductor substrate 110 is a silicon substrate, that is, the material of the semiconductor substrate 110 is single-crystal silicon. In other embodiments, the material of the semiconductor substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The semiconductor substrate may also be other types of semiconductor substrates such as silicon-on-insulator semiconductor substrate or germanium-on-insulator semiconductor substrate.

[0041] In this embodiment, the protruding portion 120 is in an integral structure with the semiconductor substrate 110, and the material of the protruding portion 120 is the same as that of the semiconductor substrate 110, both of which are silicon. In other embodiments, the material of the protruding portion can be different from that of the semiconductor substrate, and the material of the protruding portion can be other suitable materials, such as one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

[0042] The channel structure layer 200 is configured to provide a conductive channel of a field effect transistor.

[0043] As an example, the semiconductor structure is an NMOS transistor, and the material of the channel layer 40 is Si, i.e., the material of the channel layer 40 is single crystal silicon. In other embodiments, when the semiconductor structure is a PMOS transistor, to improve the performance of the PMOS transistor, a SiGe channel technology can be used, and the material of the channel layer is SiGe. In other embodiments, the material of the channel layer can also include one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

[0044] As an example, the number of the channel layers 40 is multiple, and the multiple channel layers 40 are sequentially and spacedly arranged from bottom to top. Specifically, in this embodiment, the number of the channel layers 40 is three. In other embodiments, the number of the channel layers can also be one, two, four, etc.

[0045] The isolation structure 150 is configured to isolate adjacent devices.

[0046] The top surface of the isolation structure 150 is higher than the top surface of the protruding portion 120 and lower than the bottom surface of the channel structure layer 200, because during the process of the semiconductor structure, a sacrificial layer is also formed between adjacent channel layers 40 or between the protruding portion 120 and the channel layers 40, and the isolation structure 150 covers the part of the sidewall of the sacrificial layer in contact with the protruding portion 120, so that after the sacrificial layer is removed, the isolation structure 150 and the protruding portion 120 can enclose the bottom trench 70.

[0047] In this embodiment, the material of the isolation structure 150 is silicon oxide. The isolation structure 150 can also be other suitable insulating materials, such as one or more of silicon nitride, silicon oxynitride, and germanium silicon oxide.

[0048] In this embodiment, the isolation structure 150 is filled in the area enclosed by the protruding portion 120 and the semiconductor substrate 110, and the top of the isolation structure 150 is higher than the top of the protruding portion 120 and lower than the bottom surface of the channel layer 40 adjacent to the protruding portion 120.

[0049] In this embodiment, the isolation structure 150 also covers part of the top surface of the protruding portion 120.

[0050] By surrounding the bottom trench 70 with the isolation structure 150 and the protruding portion 120, the gate dielectric layer 310 in the gate structure 300 can be located at the bottom and sidewall of the bottom trench 70, thereby reducing the width of the gate electrode layer 320 in the bottom trench 70 or even preventing the gate electrode layer 320 from being formed in the bottom trench 70, which is conducive to reducing the effective width of the parasitic channel in the protruding portion 120 below the bottom trench 70 or increasing the distance between the gate electrode layer 320 and the protruding portion 120 below the bottom trench 70, thereby increasing the difficulty of opening the parasitic device and reducing the leakage current in the parasitic channel.

[0051] In this embodiment, the bottom trench 70 is located below the channel structure layer 200, and the bottom surface of the bottom trench 70 is opposite to the bottom wall of the channel layer 40 adjacent to the protruding portion 120, which means that the bottom surface of the bottom trench 70 is opposite to the bottom wall of the channel layer 40 adjacent to the protruding portion 120, and the projection of the bottom trench 70 on the semiconductor substrate 110 corresponds to the projection of the channel layer 40 on the semiconductor substrate 110, or the projection of the bottom trench 70 on the semiconductor substrate 110 falls within the projection range of the channel layer 40 on the semiconductor substrate 110.

[0052] It should be noted that the ratio of the depth h of the bottom trench 70 to the distance between the protruding portion 120 and the bottom wall of the channel layer 40 adjacent to the protruding portion 120 should not be too small or too large. If the ratio is too small, the process difficulty will be increased; if the ratio is too large, the distance between the bottom trench 70 and the channel layer 40 above the bottom trench 70 will be too close, which will increase the difficulty of filling the gate structure 300 between the bottom trench 70 and the channel layer 40 above the bottom trench 70. Therefore, in this embodiment, the ratio of the depth h of the bottom trench 70 to the distance between the protruding portion 120 and the bottom wall of the channel layer 40 adjacent to the protruding portion 120 is 10% to 80%.

[0053] In this embodiment, the sidewall of the bottom trench 70 is recessed relative to the sidewall of the same side of the channel layer 40 in the direction perpendicular to the extension direction of the channel layer 40.

[0054] The sidewall of the bottom trench 70 is recessed relative to the sidewall of the same side of the channel layer 40 along the extension direction of the channel layer 40, so as to reduce the width of the bottom trench 70 along the extension direction of the channel layer 40, which is beneficial to prevent the gate electrode layer 320 from being formed in the bottom trench 70 or to reduce the width of the gate electrode layer 320 formed in the bottom trench 320, and is beneficial to more significantly reduce the leakage current of the parasitic channel in the protruding portion 120 below the bottom trench 70.

[0055] It should be noted that the width of the sidewall of the bottom trench 70 recessed relative to the sidewall of the same side of the channel layer 40 along the extension direction of the channel layer 40 should not be too small or too large. If the width of the sidewall of the bottom trench 70 recessed relative to the sidewall of the same side of the channel layer 40 along the extension direction of the channel layer 40 is too small, the effect of reducing the width of the bottom trench 70 along the extension direction of the channel layer 40 is not obvious. The bottom trench 70 is formed by removing the sacrificial layer covered by the isolation structure 150, and if the width of the sidewall of the bottom trench 70 recessed relative to the sidewall of the same side of the channel layer 40 along the extension direction of the channel layer 40 is too large, the width of the bottom trench 70 along the extension direction of the channel layer 40 is correspondingly too small, which causes the width of the sacrificial layer in contact with the protruding portion 120 along the extension direction of the channel layer 40 to be small, and correspondingly reduces the support strength of the sacrificial layer on the channel layer 40, thereby increasing the risk of tilting or collapse of the channel layer 40. Therefore, in the embodiment, the width of the sidewall of the bottom trench 70 recessed relative to the sidewall of the same side of the channel layer 40 along the extension direction of the channel layer 40 is 5% to 50% of the width of the channel layer 40.

[0056] As an example, the sidewall of the bottom trench 70 is recessed by 1 nanometer to 5 nanometers relative to the sidewall of the same side of the channel layer 40 along the extension direction of the channel layer 40. For example, the sidewall of the bottom trench 70 is recessed by 2 nanometers, 3 nanometers, 4 nanometers, etc. relative to the sidewall of the same side of the channel layer 40 along the extension direction of the channel layer 40.

[0057] The gate structure 300 serves as a device gate structure for controlling the opening and closing of the conductive channel.

[0058] In the gate structure 300, the gate dielectric layer 310 is located at the bottom and sidewall of the bottom trench 70.

[0059] In the embodiment, the sidewall of the gate dielectric layer 310 on the sidewall of the bottom trench 70 is separated, and the gate electrode layer 320 is also filled in the bottom trench 70 in which the gate dielectric layer 310 is formed. The gate dielectric layer 310 does not fill the bottom trench 70, so that the gate electrode layer 320 is also filled in the bottom trench 70. Since the gate dielectric layer 310 is on the sidewall of the bottom trench 70, the width of the gate electrode layer 320 in the bottom trench 70 is small, and the effective width of the parasitic channel in the protrusion 120 under the bottom trench 70 is also small, which is beneficial to reduce the leakage current in the parasitic channel.

[0060] In particular, in the embodiment, during the formation of the semiconductor structure, before the isolation structure 150 is formed, the sidewall of the sacrificial layer 30 is thinned along the direction perpendicular to the extension direction of the channel layer 40. Correspondingly, the width of the bottom trench 70 formed along the direction perpendicular to the extension direction of the channel layer 40 is smaller, so that the width of the gate electrode layer 320 formed in the bottom trench 70 is smaller, and the effective width of the parasitic channel in the protrusion 120 under the bottom trench 70 is also smaller, which is beneficial to significantly reduce the leakage current in the parasitic channel.

[0061] In the embodiment, the gate electrode layer 320 is filled at least in the gate opening 210, the top trench 80 and the second through trench 42.

[0062] The gate dielectric layer 310 is used to realize the electrical isolation between the gate electrode layer 320 and the channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0063] The gate electrode layer 320 is used as an external electrode for electrical connection between the gate structure 300 and an external circuit. The material of the gate electrode layer includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0064] In the embodiment, the gate structure 300 is a metal gate structure. Correspondingly, the gate dielectric layer 310 includes a high-k gate dielectric layer, and the gate electrode layer 320 is a metal gate electrode layer.

[0065] The high-k gate dielectric layer is made of a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, or Al2O3. In specific implementations, based on actual process requirements, the gate dielectric layer 310 may further include a gate oxide layer (not shown) located below the high-k gate dielectric layer. The material of the gate oxide layer can be silicon oxide or nitrogen-doped silicon oxide.

[0066] In this embodiment, the gate dielectric layer 310 is also located between the gate electrode layer 320 and the top surface of the isolation structure 150.

[0067] In a specific implementation, the gate electrode layer 320 may include a work function layer (not shown) and a metal electrode layer located on the work function layer. The work function layer is used to adjust the work function of the gate structure 300, thereby adjusting the threshold voltage of the field-effect transistor.

[0068] In this embodiment, a metal gate structure 300 is used as an example for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as polycrystalline silicon gate structures or amorphous silicon gate structures.

[0069] In this embodiment, there are multiple channel layers 40; the gate structure 300 at least fills the bottom trench 70, the space between the bottom trench 70 and the channel layer 40 adjacent to the protrusion 120, and the space between adjacent channel layers 40.

[0070] The portion of the gate structure 300 spanning the channel structure layer 200 is used as a first portion 300 (1); the portion of the gate structure 300 located within the bottom trench 70, above the top of the bottom trench 70, and between the channel layer 40 adjacent to the protrusion 120 is used as a second portion 300 (2); or, the portion of the gate structure 300 located within the bottom trench 70, above the top of the bottom trench 70, between the channel layer 40 adjacent to the protrusion 120, and between adjacent channel layers 40 is used as a second portion 300 (2).

[0071] In this embodiment, along the extension direction of the channel layer 40, the end of the first portion 300 (1) is recessed relative to the end on the same side of the channel layer 40 to provide space for the gate sidewall 165.

[0072] Accordingly, in this embodiment, the semiconductor structure further includes a gate sidewall 165 located on the sidewall of the first portion 300 (1), the gate sidewall 165 also spanning the channel structure layer 200 of the portion.

[0073] The gate sidewall 165 is used to define the forming position of the source-drain doped layer 170, and is also used to protect the sidewall of the gate structure 300.

[0074] In this embodiment, the material of the gate sidewall 165 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the gate sidewall 165 is a single layer or a stacked structure. As an example, the gate sidewall 165 is a single layer structure, and the material of the gate sidewall 165 is silicon nitride.

[0075] In this embodiment, the semiconductor structure further includes a dummy gate oxide layer 50 between the gate sidewall 165 and the channel structure layer 200. The material of the dummy gate oxide layer 50 is silicon oxide or silicon oxynitride.

[0076] In this embodiment, along the extension direction of the channel layer 40, the end of the second part 300(2) is recessed relative to the end of the same side of the channel layer 40, so as to provide a spatial position for the inner sidewall 180.

[0077] Correspondingly, in this embodiment, the semiconductor structure further includes an inner sidewall 180 between the second part 300(2) and the source-drain doped layer 170 along the extension direction of the channel layer 40.

[0078] The inner sidewall 180 is used to isolate the source-drain doped layer 170 from the gate structure 300, and is also used to increase the distance between the source-drain doped layer 170 and the gate structure 300, so as to reduce the parasitic capacitance between the gate structure 300 and the source-drain doped layer 170.

[0079] Correspondingly, in this embodiment, the source-drain doped layer 170 covers the sidewall of the channel structure layer 200 and the inner sidewall 180.

[0080] In this embodiment, the material of the inner sidewall 180 is an insulating material, so as to isolate the source-drain doped layer 170 from the gate structure 300. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material. As an example, the material of the inner sidewall 180 is silicon nitride.

[0081] The source-drain doped layer 170 is used as the source or the drain of the field effect transistor, and is used to provide a carrier source when the field effect transistor is working.

[0082] The source-drain doped layer 170 is located on and in contact with the protrusion 120. The source-drain doped layer 170 is usually formed by an epitaxial process. Compared with a solution of reducing the leakage current by arranging an isolation material between the source-drain doped layer and the protrusion 120, the source-drain doped layer 170 in the embodiment is located on and in contact with the protrusion 120 on both sides of the gate structure 300, which is beneficial to guarantee the epitaxial growth quality of the source-drain doped layer 170.

[0083] In the embodiment, the source-drain doped layer 170 comprises a stress layer doped with ions, and the stress layer is used to provide stress for the channel region, thereby improving the mobility of the carriers.

[0084] In the embodiment, when the PMOS transistor is formed, the source-drain doped layer 170 comprises a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when the NMOS transistor is formed, the source-drain doped layer 170 comprises a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0085] In the embodiment, the top surface of the isolation structure 150 is higher than the top surface of the protrusion 120, and the source-drain doped layer 170 is in contact with the protrusion 120 on both sides of the gate structure 300, and the isolation structure 150 also covers part of the sidewall of the source-drain doped layer 170.

[0086] In the embodiment, the semiconductor structure further comprises an interlayer dielectric layer 190 located on the isolation structure 150 on the side of the gate structure 300 and covering the source-drain doped layer 170.

[0087] The interlayer dielectric layer 190 is used to isolate adjacent devices. In the embodiment, the material of the interlayer dielectric layer 190 is silicon oxide. The material of the interlayer dielectric layer 190 can also be other insulating materials.

[0088] Figures 5-6 is a structural schematic diagram of another embodiment of the semiconductor structure of the present application. In the embodiment, Figure 5 is a sectional view along a direction perpendicular to the extension direction of the channel layer at the position of the channel layer, Figure 6 is a sectional view along the A-A1 direction. Figure 5 is a sectional view along the A-A1 direction.

[0089] The same parts of the embodiment and the foregoing embodiments will not be described here. The difference between the embodiment and the foregoing embodiments is that the bottom trench 70a is filled with the gate dielectric layer 310a. Specifically, the gate dielectric layer 310a located on the sidewall of the bottom trench 70a is in contact with each other to fill the bottom trench 70a.

[0090] In the embodiment, the gate dielectric layer 310a on the sidewall of the bottom trench 70a is in contact, thus the gate dielectric layer 310a fills the bottom trench 70a, thereby increasing the distance d between the gate electrode layer 320a and the protrusion 120a under the bottom trench 70a, i.e. the parasitic gate dielectric layer of the parasitic device composed of the gate electrode layer 320a, the protrusion 120a under the bottom trench 70a and the source / drain doped layer 170a is thicker, correspondingly increasing the difficulty of opening the parasitic device, which is beneficial to reduce the leakage current in the parasitic channel and optimize the performance of the semiconductor structure.

[0091] Specifically, in the actual process, when the thickness of the gate dielectric layer 310a on the single sidewall of the bottom trench 70a is greater than or equal to the width of the bottom trench 70a along the direction perpendicular to the channel layer 40a, the gate dielectric layer 310a can fill the bottom trench 70a.

[0092] For the specific description of the semiconductor structure of the embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0093] Correspondingly, the application also provides a transistor. With reference to Figure 3 and Figure 4 , a structure schematic diagram of an embodiment of the transistor of the application is shown.

[0094] As Figure 3 and Figure 4As shown, in the embodiment, the transistor comprises: a semiconductor substrate 110, wherein a plurality of discrete protrusions 120 are formed on the semiconductor substrate 110; an isolation structure 150, which is located on the semiconductor substrate 110 and covers sidewalls and part of top surfaces of the protrusions 120; a channel structure layer 200, which is located above the protrusions 120 and is spaced apart from the protrusions 120 and the isolation structure 150, and the channel structure layer 200 comprises one or more channel layers 40 which are sequentially and spaced apart; a bottom trench 70, which is surrounded by the isolation structure 150 and the protrusions 120, and the bottom trench 70 exposes part of the sidewalls of the isolation structure 150; a gate structure 300, which is located on the isolation structure 150 and the protrusions 120, the gate structure 300 spans the channel structure layer 200, surrounds the channel layer 40 and fills the bottom trench 70; the gate structure 300 comprises a gate dielectric layer 310 which surrounds surfaces of the channel layer 40 and is located at the bottom and sidewalls of the isolation structure 150, and a gate electrode layer 320 which is located on the gate dielectric layer 310; a gate sidewall 165, which is located on both sides of the gate structure 300 and exposes end portions of the channel structure layer 200 in the extending direction; and a source / drain doped layer 170, which is located on the protrusions 120 on both sides of the gate structure 300 and the gate sidewall 165 and contacts the end portions of the channel structure layer 200.

[0095] In the embodiment, the transistor can comprise one or more of PMOS transistors and NMOS transistors.

[0096] In the transistor, the isolation structure 150 is located on the semiconductor substrate 110 and covers sidewalls and part of top surfaces of the protrusions 120; the channel structure layer 200 is located above the protrusions 120 and is spaced apart from the protrusions 120 and the isolation structure 150; the bottom trench 70 is surrounded by the isolation structure 150 and the protrusions 120, and the bottom trench 70 exposes part of the sidewalls of the isolation structure 150; the gate structure 300 fills the bottom trench 70, and the gate dielectric layer 310 is also located at the bottom and sidewalls of the isolation structure 150.

[0097] When the sidewalls of the gate dielectric layer 310 located at the sidewalls of the isolation structure 150 are separated from each other, the gate dielectric layer 310 does not fill the bottom trench 70, so that when the gate electrode layer 320 also fills the bottom trench 70, the width of the gate electrode layer 320 located in the bottom trench 70 is small due to the gate dielectric layer 310 located at the sidewalls of the bottom trench 70, and the effective width of the parasitic channel in the protrusion 120 below the bottom trench 70 is correspondingly small, thereby reducing the leakage current in the parasitic channel; when the sidewalls of the gate dielectric layer 310 located at the sidewalls of the isolation structure 150 are in contact, so that the gate dielectric layer 310 fills the bottom trench 70, the distance between the gate electrode layer 320 and the protrusion 120 below the bottom trench 70 can be increased, that is, the parasitic gate dielectric layer 310 of the parasitic device composed of the gate electrode layer 320, the protrusion 120 below the bottom trench 70, and the source / drain doped layer 170 is thick, which correspondingly increases the difficulty of opening the parasitic device, and is beneficial to reducing the leakage current in the parasitic channel; and the source / drain doped layer 170 is in contact with the protrusion 120. The source / drain doped layer 170 is usually formed by epitaxy process. Compared with the scheme of reducing the leakage current by setting an isolation material between the source / drain doped layer and the protrusion, the present embodiment is beneficial to ensuring the epitaxial growth quality of the source / drain doped layer 170.

[0098] In summary, the present embodiment is beneficial to reducing the leakage current of the device, improving the process compatibility and the film forming quality of the source / drain doped layer, and optimizing the performance of the transistor.

[0099] The material of the semiconductor substrate 110 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0100] The material of the protrusion 120 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0101] The material of the channel layer 40 includes one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0102] The material of the isolation structure 150 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and germanium silicon oxide.

[0103] The gate dielectric layer 310 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0104] The material of the gate electrode layer 320 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

[0105] It should be noted that the transistor can further include a back-end-of-line (BEOL) structure (not shown) to realize electrical connection between the gate structure 300, the source / drain doped layer 170 and an external circuit.

[0106] For the detailed description of the transistor in the present embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0107] Correspondingly, the present application further provides a forming method of a semiconductor structure. Figures 7-28 FIG. 1 is a structural schematic diagram of the semiconductor structure corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application.

[0108] The forming method of the semiconductor structure in the present embodiment will be described in detail below with reference to the accompanying drawings.

[0109] Reference Figure 7 and Figure 8 , Figure 7 FIG. 1 is a cross-sectional view along a direction perpendicular to the extension direction of the channel stack at the position of the channel stack, Figure 8 is Figure 7 FIG. 1 is a cross-sectional view along a direction perpendicular to the extension direction of the channel stack at the position of the channel stack,

[0110] The semiconductor substrate 110 is used to provide a process platform for subsequent processes.

[0111] In the present embodiment, the forming of a gate-all-around (GAA) transistor is taken as an example for description. In other embodiments, the forming method can also be used to form a fork sheet transistor (Forksheet) or a complementary field effect transistor (CFET).

[0112] In the present embodiment, the semiconductor substrate 110 is a silicon substrate, i.e., the material of the semiconductor substrate 110 is monocrystalline silicon. In other embodiments, the material of the semiconductor substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium arsenide, and the semiconductor substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of semiconductor substrate.

[0113] In the embodiment, the protruding portion 120 is in an integral structure with the semiconductor substrate 110, and the material of the protruding portion 120 is the same as that of the semiconductor substrate 110, both of which are silicon. In other embodiments, the material of the protruding portion can be different from that of the semiconductor substrate, and the material of the protruding portion can be other suitable materials, such as one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

[0114] The channel stack 130 provides a process basis for the subsequent formation of the channel layer 40 in a suspended spaced arrangement. Specifically, the channel layer 40 is used to provide a conductive channel of a field effect transistor, and the sacrificial layer 30 is used to support the channel layer 40, thereby providing a process basis for the subsequent implementation of the suspended spaced arrangement of the channel layer 40, and the sacrificial layer 30 is also used to occupy a space position for the subsequent formation of a gate structure.

[0115] In the embodiment, the channel stack 130 is located on the protruding portion 120.

[0116] As an example, the sidewall of the one or more stacked channel stacks 130 and the protruding portion 120 is flush, and the one or more channel stacks 130 and the protruding portion 120 are in a fin structure.

[0117] As an embodiment, an NMOS transistor is formed, the material of the channel layer 40 is Si, and the material of the sacrificial layer 30 is SiGe. In the subsequent process of removing the sacrificial layer 30, the etching selectivity of SiGe and Si is relatively high, so by setting the material of the sacrificial layer 30 as SiGe and the material of the channel layer 40 as Si, the influence of the removal process of the sacrificial layer 30 on the channel layer 40 can be effectively reduced, thereby improving the quality of the channel layer 40 and further improving the device performance. In other embodiments, when a PMOS transistor is formed, in order to improve the performance of the PMOS transistor, a SiGe channel technology can be used, the material of the channel layer is SiGe, and the material of the sacrificial layer is Si. In other embodiments, the material of the channel layer can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

[0118] As an example, the number of channel stacks 130 is multiple, and the stacking direction of the multiple channel stacks 130 is perpendicular to the surface of the semiconductor substrate 110.

[0119] Specifically, in the embodiment, the number of channel stacks 130 is three. In other embodiments, the number of channel stacks can also be one, two, four, etc.

[0120] It should be noted that the subsequent steps further include: forming an isolation structure on the semiconductor substrate exposed by the channel stack 130, the isolation structure also covering the part of the side wall of the sacrificial layer 40 in contact with the protruding portion 120; removing the sacrificial layer 30 in the channel stack 130 to form a through slot, the through slot including a first through slot surrounded by the protruding portion 120 and the channel layer 40 adjacent to the protruding portion 120; the first through slot includes a bottom groove surrounded by the isolation structure and the protruding portion 120, and a top groove located on the bottom groove and in communication with the bottom groove; in the subsequent process of forming a gate structure, the gate dielectric layer in the gate structure is also formed on the side wall and bottom of the bottom groove, and the gate electrode layer on the gate dielectric layer needs to be filled at least in the top groove.

[0121] The height of the first through slot is defined by the thickness of the sacrificial layer 30 in contact with the protruding portion 120, therefore, in order to prevent the height of the subsequent top groove from being too small to facilitate the filling of the subsequent gate electrode layer in the top groove, the thickness of the sacrificial layer 30 in contact with the protruding portion 120 can be appropriately increased in the step of forming the channel stack 130.

[0122] As an embodiment, the step of providing the semiconductor substrate 110 includes: providing a semiconductor layer (not shown in the figure) and one or more channel stack materials (not shown in the figure) sequentially stacked on the semiconductor layer, the channel stack material including an initial sacrificial layer and an initial channel layer on the initial sacrificial layer; forming a hard mask layer 135 on the channel stack material; patterning the channel stack material and part of the thickness of the semiconductor layer with the hard mask layer 135 as a mask, to form a semiconductor substrate 110, a protruding portion 120 protruding from the semiconductor substrate 110, and one or more channel stacks 130 sequentially stacked on the protruding structure.

[0123] The hard mask layer 135 is used as a patterning mask for forming the channel stack 130, and the hard mask layer 135 on the top of the channel stack 135 is retained after the channel stack 130 is formed.

[0124] In this embodiment, the material of the hard mask layer 135 is silicon nitride.

[0125] Reference Figure 9 , shows a cross-sectional view along the direction perpendicular to the extension direction of the channel layer, in this embodiment, the method for forming the semiconductor structure further includes: after the semiconductor substrate 110 is provided, the side wall of the sacrificial layer 30 is thinned along the direction perpendicular to the extension direction of the channel layer 40.

[0126] Subsequently, a dummy gate structure is formed across the channel stack 130; then the dummy gate structure is removed to form a gate opening, and the sacrificial layer 30 in the channel stack 130 is removed to form a via, which is in communication with the gate opening, the via including a first via surrounded by the protrusion 120 and the channel layer 40 adjacent to the protrusion 120, the first via including a bottom trench surrounded by the isolation structure and the protrusion 120 and a top trench on the bottom trench.

[0127] By thinning the sidewall of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40, the width of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40 is reduced, and in the subsequent step of removing the sacrificial layer 30 to form the via, the width of the bottom trench along the extension direction perpendicular to the channel layer 40 is correspondingly reduced, which is beneficial to prevent the subsequent gate electrode layer from being formed in the bottom trench or to reduce the width of the gate electrode layer formed in the bottom trench. At the same time, since the top trench or a second via above the first via is in communication with the gate opening, the width of the gate electrode layer formed in the top trench or the second via is not affected. In addition, by thinning the sidewall of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40, the size of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40 is not affected, and the length of the gate structure subsequently formed in the top trench or the second via is correspondingly ensured, so that the effective channel length of the device meets the design requirements.

[0128] It should be noted that the width of the thinning of the sidewall of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40 should not be too small or too large. If the width of the thinning of the sidewall of the sacrificial layer 30 is too small, the reduction of the width of the subsequent bottom trench is not obvious. If the width of the thinning of the sidewall of the sacrificial layer 30 is too large, the width of the remaining sacrificial layer 30 is too small, which correspondingly reduces the support strength of the sacrificial layer 30 to the channel layer 40, and thus increases the risk of tilting or collapse of the channel stack 130. Therefore, in the present embodiment, the thinning width t of the single-sided sidewall of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40 is 5% to 50% of the width of the channel layer 40.

[0129] As an example, the thinning width t of the single-sided sidewall of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40 can be 1 nanometer to 5 nanometers. For example, the thinning width t of the single-sided sidewall of the sacrificial layer 30 along the extension direction perpendicular to the channel layer 40 can be 2 nanometers, 3 nanometers, 4 nanometers, etc.

[0130] In the embodiment, the isotropic etching process is used to thin the sidewall of the sacrificial layer 30 along the direction perpendicular to the extending direction of the channel layer 40. The isotropic etching process has the characteristic of isotropic etching, so that the sidewall of the sacrificial layer 30 can be etched along the direction perpendicular to the extending direction of the channel layer 40.

[0131] As an embodiment, the isotropic etching process is a vapor etching process. The vapor etching process is easy to achieve a large etching selectivity, which is beneficial to reduce the difficulty of etching the sacrificial layer 30 and reduce the probability of damaging other film structures (for example, the channel layer 40).

[0132] In the embodiment, the material of the sacrificial layer 30 is SiGe, the material of the channel layer 40 is Si, and the sidewall of the sacrificial layer 30 is etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much greater than that on Si material, which can effectively reduce the probability of damaging the channel layer 40.

[0133] In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, an isotropic dry etching process can be used to etch the sidewall of the sacrificial layer along the direction perpendicular to the extending direction of the channel layer.

[0134] Reference Figures 10-13 An isolation structure 150 is formed on the semiconductor substrate 110 exposed by the channel stack 130, and the isolation structure 150 also covers part of the sidewall of the sacrificial layer 40 in contact with the protruding part 120.

[0135] The isolation structure 150 is used to isolate adjacent devices.

[0136] In the embodiment, the isolation structure 150 also covers part of the sidewall of the sacrificial layer 40 in contact with the semiconductor substrate 110, so that in the subsequent step of removing the sacrificial layer 30 to form a through slot, the through slot includes a first through slot surrounded by the protruding part 120 and the channel layer 40 adjacent to the protruding part 120, and the first through slot corresponds to a bottom groove surrounded by the isolation structure 150 and the protruding part 120.

[0137] Correspondingly, in the subsequent step of forming a gate structure, a gate dielectric layer can be formed at the bottom and sidewall of the bottom groove, which can correspondingly reduce the width of the gate electrode layer formed in the bottom groove, or even make the gate electrode layer unable to be formed in the bottom groove, so as to reduce the effective width of the parasitic channel in the protruding part 120 below the bottom groove, or increase the distance between the gate electrode layer and the protruding part 120 below the bottom groove, thereby facilitating to increase the difficulty of opening the parasitic device and effectively reducing the leakage current in the parasitic channel.

[0138] And, the embodiment only adjusts the forming height of the isolation structure 150 so as to form a bottom trench subsequently, thereby reducing the leakage current of the device, and the modification to the existing process is small, which is beneficial to simplify the process and improve the process compatibility.

[0139] In the embodiment, the material of the isolation structure 150 is silicon oxide. The isolation structure 150 can also be other suitable insulating materials, for example, one or more of silicon nitride, silicon oxynitride and germanium silicon oxide.

[0140] In the embodiment, the isolation structure 150 is filled in the area surrounded by the convex part 120 and the semiconductor substrate 100, and the top of the isolation structure 150 is higher than the top of the convex part 120 and lower than the top of the sacrificial layer 30 in contact with the semiconductor substrate 110.

[0141] In the embodiment, the sacrificial layer 30 also exposes part of the top surface of the convex part 120, and correspondingly, the isolation structure 150 covers part of the top surface of the convex part 120.

[0142] It should be noted that the height h of the side wall of the sacrificial layer 30 covered by the isolation structure 150 should not be too small or too large in proportion to the total height of the side wall of the sacrificial layer 30 in contact with the convex part 120. If the proportion is too small, the process difficulty is easily increased; if the proportion is too large, the exposed side wall height of the sacrificial layer 30 in contact with the convex part 120 is easily too small, and the exposed part of the sacrificial layer 30 in contact with the convex part 120 is used to occupy the space position for forming the top trench, after the sacrificial layer 30 is removed to form the through trench, the filling difficulty of the gate structure in the top trench is easily large. Therefore, in the embodiment, the height h of the side wall of the sacrificial layer 30 covered by the isolation structure 150 is 10% to 80% in proportion to the total height of the side wall of the sacrificial layer 150 in contact with the sacrificial layer 150.

[0143] The specific steps of forming the isolation structure 150 in the embodiment will be described in detail below with reference to the accompanying drawings.

[0144] As shown in FIG. 1, Figures 10-11 As shown in FIG. 1, Figure 10 is a cross-sectional view along the direction perpendicular to the channel layer extending direction at the position of the channel stack 130, Figure 11 is Figure 10 is a cross-sectional view along the A-A1 direction, and the isolation material layer 140 is formed on the semiconductor substrate 110 at the side of the channel stack 130, and the isolation material layer 140 covers the top of the hard mask layer 135.

[0145] As one embodiment, the process for forming the isolation material layer 140 includes a flow-through chemical vapor deposition process. The flow-through chemical vapor deposition process has strong filling capacity, which is beneficial for improving the filling quality of the isolation material layer 140 between the channel stacks 130.

[0146] like Figures 12-13 As shown, Figure 12 For based on Figure 10 Cross-sectional view, Figure 13 for Figure 12 A cross-sectional view along the A-A1 direction, with a portion of the thickness of the insulating material layer 140 removed, exposes a portion of the sidewall of the sacrificial layer 30 in contact with the protrusion 120, as well as the channel layer 40 and the remaining sacrificial layer 30 on the sacrificial layer 30 in contact with the protrusion 120.

[0147] Specifically, in this embodiment, by adjusting the removal thickness of the isolation material layer 140, the isolation structure 150 also covers part of the sidewall of the sacrificial layer 30 that is in contact with the protrusion 120, thereby enabling compatibility with the process of forming the isolation structure 150, improving process integration and process compatibility, and also helping to save costs and reduce process risks.

[0148] The step of removing a portion of the thickness of the isolation material layer 140 may include: using a planarization process to remove a portion of the thickness of the isolation material layer 140; and after the planarization process, using an etching process to etch away the portion of the thickness of the isolation material layer 140.

[0149] Specifically, the planarization process can be a chemical mechanical planarization process; the etching process can be one or both of dry etching and wet etching processes.

[0150] refer to Figures 14-17 A dummy gate structure 160 is formed on the isolation structure 150, spanning the channel stack 130. The dummy gate structure 160 is used to pre-reserve space for the subsequent formation of the gate structure.

[0151] The pseudo-gate structure 160 covers a portion of the top and a portion of the sidewalls of the channel stack 130, and the extension direction of the pseudo-gate structure 160 is perpendicular to the extension direction of the channel stack 130.

[0152] The dummy gate structure 160 can be a stacked structure or a single-layer structure. In this embodiment, the dummy gate structure 160 is a stacked structure, including a dummy gate oxide layer 50 and a dummy gate layer 60 located on the dummy gate oxide layer 50. Specifically, the dummy gate structure 160 is a polysilicon gate structure, the material of the dummy gate oxide layer 50 can be silicon oxide or silicon oxynitride, and the material of the dummy gate layer 60 can be polysilicon.

[0153] In this embodiment, the step of forming the dummy gate structure 160 includes:

[0154] As shown in Figure 14 and Figure 15 , the cross-sectional view along the direction perpendicular to the extending direction of the channel stack is shown in Figure 14 , and the cross-sectional view along the A-A1 direction is shown in Figure 15 . Figure 14 The top part of the channel stack 130 is exposed by removing the hard mask layer 135, so that the subsequently formed dummy gate structure can cross the channel stack 130.

[0155] As shown in Figure 16 and Figure 17 , the top surface and the sidewall of the channel stack 130 exposed by the isolation structure 150 form a dummy gate oxide layer 50.

[0156] As shown in Figure 16 and Figure 17 , the cross-sectional view along the direction perpendicular to the extending direction of the channel stack is shown in Figure 16 , and the cross-sectional view along the A-A1 direction is shown in Figure 17 . Figure 16 The dummy gate layer 60 is formed on the dummy gate oxide layer 50, covering the dummy gate oxide layer 50 located at the partial top and partial sidewall of the channel stack 130.

[0157] In this embodiment, after the formation of the dummy gate structure 160, the forming method further includes: forming a gate sidewall 165 on the sidewall of the dummy gate structure 160. The gate sidewall 165 is used as an etching mask for the subsequent etching process of forming a recess, to define the formation position of the source / drain doped layer, and the gate sidewall 165 is also used to protect the sidewall of the dummy gate structure 160 and the subsequent gate structure.

[0158] In this embodiment, the material of the gate sidewall 165 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material, and the gate sidewall 165 is a single layer or a stacked structure. As an example, the gate sidewall 165 is a single layer structure, and the material of the gate sidewall 165 is silicon nitride.

[0159] Referring to Figures 18-21 , the source / drain doped layer 170 is formed in the channel stack 130 on both sides of the dummy gate structure 160, and is in contact with the protrusion 120.

[0160] The source / drain doped layer 170 is used as the source or the drain of the field effect transistor, and provides a carrier source when the field effect transistor is working.

[0161] In this embodiment, the source / drain doped layer 170 is formed in the channel stack 130 on both sides of the pseudo-gate structure 160 and the gate sidewall 165.

[0162] The source / drain doped layer 170 is typically formed by an epitaxial process. Compared with the solution of reducing leakage current by placing an isolation material between the source / drain doped layer and the protrusion, in this embodiment, the source / drain doped layer 170 is formed on the protrusions 120 on both sides of the gate structure 300 and is in contact with the protrusions 120. This has little impact on the process of forming the source / drain doped layer 170, which is beneficial to improving process compatibility and ensuring the epitaxial growth quality of the source / drain doped layer 170.

[0163] In this embodiment, the source / drain doped layer 170 includes a stress layer doped with ions. The stress layer is used to provide stress to the channel region, thereby improving the carrier mobility.

[0164] In this embodiment, when forming a PMOS transistor, the source / drain doped layer 170 includes a stress layer doped with P-type ions, and the material of the stress layer is Si or SiGe; when forming an NMOS transistor, the source / drain doped layer 170 includes a stress layer doped with N-type ions, and the material of the stress layer is Si or SiC.

[0165] In this embodiment, the step of forming the source / drain doped layer 170 includes:

[0166] like Figure 18 The diagram shows a cross-sectional view along the channel layer extension direction at the location of channel stack 130. The channel stack 130 on both sides of the dummy gate structure 160 is removed to form a groove 155, the bottom of which exposes the protrusion 120. The groove 155 provides space for the formation of source / drain doped layers.

[0167] The bottom of the groove 155 exposes the protrusion 120, so that in the subsequent epitaxial process, the protrusion 120 at the bottom of the groove 155 can be used as a basis for epitaxial growth, which helps to ensure the quality of epitaxial growth.

[0168] In this embodiment, since the isolation structure 150 also covers part of the sidewall of the sacrificial layer 30 that is in contact with the protrusion 120, after removing the channel stack 130 on both sides of the pseudo-gate structure 160 to form the groove 155, part of the groove 155 is still located in the isolation structure 150.

[0169] like Figure 21 As shown, the source / drain doped layer 170 is formed in the groove 155.

[0170] In this embodiment, an epitaxial process is used to form the source / drain doped layer 170 in the groove 155.

[0171] Specifically, in this embodiment, the protruding part 120 at the bottom of the groove 155 and the channel layer 40 at the sidewall of the groove 155 are used as the basis for epitaxial process, which is conducive to ensuring the quality of epitaxial growth and reducing defects in the source-drain doped layer 170.

[0172] In this embodiment, part of the groove 155 is also located in the isolation structure 170, so that after the source-drain doped layer 170 is formed in the groove 155, the isolation structure 170 also covers part of the sidewall of the isolation structure 170.

[0173] It should be noted that in this embodiment, the method for forming the semiconductor structure further comprises:

[0174] As shown in Figure 19 After the groove 155 is formed and before the source-drain doped layer is formed in the groove 155, part of the thickness of the sacrificial layer 30 at the sidewall of the groove 155 is etched along the extension direction of the channel layer to form a sidewall groove 175 at the sidewall of the groove 155.

[0175] The sidewall groove 175 is used to provide a spatial position for forming the inner sidewall 180.

[0176] In this embodiment, a vapor etching process is used to etch part of the thickness of the sacrificial layer 30 at the sidewall of the groove 155 along the extension direction of the channel layer.

[0177] Specifically, in this embodiment, the material of the sacrificial layer 30 is SiGe, and the material of the channel layer 40 is Si. The sacrificial layer 30 at the sidewall of the groove 155 is etched by HCl vapor. The etching rate of HCl vapor on SiGe material is much higher than that on Si material, which can effectively reduce the probability of damage to the channel layer 40.

[0178] In other embodiments, when the material of the channel layer is SiGe and the material of the sacrificial layer is Si, a dry etching process can be used to etch part of the thickness of the sacrificial layer at the sidewall of the groove along the extension direction of the channel layer.

[0179] As shown in Figure 20 The inner sidewall 180 is filled in the sidewall groove 175.

[0180] Subsequently, a gate structure is formed at the position of the sacrificial layer 30 and the dummy gate structure 160. The inner sidewall 180 is used to isolate the source-drain doped layer 170 from the gate structure and also to increase the distance between the source-drain doped layer 170 and the gate structure, so as to reduce the parasitic capacitance between the gate structure and the source-drain doped layer 170.

[0181] Accordingly, in this embodiment, the source / drain doped layer 170 covers the channel layer 40 and the inner sidewall 180.

[0182] In this embodiment, the inner sidewall 180 is made of an insulating material to achieve isolation between the source / drain doped layer 170 and the gate structure. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material, or an ultra-low-k dielectric material. As an example, the material of the inner sidewall 180 is silicon nitride.

[0183] refer to Figure 22 , for the basis Figure 21 The cross-sectional view shows that the method for forming the semiconductor structure further includes: after forming the source / drain doped layer 170, forming an interlayer dielectric layer 190 on the isolation structure 150 on the side of the dummy gate structure 160 to cover the source / drain doped layer 170.

[0184] The interlayer dielectric layer 190 is used to isolate adjacent devices and also to support the channel layer 40 during the subsequent removal of the dummy gate structure 160 and the sacrificial layer 30, thereby achieving a suspended space arrangement of the channel layer 40. In this embodiment, the material of the interlayer dielectric layer 190 is silicon oxide. The material of the interlayer dielectric layer 190 can also be other insulating materials.

[0185] In this embodiment, the interlayer dielectric layer 190 also exposes the top of the dummy gate structure 160 to facilitate subsequent removal of the dummy gate structure 160.

[0186] refer to Figure 23 and Figure 24 , Figure 23 It is a cross-sectional view at the location of the channel layer stack along the direction perpendicular to the extension of the channel layer. Figure 24 yes Figure 23 A cross-sectional view along the A-A1 direction shows the removal of the pseudo-gate structure 160, forming a gate opening 210, which exposes the channel stack 130.

[0187] The gate opening 210 provides partial space for forming the gate structure. The gate opening 210 exposes the channel stack 130 to facilitate subsequent removal of the sacrificial layer 30 through the gate opening 210.

[0188] In this embodiment, the gate opening 210 spans the channel stack 130 and is located in the interlayer dielectric layer 190.

[0189] In this embodiment, the step of removing the dummy gate structure 160 includes: using the dummy gate oxide layer 50 as an etch stop layer, removing the dummy gate layer 60 to form an initial gate opening (not shown); and removing the dummy gate oxide layer 50 exposed by the initial gate opening.

[0190] The dummy gate oxide layer 50 can be used as an etching stop layer during the process of removing the dummy gate layer 60, thereby reducing the probability of damaging the channel layer 40 during the process of removing the dummy gate layer 60.

[0191] The dummy gate oxide layer 50 is thinner than the dummy gate layer 60, and thus the process of removing the dummy gate oxide layer 50 is simpler and shorter, and the dummy gate oxide layer 50 is less likely to be damaged during the process of removing the dummy gate oxide layer 50.

[0192] Reference Figures 25-26 , Figure 25 In the cross-sectional view along the direction perpendicular to the extension direction of the channel layer at the position of the channel layer, Figure 26 In the cross-sectional view along the direction perpendicular to the extension direction of the channel layer at the position of the channel layer, Figure 25 In the cross-sectional view along the direction A-A1, the sacrificial layer 30 in the channel stack 130 is removed to form a through slot 240, the through slot 240 includes a first through slot 41 surrounded by the protruding portion 120 and the channel layer 40 adjacent to the protruding portion 120, and the first through slot 41 includes a bottom groove 70 surrounded by the isolation structure 150 and the protruding portion 120, and a top groove 80 located on the bottom groove 70 and connected to the bottom groove 70.

[0193] The through slot 240 and the gate opening 210 jointly provide a spatial position for subsequently forming a gate structure. The through slot 240 is connected to the gate opening 210, so that after the gate structure is filled in the through slot 240 and the gate opening 210, the gate structure can surround the channel layer 40.

[0194] By making the first through slot 41 include the bottom groove 70 surrounded by the isolation structure 150 and the protruding portion 120, correspondingly, in the subsequent step of forming the gate structure, the gate dielectric layer can be formed on the bottom and the sidewall of the bottom groove 70, thereby reducing the width of the gate electrode layer formed in the bottom groove 70, or even making the gate electrode layer unable to be formed in the bottom groove 70, which is beneficial to reduce the effective width of the parasitic channel in the protruding portion 120 below the bottom groove 70, or increase the distance between the gate electrode layer and the protruding portion 120 below the bottom groove 70, which is beneficial to increase the difficulty of turning on the parasitic device and reduce the leakage current in the parasitic channel.

[0195] In addition, in the embodiment, by adjusting the height of the isolation structure 150 so that the isolation structure 150 also covers part of the sidewall of the sacrificial layer 30 in contact with the protruding portion 120, the bottom groove 70 can be formed during the process of removing the sacrificial layer 30, that is, the bottom groove 70 is formed by the process of removing the sacrificial layer 30, which has little change to the existing process and is beneficial to simplify the process and improve the process compatibility.

[0196] In the embodiment, the number of the sacrifice layers 30 is multiple; therefore, in the step of removing the sacrifice layers 30 in the channel stack 130 to form the through-slots 240, the through-slots 240 also include a second through-slot 42 surrounded by the adjacent channel layers 40.

[0197] The sacrifice layers 30 are removed after forming the source-drain doped layers 170; therefore, after removing the sacrifice layers 30, the channel layers 40 are suspended in the gate openings 210 at both ends along the extension direction of the channel layers 40, and connected to the source-drain doped layers 170, so that the subsequent gate structure can surround the first channel layers 30.

[0198] In the embodiment, one or more of the channel layers 40 are used to form the channel structure layer 200 after removing the sacrifice layers 30, and the channel structure layer 200 is arranged above the protrusion 120 and spaced apart from the protrusion 120.

[0199] In the embodiment, the sacrifice layers 30 are removed by a vapor etching process. Specifically, the material of the channel layers 40 is Si, and the material of the sacrifice layers 30 is SiGe; therefore, the sacrifice layers 30 exposed in the gate openings 210 are removed by HCl vapor.

[0200] Reference is made to Figure 27 and Figure 28 , Figure 27 is a cross-sectional view along a direction perpendicular to the extension direction of the channel layers 40 at the position of the channel layers 40, Figure 28 is Figure 27 is a cross-sectional view along the A-A1 direction, the gate structure 300 is filled in the gate openings 210 and the through-slots 240, and the gate structure 300 includes a gate dielectric layer 310 surrounding the surface of the channel layers 40 and located at the bottom and sidewall of the bottom trench 70, and a gate electrode layer 320 located on the gate dielectric layer 310, and the gate electrode layer 320 is filled at least in the gate openings 210 and the top trench 80.

[0201] The gate structure 300 serves as a device gate structure for controlling the opening and closing of the conductive channel.

[0202] In the gate structure 300, the gate dielectric layer 310 is formed at the bottom and sidewall of the bottom trench 70.

[0203] In the embodiment, the sidewall of the gate dielectric layer 310 on the sidewall of the bottom trench 70 is separated, and the gate electrode layer 320 is also filled in the bottom trench 70 in which the gate dielectric layer 310 is formed. The gate dielectric layer 310 does not fill the bottom trench 70, so that the gate electrode layer 320 is also filled in the bottom trench 70. Since the gate dielectric layer 310 is on the sidewall of the bottom trench 70, the width of the gate electrode layer 320 in the bottom trench 70 is small, and the effective width of the parasitic channel in the protrusion 120 under the bottom trench 70 is also small, which is beneficial to reduce the leakage current in the parasitic channel.

[0204] In particular, in the embodiment, before the isolation structure 150 is formed, the sidewall of the sacrificial layer 30 is thinned in the direction perpendicular to the extension direction of the channel layer 40. Correspondingly, the width of the bottom trench 70 formed in the direction perpendicular to the extension direction of the channel layer 40 is smaller, so that the width of the gate electrode layer 320 formed in the bottom trench 70 is smaller, and the effective width of the parasitic channel in the protrusion 120 under the bottom trench 70 is also smaller, which is beneficial to significantly reduce the leakage current in the parasitic channel.

[0205] In the embodiment, the gate electrode layer 320 is filled at least in the gate opening 210, the top trench 80 and the second through trench 42.

[0206] The gate dielectric layer 310 is used to realize electrical isolation between the gate electrode layer 320 and the channel.

[0207] The material of the gate dielectric layer 310 includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0208] The gate electrode layer 320 is used as an external electrode for electrical connection between the gate structure 300 and an external circuit.

[0209] The material of the gate electrode layer 320 includes one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

[0210] In the embodiment, the gate structure 300 is a metal gate structure. Correspondingly, the gate dielectric layer 310 includes a high-k gate dielectric layer, and the gate electrode layer 320 is a metal gate electrode layer.

[0211] The material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In a specific implementation, based on actual process requirements, the gate dielectric layer 310 can further include a gate oxide layer (not shown in the figure) located below the high-k gate dielectric layer, and the material of the gate oxide layer can be silicon oxide or silicon oxynitride.

[0212] In this embodiment, the process of forming the gate dielectric layer 310 includes an atomic layer deposition process. The atomic layer deposition process has good gap filling capability and step coverage capability, which is beneficial to the formation of the gate dielectric layer 310 on the surface of the channel layer 40, the bottom and sidewall of the bottom trench 70, the top wall and sidewall of the top trench 80, and the inner surface of the second via 42, and is also beneficial to making the gate dielectric layer 310 thinner, so that the first via 41 and the second via 42 have sufficient space for forming the gate electrode layer 320.

[0213] In this embodiment, the gate dielectric layer 310 is also formed on the bottom and sidewall of the gate opening 210.

[0214] In a specific implementation, the gate electrode layer 320 can include a work function layer (not shown in the figure) and a metal electrode layer located on the work function layer, and the work function layer is used to adjust the work function of the gate structure 300, thereby adjusting the threshold voltage of the field effect transistor.

[0215] In this embodiment, the gate structure 300 is taken as an example of a metal gate structure for illustration. In other embodiments, based on actual process requirements, the gate structure can also be other types of gate structures, such as a polysilicon gate structure or an amorphous silicon gate structure.

[0216] The part of the gate structure 300 that crosses part of the channel structure layer 200 is used as a first part 300(1); the part of the gate structure 300 located between the first vias 41 is used as a second part 300(2), or the part of the gate structure 300 located between the first via 41 and the second via 42 is used as the second part 300(2).

[0217] Figures 29-30 is a structure diagram corresponding to another embodiment of the forming method of the semiconductor structure of the present application. Among them, Figure 29 is a cross-sectional view along a direction perpendicular to the channel layer at the position of the channel layer, Figure 30 is a cross-sectional view along a direction perpendicular to the channel layer at the position of the channel layer, Figure 29The sectional view along the direction of A-A1. The same as the previous embodiment, the different between the present embodiment and the previous embodiment is that in the step of forming the gate structure 300a, the gate dielectric layer 310a on the sidewall of the bottom trench 70a is in contact.

[0218] In the present embodiment, the gate dielectric layer 310a on the sidewall of the bottom trench 70a is in contact, and the gate dielectric layer 310a fills the bottom trench 70a, thereby increasing the distance d between the gate electrode layer 320a and the protrusion 120a below the bottom trench 70a, i.e. the parasitic gate dielectric layer of the parasitic device composed of the gate electrode layer 320a, the protrusion 120a below the bottom trench 70a and the source / drain doped layer 170a is thicker, which increases the difficulty of opening the parasitic device, and is beneficial to reduce the leakage current in the parasitic channel, and optimizes the performance of the semiconductor structure.

[0219] Specifically, in the actual process, when the thickness of the gate dielectric layer 310a on the single sidewall of the bottom trench 70a is greater than or equal to the width of the bottom trench 70a along the direction perpendicular to the channel layer 40a, the gate dielectric layer 310a can fill the bottom trench 70a.

[0220] The specific description of the forming method of the semiconductor structure of the present embodiment can refer to the corresponding description in the previous embodiment, which will not be repeated here.

[0221] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a semiconductor substrate having a plurality of discrete protrusions thereon; a channel structure layer located above and spaced apart from the protrusions, the channel structure layer comprising one or more channel layers arranged in sequence and spaced apart; an isolation structure located on the semiconductor substrate and surrounding the protrusions, the isolation structure having a top surface higher than a top surface of the protrusions and lower than a bottom surface of the channel structure layer; a bottom trench formed by the isolation structure and the protrusions, the bottom trench being located below the channel structure layer; wherein, along a direction perpendicular to an extension direction of the channel layers, sidewalls of the bottom trench are recessed relative to sidewalls of the channel layers on the same side; a gate structure located on the isolation structure and the protrusions, the gate structure spanning the channel structure layer and surrounding the channel layers and filling the bottom trench; the gate structure comprising a gate dielectric layer surrounding surfaces of the channel layers and located on bottom and sidewalls of the bottom trench, and a gate electrode layer located on the gate dielectric layer; gate sidewalls located on both sides of the gate structure and exposing end portions of the channel structure layer in the extension direction; source / drain doped layers located on the protrusions on both sides of the gate structure and the gate sidewalls and in contact with the end portions of the channel structure layer; wherein the source / drain doped layers are in contact with the protrusions.

2. The semiconductor structure of claim 1, wherein, The material of the semiconductor substrate comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium arsenide; The material of the protrusions comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium arsenide; The material of the channel layers comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium arsenide.

3. The semiconductor structure of claim 1, wherein, The material of the isolation structure comprises one or more of silicon oxide, silicon nitride, silicon oxynitride and germanium silicon oxide.

4. The semiconductor structure of claim 1, wherein, The bottom trench is filled by the gate dielectric layer; Alternatively, the gate electrode layer also fills the bottom trench formed with the gate dielectric layer.

5. The semiconductor structure of claim 1, wherein, The material of the gate dielectric layer comprises one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3; The material of the gate electrode layer comprises one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt and Ni.

6. The semiconductor structure of claim 1, wherein, The width of the sidewalls of the bottom trench recessed relative to the sidewalls of the channel layers on the same side, along a direction perpendicular to the extension direction of the channel layers, is 5% to 50% of the width of the channel layers.

7. The semiconductor structure of claim 1, wherein, The depth of the bottom trench is 10% to 80% of the distance between the substrate and the bottom wall of the channel layer adjacent to the substrate.

8. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises an interlayer dielectric layer located on the isolation structure on the side of the gate structure and covering the source / drain doped layers.

9. A transistor, characterized by Comprising: a semiconductor substrate having a plurality of discrete protrusions thereon; an isolation structure located on the semiconductor substrate and covering sidewalls and part of top surfaces of the protrusions; a channel structure layer located above the protrusions and spaced apart from the protrusions and the isolation structure, the channel structure layer comprising one or more channel layers spaced apart in sequence; a bottom trench enclosed by the isolation structure and the protrusions, the bottom trench exposing sidewalls of the isolation structure; a gate structure located on the isolation structure and the protrusions, the gate structure spanning the channel structure layer and surrounding the channel layers and filling the bottom trench; the gate structure comprising a gate dielectric layer surrounding surfaces of the channel layers and located on top surfaces of the protrusions and sidewalls and top surfaces of the isolation structure, and a gate electrode layer located on the gate dielectric layer; gate sidewalls located on both sides of the gate structure and exposing ends of the channel structure layer in a direction in which the channel structure layer extends; source / drain doped layers located on the protrusions on both sides of the gate structure and the gate sidewalls and in contact with the ends of the channel structure layer; wherein the source / drain doped layers are in contact with the protrusions.

10. The transistor of claim 9, wherein, The material of the semiconductor substrate comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. The material of the protrusions comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. The material of the channel layers comprises one or more of monocrystalline silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.

11. The transistor of claim 9, wherein, The material of the isolation structure comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, and germanium silicon oxide.

12. The transistor of claim 9, wherein, The gate dielectric layer comprises one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3. The material of the gate electrode layer comprises one or more of TiN, TaN, Ti, Ta, TiAL, TiALC, TiSiN, W, Co, Al, Cu, Ag, Au, Pt, and Ni.

13. A method of forming a semiconductor structure, comprising: The method comprises: providing a semiconductor substrate, the semiconductor substrate having a plurality of discrete protrusions formed thereon, and one or more channel stacks formed on the protrusions in sequence from bottom to top, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming an isolation structure on the semiconductor substrate exposed by the channel stacks, the isolation structure also covering part of the sidewalls of the sacrificial layer in contact with the protrusions; wherein the isolation structure covers sidewalls and part of top surfaces of the protrusions; forming a dummy gate structure spanning the channel stacks on the isolation structure; forming source / drain doped layers in the channel stacks on both sides of the dummy gate structure, the source / drain doped layers being in contact with the protrusions; removing the dummy gate structure to form a gate opening and expose the channel stacks; removing the sacrificial layers in the channel stacks to form through trenches, the through trenches comprising first through trenches enclosed by the protrusions and channel layers adjacent to the protrusions; wherein the first through trenches comprise bottom trenches enclosed by the isolation structure and the protrusions, and top trenches located on the bottom trenches and in communication with the bottom trenches; Filling a gate structure in the gate opening and the via, the gate structure comprising a gate dielectric layer surrounding surfaces of the channel layers and bottom and sidewalls of the bottom trench, and a gate electrode layer on the gate dielectric layer, the gate electrode layer filling at least the gate opening and the top trench.

14. The method of forming a semiconductor structure of claim 13, wherein, In the step of providing the substrate, the number of the channel layers is plural; In the step of removing the sacrificial layer in the channel layers to form the via, the via further comprises a second via surrounded by adjacent channel layers; In the step of forming the gate structure, the gate electrode layer fills at least the gate opening, the top trench and the second via.

15. The method of forming a semiconductor structure according to claim 13 or 14, wherein The gate dielectric layer on the sidewall of the bottom trench is in contact. Alternatively, the sidewall of the gate dielectric layer on the sidewall of the bottom trench is separated, and the gate electrode layer further fills the bottom trench where the gate dielectric layer is formed.

16. The method of forming a semiconductor structure of claim 13, wherein, The method further comprises, after the step of providing the substrate, before the step of forming the isolation structure, thinning the sidewall of the sacrificial layer along a direction perpendicular to the extension direction of the channel layers.

17. The method of forming a semiconductor structure of claim 13, wherein, The sidewall of the sacrificial layer is thinned along a direction perpendicular to the extension direction of the channel layers by using an isotropic etching process.

18. The method of forming a semiconductor structure of claim 13, wherein, The step of forming the source / drain doping layer comprises: removing the channel layers on both sides of the dummy gate structure to form a recess, the bottom of the recess exposing the protruding portion; and forming the source / drain doping layer in the recess. The method further comprises, after the step of forming the recess and before the step of forming the source / drain doping layer, etching a portion of the thickness of the sacrificial layer on the sidewall of the recess along the extension direction of the channel layers to form a sidewall trench on the sidewall of the recess; and filling an inner sidewall in the sidewall trench. In the step of forming the source / drain doping layer, the source / drain doping layer covers the channel layers and the inner sidewall.

19. The method of forming a semiconductor structure of claim 13, wherein, The method further comprises, after the step of forming the source / drain doping layer and before the step of removing the dummy gate structure, forming an interlayer dielectric layer on the isolation structure on the side of the dummy gate structure to cover the source / drain doping layer.

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