Magnetoelectric spin transistor, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a magnetoelectric spin transistor, a manufacturing method thereof and electronic equipment, relates to the technical field of spin transistors, and aims to enable a channel material to obtain enhanced spin-orbit coupling while keeping a long spin diffusion length. The magnetoelectric spin transistor comprises a laminated heterostructure, a source electrode, a drain electrode, a grid electrode and a grid dielectric layer. The laminated heterostructure comprises a magnetoelectric substrate layer and a channel layer which are arranged in sequence, and a strong spin orbit coupling material layer which is arranged between the channel layer and the magnetoelectric substrate layer or is arranged on one side, deviating from the magnetoelectric substrate layer, of the channel layer. The channel layer is in contact with the magnetoelectric substrate layer and the strong spin-orbit coupling material layer. The source electrode, the drain electrode and the grid electrode are arranged on the side, opposite to the magnetoelectric substrate layer, in the laminated heterostructure at intervals in the thickness direction perpendicular to the laminated heterostructure. The grid electrode is located between the source electrode and the drain electrode. And the channel layer is made of a weak spin-orbit coupling material.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of transistor technology, in particular to a magnetoelectric spin transistor, a manufacturing method thereof and an electronic device. BACKGROUND

[0002] The magnetoelectric spin transistor is an important research direction in the field of super-low power consumption spin electronics in the post-Moore era, aiming to control information storage and processing with an electric field (rather than energy-consuming current), so as to realize super-low power consumption calculation. Specifically, the core idea of the magnetoelectric spin transistor is to use voltage (electric field) to control the magnetization state (direction) of the magnetic material, and then pass through the blocking or passing effect of the magnetization state on the spin-polarized current, and finally read out the size of the output current.

[0003] However, the existing magnetoelectric spin transistor generally uses a strong spin-orbit coupling material as a channel. Although such a material is conducive to spin regulation, its spin diffusion length is usually short, which limits spin transmission and reduces the cascading performance and overall performance of the device, making it difficult to meet the demand of logic cascading application. SUMMARY

[0004] The purpose of the present application is to provide a magnetoelectric spin transistor and a manufacturing method thereof, which, through quantum near-neighbor effect, enables a channel material with long spin diffusion length to maintain its spin transport ability while obtaining enhanced spin-orbit coupling effect, so as to realize effective manipulation of spin state and improve the working performance of the magnetoelectric spin transistor.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present application provides a magnetoelectric spin transistor, which comprises a laminated heterostructure, a source electrode, a drain electrode, a gate electrode and a gate dielectric layer. The laminated heterostructure comprises a magnetoelectric substrate layer and a channel layer arranged in sequence, and a strong spin-orbit coupling material layer arranged between the channel layer and the magnetoelectric substrate layer or arranged on the side of the channel layer away from the magnetoelectric substrate layer. The channel layer is in contact with the magnetoelectric substrate layer and the strong spin-orbit coupling material layer, respectively. The source electrode, the drain electrode and the gate electrode are arranged in the laminated heterostructure on the side opposite to the magnetoelectric substrate layer, along the thickness direction perpendicular to the laminated heterostructure. The gate electrode is located between the source electrode and the drain electrode. The gate dielectric layer is located between the gate electrode and the laminated heterostructure. The material of the channel layer is a weak spin-orbit coupling material.

[0006] In the case of the above technical solution, the magnetoelectric spin transistor provided by the application is in a working state, a voltage is applied between the gate and the magnetoelectric substrate layer, and the magnetization (direction) of the magnetoelectric material in the magnetoelectric substrate is regulated by the voltage due to the magnetoelectric effect, so as to realize voltage-controlled magnetization. Secondly, the spin-polarized electrons pass through the channel layer and reach the drain, and the passing probability is controlled by the relative orientation between the electron spin direction and the magnetization direction of the magnetoelectric substrate. Specifically, when the electron spin direction is parallel to the magnetization direction of the magnetoelectric substrate, the spin-dependent scattering is weak, and the electron passing probability is high; when the two are anti-parallel, the spin-dependent scattering is significantly enhanced, and the electron passing probability is reduced. By controlling the above relative orientation relationship, information storage and switching control can be realized. In the above case, the magnetoelectric spin transistor provided by the application not only includes a channel layer made of a weak spin-orbit coupling material, but also has the advantages that the spin flip scattering is weak, the spin information carried by the injected electron current will not lose its directionality in the channel layer, and the magnetoelectric spin transistor can read out signals with high signal-to-noise ratio. Moreover, the magnetoelectric spin transistor provided by the application further includes a strong spin-orbit coupling material layer (which can be a dielectric layer) in contact with the channel layer, which can enhance the spin-orbit coupling strength of the channel layer through quantum near-neighbor effect (the wave functions of adjacent materials overlap at the interface, so the channel layer will inherit the characteristics of the strong spin-orbit coupling material layer), so that the spin of the channel layer is easy to be manipulated, and the working performance of the magnetoelectric spin transistor is improved.

[0007] In an example, the source is used to inject spin-polarized current into the channel layer. In this way, when the magnetoelectric spin transistor is in a working state, the source of the ferromagnetic material is a spin injection end, and is used to inject a highly polarized electron current into the channel layer when a voltage is applied, and the spin direction of the electron current is consistent with the fixed magnetization direction of the source.

[0008] In an example, the channel layer is located between the strong spin-orbit coupling material layer and the magnetoelectric substrate layer, and the strong spin-orbit coupling material layer covers part of the region on the side of the channel layer away from the magnetoelectric substrate layer. The source and the drain are spaced apart on the channel layer, and the source and the drain are both spaced apart from the strong spin-orbit coupling material layer. The gate and the gate dielectric layer are located on the side of the strong spin-orbit coupling material layer away from the magnetoelectric substrate layer.

[0009] In an example, the channel layer includes at least one of a silicon layer, a silicon germanium layer, a graphene layer, a gallium arsenide layer, and a two-dimensional electron gas layer formed by a gallium nitride and gallium aluminum nitride heterostructure.

[0010] In an example, the thickness of the channel layer is greater than or equal to 1 nm and less than or equal to 3 nm.

[0011] In an example, the material of the strong spin-orbit coupling material layer includes at least one of transition metal chalcogenide, PbTiO3, Bi2Se3, Bi2Te3, LaAlO3, SrTiO3, and Bi2O3.

[0012] In an example, the thickness of the strong spin-orbit coupling material layer is greater than or equal to 3 nm and less than or equal to 100 nm.

[0013] In an example, the ratio between the thickness of the channel layer and the thickness of the strong spin-orbit coupling material layer is greater than or equal to 1 and less than or equal to 30.

[0014] In an example, the magnetoelectric spin transistor further includes a dielectric layer, the dielectric layer is located on a partial region of the magnetoelectric substrate layer in the stacked heterostructure, and the channel layer and the strong spin-orbit coupling material layer are exposed outside the dielectric layer.

[0015] In an example, the material of the dielectric layer includes at least one of Al2O3, ZrO2, HfO2, and SiO2.

[0016] In an example, the thickness of the dielectric layer is greater than or equal to 20 nm and less than or equal to 50 nm.

[0017] In an example, the source electrode, the drain electrode, and the gate electrode are metal electrodes.

[0018] In an example, the material of the magnetoelectric substrate layer includes at least one of C2O3, BiFeO3, LuFeO3, Yb 1-x Lu x FeO3, LiMPO4, and Y2NiMnO6.

[0019] In a second aspect, the present application provides an electronic device, which includes the magnetoelectric spin transistor provided by the first aspect and various implementation solutions thereof. The electronic device includes a smart phone, a personal computer, a tablet computer, a wearable device, a neuromorphic computing chip, and the like.

[0020] The beneficial effects of the second aspect and various implementation solutions thereof in the present application can be analyzed with reference to the beneficial effects of the first aspect and various implementation solutions thereof, which will not be repeated here.

[0021] In a third aspect, the present application provides a method for manufacturing a magnetoelectric spin transistor, which comprises: first, forming a layered heterostructure. The layered heterostructure comprises a magnetoelectric substrate layer and a channel layer arranged in sequence, and a strong spin-orbit coupling material layer arranged between the channel layer and the magnetoelectric substrate layer or arranged on a side of the channel layer away from the magnetoelectric substrate layer. The channel layer is in contact with the magnetoelectric substrate layer and the strong spin-orbit coupling material layer respectively. The material of the channel layer is a weak spin-orbit coupling material. Next, a source electrode, a drain electrode, a gate electrode and a gate dielectric layer are formed on a side of the layered heterostructure opposite to the magnetoelectric substrate layer. The source electrode, the drain electrode and the gate electrode are arranged at intervals along a thickness direction perpendicular to the layered heterostructure. The gate electrode is located between the source electrode and the drain electrode, and the gate dielectric layer is located between the gate electrode and the layered heterostructure.

[0022] In an example, after the layered heterostructure is formed and before the source electrode, the drain electrode and the gate electrode are formed, the method for manufacturing the magnetoelectric spin transistor further comprises: forming a dielectric layer on a partial region of a side of the layered heterostructure opposite to the magnetoelectric substrate layer, and the channel layer and the strong spin-orbit coupling material layer are exposed outside the dielectric layer.

[0023] The beneficial effects of the third aspect of the present application and various implementation manners thereof can be analyzed with reference to the beneficial effects of the first aspect and various implementation manners thereof, which will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are included to provide a further understanding of the present application and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings: Figure 1 A longitudinal sectional view of a structure of a magnetoelectric spin transistor provided for an embodiment of the present application; Figure 2 A positional relationship between a channel layer and a strong spin-orbit coupling material layer in a magnetoelectric spin transistor provided for an embodiment of the present application Figure One ; Figure 3 A positional relationship between a channel layer and a strong spin-orbit coupling material layer in a magnetoelectric spin transistor provided for an embodiment of the present application Figure Two ; Figure 4 A structure of a magnetoelectric spin transistor in a manufacturing process provided for an embodiment of the present application Figure One ; Figure 5 A structure of a magnetoelectric spin transistor in a manufacturing process provided for an embodiment of the present application Figure Two ; Figure 6 A structure of a magnetoelectric spin transistor in a manufacturing process provided for an embodiment of the present application Figure Three ; Figure 7 Structure schematic of a magnetoelectric spin transistor provided by an embodiment of the present application during manufacturing process Figure Four ; Figure 8 Structure schematic of a magnetoelectric spin transistor provided by an embodiment of the present application during manufacturing process Figure Five ; Figure 9 Structure schematic of a magnetoelectric spin transistor provided by an embodiment of the present application during manufacturing process Figure Six .

[0025] Reference signs: 11 is a magnetoelectric substrate layer, 12 is a channel layer, 13 is a strong spin-orbit coupling material layer, 14 is a source electrode, 15 is a drain electrode, 16 is a gate electrode, 17 is a gate dielectric layer, and 18 is a dielectric layer. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary of the present application, but not intended to limit the scope of the present application. Furthermore, in the following description, well-known functions or constructions are not described in detail since they would obscure the application in unnecessary detail.

[0027] Various structure schematics according to embodiments of the present application are shown in the accompanying drawings. These drawings are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0028] In the context of the present application, when a layer / element is said to be located "on" another layer / element, the layer / element can be directly located on the other layer / element, or an intervening layer / element can be present therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved by the present application, technical solutions, and beneficial effects more clear, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application, and not to limit the present application.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0031] Magnetoelectric spin transistors (METS) represent a significant research direction in ultra-low-power spintronics in the post-Moore's Law era. Their aim is to use an electric field (rather than energy-consuming current) to control information storage and processing, thereby achieving ultra-low-power computing. Specifically, the core idea of ​​METS is to use voltage (electric field) to control the magnetization state (direction) of a magnetic material, and then, through the opposition or passage effect of this magnetization state on the spin-polarized current, ultimately read out the magnitude of the output current.

[0032] However, existing magnetoelectric spin transistors generally use strongly spin-orbit coupled materials as channels. While such materials are advantageous for achieving spin control, their spin diffusion length is usually short, which limits spin transport and reduces the cascadability and overall performance of the device, making it difficult to meet the requirements of logic cascading applications.

[0033] To address the aforementioned technical problems, embodiments of the present invention provide a magnetoelectric spin transistor, its manufacturing method, and an electronic device. Specifically, the magnetoelectric spin transistor provided by the present invention, through the quantum nearest neighbor effect, enables the channel material with a long spin diffusion length to achieve enhanced spin-orbit coupling while maintaining its spin transport capability, thereby realizing effective control over the spin state and improving the operating performance of the magnetoelectric spin transistor.

[0034] In a first aspect, embodiments of the present invention provide a magnetoelectric spin transistor. For example... Figures 1 to 3As shown, the magnetoelectric spin transistor includes a stacked heterostructure, a source 14, a drain 15, a gate 16, and a gate dielectric layer 17. The stacked heterostructure includes a 11 and a channel layer 12 arranged sequentially, and a strong spin-orbit coupling material layer 13 disposed between the channel layer 12 and 11 or on the side of the channel layer 12 opposite to 11. The channel layer 12 is in contact with both 11 and the strong spin-orbit coupling material layer 13. Along the thickness direction perpendicular to the stacked heterostructure, the source 14, drain 15, and gate 16 are spaced apart on the side of the stacked heterostructure opposite to 11. The gate 16 is located between the source 14 and the drain 15. The gate dielectric layer 17 is located between the gate 16 and the stacked heterostructure. The channel layer 12 is made of a weak spin-orbit coupling material, and the source 14 is used to inject spin-polarized current into the channel layer 12.

[0035] When the above technical solution is adopted, the magnetoelectric spin transistor provided in this embodiment of the invention is in operation. A voltage is applied between the gate and the magnetoelectric substrate. Due to the magnetoelectric effect, the magnetization intensity (direction) of the magnetoelectric material in the magnetoelectric substrate is modulated by the voltage, achieving voltage-controlled magnetization. Secondly, when spin-polarized electrons cross the channel layer and reach the drain, their passage probability is controlled by the relative orientation between the electron spin direction and the magnetization direction of the magnetoelectric substrate. Specifically, when the electron spin direction is parallel to the magnetization direction of the magnetoelectric substrate, spin-dependent scattering is weak, and the electron passage probability is high; while when they are antiparallel, spin-dependent scattering is significantly enhanced, and the electron passage probability decreases. By controlling the above relative orientation relationship, information storage and switching control can be achieved. In the above case, the magnetoelectric spin transistor provided in this embodiment of the invention not only includes a channel layer based on a weakly spin-orbit coupling material, but also, due to its weak spin-flip scattering, the spin information carried by the injected electron stream will not lose its directionality even after traveling a long distance in the channel layer, which is beneficial for ensuring that the magnetoelectric spin transistor can read out signals with a high signal-to-noise ratio. Furthermore, the magnetoelectric spin transistor provided in this embodiment of the invention also includes a strong spin-orbit coupling material layer (usually a dielectric layer) in contact with the channel layer. This layer can enhance the spin-orbit coupling strength of the channel layer through the quantum nearest neighbor effect (wave functions at the interface of adjacent materials overlap, so the channel layer inherits the characteristics of the strong spin-orbit coupling material layer), thereby making the spin of the channel layer easier to manipulate and improving the working performance of the magnetoelectric spin transistor.

[0036] It should be noted that the strongly self-selected orbital coupling material layer (which can be a dielectric layer) in the embodiments of the present invention only enhances the spin-orbit coupling strength of the channel layer through the quantum nearest neighbor effect, and does not serve as a channel or for transmitting electron flow.

[0037] In practical applications, this invention does not specifically limit the types of materials used in the magnetoelectric substrate layer, weak spin-orbit coupling materials, and strong spin-orbit coupling materials in the stacked heterostructure; these can be set according to actual needs. It should be noted that weak and strong spin-orbit coupling materials are relative concepts, distinguished by the strength of the spin-orbit coupling interaction (SOC) relative to other energy scales (such as crystal field splitting, electron kinetic energy, and electron-electron interactions). Specifically, weak spin-orbit coupling materials are mainly composed of light elements, and the SOC strength corresponding to a weak spin-orbit coupling material is approximately proportional to the fourth power of the atomic number Z (Z0). 4 For example, weak spin-orbit coupling materials may include carbon-based materials or conventional semiconductor materials. For instance, the channel layer may include at least one of the following: a silicon layer, a silicon-germanium layer, a graphene layer, a gallium arsenide layer, and a two-dimensional electron gas layer composed of gallium nitride and gallium aluminum nitride heterostructures.

[0038] Strong spin-orbit coupling materials are primarily composed of heavy elements, i.e., elements with high atomic numbers (Z). For example, strong spin-orbit coupling materials can include 5d transition metal compounds, 4d / 5d chalcogenides, or bismuth-based materials. For instance, the materials used in the strong spin-orbit coupling material layer include at least one of the following: transition metal chalcogenides, PbTiO3, Bi2Se3, Bi2Te3, LaAlO3, SrTiO3, and Bi2O3.

[0039] For example, the material of the magnetoelectric substrate layer may include C2O3, BiFeO3, LuFeO3, Yb 1-x Lu x At least one of FeO3, LiMPO4 and Y2NiMnO6.

[0040] As for the thickness of the magnetoelectric substrate layer, channel layer, and strong spin-orbit coupling material layer in the stacked heterostructure, it can be set according to actual needs, and no specific limit is made here.

[0041] For example, the thickness of the channel layer can be greater than or equal to 1 nm and less than or equal to 5 nm. Optionally, the thickness of the channel layer can be from 1 nm to 3 nm. For example, the thickness of the channel layer can be 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.2 nm, 2.5 nm, 2.8 nm, or 3 nm, etc. This setting can prevent poor continuity and high interface scattering in the channel layer due to excessively small channel layer thickness, thus giving the channel layer stable bulk electronic properties. In addition, it can also prevent the limited influence of the quantum nearest neighbor effect (because the nearest neighbor effect is a short-range interaction) due to excessively large channel layer thickness, which is beneficial to improving the operating performance of the magnetoelectric spin transistor.

[0042] For example, the thickness of the strong spin-orbit coupling material layer can be greater than or equal to 3 nm and less than or equal to 100 nm. For instance, the thickness of the strong spin-orbit coupling material layer can be 3 nm, 3.2 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 8 nm, 10 nm, 20 nm, 30 nm, 50 nm, 80 nm, or 100 nm. This setting can prevent geometric effects caused by an excessively thin spin-orbit coupling material layer, thus improving the operating performance of the magnetoelectric spin transistor. Furthermore, it can prevent the magnetoelectric spin transistor from becoming too large due to an excessively thick spin-orbit coupling material layer, facilitating the miniaturization of the magnetoelectric spin transistor.

[0043] For example, the ratio between the thickness of the channel layer and the thickness of the strong spin-orbit coupling material layer can be greater than or equal to 1 and less than or equal to 30. For instance, the ratio can be 1, 2, 3, 5, 8, 10, 15, 20, 25, or 30. The application principle of the beneficial effect in this case can refer to the previously described principles for preventing the channel layer thickness from being too large or too small, and for preventing the strong spin-orbit coupling material layer thickness from being too large or too small; these will not be repeated here.

[0044] In addition, in practical applications, such as Figure 3 As shown, the strong spin-orbit coupling material layer 13 can be located between part of the channel layer 12 and part of 11.

[0045] Or, such as Figure 2 As shown, the channel layer 12 can be located between the strong spin-orbit coupling material layers 13 and 11, with the strong spin-orbit coupling material layer 13 covering a portion of the channel layer 12 on the side opposite to 11. The source electrode 14 and drain electrode 15 are spaced apart on the channel layer 12, and both are spaced apart from the strong spin-orbit coupling material layer 13. The gate electrode 16 and the gate dielectric layer 17 are located on the side of the strong spin-orbit coupling material layer 13 opposite to 11. This arrangement helps to increase the contact area between the channel layer 12 and the strong spin-orbit coupling material layers 13 and 11, respectively, thus improving the operating performance of the magnetoelectric spin transistor.

[0046] For the aforementioned source, drain, and gate, exemplarily, the source can be used to inject spin-polarized current into the channel layer. With this configuration, when the magnetoelectric spin transistor is in operation, the ferromagnetic source is the spin injection terminal, used to inject a highly polarized electron flow into the channel layer when a voltage is applied, with its spin direction aligned with the fixed magnetization direction of the source. The source and drain are spaced apart from a layer of strongly spin-orbit coupled material.

[0047] In terms of materials, the source electrode can include a ferromagnetic layer made of any ferromagnetic material. The gate and drain electrodes can include any conductive metallic material. The materials of the gate and drain electrodes can be ferromagnetic or non-ferromagnetic.

[0048] For example, the source, drain, and gate can all be metal electrodes. For instance, the materials of the source, drain, and gate can include at least one of iron, nickel, and cobalt. The materials of the source, drain, and gate can be the same or different.

[0049] It should be noted that, in addition to injecting spin-polarized current into the channel layer through the source electrode as described above, it can also be achieved through spin wave-based injection, thermally induced spin injection, or two-dimensional van der Waals heterojunction interface injection. For example, in spin wave-based injection, spin waves can be excited in a magnetic insulator through piezoelectric effects. When these spin waves propagate through the magnetic material to the region coupled with the ferromagnetic channel layer, they can transfer spin angular momentum to the channel layer through magnetic dipole coupling or exchange coupling, thereby changing its magnetization state. As another example, in thermally induced spin injection, when an in-plane temperature gradient is applied to a heavy metal strip (e.g., one end is heated by a laser), a vertically oriented pure spin current is generated due to SOC (Solar Oxidation Current). This spin current can be injected into the adjacent ferromagnetic channel layer and apply SOT.

[0050] In one example, such as Figure 1 As shown, the magnetoelectric spin transistor may further include a dielectric layer 18, which is located on a portion of the stacked heterostructure opposite to 11. The channel layer 12 and the strong spin-orbit coupling material layer 13 are exposed outside the dielectric layer 18. The presence of the dielectric layer 18 can passivate the surface dangling bonds of 11, allowing the gate voltage to penetrate the interface more effectively, generating a stronger effective electric field inside 11, thereby more effectively exciting the magnetoelectric effect.

[0051] As for the material and thickness of the dielectric layer, they can be set according to actual needs, and no specific limitations are made here.

[0052] For example, the material of the dielectric layer may include at least one of Al2O3, ZrO2, HfO2 and SiO2.

[0053] For example, the thickness of the dielectric layer can be greater than or equal to 20 nm and less than or equal to 50 nm. For instance, the thickness of the dielectric layer can be 20 nm, 22 nm, 25 nm, 28 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm, etc.

[0054] Secondly, embodiments of the present invention provide an electronic device including the magnetoelectric spin transistor provided in the first aspect and its various implementations. The electronic device includes smartphones, personal computers, tablet computers, wearable devices, and integrated sensing-memory-computing chips, etc.

[0055] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0056] Thirdly, embodiments of the present invention provide a method for manufacturing a magnetoelectric spin transistor. The following will be based on... Figures 4 to 9 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for manufacturing this magnetoelectric spin transistor includes the following steps: First, such as Figure 4 As shown, a layered heterostructure is formed. The layered heterostructure includes a channel layer 11 and a channel layer 12 arranged sequentially, and a strong spin-orbit coupling material layer 13 disposed between the channel layer 12 and 11 or disposed on the side of the channel layer 12 opposite to 11. The channel layer 12 is in contact with both 11 and the strong spin-orbit coupling material layer 13. The material of the channel layer 12 is a weak spin-orbit coupling material.

[0057] Specifically, the formation process of the stacked heterostructure can be determined based on the relative positional relationship between the channel layer, the magnetoelectric substrate layer, and the strongly spin-orbit coupled material layer.

[0058] For example, when the strong spin-orbit coupling material layer is located between a portion of the channel layer and a portion of the magnetoelectric substrate layer, after providing the magnetoelectric substrate layer, a strong spin-orbit coupling material layer can be formed on a portion of the magnetoelectric substrate layer using processes such as chemical vapor deposition or lift-off. Then, a channel layer is formed on the magnetoelectric substrate layer and the strong spin-orbit coupling material layer using processes such as chemical vapor deposition.

[0059] For example, such as Figure 4 As shown, when the channel layer is located between the strong spin-orbit coupling material layers 13 and 11, a channel layer covering 11 can be formed using processes such as chemical vapor deposition. Next, a strong spin-orbit coupling material layer 13 can be formed on the channel layer using processes such as chemical vapor deposition or stripping.

[0060] Next, if the manufactured magnetoelectric spin transistor includes a dielectric layer, then as follows Figure 5 As shown, atomic layer deposition and etching processes can be used to form a dielectric layer 18 on a portion of the side opposite to 11 in the stacked heterostructure, with the channel layer 12 and the strong spin-orbit coupling material layer 13 exposed outside the dielectric layer 18.

[0061] Next, asFigures 6 to 9 As shown, electron beam evaporation and electron beam etching processes can be used to form a source 14, a drain 15, a gate 16, and a gate dielectric layer 17 on the side opposite to 11 in the stacked heterostructure. The source 14, drain 15, and gate 16 are spaced apart along a direction perpendicular to the thickness of the stacked heterostructure. The gate 16 is located between the source 14 and the drain 15, and the gate dielectric layer 17 is located between the gate 16 and the stacked heterostructure.

[0062] For example, such as Figure 6 As shown, electron beam evaporation and electron beam etching processes can be used to first form the source 14 and drain 15 on the side opposite to 11 in the stacked heterostructure, thereby defining the location of the channel. Next, as... Figure 7 As shown, the channel layer 12 and the strong spin-orbit coupling material layer 13 are patterned using processes such as electron beam etching. Next, as... Figure 8 As shown, the gate dielectric layer 17 can be formed using processes such as atomic layer deposition. Next, as... Figure 9 As shown, the gate 16 is formed using processes such as electron beam evaporation and electron beam etching.

[0063] It should be noted that when the source and drain materials are the same, they can be formed simultaneously or separately. When the source and drain materials are different, the formation order of the source and drain can be set according to actual needs, and no specific limitation is made here.

[0064] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0065] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0066] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A magnetoelectric spin transistor, characterized in that, include: Stacked heterostructure, source, drain, gate and gate dielectric layer; The stacked heterostructure includes a magnetoelectric substrate layer and a channel layer arranged sequentially, and a strong spin-orbit coupling material layer disposed between the channel layer and the magnetoelectric substrate layer or disposed on the side of the channel layer away from the magnetoelectric substrate layer. The channel layer is in contact with the magnetoelectric substrate layer and the strong spin-orbit coupling material layer, respectively. Along a direction perpendicular to the thickness of the stacked heterostructure, the source, the drain, and the gate are spaced apart and disposed on the side of the stacked heterostructure opposite to the magnetoelectric substrate layer; the gate is located between the source and the drain; and the gate dielectric layer is located between the gate and the stacked heterostructure. The channel layer is made of a weak spin-orbit coupling material.

2. The magnetoelectric spin transistor according to claim 1, characterized in that, The source electrode is used to inject spin-polarized current into the channel layer.

3. The magnetoelectric spin transistor according to claim 1 or 2, characterized in that, The channel layer is located between the strong spin-orbit coupling material layer and the magnetoelectric substrate layer, and the strong spin-orbit coupling material layer covers a portion of the channel layer on the side opposite to the magnetoelectric substrate layer. The source and the drain are disposed on the channel layer at intervals, and both the source and the drain are disposed at intervals from the strong spin-orbit coupling material layer; the gate and the gate dielectric layer are disposed on the side of the strong spin-orbit coupling material layer away from the magnetoelectric substrate layer.

4. The magnetoelectric spin transistor according to claim 1 or 2, characterized in that, The channel layer includes at least one of the following: a silicon layer, a silicon-germanium layer, a graphene layer, a gallium arsenide layer, and a two-dimensional electron gas layer composed of gallium nitride and gallium aluminum nitride heterostructures. And / or, the thickness of the channel layer is greater than or equal to 1 nm and less than or equal to 3 nm.

5. The magnetoelectric spin transistor according to claim 1 or 2, characterized in that, The material of the strong spin-orbit coupling material layer includes at least one of the following: transition metal chalcogenides, PbTiO3, Bi2Se3, Bi2Te3, LaAlO3, SrTiO3, and Bi2O3; And / or, the thickness of the strong spin-orbit coupling material layer is greater than or equal to 3 nm and less than or equal to 100 nm.

6. The magnetoelectric spin transistor according to claim 1 or 2, characterized in that, The ratio between the thickness of the channel layer and the thickness of the strong spin-orbit coupling material layer is greater than or equal to 1 and less than or equal to 30. And / or, the magnetoelectric spin transistor further includes a dielectric layer located on a portion of the stacked heterostructure opposite to the magnetoelectric substrate layer, wherein the channel layer and the strong spin-orbit coupling material layer are exposed outside the dielectric layer.

7. The magnetoelectric spin transistor according to claim 6, characterized in that, The dielectric layer is made of at least one of Al2O3, ZrO2, HfO2, and SiO2. And / or, the thickness of the dielectric layer is greater than or equal to 20 nm and less than or equal to 50 nm.

8. The magnetoelectric spin transistor according to claim 1 or 2, characterized in that, The source, the drain, and the gate are all metal electrodes; And / or, the material of the magnetoelectric substrate layer includes C2O3, BiFeO3, LuFeO3, Yb 1-x Lu x At least one of FeO3, LiMPO4 and Y2NiMnO6.

9. An electronic device, characterized in that, include: The magnetoelectric spin transistor as described in any one of claims 1 to 8; The electronic devices include smartphones, personal computers, tablets, wearable devices, and integrated sensing, storage, and computing chips.

10. A method for manufacturing a magnetoelectric spin transistor, characterized in that, include: A stacked heterostructure is formed; the stacked heterostructure includes a magnetoelectric substrate layer and a channel layer arranged sequentially, and a strong spin-orbit coupling material layer disposed between the channel layer and the magnetoelectric substrate layer or disposed on the side of the channel layer away from the magnetoelectric substrate layer; The channel layer is in contact with the magnetoelectric substrate layer and the strong spin-orbit coupling material layer, respectively. The channel layer is made of a weak spin-orbit coupling material; On the side opposite to the magnetoelectric substrate in the stacked heterostructure, a source, a drain, a gate, and a gate dielectric layer are formed; the source, the drain, and the gate are spaced apart along a direction perpendicular to the thickness of the stacked heterostructure; the gate is located between the source and the drain, and the gate dielectric layer is located between the gate and the stacked heterostructure.

11. The method for manufacturing a magnetoelectric spin transistor according to claim 10, characterized in that, After forming the stacked heterostructure and before forming the source, drain, and gate, the manufacturing method of the magnetoelectric spin transistor further includes: A dielectric layer is formed on a portion of the side opposite to the magnetoelectric substrate in the stacked heterostructure, and the channel layer and the strong spin-orbit coupling material layer are exposed outside the dielectric layer.

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