Method of adjusting gate dielectric and structure thereof

Abstract

This disclosure relates to methods and structures for adjusting gate dielectrics. One method includes forming a plurality of semiconductor nanostructures and forming a hard mask including a top portion over the plurality of semiconductor nanostructures; an inner portion between the plurality of semiconductor nanostructures; and sidewall portions on the sidewalls of the plurality of semiconductor nanostructures. The method further includes etching the sidewall portions of the hard mask, wherein at least the top portion of the hard mask is retained; performing a first oxidation process to oxidize the sidewall portions of the semiconductor nanostructures to form a first oxide layer; removing the top and inner portions of the hard mask; and performing a second oxidation process to oxidize the top and bottom portions of the semiconductor nanostructures to form a second oxide layer. The second oxide layer includes the first oxide layer. The second oxide layer surrounds the remainder of the plurality of semiconductor nanostructures.

Description

Technical Field

[0001] This disclosure relates to a method and structure for adjusting the gate dielectric. Background Technology

[0002] Technological advancements in integrated circuit (IC) materials and design have resulted in several generations of ICs, each featuring smaller and more complex integrated circuits than previous generations. Throughout IC development, functional density (e.g., the number of interconnect devices per chip area) has typically increased, while geometric dimensions have decreased. This miniaturization process generally provides benefits through increased manufacturing efficiency and reduced associated costs.

[0003] This miniaturization also increases the complexity of IC fabrication and manufacturing, and similar advancements in IC fabrication and manufacturing are needed to achieve these progresses. For example, Gate-All-Around (GAA) transistors have been introduced to replace planar transistors. The structure and manufacturing methods of GAA transistors are currently under development. Summary of the Invention

[0004] According to one aspect of this disclosure, a method for adjusting a gate dielectric is provided, comprising: forming a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of the plurality of semiconductor nanostructures; forming a hard mask including: a top portion located above the plurality of semiconductor nanostructures; an inner portion located between the plurality of semiconductor nanostructures; and a sidewall portion located on the sidewalls of the plurality of semiconductor nanostructures; etching the sidewall portions of the hard mask, wherein at least the top portion of the hard mask is retained; performing a first oxidation process to oxidize the sidewall portions of the semiconductor nanostructures to form a first oxide layer; removing the top portion and the inner portion of the hard mask; and performing a second oxidation process to oxidize the top portion and the bottom portion of the semiconductor nanostructures to form a second oxide layer, wherein the second oxide layer surrounds the remaining portion of the plurality of semiconductor nanostructures, and wherein the second oxide layer includes the first oxide layer.

[0005] According to one aspect of this disclosure, a method for adjusting a gate dielectric is provided, comprising: forming a plurality of semiconductor nanostructures and a plurality of sacrificial layers, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are alternately disposed; removing the plurality of sacrificial layers to leave a space between the plurality of semiconductor nanostructures; oxidizing an outer portion of the plurality of semiconductor nanostructures to form an oxide layer surrounding an inner portion of the plurality of semiconductor nanostructures, wherein each of the oxide layers comprises: a sidewall portion located on a sidewall of the inner portion of the plurality of semiconductor nanostructures, wherein the sidewall portion has a first thickness; and a top portion located on a top of the inner portion of the plurality of semiconductor nanostructures, wherein the top portion has a second thickness less than the first thickness; and forming a gate stack in the space between the plurality of semiconductor nanostructures.

[0006] According to one aspect of this disclosure, a method for adjusting a gate dielectric is provided, comprising: forming a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of the plurality of semiconductor nanostructures; forming a source region and a drain region connected to opposite ends of the plurality of semiconductor nanostructures; forming an oxide layer surrounding the nanostructures of the plurality of semiconductor nanostructures, wherein the oxide layer includes: a sidewall portion located on a sidewall of the nanostructure, wherein the sidewall portion has a first thickness; a top portion covering the nanostructure; and a bottom portion covering the nanostructure, wherein the top portion and the bottom portion have a second thickness less than the first thickness; and forming a gate stack, wherein the gate stack includes portions located in the spacing between the plurality of semiconductor nanostructures. Attached Figure Description

[0007] The best understanding of all aspects of this disclosure can be achieved by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figures 12-18 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A and Figure 21B A view is shown of an intermediate stage in the formation of a nanostructured transistor according to some embodiments.

[0009] Figures 22-27 A cross-sectional view of an intermediate stage of forming an interface layer according to some embodiments is shown.

[0010] Figure 28 and Figure 29 A cross-sectional view is shown of an intermediate stage in the formation of an interface layer for transistors with different channel lengths, according to some embodiments.

[0011] Figure 30A , Figure 30B and Figure 31 A view is shown of an intermediate stage in the formation of an interface layer for transistors with different channel pitches, according to some embodiments.

[0012] Figure 32 A process flow for forming nanostructured transistors according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, this document may use spatially relevant terms (e.g., "below," "under," "lower," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein shall be interpreted accordingly.

[0015] A gate-all-around (GAA) transistor and its fabrication method are provided. According to some embodiments, the channel region (nanostructure) of the transistor is oxidized in two oxidation processes. In a first oxidation process, the sidewalls of the nanostructure are oxidized. In a second oxidation process, the top surface portion, bottom surface portion, and sidewall portion of the nanostructure are oxidized. Therefore, the nanostructure is thicker at the sidewalls and corner regions than at the top and bottom surface portions. This reduces gate-to-channel leakage current and improves reliability.

[0016] The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of this disclosure, and modifications that may be made within the contemplated scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to designate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1-4 , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figures 12-18 , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A and Figure 21B A cross-sectional view of an intermediate stage in the formation of a GAA transistor according to some embodiments of the present disclosure is shown. The corresponding process is also schematically reflected in… Figure 32 The process flow shown is as follows.

[0018] refer to Figure 1 The diagram shows a perspective view of wafer 10. Wafer 10 includes a multilayer structure comprising a multilayer stack 22 on substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium (SiGe) substrate, etc.; however, other substrates and / or structures may also be used, such as semiconductor-on-insulator (SOI), strained SOI, silicon-germanium-on-insulator, etc. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor substrate.

[0019] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. The corresponding processes are described in... Figure 32 The process flow 200 shown is referred to as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material different from the first semiconductor material.

[0020] According to some embodiments, the first semiconductor material of the first layer 22A is formed from or includes materials such as SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, and GaAsSb. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is achieved through epitaxial growth, and the corresponding deposition methods may include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to a range of approximately Peace Treaty The initial thickness. However, any suitable thickness can be used while remaining within the range of the embodiments.

[0021] Once the first layer 22A has been deposited on the substrate 20, the second layer 22B is deposited on top of the first layer 22A. According to some embodiments, the second layer 22B is formed of or comprises a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations of these materials, etc., and the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, according to some embodiments where the first layer 22A is silicon-germanium, the second layer 22B can be formed of silicon, and vice versa. It is understood that any suitable combination of materials can be used for the first layer 22A and the second layer 22B.

[0022] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to a different thickness than the first layer 22A. For example, according to some embodiments, the thickness of the second layer 22A is in the range of about 4 nm to 7 nm, while the thickness of the second layer 22B is in the range of about 8 nm to 12 nm.

[0023] Once the second layer 22B has been formed on top of the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired top layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness, and the second layers 22B have the same or similar thickness. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as sacrificial layer 22A throughout the description. According to other embodiments, the second layer 22B is a sacrificial layer and is removed in a subsequent process.

[0024] According to some embodiments, one or more pad oxide layers and one or more hard mask layers (not shown) may be formed on top of the multilayer stack 22. These layers are patterned and used for subsequent patterning of the multilayer stack 22.

[0025] refer to Figure 2 A portion of the underlying substrate 20 and the multilayer stack 22 are patterned in one or more etching processes to form trenches 23. The corresponding processes are performed in... Figure 32 The process flow 200 shown is referred to as process 204. Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', a portion of substrate 20 is retained and is hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layers 22A and 22B. hereinafter, semiconductor layer 22A is alternatively referred to as sacrificial layer, and semiconductor layer 22B is alternatively referred to as nanostructure. These portions of multilayer stack 22' and the underlying substrate strip 20' are collectively referred to as semiconductor strip 24.

[0026] In the above embodiments, the GAA transistor structure can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate using a photolithography process and then patterned thereon. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0027] Figure 3 The diagram shows the formation of isolation region 26, also referred to throughout the description as the Shallow Trench Isolation (STI) region. The corresponding process is... Figure 32The process flow 200 shown is referred to as process 206. STI region 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, etc. STI region 26 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPCVD, etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, may then be performed to planarize the top surface of the dielectric material, and the remaining portion of the dielectric material constitutes STI region 26.

[0028] STI region 26 is then recessed such that the top portion of semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of STI region 26 to form protruding fins 28. Protruding fins 28 include the top portion of a multilayer stack 22' and substrate strip 20'. The recess of STI region 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. Plasma may be generated during the etching process. Argon may also be included. According to an alternative embodiment of this disclosure, the recess of STI region 26 is performed by a wet etching process. For example, etching chemicals may include HF.

[0029] refer to Figure 4 A dummy gate stack 30 and gate spacers 38 are formed on the top surface and sidewalls of the (protruding) fin 28. The corresponding process is as follows: Figure 32 The process flow 200 is shown as process 208. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 on top of the dummy gate dielectric 32. The dummy gate dielectric 32 may be formed by oxidizing a surface portion of the protruding fin 28 to form an oxide layer, or by depositing a dielectric layer (e.g., a silicon oxide layer). The dummy gate electrode 34 may be formed, for example, using polysilicon or amorphous silicon, or other materials such as amorphous carbon.

[0030] Each dummy gate stack 30 may further include one or more hard mask layers 36 above the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or multiple layers thereof. The dummy gate stack 30 may span one or more protruding fins 28 and an STI region 26 between the protruding fins 28. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 28. The formation of the dummy gate stack 30 includes forming a dummy gate dielectric layer, depositing a dummy gate electrode layer on the dummy gate dielectric layer, depositing one or more hard mask layers, and then patterning the formed layers by one or more patterning processes.

[0031] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of this disclosure, the gate spacers 38 are formed of a dielectric material, such as silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include depositing one or more dielectric layers, and then performing one or more anisotropic etching processes on the dielectric layers(one or more). The remaining portion of the dielectric layers(one or more) constitutes the gate spacers 38.

[0032] Figure 5A and Figure 5B It shows Figure 4 Cross-sectional view of the structure shown. Figure 5A It shows Figure 4 The reference cross section A1-A1 cuts through the portion of the protruding fin 28 that is not covered by the dummy gate stack 30 and the gate spacer 38, and is perpendicular to the gate length direction. Figure 5B It shows Figure 4 The reference cross section BB is parallel to the longitudinal direction of the protruding fin 28.

[0033] refer to Figure 6A and Figure 6B 28 protruding fins Figure 4 The portion of the gate that is not directly beneath the dummy gate stack 30 and the gate spacer 38 is recessed by an etching process to form a recess 42. The corresponding process is... Figure 32 The process flow 200 shown is referred to as process 210. For example, a dry etching process can be performed using C2F6; CF4; SO2; a mixture of HBr, Cl2, and O2; or a mixture of HBr, Cl2, O2, and CH2F2, etc., to etch the multilayer semiconductor stack 22' and the underlying substrate strip 20'. The bottom of the recess 42 is at least flush with, or may be lower than (e.g., Figure 6B (As shown) The bottom of the multilayer semiconductor stack 22'. The etching can be anisotropic, such that the sidewalls of the multilayer semiconductor stack 22' facing the recess 42 are vertical and straight, as shown. Figure 6B As shown.

[0034] refer to Figure 7A and Figure 7B The sacrificial semiconductor layer 22A is laterally recessed to form a lateral recess 41, which is recessed from the edges of the corresponding upper and lower nanostructures 22B. The corresponding process is... Figure 32 The process flow 200 shown is referred to as process 212.

[0035] The lateral recesses of the sacrificial semiconductor layer 22A can be achieved using a wet etching process. This wet etching process uses an etchant that is more selective for the material of the sacrificial semiconductor layer 22A (e.g., silicon-germanium (SiGe)) than for the materials of the nanostructure 22B and the substrate 20 (e.g., silicon (Si)). For example, in an embodiment where the sacrificial semiconductor layer 22A is formed of silicon-germanium and the nanostructure 22B is formed of silicon, the wet etching process can be performed using an etchant such as hydrochloric acid (HCl). The wet etching process can be performed using immersion processes, spraying processes, spin coating processes, etc.

[0036] According to an alternative embodiment, the lateral recess of the sacrificial semiconductor layer 22A is performed by an isotropic dry etching process, or a combination of a dry etching process and a wet etching process.

[0037] refer to Figure 8A and Figure 8B This forms the internal spacer 44. The corresponding process is as follows: Figure 32 The process flow 200 shown is referred to as process 214. According to some embodiments, the formation of the internal spacer 44 includes depositing a conformal dielectric layer that extends to the lateral recess 41. Figure 7B Next, an etching process (also known as a spacer trimming process) is performed to trim the portion of the spacer layer outside the lateral recess 41, leaving the portion of the spacer layer within the lateral recess 41. The remaining portion of the spacer layer is referred to as the inner spacer 44. The inner spacer 44 may be a single-layer spacer or may include multiple sublayers (e.g., two or three sublayers).

[0038] refer to Figure 9A and Figure 9B An epitaxial source / drain region 48 is formed in the recess 42. The corresponding process is carried out in... Figure 32 The process flow 200 is shown as process 216. According to some embodiments, the source / drain region 48 may apply stress to the nanostructure 22B that serves as the channel for the corresponding GAA transistor, thereby improving performance.

[0039] Depending on whether the resulting transistor is a p-type or n-type transistor, in-situ doping with p-type or n-type impurities can be achieved through epitaxy. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeB) or silicon boron (SiB) can be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphide (SiP) or silicon carbon phosphide (SiCP) can be grown. After the recess 42 is filled by the epitaxial region 48, further epitaxial growth of the epitaxial region 48 allows it to expand horizontally and form facets. Further growth of the epitaxial region 48 can also cause adjacent epitaxial regions 48 to merge. Voids (air gaps) 49 may be generated.

[0040] refer to Figure 10A and Figure 10B This forms a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. The corresponding process is as follows: Figure 32 The process flow 200 shown is designated as process 218. Figure 21 also shows the corresponding structure. CESL 50 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. ILD 52 can be formed from an oxygen-containing dielectric material, which may be silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0041] CESL 50 and ILD 52 are planarized using a planarization process such as CMP or mechanical polishing. According to some embodiments, the planarization process may remove the hard mask 36 to expose the dummy gate electrode 34, such as... Figure 10A As shown. According to an alternative embodiment, the planarization process may expose the hard mask 36 and stop on the hard mask 36. According to some embodiments, after the planarization process, the top surfaces of the dummy gate electrode 34 (or hard mask 36), the gate spacer 38, and the ILD 52 are flush within a process variation.

[0042] Next, the dummy gate electrode 34 and dummy gate dielectric 32 (and hard mask 36, if remaining) are removed in one or more etching processes to form the recess 58, as shown. Figure 11A and Figure 11B As shown. The corresponding process is in Figure 32 The process flow 200 shown is referred to as process 220.

[0043] The sacrificial layer 22A is then removed to extend the recesses 58 between the nanostructures 22B. The corresponding process is... Figure 32 The process flow 200 shown is also referred to as process 220. The sacrificial layer 22A can be removed by performing an isotropic etching process (e.g., a wet etching process using an etchant that is selective to the material of the sacrificial layer 22A), while the nanostructure 22B, the substrate 20, and the STI region 26 remain relatively unetched compared to the sacrificial layer 22A.

[0044] Figures 12 to 18 A view showing an interface layer 64 forming around the nanostructure 22B according to some embodiments is shown. Figure 12 It shows Figure 11A Part of region 59.

[0045] refer to Figure 13 This forms a hard mask 110. The corresponding process is as follows: Figure 32 The process flow 200 shown is designated as process 222. The hard mask 110 may include metal oxides, metal nitrides, metal oxynitrides, metal nitrides, metal oxynitrides, etc. The metal in the hard mask 110 may include Al, Hf, Zr, Ti, La, etc., or combinations thereof, but other metals may also be used. Non-metallic materials may also be used to form the hard mask 110.

[0046] According to some embodiments, the hard mask 110 can be deposited using a conformal deposition process (e.g., ALD, CVD, etc.) to fill the gaps between the nanostructures 22B. For example, when the hard mask 110 comprises a metal oxide, it can be deposited using a chlorine-based precursor or a metal-organic precursor, along with reactants (oxidants or nitrides) via ALD. The wafer temperature during the deposition process can be in the range of about 100°C to about 500°C. The pressure in the deposition chamber can be in the range of about 0.1 Torr to about 10 Torr.

[0047] refer to Figure 14 Process 112 is performed on the hard mask 110. The corresponding process is... Figure 32 The process flow 200 shown is designated as process 224. Processing process 112 can be an anisotropic processing process, such that the top portion 110T of the hard mask 110 is processed and its properties are altered, while the lower portion 110L of the hard mask 110 remains unprocessed. The lower portion 110L includes sidewall portions on the sidewalls of the nanostructures 22B and internal portions between the nanostructures 22B. Processing process 112 can be performed using oxygen-containing process gases (e.g., O2), nitrogen-containing process gases (e.g., NH3), or combinations thereof. Other process gases that can alter the properties of the hard mask 110 (e.g., carbon-containing gases such as CO2) can also be used.

[0048] The processing technology can alter the composition of the hard mask 110 by adding one or more elements not present in the deposited hard mask 110, increasing the atomic percentage of the elements in the deposited hard mask 110, and / or improving the quality (e.g., density) of the hard mask 110.

[0049] For example, when the hard mask 110 comprises a metal oxide (e.g., aluminum oxide), NH3 can be used to add nitrogen and change the top portion 110T to aluminum oxynitride, thereby creating higher etch selectivity between the lower portion 110L and the top portion 110T. When the hard mask 110 comprises a metal oxide (e.g., aluminum oxide), oxygen (O2) can also be used to improve the quality of the hard mask 110, for example, by adding oxygen to repair defects and density in the top portion 110T. On the other hand, the lower portion 110L is not processed. Therefore, the top portion 110T and the lower portion 110L may comprise the same material but have different properties, such as different densities, different porosities, and / or different dangling bonds.

[0050] According to some embodiments, the processing gas may include gases used for adding desired elements (as described above) or densifying the hard mask 110, and may not contain inert gases such as N2, He, Ar, Xe, etc. Alternatively, inert gases such as N2, He, Ar, Xe, etc., may be added in addition to the gases used for adding desired elements or densifying the hard mask 110. The wafer temperature during processing 112 may be in the range of about 100°C to about 600°C. The pressure inside the processing chamber may be in the range of about 0.01 Torr to about 10 Torr.

[0051] Next, as Figure 15 As shown, etching process 116 is performed to etch the lower portion 110L of the hard mask 110. The corresponding process is... Figure 32 The process flow 200 shown is illustrated as process 226. According to some embodiments, etching process 116 includes an isotropic etching process. The etching chemicals are selected to etch the lower portion 110L, and the treated top portion 110T has at least a reduced etching rate ER-110T compared to the etching rate ER-110L of the lower portion 110L. For example, the etching rate ratio ER-110T / ER-110L can be less than about 0.1, and can be in the range between about 0.01 and about 0.1.

[0052] Etching process 116 can be performed by dry (vapor phase) etching or wet etching. For example, when using wet etching, a chemical solution of NH4OH, HCl, and / or an oxidizing agent can be used. The oxidizing agent may or may not be mixed with deionized water (DI). The oxidizing agent may include, for example, hydrogen peroxide.

[0053] According to some embodiments, after etching process 116, the lower portion 110L is removed, and the sidewalls of the nanostructure 22B are exposed. The top portion 110T may be retained. It is understood that the top portion 110T may (or may not) have a cantilevered portion that laterally protrudes beyond the edge of the nanostructure 22B, wherein the sidewalls of the cantilevered portion are schematically illustrated by dashed lines 118. The remaining portion of the hard mask 110 may have a portion 110S located in the spacing between the nanostructures 22B.

[0054] The outer wall of portion 110S can be vertically aligned with the outer edge of nanostructure 22B, or it can be laterally recessed. For example, dashed line 119 represents the outer wall of portion 110S when it is laterally recessed. Lateral recesses can help form a thicker IL at the corners of nanostructure 22B. According to some embodiments, the ratio W1 / L1 can be greater than about 0.05 and can be in the range between about 0.05 and about 0.1, where W1 is the width of the recess and L1 is the length of nanostructure 22B.

[0055] According to an alternative embodiment, after etching process 116, the sidewall portions of the hard mask 110 (including those in the lower portion 110L) are thinned, and the resulting thinned sidewall portions may have a sufficiently small thickness (measured in the lateral direction) to allow the nanostructure 22B to be embedded within the hard mask. Figure 16 The process shown involves oxidation. According to some embodiments, the thickness of the thinned sidewall portion is less than about 10% of the thickness of the top portion 110T (measured in the vertical direction), and less than about 10% of the thickness of the sidewall portion before the etching process 116 is performed.

[0056] According to some embodiments, one or more cycles can be performed after etching process 116. Each cycle includes... Figures 13-15 The process is illustrated. In each cycle, a hard mask is formed on the remaining top portion 110T, portion 110S, and nanostructure 22B. The material of the hard mask deposited in each cycle can be the same as or different from the material of the hard mask in other cycles. Using different materials to form the hard mask in different cycles can improve etch resistance.

[0057] If possible Figure 13 , Figure 14 and Figure 15 It is understood that each cycle increases the thickness (height, measured vertically) of the top portion of the hard mask 110 until the height is large enough to protect the top nanostructure 22B from oxidation from the top in the subsequent oxidation process 120. According to an alternative embodiment, no further cycles are performed.

[0058] According to some embodiments, after etching process 116, the process continues to oxidation process 120, such as... Figure 16 As shown. The corresponding process is in Figure 32 The process flow 200 shown is referred to as process 228.

[0059] According to some embodiments, the oxidizing gas used in oxidation process 120 may include O2 and may or may not include inert gases, such as N2, He, Ar, Xe, etc. The oxidation process can be performed by generating plasma from the oxidizing gas and using the plasma for oxidation process 120. The plasma used for oxidation process 120 may include ions and free radicals of the oxidizing gas. Alternatively, ions may be removed, leaving free radicals for oxidation process 120. The wafer temperature during oxidation process 120 can be in the range of about 100°C to about 600°C. The pressure in the oxidation chamber can be in the range of about 0.01 Torr to about 10 Torr.

[0060] As a result of oxidation process 120, an oxide layer 64S is formed on the sidewalls of nanostructure 22B. The thickness T1 of the oxide layer 64S can be approximately... Peace Treaty Within the range between. Due to the protection of the top portion 110T and the inner portion 110S, no oxides are generated on the top and bottom surfaces of at least the inner portion of the nanostructure 22B.

[0061] After forming the 64S oxide layer, the etching process 124 is performed. Figure 17 The remaining top portion 110T and inner portion 110S of the hard mask 110 are removed. Etching process 124 includes an isotropic etching process. The corresponding process is... Figure 32 The process flow 200 shown is designated as process 230. Etching process 124 can be performed by dry (vapor phase) etching or wet etching. Etching chemicals can be selected from those used in etching process 116. Figure 15 The etching chemicals are from the same candidate group and may be the same as or different from the etching chemicals used in etching process 116.

[0062] Depending on the material of the top portion 110T, when using wet etching, a chemical solution of NH4OH, HCl, and / or an oxidizing agent can be used. The oxidizing agent may or may not be mixed in deionized water (DI). The oxidizing agent may include, for example, hydrogen peroxide. When the chemicals are the same as those used in etching process 116, etching process 124 may employ a longer etching time, a higher etching chemical temperature, etc., than etching process 116 to ensure that the top portion 110T and the inner portion 110S are removed. After etching process 124, the recess (spacing) 58 is regenerated.

[0063] refer to Figure 18 An oxidation process 128 is performed to form an oxide layer 64 (also known as an interface layer (IL) 64). The corresponding process is... Figure 32The process flow 200 is shown as process 232. Oxidation process 128 can be performed using oxygen, for example, by generating plasma from oxygen-containing gas. Oxidation process 128 may also include a chemical oxidation process. As a result, IL 64 is formed on the top and bottom surfaces of nanostructure 22B and has a thickness T4, which is measured vertically and at the center of nanostructure 22B.

[0064] The sidewall portion of IL 64 formed on the sidewall of nanostructure 22B includes the previously formed oxide layer 64S. Figure 17 The newly formed oxide has a thickness T3, which is measured horizontally at the mid-level of the nanostructure 22B. Thickness T3 is greater than thickness T4. The difference (T3-T4) can be approximately... Peace Treaty The ratio T3 / T4 can be greater than approximately 1.1, for example, it can be in the range between approximately 1.1 and approximately 4.

[0065] Figure 19A The structure formed by the aforementioned process is shown, with a large area of ​​the structure shown. Figure 19A and Figure 19B They respectively show from Figure 11A and Figure 11B A cross-sectional view obtained from the same cross-section shown. (e.g.) Figure 19B As shown, IL 64 is formed on the exposed surface exposed to the spacing 58.

[0066] refer to Figure 20A and Figure 20B A high-k dielectric layer 66 is deposited on top of IL 64. The corresponding process is as follows: Figure 32 The process flow 200 shown is referred to as process 234. IL 64 and the high-k dielectric layer 66 are individually and collectively referred to as gate dielectric 62. According to some embodiments, the high-k dielectric layer 66 includes one or more high-k dielectric layers. For example, the high-k dielectric layer 66 may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, multilayers thereof, and / or combinations thereof.

[0067] Then the gate electrode 68 is formed, such as Figure 21A and Figure 21B As shown. The corresponding process is in Figure 32The process flow 200 shown is designated as process 236. Gate dielectric 62 and gate electrode 68 together form a replacement gate stack 70. During the formation of gate electrode 68, a conductive layer is first formed over a high-k dielectric layer 66, filling the remaining portion of recess 58, followed by a planarization process, such as CMP or mechanical polishing, to remove excess material. Gate electrode 68 may include a metallic material, such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. This forms a GAA transistor 72.

[0068] Figures 22-27 The formation of IL 64 according to an alternative embodiment is shown. These embodiments are similar to the foregoing embodiments, except that the top portion 110T is formed to be thicker than the sidewall portions (during deposition). Therefore, after removing the sidewalls (lower portion 110L), some portion of the top portion 110T remains. Unless otherwise stated, the materials, structure, and forming processes of the components in these embodiments are substantially the same as those of the same components indicated by the same reference numerals in the foregoing embodiments. The details regarding materials, structure, and forming processes provided in each embodiment throughout the description may be applied to any other embodiment where appropriate.

[0069] The initial steps of these embodiments and Figures 1-11A / Figure 11B The results are basically the same. Figure 22 The resulting structure is shown, which is similar to... Figure 12 The structures shown are basically the same. Next, refer to... Figure 23 , deposited hard mask 110.

[0070] According to some embodiments, the hard mask 110 is deposited such that the thickness T2T of the top portion is greater than the thickness T2S of the lower portion 110L. The spacing between the nanostructures 22B is also completely filled. The difference (T2T-T2S) can be greater than approximately And can be in about Peace Treaty Within the range, and can also be greater than approximately

[0071] According to some embodiments, the material of the hard mask 110 may be selected from the same group of candidate materials discussed in the foregoing embodiments. For example, the hard mask 110 may include metal oxides, metal nitrides, metal oxynitrides, metal nitrides, metal oxynitrides, etc. The metal in the hard mask 110 may include Al, Hf, Zr, Ti, La, etc., or combinations thereof, but other metals may also be used. Non-metallic materials may also be used to form the hard mask 110.

[0072] In embodiments where the hard mask 110 comprises a metal oxide, the hard mask 110 can be deposited via ALD using a chlorine-based precursor or a metal-organic precursor, and reactants (oxidants or nitrides). The wafer temperature during the deposition process can range from about 100°C to about 500°C. The pressure in the deposition chamber can range from about 0.1 Torr to about 10 Torr.

[0073] According to some embodiments, to achieve a large difference between thicknesses T2T and T2S, the deposition process incorporates the effects of both isotropic and anisotropic deposition. According to some embodiments, deposition is achieved via ALD, a method that is inherently isotropic. The anisotropic effect is achieved by utilizing the fact that the diffusion length of the precursor and reactant at the top of the wafer is less than the diffusion length on the sidewalls. For example, the pulse delivery time for conducting the metal-containing precursor can be shortened, and the pulse delivery time can be shorter than a reference time. Figure 13 The pulse delivery time in the discussed embodiments. On the other hand, the purge time of the metal-containing precursor, as well as the pulse delivery time and purge time of the reactants, have little effect on the diffusion length, and therefore can be compared with the reference. Figure 13 The examples discussed are the same.

[0074] By utilizing a shorter diffusion length, a smaller amount of metal-containing precursor molecules adsorb onto the sidewalls of nanostructure 22B and into the gaps between nanostructures 22B during each pulse delivery. Therefore, in each ALD cycle, the growth of the hard mask 110 on top of nanostructure 22B is faster than its growth in the gaps between nanostructures 22B and on the sidewalls.

[0075] According to some embodiments, no processing is performed on the hard mask 110 to change the characteristics of the top portion 110T. According to an alternative embodiment, processing 112 is performed to change the characteristics of the top portion 110T to be different from the characteristics of the lower portion 110L. Details of processing 112 can be found in [reference needed]. Figure 14 This will not be elaborated further here. Process 112 is shown as a dashed line to indicate whether it can be performed or not.

[0076] Figure 24 The etching process 116 for the lower portion 110L is shown, leaving the inner portion 110S between the nanostructures 22B. See reference for details. Figure 15 The discussion on this will not be repeated here. In etching process 116, since the top portion 110T is thicker than the lower portion 110L, the sidewall portion of the hard mask 110 on the sidewall of the nanostructure 22B is removed, while some portions of the top portion are retained. If the top portion 110T is further processed, the remaining top portion 110T can be thicker.

[0077] According to some embodiments, one or more cycles can be performed after etching process 116. Each cycle includes... Figures 23-24 The process is illustrated. In each cycle, a hard mask is formed on the remaining top portion 110T, portion 110S, and nanostructure 22B. The material of the hard mask deposited in each cycle can be the same as or different from the material of the hard mask in other cycles. Using different materials to form the hard mask in different cycles can improve etch resistance.

[0078] Each cycle increases the thickness (height, measured vertically) of the top portion of the hard mask 110 until the height is large enough to protect the top nanostructure 22B from oxidation from the top in the subsequent oxidation process 120. According to an alternative embodiment, no further cycles are performed.

[0079] Figure 25 An oxidation process 120 for forming an oxide layer 64S is shown. Figure 26 An etching process 124 for removing the remainder of the hard mask 110 is shown. Figure 27 The oxidation process 126 for forming IL 64 is shown. Details of these processes can be found in [reference needed]. Figure 16 , Figure 17 and Figure 18 The discussion on this topic will not be repeated here.

[0080] Figure 27 The resulting structure is also Figure 19A and Figure 19B As shown in the image. Next, execute... Figure 20A , Figure 20B , Figure 21A and Figure 21B The process shown is used to complete the formation of GAA transistor 72.

[0081] Figures 28 to 31 The process of forming transistors with different structures in different device regions is shown. Device regions 100A, 100B, 100C, and 100D can be located in the same device die and can be formed by a common process (as shown in the foregoing figures).

[0082] Figure 28 and Figure 29 Device regions 100A and 100B are shown, in which GAA transistors 72A and 72B are formed with different channel lengths. Figure 28 The structure shown corresponds to Figure 19B The structure and process are shown. The channel length L2 in device region 100B is greater than the channel length L1 in device region 100A. According to some embodiments, the channel length ratio L2 / L1 can be greater than about 1.2, and can be in the range between about 1.2 and about 5.

[0083] Figure 29The resulting GAA transistors 72A and 72B are shown, and the structure shown corresponds to Figure 21A The structure is shown. According to some embodiments, the thickness difference (T3A-T4A) in device region 100A and the thickness difference (T3B-T4B) in device region 100B can be approximately... Peace Treaty Within the range between.

[0084] Due to the pattern loading effect, the ratio T3B / T4B can be different from and can be greater than the thickness ratio T3A / T4A. The ratio (T3B / T4B) / (T3A / T4A) can be greater than about 1.1 and can be in the range between about 1.1 and about 2, for example, depending on the value of the channel length ratio L2 / L1.

[0085] Figure 30A , Figure 30B and Figure 31 Device regions 100C and 100D are shown, in which GAA transistors 72C and 72D are formed with different channel pitches. Figure 30A and Figure 30B The structure shown corresponds to Figure 19B The structure and process are shown. Figure 30A A cross-sectional view is shown, while Figure 30B A top view is shown. (See attached image.) Figure 30A As shown, the vertical channel spacing S2 in device region 100D is greater than the vertical channel spacing S1 in device region 100C. For example... Figure 30B As shown, the horizontal channel spacing S2' in device region 100D is greater than the horizontal channel spacing S1' in device region 100C. According to some embodiments, the channel spacing ratios S2 / S1 and S2' / S1' can be greater than about 1.2, and can be in the range between about 1.2 and about 5.

[0086] Figure 31 The resulting GAA transistors 72C and 72D are shown, and the structure shown corresponds to Figure 21A The structure is shown. According to some embodiments, the thickness difference (T3C-T4C) in device region 100C and the thickness difference (T3D-T4D) in device region 100D can be approximately... Peace Treaty Within the range between.

[0087] Due to the pattern loading effect, the ratio T3D / T4D can be different from and can be greater than the thickness ratio T3C / T4C. The ratio (T3D / T4D) / (T3C / T4C) can be greater than about 1.1 and can be in the range between about 1.1 and about 2, for example, depending on the value of the channel spacing ratio S2 / S1.

[0088] The embodiments of this disclosure have several advantageous features. By oxidizing the sidewall portions of the nanostructure before forming the IL surrounding the nanostructure 22B, the sidewall and corner portions of the IL can be formed to be thicker than the internal portions of the IL within the spacing between the nanostructures. Due to geometric effects, the sidewall and corner portions of the IL at the edge of the nanostructure experience higher carrier concentrations and higher electric fields compared to the edge center. Higher gate-to-channel leakage and increased reliability risks may exist at the edge. By increasing the thickness of the IL at the edge, gate-to-channel leakage and reliability risks are reduced.

[0089] According to some embodiments of the present disclosure, a method includes: forming a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of the plurality of semiconductor nanostructures; forming a hard mask including a top portion located above the plurality of semiconductor nanostructures; an inner portion located between the plurality of semiconductor nanostructures; and a sidewall portion located on the sidewalls of the plurality of semiconductor nanostructures; etching the sidewall portions of the hard mask, wherein at least the top portion of the hard mask is retained; performing a first oxidation process to oxidize the sidewall portions of the semiconductor nanostructures to form a first oxide layer; removing the top portion and the inner portion of the hard mask; and performing a second oxidation process to oxidize the top portion and the bottom portion of the semiconductor nanostructures to form a second oxide layer, wherein the second oxide layer surrounds the remaining portions of the plurality of semiconductor nanostructures, and wherein the second oxide layer includes the first oxide layer.

[0090] In one embodiment, the method further includes performing a processing step on the top portion before the sidewall portions of the hard mask are etched, wherein the sidewall portions and the inner portions are masked from the processing step. In another embodiment, the hard mask comprises a metallic compound including elements selected from the group consisting of oxygen, nitrogen, and combinations thereof, wherein the processing step is performed using a process gas comprising oxygen.

[0091] In one embodiment, the hard mask comprises a metal compound including elements selected from the group consisting of oxygen, nitrogen, and combinations thereof, wherein the processing is performed using a process gas comprising nitrogen. In another embodiment, the processing includes a plasma processing process. In yet another embodiment, the top portion of the hard mask has a first thickness, and the sidewall portions of the hard mask have a second thickness less than the first thickness.

[0092] In an embodiment, the method further includes forming a plurality of sacrificial layers, wherein a plurality of semiconductor nanostructures and a plurality of sacrificial layers are alternately disposed; removing the plurality of sacrificial layers, wherein a hard mask is formed after the plurality of sacrificial layers are removed; and forming a gate stack after the formation of a second oxide layer, wherein the gate stack includes portions located between the plurality of semiconductor nanostructures.

[0093] In one embodiment, when the first oxidation process is performed, at least the internal portion of the hard mask is retained. In another embodiment, after etching the sidewall portions of the hard mask, the sidewalls of the plurality of semiconductor nanostructures are exposed. In yet another embodiment, after etching the sidewall portions of the hard mask, the internal portion of the hard mask is laterally recessed more than the corresponding sidewalls of the plurality of semiconductor nanostructures.

[0094] According to some embodiments of the present disclosure, a method includes forming a plurality of semiconductor nanostructures and a plurality of sacrificial layers, wherein the plurality of semiconductor nanostructures and the plurality of sacrificial layers are alternately disposed; removing the plurality of sacrificial layers to leave spaces between the plurality of semiconductor nanostructures; oxidizing the outer portions of the plurality of semiconductor nanostructures to form an oxide layer surrounding an inner portion of the plurality of semiconductor nanostructures, wherein each oxide layer includes a sidewall portion located on a sidewall of the inner portion of the plurality of semiconductor nanostructures, wherein the sidewall portion has a first thickness; and a top portion located on top of the inner portion of the plurality of semiconductor nanostructures, wherein the top portion has a second thickness less than the first thickness; and forming a gate stack in the spaces between the plurality of semiconductor nanostructures.

[0095] In one embodiment, the sidewall portions of the oxide layer are formed by a greater number of oxidation processes than the top portions. In another embodiment, the oxide layer also includes a bottom portion located at the bottom of the inner portions of the plurality of semiconductor nanostructures, and wherein the bottom portion has a second thickness. In another embodiment, oxidizing the outer portions of the plurality of semiconductor nanostructures includes performing a first oxidation process to oxidize the sidewall portions of the plurality of semiconductor nanostructures, wherein the top and bottom portions of the plurality of semiconductor nanostructures are protected from the first oxidation process.

[0096] In one embodiment, the top and bottom portions of a plurality of semiconductor nanostructures are protected by a hard mask that fills the space between the plurality of semiconductor nanostructures, and the method further includes performing a second oxidation process to oxidize the top portions of the plurality of semiconductor nanostructures to form the top portion of an oxide layer.

[0097] In an embodiment, the method further includes forming a hard mask on a plurality of semiconductor nanostructures prior to a first oxidation process; and partially etching the hard mask. In an embodiment, prior to partially etching the hard mask, a processing step is performed to process the top portion of the hard mask, and the lower portion of the hard mask is protected from processing by the top portion, wherein the lower portion of the hard mask is removed during the partial etching.

[0098] According to some embodiments of the present disclosure, a method includes forming a plurality of semiconductor nanostructures, wherein an upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps with a lower semiconductor nanostructure of the plurality of semiconductor nanostructures; forming source regions and drain regions connected to opposite ends of the plurality of semiconductor nanostructures; forming an oxide layer surrounding the nanostructures of the plurality of semiconductor nanostructures, wherein the oxide layer includes sidewall portions located on the sidewalls of the nanostructures, wherein the sidewall portions have a first thickness; a top portion covering the nanostructures; and a bottom portion covering the nanostructures, wherein the top portion and the bottom portion have a second thickness less than the first thickness; and forming a gate stack, wherein the gate stack includes portions located in the spacing between the plurality of semiconductor nanostructures.

[0099] In one embodiment, the ratio of the first thickness to the second thickness is greater than about 1.1. In another embodiment, the ratio of the first thickness to the second thickness is less than about 4.

[0100] Example 1. A method for adjusting the gate dielectric, comprising:

[0101] Multiple semiconductor nanostructures are formed, wherein the upper semiconductor nanostructure of the multiple semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the multiple semiconductor nanostructures;

[0102] Forming a hard mask, the hard mask comprising:

[0103] The top portion is located on top of the plurality of semiconductor nanostructures;

[0104] The internal portion is located between the plurality of semiconductor nanostructures; and

[0105] The sidewall portion is located on the sidewall of the plurality of semiconductor nanostructures;

[0106] Etch the sidewall portions of the hard mask, wherein at least the top portion of the hard mask is retained;

[0107] A first oxidation process is performed to oxidize the sidewall portions of the semiconductor nanostructure to form a first oxide layer;

[0108] Remove the top and inner portions of the hard mask; and

[0109] A second oxidation process is performed to oxidize the top and bottom portions of the semiconductor nanostructure to form a second oxide layer, wherein the second oxide layer surrounds the remaining portions of the plurality of semiconductor nanostructures, and wherein the second oxide layer comprises the first oxide layer.

[0110] Example 2. The method described in Example 1 further includes:

[0111] Before the sidewall portions of the hard mask are etched, a processing step is performed on the top portion, wherein the sidewall portions and the interior portions are masked from the processing step.

[0112] Example 3. The method according to Example 2, wherein the hard mask comprises a metal compound comprising elements selected from the group consisting of oxygen, nitrogen, and combinations thereof, wherein the processing is performed using a process gas comprising oxygen.

[0113] Example 4. The method according to Example 2, wherein the hard mask comprises a metal compound comprising elements selected from the group consisting of oxygen, nitrogen, and combinations thereof, wherein the processing is performed using a process gas comprising nitrogen.

[0114] Example 5. The method according to Example 2, wherein the processing technology includes a plasma processing technology.

[0115] Example 6. The method according to Example 1, wherein the top portion of the hard mask has a first thickness, and the sidewall portion of the hard mask has a second thickness less than the first thickness.

[0116] Example 7. The method described in Example 1 further includes:

[0117] Multiple sacrificial layers are formed, wherein the multiple semiconductor nanostructures and the multiple sacrificial layers are alternately arranged;

[0118] Remove the plurality of sacrificial layers, wherein the hard mask is formed after the plurality of sacrificial layers have been removed; and

[0119] After the second oxide layer is formed, a gate stack is formed, wherein the gate stack includes portions located between the plurality of semiconductor nanostructures.

[0120] Example 8. The method according to Example 1, wherein, when the first oxidation process is performed, at least the inner portion of the inner portion of the hard mask is retained.

[0121] Example 9. The method according to Example 1, wherein the sidewalls of the plurality of semiconductor nanostructures are exposed after the sidewall portions of the hard mask are etched.

[0122] Example 10. The method according to Example 9, wherein, after etching the sidewall portions of the hard mask, the interior portions of the hard mask are laterally recessed more than the corresponding sidewalls of the plurality of semiconductor nanostructures.

[0123] Example 11. A method for adjusting the gate dielectric, comprising:

[0124] Multiple semiconductor nanostructures and multiple sacrificial layers are formed, wherein the multiple semiconductor nanostructures and the multiple sacrificial layers are alternately arranged;

[0125] Remove the plurality of sacrificial layers to leave space between the plurality of semiconductor nanostructures;

[0126] The outer portions of the plurality of semiconductor nanostructures are oxidized to form an oxide layer surrounding the inner portions of the plurality of semiconductor nanostructures, wherein each of the oxide layers comprises:

[0127] A sidewall portion, located on the sidewall of the inner portion of the plurality of semiconductor nanostructures, wherein the sidewall portion has a first thickness; and

[0128] A top portion, located on top of the inner portion of the plurality of semiconductor nanostructures, wherein the top portion has a second thickness less than the first thickness; and

[0129] A gate stack is formed in the space between the plurality of semiconductor nanostructures.

[0130] Example 12. The method according to Example 11, wherein the sidewall portion of the oxide layer is formed by more oxidation processes than the top portion.

[0131] Example 13. The method according to Example 11, wherein the oxide layer further comprises: a bottom portion located at the bottom of the inner portion of the plurality of semiconductor nanostructures, and wherein the bottom portion has the second thickness.

[0132] Example 14. The method according to Example 11, wherein oxidizing the outer portions of the plurality of semiconductor nanostructures comprises:

[0133] A first oxidation process is performed to oxidize the sidewall portions of the plurality of semiconductor nanostructures, wherein the top and bottom portions of the plurality of semiconductor nanostructures are protected from the first oxidation process.

[0134] Example 15. The method according to Example 14, wherein the top and bottom portions of the plurality of semiconductor nanostructures are protected by a hard mask filling the space between the plurality of semiconductor nanostructures, and the method further includes:

[0135] A second oxidation process is performed to oxidize the top portions of the plurality of semiconductor nanostructures to form the top portion of the oxide layer.

[0136] Example 16. The method according to Example 15 further includes, prior to the first oxidation process:

[0137] The hard mask is formed on the plurality of semiconductor nanostructures; and

[0138] The hard mask was partially etched.

[0139] Example 17. The method according to Example 16 further includes: performing a processing step to process a top portion of the hard mask before partially etching the hard mask, and protecting a lower portion of the hard mask from processing by the top portion, wherein the lower portion of the hard mask is removed during the partial etching of the hard mask.

[0140] Example 18. A method for adjusting the gate dielectric, comprising:

[0141] Multiple semiconductor nanostructures are formed, wherein the upper semiconductor nanostructure of the multiple semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the multiple semiconductor nanostructures;

[0142] Source and drain regions are formed at opposite ends of the plurality of semiconductor nanostructures;

[0143] An oxide layer is formed surrounding the nanostructures in the plurality of semiconductor nanostructures, wherein the oxide layer comprises:

[0144] A sidewall portion is located on the sidewall of the nanostructure, wherein the sidewall portion has a first thickness;

[0145] The top portion covers the nanostructure; and

[0146] The bottom portion covers the nanostructure, wherein the top and bottom portions have a second thickness less than the first thickness; and

[0147] A gate stack is formed, wherein the gate stack includes portions located in the spacing between the plurality of semiconductor nanostructures.

[0148] Example 19. The method according to Example 18, wherein the ratio of the first thickness to the second thickness is greater than about 1.1.

[0149] Example 20. The method according to Example 19, wherein the ratio is less than about 4.

[0150] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for adjusting the gate dielectric, comprising: Multiple semiconductor nanostructures are formed, wherein the upper semiconductor nanostructure of the multiple semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the multiple semiconductor nanostructures; Forming a hard mask, the hard mask comprising: The top portion is located on top of the plurality of semiconductor nanostructures; The internal portion is located between the plurality of semiconductor nanostructures; and The sidewall portion is located on the sidewall of the plurality of semiconductor nanostructures; The sidewall portions of the hard mask are etched, wherein at least the top portion of the hard mask is retained; a first oxidation process is performed to oxidize the sidewall portions of the semiconductor nanostructure to form a first oxide layer; Remove the top and inner portions of the hard mask; and A second oxidation process is performed to oxidize the top and bottom portions of the semiconductor nanostructure to form a second oxide layer, wherein the second oxide layer surrounds the remaining portions of the plurality of semiconductor nanostructures, and wherein the second oxide layer comprises the first oxide layer.

2. The method according to claim 1, further comprising: Before the sidewall portions of the hard mask are etched, a processing step is performed on the top portion, wherein the sidewall portions and the interior portions are masked from the processing step.

3. The method according to claim 2, wherein, The hard mask comprises a metal compound including elements selected from the group consisting of oxygen, nitrogen, and combinations thereof, wherein the processing is performed using a process gas comprising oxygen.

4. The method according to claim 2, wherein, The hard mask comprises a metal compound including elements selected from the group consisting of oxygen, nitrogen, and combinations thereof, wherein the processing is performed using a process gas comprising nitrogen.

5. The method according to claim 2, wherein, The processing technology includes plasma treatment.

6. The method according to claim 1, wherein, The top portion of the hard mask has a first thickness, and the sidewall portion of the hard mask has a second thickness that is less than the first thickness.

7. The method according to claim 1, further comprising: Multiple sacrificial layers are formed, wherein the multiple semiconductor nanostructures and the multiple sacrificial layers are alternately arranged; Remove the plurality of sacrificial layers, wherein the hard mask is formed after the plurality of sacrificial layers have been removed; and After the second oxide layer is formed, a gate stack is formed, wherein the gate stack includes portions located between the plurality of semiconductor nanostructures.

8. The method according to claim 1, wherein, When the first oxidation process is performed, at least the inner portion of the inner part of the hard mask is preserved.

9. A method for adjusting the gate dielectric, comprising: Multiple semiconductor nanostructures and multiple sacrificial layers are formed, wherein the multiple semiconductor nanostructures and the multiple sacrificial layers are alternately arranged; Remove the plurality of sacrificial layers to leave space between the plurality of semiconductor nanostructures; The outer portions of the plurality of semiconductor nanostructures are oxidized to form an oxide layer surrounding the inner portions of the plurality of semiconductor nanostructures, wherein each of the oxide layers comprises: A sidewall portion, located on the sidewall of the inner portion of the plurality of semiconductor nanostructures, wherein the sidewall portion has a first thickness; and A top portion, located on top of the inner portion of the plurality of semiconductor nanostructures, wherein the top portion has a second thickness less than the first thickness; and A gate stack is formed in the space between the plurality of semiconductor nanostructures.

10. A method for adjusting the gate dielectric, comprising: Multiple semiconductor nanostructures are formed, wherein the upper semiconductor nanostructure of the multiple semiconductor nanostructures overlaps with the lower semiconductor nanostructure of the multiple semiconductor nanostructures; Source and drain regions are formed at opposite ends of the plurality of semiconductor nanostructures; An oxide layer is formed surrounding the nanostructures in the plurality of semiconductor nanostructures, wherein the oxide layer comprises: A sidewall portion is located on the sidewall of the nanostructure, wherein the sidewall portion has a first thickness; The top portion covers the nanostructure; and The bottom portion covers the nanostructure, wherein the top and bottom portions have a second thickness less than the first thickness; and A gate stack is formed, wherein the gate stack includes portions located in the spacing between the plurality of semiconductor nanostructures.

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