Semiconductor structure and method of fabricating the same

Abstract

A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure includes a substrate, a gate dielectric layer, a floating gate, a first dielectric layer, and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer, the floating gate having at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed over the first dielectric layer, the control gate at least partially overlapping the floating gate.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a flash memory structure and a method of fabricating the same. BACKGROUND

[0002] Flash memory has been widely developed and used for the past decades. Among various types of flash memory, embedded super flash memory requires high speed write and erase operations. To achieve high speed write and erase operations, a great amount of research and development have been disclosed to fabricate and improve the structure. SUMMARY

[0003] One embodiment of the present invention discloses a semiconductor structure, comprising: a substrate, a gate dielectric layer, a floating gate, a first dielectric layer, and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer, the floating gate having at least one tip, the at least one tip being located on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed over the first dielectric layer, the control gate at least partially overlapping the floating gate.

[0004] Another embodiment of the present invention discloses a method of fabricating a semiconductor structure, comprising the steps of: providing a substrate; forming a gate dielectric layer on the substrate; forming a floating gate on the gate dielectric layer, the floating gate having at least one tip, the at least one tip being located on a top surface of the floating gate; forming a first dielectric layer on the floating gate; and forming a control gate over the first dielectric layer, the control gate at least partially overlapping the floating gate.

[0005] According to the above-mentioned embodiments, the present invention provides a semiconductor structure and a method of fabricating the same. By disposing the floating gate with a tip and the control gate at least partially overlapping the floating gate, the erase path between the floating gate and the control gate can be shortened, further having the advantages of reducing the size of the memory cell, improving the quality of the fabrication process, reducing the operating voltage, improving the durability, high speed write and erase operations, and the like. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following embodiments are described in detail below, together with the accompanying drawings.

[0007] Figures 1A-1H A series of process structure cross-sectional schematic diagrams of fabricating a semiconductor structure shown in the first embodiment of the present invention;

[0008] Figures 2A-2GA series of process structure cross-sectional view illustrations of fabricating a semiconductor structure for the second embodiment of the present specification.

[0009] Symbol explanation

[0010] 10, 20: semiconductor structure

[0011] 100: substrate

[0012] 101: floating gate

[0013] 101a: inner sidewall

[0014] 101b: outer sidewall

[0015] 102: gate dielectric layer

[0016] 103: dielectric layer

[0017] 104: dielectric layer

[0018] 105: control gate

[0019] 111: etching process

[0020] 200: gate dielectric material layer

[0021] 201: floating gate

[0022] 201a: inner sidewall

[0023] 201b: outer sidewall

[0024] 202: gate dielectric layer

[0025] 203: dielectric layer

[0026] 204: dielectric layer

[0027] 205: control gate

[0028] 211: etching process

[0029] 300: patterned hardmask layer

[0030] 300a: patterned portion

[0031] 400: conductive material layer

[0032] 400a: conductive block

[0033] 400b: top recess

[0034] 400c: tip

[0035] 500, 600: dielectric material layer

[0036] 700: layer of conductive material DETAILED DESCRIPTION

[0037] The present specification provides a semiconductor structure and a method of fabricating the same. By providing a floating gate with a pointed end and a control gate at least partially overlapping the floating gate, the erase path between the floating gate and the control gate can be shortened, further having the advantages of reducing the size of the memory cell, improving the quality of the fabrication process, reducing the operating voltage, improving the durability, high-speed write operation and erase operation, and the like. In order to make the above-mentioned embodiments and other objects, features and advantages of the present specification more apparent, several embodiments will be described below in detail with reference to the accompanying drawings.

[0038] However, it must be pointed out that these specific embodiments and methods are not intended to limit the present application. The present application can still be implemented using other features, elements, methods and parameters. The preferred embodiments are presented only to illustrate the technical features of the present application and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and changes without departing from the spirit of the present application based on the description of the following specification. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0039] In addition, the use of ordinal numbers such as "first", "second", "third" and the like in the specification and claims is intended to modify the elements of the claims and does not in itself imply any previous ordinal number or represent the order or sequence of manufacture of one element with respect to another. The use of such ordinal numbers is only intended to clearly distinguish one element with the same name from another.

[0040] Figures 1A-1H is a series of process structure cross-sectional schematic diagrams of fabricating a semiconductor structure 10 according to the first embodiment of the present specification.

[0041] Referring to Figure 1A , first, a substrate 100 is provided. Next, a gate dielectric material layer 200 is formed on the substrate 100. Next, a patterned hard mask layer 300 is formed above the substrate 100. In one embodiment, the patterned hard mask layer 300 includes a plurality of patterned portions 300a, which are located above the gate dielectric material layer 200.

[0042] For example, the substrate 100 can include silicon (Si), germanium (Ge) or gallium arsenide (GaAs), but is not limited thereto. For example, the gate dielectric material layer 200 can include silicon oxide (SiO x) or high dielectric constant material, but not limited thereto. For example, the patterned portions 300a of the patterned hard mask layer 300 can comprise silicon nitride, but not limited thereto. In one embodiment, the step of forming the patterned hard mask layer 300 comprises forming a silicon nitride layer on the gate dielectric material layer 200, and then performing a photoresist etching process to remove a portion of the silicon nitride layer, thereby forming the patterned hard mask layer 300 having a plurality of patterned portions 300a on the gate dielectric material layer 200.

[0043] Referring to Figure 1B , a conductive material layer 400 is deposited on the plurality of patterned portions 300a of the patterned hard mask layer 300. Thereafter, the conductive material layer 400 is planarized so that the conductive material layer 400 fills the recesses or spaces between adjacent two of the patterned portions 300a. For example, the conductive material layer 400 can comprise (but not limited to) doped polysilicon, silicon, germanium, metal or other conductive material.

[0044] Referring to Figure 1C , an etching process 111 is performed using the patterned hard mask layer 300 as a stop layer without using any etching mask to remove a portion of the conductive material layer 400. In one embodiment, the etching process 111 is an anisotropic dry etch, but not limited thereto. By virtue of the etching selectivity difference between the patterned hard mask layer 300 and the conductive material layer 400, the etching process 111 can leave a portion of the conductive material layer 400 between adjacent two of the patterned portions 300a to form a conductive block 400a having a top recess 400b and two sharp ends 400c located on opposite sides of the top recess 400b. In other words, the two sharp ends 400c are respectively adjacent to opposite sidewalls of the conductive block 400a.

[0045] Referring to Figure 1D , the plurality of patterned portions 300a of the patterned hard mask layer 300 are removed to leave a plurality of conductive blocks 400a on the gate dielectric material layer 200. In one embodiment, each of the conductive blocks 400a can be used as a floating gate 101 of the semiconductor structure 10. For example, the thickness of the floating gate 101 can be in the range of to , but not limited thereto. For the purpose of simplicity and clarity, only two conductive blocks 400a are shown in Figure 1D . However, in other embodiments, more conductive blocks 400a can be included on the gate dielectric material layer 200.

[0046] Referring to Figure 1E and Figure 1F, a dielectric material layer 500 and a dielectric material layer 600 are sequentially formed above the floating gate 101. The dielectric material layer 500 and the dielectric material layer 600 can be composed of the same or different materials. For example, the dielectric material layer 500 and the dielectric material layer 600 can include silicon oxide (SiO x ), silicon oxynitride (SiO x N), or a combination thereof, but are not limited thereto.

[0047] For example, in this embodiment, the dielectric material layer 500 and the dielectric material layer 600 can be two silicon oxide layers sequentially formed and covering above the gate dielectric material layer 200 and the floating gate 101 by a deposition fabrication process. In another embodiment, the dielectric material layer 500 can be a silicon oxide dielectric liner layer formed on the surface of the floating gate 101 by a thermal oxidation fabrication process, and the dielectric material layer 600 can be a silicon oxide layer formed and covering above the gate dielectric material layer 200 and the dielectric material layer 500 by a deposition fabrication process.

[0048] Referring to Figure 1G , a conductive material layer 700 is formed on the dielectric material layer 600 by a deposition fabrication process. For example, the conductive material layer 700 can include doped polysilicon, silicon, germanium, metal, or other conductive materials, but is not limited thereto. The thickness of the conductive material layer 700 can be between and , preferably , but is not limited thereto.

[0049] Referring to Figure 1H , an etching fabrication process is performed to complete the preparation of the semiconductor structure 10. In this embodiment, the etching fabrication process is, for example, a polysilicon etching (poly etch), but is not limited thereto. In this embodiment, the semiconductor structure 10 includes the substrate 100, the gate dielectric layer 102, the floating gate 101, the dielectric layer 103, the dielectric layer 104, and the control gate 105 sequentially stacked above the substrate 100.

[0050] In detail, the gate dielectric layer 102 is disposed on the substrate 100. The floating gate 101 is disposed above the gate dielectric layer 102, and the floating gate 101 has two tips 400c located on the top surface of the floating gate 101 and located on opposite sides of the top surface of the floating gate 101. The dielectric layer 103 is disposed on the floating gate 101, the dielectric layer 104 is disposed on the dielectric layer 103, and the control gate 105 is disposed on the dielectric layer 104.

[0051] In this embodiment, the control gate 105 at least partially overlaps the floating gate 101. In other words, in the longitudinal direction, the control gate 105 does not completely overlap the floating gate 101. The control gate 105 partially covers the top surface of the dielectric layer 104. In other words, the control gate 105 does not completely cover the top surface of the dielectric layer 104. The inner sidewall 101a of the floating gate 101 is covered by the dielectric layer 103. For example, the inner sidewall 101a of the floating gate 101 can be completely covered by the dielectric layer 103, but is not limited thereto. The outer sidewall 101b of the floating gate 101 is covered by the dielectric layer 103. For example, the outer sidewall 101b of the floating gate 101 can be completely covered by the dielectric layer 103, but is not limited thereto. The top surface of the floating gate 101 is covered by the dielectric layer 103. For example, the top surface of the floating gate 101 can be completely covered by the dielectric layer 103, but is not limited thereto.

[0052] Figures 2A-2G is a series of process structure cross-sectional schematic views of fabricating a semiconductor structure 20 according to a second embodiment of the present specification. The fabrication method of the semiconductor structure 20 is substantially similar to the fabrication method of the semiconductor structure 10, with the main difference being the fabrication method of the floating gate 201.

[0053] Please refer to Figure 2A , first, a substrate 100 is provided. Next, a gate dielectric material layer 200 is formed on the substrate 100. Next, a patterned hard mask layer 300 is formed above the substrate 100. In one embodiment, the patterned hard mask layer 300 can include a plurality of patterned portions 300a located above the gate dielectric material layer 200.

[0054] For example, the substrate 100 can include silicon (Si), germanium (Ge), or gallium arsenide (GaAs), but is not limited thereto. For example, the gate dielectric material layer 200 can include silicon oxide (SiO x ) or a high dielectric constant material, but is not limited thereto. For example, the patterned portions 300a of the patterned hard mask layer 300 can include silicon nitride, but is not limited thereto. For example, in this embodiment, the step of forming the patterned hard mask layer 300 includes forming a silicon nitride layer on the gate dielectric material layer 200, and then performing a photoresist etching process to remove a portion of the silicon nitride layer, thereby forming the patterned hard mask layer 300 having a plurality of patterned portions 300a above the gate dielectric material layer 200.

[0055] Please refer to Figure 2BIn this embodiment, the patterned hard mask layer 300 can include a single pattern portion 300a. In one embodiment, a conductive material layer 400 is deposited on the single pattern portion 300a of the patterned hard mask layer 300. For example, the conductive material layer 400 can include (but not limited to) doped polysilicon, silicon, germanium, metal or other conductive material.

[0056] Referring to Figure 2C Without using any etch mask, an etch fabrication process 211 is performed to remove a portion of the conductive material layer 400 using the patterned hard mask layer 300 as a stop layer. In one embodiment, the etch fabrication process 211 is, for example, an anisotropic etch or a blanket etch, but not limited thereto. By virtue of the difference in etch selectivity between the patterned hard mask layer 300 and the conductive material layer 400, the etch fabrication process 211 can leave a portion of the conductive material layer 400 on opposite sidewalls of a single pattern portion 300a of the plurality of pattern portions 300a to form two conductive blocks 400a, each having a single tip 400c. In one embodiment, one of the two conductive blocks 400a is used as a floating gate 201. In another embodiment, both of the two conductive blocks 400a are used as floating gates 201.

[0057] After removing the single pattern portion 300a of the patterned hard mask layer 300, the plurality of conductive blocks 400a are left on the gate dielectric material layer 200. In one embodiment, each of the conductive blocks 400a can be used as a floating gate 201 of the semiconductor structure 20. For example, the thickness of the floating gate 201 can be in the range of to but not limited thereto. For the purpose of simplicity and clarity, only two conductive blocks 400a are shown in Figure 2C . However, in other embodiments, more conductive blocks 400a can be included on the gate dielectric material layer 200.

[0058] Referring to Figure 2D and Figure 2E A dielectric material layer 500 and a dielectric material layer 600 are sequentially deposited on the floating gate 201. The dielectric material layer 500 and the dielectric material layer 600 can be composed of the same or different materials. For example, the dielectric material layer 500 and the dielectric material layer 600 can include silicon oxide (SiO x ), silicon oxynitride (SiO x N) or a combination thereof, but not limited thereto.

[0059] For example, in this embodiment, dielectric material layer 500 and dielectric material layer 600 can be two silicon oxide layers sequentially formed and covering the gate dielectric material layer 200 and the floating gate 201 by a deposition process. In another embodiment, dielectric material layer 500 can be a silicon oxide dielectric liner layer formed on the surface of the floating gate 201 by a thermal oxidation process; dielectric material layer 600 is a silicon oxide layer formed and covering the gate dielectric material layer 200 and dielectric layer 500 by a deposition process.

[0060] Please refer to Figure 2F A conductive material layer 700 is formed on the dielectric material layer 600 using a deposition process. For example, the conductive material layer 700 may include, but is not limited to, doped polysilicon, silicon, germanium, metal, or other conductive materials. The thickness of the conductive material layer 700 may be between […]. to Between, the better is But it is not limited to this.

[0061] Please refer to Figure 2G An etching process is performed to fabricate the semiconductor structure 20. In this embodiment, the etching process is, for example, polysilicon etching, but is not limited thereto. In this embodiment, the semiconductor structure 20 includes a substrate 100, a gate dielectric layer 202, a floating gate 201, a dielectric layer 203, a dielectric layer 204, and a control gate 205, which are sequentially stacked on the substrate 100.

[0062] In detail, the gate dielectric layer 202 is disposed on the substrate 100. A floating gate 201 is disposed on the gate dielectric layer 202, and the floating gate 201 has a single tip 400c located on the top surface of the floating gate 201, the single tip 400c being adjacent to the control gate 205. A dielectric layer 203 is disposed on the floating gate 201, a dielectric layer 204 is disposed on the dielectric layer 203, and the control gate 205 is disposed on the dielectric layer 204.

[0063] In the embodiment, the control gate 205 at least partially overlaps the floating gate 201. In other words, in the longitudinal direction, the control gate 205 does not completely overlap the floating gate 201. The control gate 205 partially covers the top surface of the dielectric layer 204. In other words, the control gate 205 does not completely cover the top surface of the dielectric layer 204. The inner sidewall 201a of the floating gate 201 is covered by the dielectric layer 203. For example, the inner sidewall 201a of the floating gate 201 can be completely covered by the dielectric layer 203, but is not limited thereto. The outer sidewall 201b of the floating gate 201 is covered by the dielectric layer 203. For example, the outer sidewall 201b of the floating gate 201 can be completely covered by the dielectric layer 203, but is not limited thereto. The top surface of the floating gate 201 is covered by the dielectric layer 203. For example, the top surface of the floating gate 201 can be completely covered by the dielectric layer 203, but is not limited thereto.

[0064] According to the above embodiment, a semiconductor structure is disclosed. The semiconductor structure includes a substrate, a gate dielectric layer, a floating gate, a first dielectric layer, and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer, and the floating gate has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer, and the control gate at least partially overlaps the floating gate.

[0065] By disposing the floating gate with the tip and the control gate at least partially overlapping the floating gate, the erase path between the floating gate and the control gate can be shortened, and further advantages of reducing the size of the memory cell, improving the quality of the manufacturing process, reducing the operating voltage, improving the durability, high-speed write operation and erase operation, etc. can be achieved.

[0066] Although the present application has been disclosed in the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be defined by the appended claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate; a gate dielectric layer disposed on the substrate; a floating gate disposed on the gate dielectric layer; wherein the floating gate has an outer sidewall, an inner sidewall, and a top surface connecting the outer sidewall and the inner sidewall, the outer sidewall of the floating gate forms a first tip with the top surface, the inner sidewall of the floating gate forms a second tip with the top surface, the first tip is lower than the second tip, and a bottom surface of the floating gate is connected with the gate dielectric layer, and the bottom surface is planar; a first dielectric layer disposed on the floating gate; and a control gate disposed above the first dielectric layer; wherein the control gate at least partially overlaps the floating gate, a portion of the first dielectric layer is between the top surface of the floating gate and the control gate, another portion of the first dielectric layer is between the outer sidewall of the floating gate and the control gate, wherein the first dielectric layer has a first protrusion adjacent to the first tip and a second protrusion adjacent to the second tip, and the first protrusion is lower than the second protrusion.

2. The semiconductor structure of claim 1, further comprising: a second dielectric layer disposed on the first dielectric layer; wherein the control gate partially covers a top surface of the second dielectric layer.

3. The semiconductor structure of claim 1, wherein the inner sidewall of the floating gate is covered by the first dielectric layer.

4. A method of fabricating a semiconductor structure, comprising: providing a substrate; forming a gate dielectric layer on the substrate; forming a floating gate on the gate dielectric layer; wherein the floating gate has an outer sidewall, an inner sidewall, and a top surface connecting the outer sidewall and the inner sidewall, the outer sidewall of the floating gate forms a first tip with the top surface, the inner sidewall of the floating gate forms a second tip with the top surface, the first tip is lower than the second tip, and a bottom surface of the floating gate is connected with the gate dielectric layer, and the bottom surface is planar; forming a first dielectric layer on the floating gate; and forming a control gate above the first dielectric layer; wherein the control gate at least partially overlaps the floating gate, a portion of the first dielectric layer is between the top surface of the floating gate and the control gate, another portion of the first dielectric layer is between the outer sidewall of the floating gate and the control gate; the first dielectric layer has a first protrusion adjacent to the first tip and a second protrusion adjacent to the second tip, and the first protrusion is lower than the second protrusion.

5. The method of claim 4, wherein forming the floating gate comprises: forming a patterned hardmask layer above the substrate; depositing a conductive material layer on the patterned hardmask layer; performing an etch fabrication process using the patterned hardmask layer as a stop layer to remove a portion of the conductive material layer; and removing the patterned hardmask layer to form the floating gate.

6. The method of claim 5, wherein the patterned hardmask layer comprises a plurality of patterned portions; ​ ​ ​ After the etching fabrication process, a portion of the conductive material layer remains on opposite sidewalls of the individual patterned portions of the plurality of patterned portions to form two conductive blocks, each having two tips of different heights.

7. The fabrication method of claim 6, wherein one of the two conductive blocks is used as the floating gate.

8. The fabrication method of claim 5, wherein the patterned hard mask layer comprises silicon nitride.

9. The fabrication method of claim 4, further comprising: forming a second dielectric layer over the first dielectric layer; wherein the control gate portion covers a top surface of the second dielectric layer.

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