Pixels of organic light-emitting diode display devices

Abstract

The pixels of the organic light-emitting diode (OLED) display device include: a first capacitor; a second capacitor; a first transistor configured to generate a drive current; a second transistor configured to transmit a data voltage to a first node; a third transistor configured to connect the first transistor diode; a fourth transistor configured to transmit an initialization voltage to a second node; a fifth transistor configured to transmit a reference voltage to the first node; a sixth transistor configured to couple the drain of the first transistor to the anode of the OLED; a seventh transistor configured to transmit the initialization voltage to the anode of the OLED; and an eighth transistor configured to transmit the initialization voltage to the drain of the first transistor.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device, and more specifically to a pixel of an organic light-emitting diode (OLED) display device and the OLED display device. Background Technology

[0002] Typically, OLED displays can display images at a fixed frame rate (or constant refresh rate), such as approximately 60Hz, 120Hz, or 240Hz. However, the frame rate at which the host processor (e.g., graphics processing unit (GPU) or graphics card) provides frame data to the OLED display can differ from the frame rate of the OLED display. In particular, frame rate mismatch can be exacerbated when the host processor provides frame data for game images (gaming images) that require complex rendering to the OLED display, and this frame rate mismatch can cause tearing of borders in the images displayed on the OLED display.

[0003] To prevent or reduce screen tearing, variable frequency modes (e.g., Free-Sync mode, G-Sync mode, etc.) have been developed in which the host processor provides frame data to the OLED display device at a variable frame frequency by changing the length (or duration) of the blanking period in each frame segment. OLED display devices supporting variable frequency modes can display images synchronously with the variable frame frequency, or can drive the display panel at a variable frame frequency or a variable drive frequency, thereby reducing or preventing screen tearing.

[0004] However, in an OLED display device operating in a variable frequency mode, the brightness of the display panel driven at a first driving frequency and the brightness of the display panel driven at a second driving frequency different from the first driving frequency can be different from each other, and therefore, flicker may occur when the driving frequency of the display panel is changed. Summary of the Invention

[0005] Some embodiments provide a pixel for an organic light-emitting diode (OLED) display device that is applicable not only to a normal mode but also to a variable frequency mode.

[0006] Some embodiments provide an OLED display device applicable not only to normal mode but also to variable frequency mode.

[0007] According to embodiments of this disclosure, a pixel of an OLED display device is provided. The pixel includes: a first capacitor coupled between a first power supply voltage line and a first node; a second capacitor coupled between the first node and a second node; a first transistor configured to generate a drive current based on a voltage at the second node; a second transistor configured to transmit a data voltage to the first node in response to a first scan signal; a third transistor configured to connect the first transistor diode in response to a second scan signal; a fourth transistor configured to transmit an initialization voltage to the second node in response to a third scan signal; a fifth transistor configured to transmit a reference voltage to the first node in response to the second scan signal; a sixth transistor configured to couple the drain of the first transistor and the anode of an organic light-emitting diode in response to an emission signal; a seventh transistor configured to transmit the initialization voltage to the anode of the organic light-emitting diode in response to a fourth scan signal; an eighth transistor configured to transmit the initialization voltage to the drain of the first transistor in response to a fifth scan signal; and the organic light-emitting diode including the anode and a cathode coupled to the second power supply voltage line.

[0008] In an embodiment, the eighth transistor may include: a gate for receiving the fifth scan signal; a source coupled to the drain of the first transistor; and a drain coupled to an initialization voltage line.

[0009] In an embodiment, in a normal mode where the display panel is driven at a fixed frame frequency, the seventh transistor can be turned on to initialize the organic light-emitting diode, and in a variable frequency mode where the display panel is driven at a variable frame frequency, the seventh transistor can be turned off.

[0010] In an embodiment, in a normal mode where the display panel is driven at a fixed frame frequency, the eighth transistor may not be turned on, and in a variable frequency mode where the display panel is driven at a variable frame frequency, the eighth transistor may be turned on to initialize the drain of the first transistor.

[0011] In an embodiment, each frame period in the normal mode of driving the display panel at a fixed frame frequency may include a gate initialization period for initializing the gate of the first transistor, a threshold voltage compensation period for compensating the threshold voltage of the first transistor, a diode initialization period for initializing the organic light-emitting diode, a data writing period for applying the data voltage to the first node, and an emission period for the organic light-emitting diode to emit light. In the variable frequency mode of driving the display panel at a variable frame frequency, each frame period may include the gate initialization period, the threshold voltage compensation period, the drain initialization period for initializing the drain of the first transistor, the data writing period, and the emission period.

[0012] In an embodiment, during the drain initialization period, the transmit signal may have a cutoff level, the fifth scan signal may have a turn-on level, the first scan signal, the second scan signal, the third scan signal, and the fourth scan signal may have the cutoff level, and the eighth transistor may be turned on to apply the initialization voltage to the drain of the first transistor.

[0013] In an embodiment, the duration of the threshold voltage compensation period can be longer than the duration of the data writing period.

[0014] In an embodiment, the diode initialization period may overlap with the gate initialization period or the threshold voltage compensation period.

[0015] In this embodiment, the drain initialization period may be located between the data writing period and the transmission period.

[0016] In an embodiment, the second transistor, the third transistor, the fourth transistor, and the fifth transistor may be dual transistors.

[0017] In an embodiment, a first portion of the first transistor to the eighth transistor may be implemented by a p-type metal-oxide-semiconductor (PMOS) transistor, and a second portion of the first transistor to the eighth transistor may be implemented by an n-type metal-oxide-semiconductor (NMOS) transistor.

[0018] In an embodiment, the initialization voltage transmitted by the fourth transistor may be a first initialization voltage, the initialization voltage transmitted by the seventh transistor may be a second initialization voltage, and the initialization voltage transmitted by the eighth transistor may be a third initialization voltage. The second initialization voltage and the third initialization voltage are different from each other and are transmitted through different initialization voltage lines.

[0019] In one embodiment, the initialization voltage transmitted by the seventh transistor may be a second initialization voltage, and the initialization voltage transmitted by the eighth transistor may be a third initialization voltage. The second initialization voltage and the third initialization voltage are different from each other and are transmitted through different initialization voltage lines.

[0020] In an embodiment, the initialization voltage transmitted by the fourth transistor may be the same voltage as the initialization voltage transmitted by the seventh transistor or the initialization voltage transmitted by the eighth transistor.

[0021] In an embodiment, the initialization voltage transmitted by the fourth transistor, the initialization voltage transmitted by the seventh transistor, and the initialization voltage transmitted by the eighth transistor may be different from each other and may be transmitted through different initialization voltage lines.

[0022] In an embodiment, the signal line transmitting the fourth scan signal and the signal line transmitting the fifth scan signal can be electrically connected to each other.

[0023] In an embodiment, each frame period may include a gate initialization period for initializing the gate of the first transistor, a threshold voltage compensation period for compensating the threshold voltage of the first transistor, a diode and drain initialization period for initializing the organic light-emitting diode and the drain of the first transistor, a data writing period for applying the data voltage to the first node, and an emission period for the organic light-emitting diode to emit light.

[0024] In one embodiment, a pixel of an OLED display device is provided. The pixel includes: a first capacitor coupled between a first power supply voltage line and a first node; a second capacitor coupled between the first node and a second node; a first transistor configured to generate a drive current based on the voltage of the second node; a second transistor configured to transmit a data voltage to the first node in response to a first scan signal; a fourth transistor configured to transmit a first initialization voltage to the second node in response to a third scan signal; a sixth transistor configured to couple the drain of the first transistor and the anode of an organic light-emitting diode in response to an emission signal; an eighth transistor configured to transmit a third initialization voltage to the drain of the first transistor in response to a fifth scan signal; and the organic light-emitting diode including the anode and a cathode coupled to the second power supply voltage line.

[0025] In an embodiment, the pixel may include: a third transistor configured to connect the first transistor diode in response to a second scan signal; a fifth transistor configured to transmit a reference voltage to the first node in response to the second scan signal; and a seventh transistor configured to transmit a second initialization voltage to the anode of the organic light-emitting diode in response to a fourth scan signal.

[0026] According to an embodiment, an OLED display device is provided, the OLED display device including a display panel, the display panel including a plurality of pixels, a data driver configured to provide a data voltage to each of the plurality of pixels, a scan driver configured to provide a gate write signal, a gate initialization signal and a gate drain signal to each of the plurality of pixels, an emitter driver configured to provide an emitter signal to each of the plurality of pixels, and a controller configured to control the data driver, the scan driver and the emitter driver. Each of the plurality of pixels includes: a first capacitor coupled between a first power supply voltage line and a first node; a second capacitor coupled between the first node and a second node; a driving transistor configured to generate a driving current based on the voltage of the second node; a switching transistor configured to transmit the data voltage to the first node in response to the gate write signal; a gate initialization transistor configured to transmit the gate initialization voltage to the second node in response to the gate initialization signal; an emitter transistor configured to couple the drain of the driving transistor and the anode of an organic light-emitting diode in response to the emitter signal; a drain initialization transistor configured to transmit a drain initialization voltage to the drain of the driving transistor in response to the gate drain signal; and the organic light-emitting diode including the anode and a cathode coupled to the second power supply voltage line.

[0027] According to an embodiment, a pixel of an OLED display device is provided. The pixel of the OLED display device includes: a first capacitor coupled between a first power supply voltage line and a first node; a second capacitor coupled between the first node and a second node; a first transistor coupled between the first power supply voltage line and a third node; a second transistor coupled between a data line and the first node; a third transistor coupled between the second node and the third node; a fourth transistor coupled between the second node and an initialization voltage line; a fifth transistor coupled between the first node and a reference voltage line; a sixth transistor coupled between the third node and the anode of an organic light-emitting diode (OLED); a seventh transistor coupled between the initialization voltage line and the anode of the OLED; an eighth transistor coupled between the initialization voltage line and the third node; and the OLED including the anode and a cathode coupled to the second power supply voltage line.

[0028] In one embodiment, the control electrode of the seventh transistor and the control electrode of the eighth transistor can be coupled to different scan lines, which are activated at different time periods.

[0029] In one embodiment, the control electrode of the seventh transistor and the control electrode of the eighth transistor may be coupled to the same scan line.

[0030] As described above, the pixels of the OLED display device according to the embodiments may include a first capacitor coupled between a first power supply voltage line and a first node; a second capacitor coupled between the first node and a second node; a first transistor configured to generate a drive current based on the voltage of the second node; a second transistor configured to transmit a data voltage to the first node in response to a first scan signal; a third transistor configured to connect the first transistor diode in response to a second scan signal; a fourth transistor configured to transmit an initialization voltage to the second node in response to a third scan signal; a fifth transistor configured to transmit a reference voltage to the first node in response to the second scan signal; a sixth transistor configured to couple the drain of the first transistor and the anode of the organic light-emitting diode in response to an emission signal; a seventh transistor configured to transmit the initialization voltage to the anode of the organic light-emitting diode in response to a fourth scan signal; an eighth transistor configured to transmit the initialization voltage to the drain of the first transistor in response to a fifth scan signal; and the organic light-emitting diode including the anode and a cathode coupled to the second power supply voltage line. Therefore, the pixel can emit light with substantially constant brightness not only in normal mode but also in variable frequency mode, and is thus applicable not only to the normal mode but also to the variable frequency mode. Attached Figure Description

[0031] The illustrative, non-limiting embodiments will become clearer from the following detailed description and in conjunction with the accompanying drawings.

[0032] Figure 1 This is a circuit diagram illustrating the pixels of an organic light-emitting diode (OLED) display device according to an embodiment.

[0033] Figure 2 This is a diagram illustrating an example of the G value of a conventional display panel that initializes each pixel of an OLED in each frame period.

[0034] Figure 3 The diagram shows examples of the brightness of a conventional display panel driven at a frame rate of approximately 120 Hz and examples of the brightness of a conventional display panel driven at a frame rate of approximately 60 Hz.

[0035] Figure 4 The figures illustrate examples of the brightness of a conventional display panel in normal mode, an example of the brightness of a conventional display panel in variable frequency mode, an example of the brightness of a display panel in normal mode according to an embodiment, and an example of the brightness of a display panel in variable frequency mode according to an embodiment.

[0036] Figure 5It is a timing diagram used to describe the operation of pixels in normal mode according to an embodiment.

[0037] Figure 6 This is a circuit diagram used to describe an example of pixel operation during the gate initialization period.

[0038] Figure 7 This is a circuit diagram used to describe an example of pixel operation during a threshold voltage compensation period.

[0039] Figure 8 This is a circuit diagram used to describe an example of pixel operation during the diode initialization period.

[0040] Figure 9 This is a circuit diagram used to describe an example of pixel operation during a data writing period.

[0041] Figure 10 This is a circuit diagram used to describe an example of pixel operation during the emission period.

[0042] Figure 11 It is a timing diagram used to describe the operation of pixels in variable frequency mode according to an embodiment.

[0043] Figure 12 This is a circuit diagram used to describe an example of pixel operation during the drain initialization period.

[0044] Figure 13 It is a timing diagram used to describe the operation of pixels in normal mode according to an embodiment.

[0045] Figure 14 It is a timing diagram used to describe the operation of pixels in normal mode according to an embodiment.

[0046] Figure 15 It is a timing diagram used to describe the operation of pixels in variable frequency mode according to an embodiment.

[0047] Figure 16 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0048] Figure 17 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0049] Figure 18 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0050] Figure 19 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0051] Figure 20This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0052] Figure 21 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0053] Figure 22 This is a timing diagram used to describe the operation of pixels in an OLED display device according to an embodiment.

[0054] Figure 23 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0055] Figure 24 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0056] Figure 25 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0057] Figure 26 This is a block diagram illustrating an OLED display device according to an embodiment.

[0058] Figure 27 This is a diagram illustrating the operation of an OLED display device in a variable frequency mode according to an embodiment.

[0059] Figure 28 It is an electronic device including an OLED display device according to an embodiment. Detailed Implementation

[0060] In the following sections, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0061] Figure 1 This is a circuit diagram illustrating the pixels of an organic light-emitting diode (OLED) display device according to an embodiment. Figure 2 This is a diagram illustrating an example of how the G value of a conventional display panel initializes each pixel of an OLED within each frame period. Figure 3 The diagrams show examples of the brightness of a conventional display panel driven at a frame rate of approximately 120Hz and an example of the brightness of a conventional display panel driven at a frame rate of approximately 60Hz. Figure 4 The figures illustrate examples of the brightness of a conventional display panel in normal mode, an example of the brightness of a conventional display panel in variable frequency mode, an example of the brightness of a display panel in normal mode according to an embodiment, and an example of the brightness of a display panel in variable frequency mode according to an embodiment.

[0062] Reference Figure 1According to an embodiment, the pixel 100 of the OLED display device may include a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an organic light-emitting diode EL.

[0063] In some embodiments, such as Figure 1 As shown, the first initialization voltage VINT1 applied to the gate of the first transistor T1 via the fourth transistor T4, the second initialization voltage VINT2 applied to the anode of the organic light-emitting diode EL via the seventh transistor T7, and the third initialization voltage VINT3 applied to the drain of the first transistor T1 via the eighth transistor T8 can be the same initialization voltage VINT provided to the pixel 100 through the same line. Furthermore, in some embodiments, such as... Figure 1 As shown, the first transistor T1 to the eighth transistor T8 can be implemented using, but is not limited to, p-type metal-oxide-semiconductor (PMOS) transistors.

[0064] A first capacitor C1 may be coupled between a line of a first power supply voltage ELVDD (e.g., a high power supply voltage) (i.e., the first power supply voltage line) and a first node N1. In some embodiments, the first capacitor C1 may include a first electrode coupled to the line of the first power supply voltage ELVDD and a second electrode coupled to the first node N1.

[0065] The second capacitor C2 may be coupled between the first node N1 and the second node N2. In some embodiments, the second capacitor C2 may include a first electrode coupled to the first node N1 and a second electrode coupled to the second node N2.

[0066] The first transistor T1 can generate a drive current based on the voltage of the second node N2 or the voltage of the second electrode of the second capacitor C2. The first transistor T1 can be referred to as a drive transistor. In some embodiments, the first transistor T1 may include a gate coupled to the second node N2, a source coupled to a line coupled to the first power supply voltage ELVDD, and a drain coupled to the third transistor T3, the sixth transistor T6, and the eighth transistor T8. The point where the drain of the first transistor T1 is coupled to the third transistor T3, or the point where the drain of the first transistor T1 is coupled to the sixth transistor T6 and the eighth transistor T8, can be referred to as the third node.

[0067] The second transistor T2 can apply the data voltage VDAT of the data line DL to the first node N1 in response to the first scan signal SCAN1. The second transistor T2 can be referred to as a switching transistor or a scan transistor, and the first scan signal SCAN1 can be referred to as a gate write signal GW. In some embodiments, the second transistor T2 may include a gate that receives the first scan signal SCAN1, a source coupled to the first node N1, and a drain coupled to the data line DL.

[0068] The third transistor T3 can connect the diode of the first transistor T1 in response to the second scan signal SCAN2. The third transistor T3 can be referred to as a compensation transistor, and the second scan signal SCAN2 can be referred to as a gate compensation signal GC. In some embodiments, the third transistor T3 may include a gate that receives the second scan signal SCAN2, a source coupled to the drain of the first transistor T1, and a drain coupled to the second node N2.

[0069] The fourth transistor T4 can transmit the first initialization voltage VINT1 to the second node N2 in response to the third scan signal SCAN3. The fourth transistor T4 can be referred to as the gate initialization transistor, and the third scan signal SCAN3 can be referred to as the gate initialization signal GI. In some embodiments, the fourth transistor T4 may include a gate receiving the third scan signal SCAN3, a source coupled to the second node N2, and a drain coupled to the line of the first initialization voltage VINT1.

[0070] The fifth transistor T5 can apply a reference voltage VREF to the first node N1 in response to the second scan signal SCAN2. The fifth transistor T5 can be referred to as the reference transistor. In some embodiments, the fifth transistor T5 may include a gate receiving the second scan signal SCAN2, a source coupled to a line connected to the reference voltage VREF, and a drain coupled to the first node N1.

[0071] The sixth transistor T6 can couple the drain of the first transistor T1 and the anode of the organic light-emitting diode EL in response to the emission signal EM. Therefore, the drive current generated by the first transistor T1 can be provided to the organic light-emitting diode EL. The sixth transistor T6 can be referred to as the emission transistor. In some embodiments, the sixth transistor T6 may include a gate for receiving the emission signal EM, a source coupled to the drain of the first transistor T1, and a drain coupled to the anode of the organic light-emitting diode EL.

[0072] The seventh transistor T7 can transmit the second initialization voltage VINT2 to the anode of the organic light-emitting diode EL in response to the fourth scan signal SCAN4. The seventh transistor T7 can be referred to as the diode initialization transistor, and the fourth scan signal SCAN4 can be referred to as the gate bypass signal GB. In some embodiments, the seventh transistor T7 may include a gate (control electrode) receiving the fourth scan signal SCAN4, a source coupled to the anode of the organic light-emitting diode EL, and a drain coupled to the line of the second initialization voltage VINT2.

[0073] The eighth transistor T8 can transmit the third initialization voltage VINT3 to the drain of the first transistor T1 in response to the fifth scan signal SCAN5. The eighth transistor T8 can be referred to as the drain initialization transistor, and the fifth scan signal SCAN5 can be referred to as the gate-drain signal GD. In some embodiments, the eighth transistor T8 may include a gate (control electrode) receiving the fifth scan signal SCAN5, a source coupled to the drain of the first transistor T1, and a drain coupled to the line of the third initialization voltage VINT3.

[0074] While the sixth transistor T6 is turned on, the organic light-emitting diode EL can emit light based on the drive current generated by the first transistor T1. In some embodiments, the organic light-emitting diode EL may include an anode coupled to the sixth transistor T6 and the seventh transistor T7, and a cathode coupled to a line (i.e., the second power supply voltage line) coupled to a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0075] The OLED display device according to the embodiment can support not only a normal mode in which the display panel including pixels 100 is driven at a fixed frame frequency (e.g., approximately 60Hz, approximately 120Hz, or approximately 240Hz, etc.), but also a variable frequency mode in which the display panel is driven at a variable frame frequency. For example, the variable frame frequency may have, but is not limited to, a range from approximately 1Hz to approximately 120Hz, a range from approximately 1Hz to approximately 240Hz, etc.

[0076] In variable frequency mode, even when displaying images with the same grayscale level, the brightness of a conventional display panel that initializes 100 organic light-emitting diodes (OLEDs) can be changed according to the frequency. Figure 2 An example of the G value is shown for a conventional display panel where the maximum frequency of the variable frame rate is 120Hz. Figure 2In the example, the G value can be determined using the equation “G-VALUE = (LUM(MAXFREQ) - LUM(MAXFREQ / 2)) / LUM(MAXFREQ)”, where G-VALUE represents the G value, LUM(MAXFREQ) represents the brightness of a conventional display panel driven at its maximum frequency (e.g., approximately 120Hz) with a variable frame rate, and LUM(MAXFREQ / 2) represents the brightness of a conventional display panel driven at half the maximum frequency (e.g., approximately 60Hz). Figure 2 In the example, the G value of a conventional display panel can have an absolute value of less than approximately 4% at gray levels greater than approximately 60 gray levels, but can have an absolute value greater than approximately 4% at gray levels less than or equal to approximately 60 gray levels. Therefore, in variable frequency mode, when displaying low gray level images (e.g., below 60 gray levels), a conventional display panel may have a large brightness difference between different drive frequencies (or different frame frequencies), and flicker may occur when the drive frequency (or frame frequency) of the conventional display panel changes.

[0077] like Figure 3As shown, because the number of brightness valleys (see solid line 210) in a conventional display panel varies between different driving frequencies, it can lead to brightness differences between different driving frequencies at low gray levels (e.g., gray levels below 60 gray levels). Here, a brightness valley refers to the phenomenon where a pixel emits light below the target brightness during the initial period of a frame. Since the organic light-emitting diode (OLED) is initialized or discharged at the beginning of each frame period, the OLED cannot emit light until its parasitic capacitor is charged, and therefore the conventional display panel may have brightness valleys in each frame period. When displaying a high gray level image (e.g., above 60 gray levels), because the driving current of the first transistor T1 is relatively high, the time period from the beginning of the frame period to the full charging of the parasitic capacitor of the OLED can be relatively short. Therefore, after the parasitic capacitor of the OLED is charged, the brightness of the conventional display panel may be relatively high, and thus, the brightness valley at the beginning of the frame period may have virtually no impact on the average brightness in the frame period. However, when displaying low grayscale images (e.g., below 60 grayscale levels), because the drive current of the first transistor T1 is relatively low, the time period from the start of a frame segment to the complete charging of the parasitic capacitor of the organic light-emitting diode EL can be relatively long. Therefore, after the parasitic capacitor of the organic light-emitting diode EL is charged, the brightness of the conventional display panel may be relatively low, and thus, the brightness valley at the start of a frame segment may affect the average brightness within that frame segment. Therefore, when displaying low grayscale images, if the conventional display panel is driven at different drive frequencies, the number of frame segments within the same time period may differ, the number of brightness valleys within the same time period may differ, and therefore, the average brightness within the same time period may differ.

[0078] For example, in displaying an image with approximately 16 gray levels Figure 3In the example, a conventional display panel driven at 120Hz can have two frame periods FP1 during the same time period, and a conventional display panel driven at approximately 60Hz can have one frame period FP2. Therefore, in a conventional display panel, since each pixel initializes an organic light-emitting diode (OLED) in each frame period FP1 and FP2, and the parasitic capacitor of the OLED is discharged in each frame period FP1 and FP2, the OLED does not emit light until the parasitic capacitor is charged by the driving current generated by the first transistor T1, and the conventional display panel may have brightness valleys in each frame period FP1 and FP2 (see solid line 210). That is, when displaying a low grayscale image (e.g., 16 grayscale levels), a conventional display panel driven at approximately 120Hz can have two brightness valleys during the same time period, and a conventional display panel driven at approximately 60Hz can have one brightness valley (see alternating long and short dashed lines 230), and therefore, the brightness of a conventional display panel driven at approximately 60Hz can be higher than the brightness of a conventional display panel driven at approximately 120Hz.

[0079] The brightness difference between different driving frequencies may not cause flicker in normal mode when a conventional display panel is driven at a fixed frame rate, but it may cause flicker in variable frequency mode when a conventional display panel is driven at a variable frame rate. For example, as Figure 4 As shown in Figure 310, in normal mode, a conventional OLED display device receives frame data FDAT as input image data IDAT at a fixed frame frequency (e.g., approximately 120 Hz). In each frame period FP1, FP2, FP3, and FP4, each pixel of the conventional display panel can initialize an organic light-emitting diode in response to a fourth scan signal (or a gate bypass signal), and the conventional display panel can have a brightness valley in each frame period FP1, FP2, FP3, and FP4 with a constant time length. In this case, the conventional display panel may have a uniform average brightness during a specific time period and therefore may not experience flicker. However, as... Figure 4 As shown in Figure 320, in a conventional OLED display device, by varying the frame frequency, the number of brightness valleys in each specific time period may be changed in a variable frequency mode that receives frame data FDAT as input image data IDAT at a variable frame frequency (e.g., approximately 120 Hz in the first frame period FP1 and the third frame period FP3, and approximately 60 Hz in the second frame period FP2). The average brightness of the conventional display panel for a specific time period may be changed, and therefore, flicker may occur (e.g., between the second frame period FP2, which corresponds to approximately 60 Hz, and the third frame period FP3, which corresponds to approximately 120 Hz).

[0080] However, in the OLED display device according to the embodiment, in order to prevent or reduce flicker, the seventh transistor T7 can be turned on in normal mode to initialize the organic light-emitting diode EL, but can be turned off in variable frequency mode. Therefore, as Figure 4 As shown in Figure 330, in the normal mode of the OLED display device according to the embodiment, where frame data FDAT is received as input image data IDAT at a fixed frame frequency (e.g., approximately 120 Hz), pixel 100 according to the embodiment can initialize organic light-emitting diodes EL in response to a fourth scan signal SCAN4 (or gate bypass signal GB) in each frame period FP1, FP2, FP3, and FP4 having a fixed time length. However, as Figure 4 As shown in Figure 340, in the variable frequency mode of the OLED display device according to the embodiment, which receives frame data FDAT as input image data IDAT at a variable frame frequency (e.g., approximately 120Hz in the first frame period FP1 and the third frame period FP3, and approximately 60Hz in the second frame period FP2), pixel 100 according to the embodiment may not receive the fourth scan signal SCAN4, the seventh transistor T7 of pixel 100 may not be turned on, and the organic light-emitting diode EL of pixel 100 may not be initialized. Therefore, in the variable frequency mode, the display panel including pixel 100 according to the embodiment may not have a brightness valley 350, thus preventing or reducing flicker caused by the brightness difference between different driving frequencies.

[0081] However, if the organic light-emitting diode (OLED) EL of pixel 100 is not initialized, or if the parasitic capacitor of the OLED EL is not discharged, the OLED EL may emit light momentarily (or instantaneously) during each frame period FP1, FP2, and FP3, and due to the charge remaining on the drain of the first transistor T1, the display panel including pixel 100 may have a momentary (or instantaneous) brightness peak 360. However, in the OLED display device according to the embodiment, the eighth transistor T8 may not be turned on in normal mode, but may be turned on in variable frequency mode to initialize the drain of the first transistor T1. Therefore, as... Figure 4 As shown in Figure 330, in normal mode, according to the embodiment, pixel 100 may not receive the fifth scan signal SCAN5, the eighth transistor T8 of pixel 100 may not be turned on, and the drain of the first transistor T1 of pixel 100 may not be initialized. However, as Figure 4As shown in Figure 340, in variable frequency mode, according to the embodiment, pixel 100 can initialize the drain of the first transistor T1 in response to the fifth scan signal SCAN5 (or gate-drain signal GD) in each frame period FP1, FP2, and FP3. Therefore, the charge remaining on the drain of the first transistor T1 can be removed, and the display panel including pixel 100 may not have an instantaneous brightness peak 360. Therefore, the display panel including pixel 100 according to the embodiment has a substantially uniform brightness 370 in variable frequency mode.

[0082] As described above, the pixel 100 according to the embodiment may include not only a seventh transistor T7 for diode initialization (or anode initialization), but also an eighth transistor T8 for drain initialization. Furthermore, in variable frequency mode, diode initialization via the seventh transistor T7 may be omitted, and drain initialization via the eighth transistor T8 may be performed. Therefore, the pixel 100 according to the embodiment has a substantially uniform brightness 370 (especially at low gray levels). Thus, the pixel 100 according to the embodiment is suitable not only for normal mode but also for variable frequency mode.

[0083] Figure 5 This is a timing diagram used to describe the operation of pixels in normal mode according to an embodiment. Figure 6 This is a circuit diagram used to describe an example of pixel operation during the gate initialization period. Figure 7 This is a circuit diagram illustrating an example of pixel operation during a threshold voltage compensation period. Figure 8 This is a circuit diagram illustrating an example of pixel operation during the diode initialization period. Figure 9 This is a circuit diagram illustrating an example of pixel operation during a data write period, and Figure 10 This is a circuit diagram used to describe an example of pixel operation during the emission period.

[0084] Reference Figure 1 and Figure 5 In the normal mode of driving the display panel at a fixed frame frequency, each frame period FP includes a gate initialization period GIP for initializing the gate of the first transistor T1, a threshold voltage compensation period VCP for compensating the threshold voltage of the first transistor T1, a diode initialization period AIP for initializing the organic light-emitting diode EL, a data writing period DWP for applying the data voltage VDAT to the first node N1, and an emission period EMP for the organic light-emitting diode EL to emit light. In some embodiments, such as Figure 5As shown, the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, the fifth scan signal SCAN5, and the transmit signal EM can be, but are not limited to, active low signals having a low level as an on level and a high level as an off level.

[0085] During the gate initialization period (GIP), the transmit signal EM can be at a cutoff level, the third scan signal SCAN3 can be at a conduction level, and the first scan signal SCAN1, the second scan signal SCAN2, the fourth scan signal SCAN4, and the fifth scan signal SCAN5 can be at a cutoff level. During the gate initialization period (GIP), as follows... Figure 6 As shown, the fourth transistor T4 can be turned on in response to the third scan signal SCAN3 having an on level. Therefore, the fourth transistor T4 can apply an initialization voltage VINT (or a first initialization voltage VINT1) to the gate of the second node N2 or the first transistor T1, and the gate of the first transistor T1 can be initialized. In some embodiments, the length of the gate initialization period GIP can correspond to, but is not limited to, three horizontal times (or 3H times). Here, one horizontal time (or 1H time) can be the time allocated to a row of pixels 100, and a frame period FP can include multiple horizontal times, the number of which is greater than or equal to the number of pixel rows of the display panel. Furthermore, in some embodiments, a horizontal time (or 1H time) of the OLED display device can be determined based on the fixed frame frequency in normal mode (or the maximum frequency of the variable frame frequency in variable frequency mode) and the number of pixel rows of the display panel.

[0086] During the threshold voltage compensation period VCP, the transmit signal EM can have a cutoff level, the second scan signal SCAN2 can have a conduction level, and the first scan signal SCAN1, the third scan signal SCAN3, the fourth scan signal SCAN4, and the fifth scan signal SCAN5 can have a cutoff level. During the threshold voltage compensation period VCP, as... Figure 7As shown, the third transistor T3 and the fifth transistor T5 can be turned on in response to a second scan signal SCAN2 having a conduction level. Therefore, the fifth transistor T5 can apply a reference voltage VREF to the first electrode of the first node N1 or the second capacitor C2. In some embodiments, the reference voltage VREF can have a voltage level substantially the same as the voltage level of the first power supply voltage ELVDD, but the voltage level of the reference voltage VREF is not limited to this. Furthermore, the third transistor T3 can diode-connect the first transistor T1. Therefore, a voltage ELVDD-VTH, which is the first power supply voltage ELVDD minus the threshold voltage VTH, can be applied to the second electrode of the second node N2 or the second capacitor C2 through the diode-connected first transistor T1. In some embodiments, the duration of the threshold voltage compensation period VCP can correspond to, but is not limited to, three level times (or 3H time). Furthermore, in some embodiments, as... Figure 5 As shown, the threshold voltage compensation period VCP can be separated from the data write period DWP, and the threshold voltage compensation period VCP can have a duration, for example, a horizontal time three times longer than the duration of the data write period DWP (e.g., corresponding to a 1H time). Therefore, since the threshold voltage compensation period VCP has a longer duration than the duration of the data write period DWP, the threshold voltage VTH of the first transistor T1 can be adequately compensated.

[0087] During the diode initialization period (AIP) (or anode initialization period), the transmit signal EM can have a cutoff level, the fourth scan signal SCAN4 can have a conduction level, and the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the fifth scan signal SCAN5 can have a cutoff level. During the diode initialization period (AIP), as follows... Figure 8 As shown, the seventh transistor T7 can be turned on in response to the fourth scan signal SCAN4, which has an on-level. Therefore, an initialization voltage VINT (or a second initialization voltage VINT2) can be applied to the anode of the organic light-emitting diode EL through the seventh transistor T7, and the organic light-emitting diode EL can be initialized. In some embodiments, the duration of the diode initialization period AIP can correspond to, but is not limited to, a horizontal time (or 1H time).

[0088] During the data writing period (DWP), the transmit signal EM can have a cutoff level, the first scan signal SCAN1 can have a conduction level, and the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the fifth scan signal SCAN5 can have a cutoff level. For example... Figure 9As shown, during the data write period DWP, the second transistor T2 can be turned on in response to the first scan signal SCAN1, which has an on level. Therefore, the second transistor T2 can apply the data voltage VDAT to either the first node N1 or the first electrode of the second capacitor C2. Consequently, the voltage at the first electrode of the second capacitor C2 can change the difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF, from the reference voltage VREF to the data voltage VDAT. If the voltage at the first electrode of the second capacitor C2 changes the difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF, then the floating voltage at the second electrode of the second capacitor C2 can also change the difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF. Therefore, during the data write period DWP, the voltage at the second electrode of the second capacitor C2 or the voltage at the second node N2 can become the voltage ELVDD-VTH+VDAT-VREF, which is the sum of the difference VDAT-VREF between the data voltage VDAT and the reference voltage VREF and the voltage ELVDD-VTH obtained by subtracting the threshold voltage VTH from the first power supply voltage ELVDD. In some embodiments, the duration of the data write period DWP can correspond to, but is not limited to, a horizontal time (or 1 hour).

[0089] During the transmit phase (EMP), the transmit signal EM can be on, and the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and the fifth scan signal SCAN5 can be off. During the transmit phase (EMP), such as... Figure 10As shown, the sixth transistor T6 can be turned on in response to a transmit signal EM having a conduction level. Therefore, the first transistor T1 can generate a drive current IDR based on the voltage ELVDD-VTH+VDAT-VREF of the second node N2 or the voltage ELVDD-VTH+VDAT-VREF of the second electrode of the second capacitor C2. The sixth transistor T6 can provide the drive current IDR to the organic light-emitting diode EL, and the organic light-emitting diode EL can emit light based on the drive current IDR. The drive current IDR generated by the first transistor T1 can be determined according to the equation “β / 2*(VSG-VTH)^2”. Here, β can be the transistor gain determined by the mobility, capacitance, width, and length of the first transistor T1, VSG can be the source-gate voltage of the first transistor T1, and VTH can be the threshold voltage of the first transistor T1. Furthermore, since the source voltage of the first transistor T1 is the first power supply voltage ELVDD, and the gate voltage of the first transistor T1 is either the voltage of the second node N2 or "ELVDD-VTH+VDAT-VREF", "VSG-VTH" can be "ELVDD-ELVDD+VTH-VDAT+VREF-VTH=VREF-VDAT". Therefore, the drive current IDR can be determined based on the reference voltage VREF and the data voltage VDAT, regardless of the threshold voltage VTH of the first transistor T1.

[0090] Figure 11 This is a timing diagram used to describe the operation of pixels in variable frequency mode according to an embodiment, and Figure 12 This is a circuit diagram used to describe an example of pixel operation during the drain initialization period.

[0091] Reference Figure 1 and Figure 11 In the variable frequency mode of driving the display panel with a variable frame frequency, each frame period FP may include a gate initialization period GIP, a threshold voltage compensation period VCP, a drain initialization period DIP for initializing the drain of the first transistor T1, a data write period DWP, and an emission period EMP. In the variable frequency mode, the operation of pixel 100 during the gate initialization period GIP, threshold voltage compensation period VCP, data write period DWP, and emission period EMP can be as described above. Figure 5 , Figure 6 , Figure 7 , Figure 9 and Figure 10 The operation of pixel 100 in normal mode is basically the same as described.

[0092] During the drain initialization phase (DIP), the transmit signal EM can have a cutoff level, the fifth scan signal SCAN5 can have a conduction level, and the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, and the fourth scan signal SCAN4 can have a cutoff level. During the drain initialization phase (DIP), as follows... Figure 12 As shown, the eighth transistor T8 can be turned on in response to the fifth scan signal SCAN5, which has an on level. Therefore, the eighth transistor T8 can apply an initialization voltage VINT (or a third initialization voltage VINT3) to the drain of the first transistor T1, and the drain of the first transistor T1 can be initialized. In some embodiments, the duration of the drain initialization period DIP can correspond to, but is not limited to, a horizontal time (or 1H time).

[0093] Figure 13 This is a timing diagram used to describe the operation of pixels in normal mode according to an embodiment, and Figure 14 It is a timing diagram used to describe the operation of pixels in normal mode according to an embodiment.

[0094] Reference Figure 13 and Figure 14 In some embodiments, the diode initialization period AIP in normal mode may overlap with the gate initialization period GIP or the threshold voltage compensation period VCP. In an example, such as... Figure 13 As shown, the diode initialization period AIP can overlap with the gate initialization period GIP. In another example, as... Figure 14 As shown, the diode initialization period AIP can overlap with the threshold voltage compensation period VCP.

[0095] Figure 15 It is a timing diagram used to describe the operation of pixels in variable frequency mode according to an embodiment.

[0096] Reference Figure 15 In some embodiments, the drain initialization period (DIP) in variable frequency mode can be located between the data write period (DWP) and the transmit period (EMP). For example, as... Figure 15 As shown, the drain initialization period (DIP) can be located after the data write period (DWP) and before the transmit period (EMP).

[0097] Figure 16 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0098] Reference Figure 16According to an embodiment, the pixel 400 of the OLED display device may include a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2D, a third transistor T3D, a fourth transistor T4D, a fifth transistor T5D, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an organic light-emitting diode EL. Except that at least one of the first transistor T1, second transistor T2D, third transistor T3D, fourth transistor T4D, fifth transistor T5D, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be implemented using a dual-transistor configuration with two sub-transistors connected in series, Figure 16 The 400 pixels can have the same Figure 1 Similar configuration and operation to the 100 pixel version.

[0099] In some embodiments, such as Figure 16 As shown, each of the second transistor T2D, the third transistor T3D, the fourth transistor T4D, and the fifth transistor T5D can be implemented using a dual transistor configuration including sub-transistors connected in series. Since the second transistor T2D to the fifth transistor T5D, directly coupled to the first capacitor C1 and the second capacitor C2, are implemented using a dual transistor configuration, leakage current flowing from / to the first capacitor C1 and the second capacitor C2 through the second transistor T2D to the fifth transistor T5D can be reduced. Therefore, in variable frequency mode, pixel 400, or a display panel including pixel 400, can display an image with uniform brightness during a frame period.

[0100] Figure 17 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0101] Reference Figure 17 According to an embodiment, the pixel 500 of the OLED display device may include a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2N, a third transistor T3N, a fourth transistor T4N, a fifth transistor T5N, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an organic light-emitting diode EL. Except for the first portions of the first transistor T1, second transistor T2N, third transistor T3N, fourth transistor T4N, fifth transistor T5N, sixth transistor T6, seventh transistor T7, and eighth transistor T8, which can be implemented using p-type metal-oxide-semiconductor (PMOS) transistors, Figure 17 The 500 pixels can have the same Figure 1The pixel 100 has a similar configuration and similar operation, and the second part of the first transistor T1, the second transistor T2N, the third transistor T3N, the fourth transistor T4N, the fifth transistor T5N, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be implemented by n-type metal oxide semiconductor (NMOS) transistors.

[0102] In some embodiments, such as Figure 17 As shown, the second transistor T2N, the third transistor T3N, the fourth transistor T4N, and the fifth transistor T5N can be implemented using NMOS transistors with relatively smaller leakage current than PMOS transistors. In this case, the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 are active low signals having a low level as an on-state level and a high level as an off-state level. Figure 5 , Figure 11 , Figure 13 , Figure 14 and Figure 15 Unlike other examples, the first scan signal SCAN1, the second scan signal SCAN2, and the third scan signal SCAN3 applied to the second transistor T2N, the third transistor T3N, the fourth transistor T4N, and the fifth transistor T5N, which are implemented using NMOS transistors, can be active high signals having a high level as an on level and a low level as an off level. Since the second transistor T2N to the fifth transistor T5N, which are directly coupled to the first capacitor C1 and the second capacitor C2, are implemented using NMOS transistors, the leakage current flowing out of / into the first capacitor C1 and the second capacitor C2 through the second transistor T2N to the fifth transistor T5N can be reduced. Therefore, in variable frequency mode, pixel 500 or a display panel including pixel 500 can display an image with uniform brightness during a frame period.

[0103] although Figure 17An example is shown where the second transistor T2N to the fifth transistor T5N are implemented using NMOS transistors; however, according to embodiments, any one or more of the first transistor T1 to the eighth transistor T8 can be implemented using NMOS transistors. In some embodiments, the third transistor T3N and the fourth transistor T4N, whose source / drain is directly coupled to the second node N2, can be implemented using NMOS transistors, and therefore the leakage current flowing from / to the second node N2 through the third transistor T3N and the fourth transistor T4N can be reduced. In other embodiments, the second transistor T2N and the fifth transistor T5N, whose source / drain is directly coupled to the first node N1, can be implemented using NMOS transistors, and therefore the leakage current flowing from / to the first node N1 through the second transistor T2N and the fifth transistor T5N can be reduced.

[0104] Figure 18 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment. Figure 19 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment, and Figure 20 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0105] Reference Figure 18 , Figure 19 and Figure 20 According to an embodiment, pixels 600, 700, and 800 of the OLED display device may include a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an organic light-emitting diode EL. Except that the second initialization voltage VINT2 applied via the seventh transistor T7 for diode initialization (or anode initialization) and the third initialization voltage VINT3 applied via the eighth transistor T8 for drain initialization can be different voltages provided to pixels 600, 700, and 800 through different lines, Figure 18 600 pixels Figure 19 700 pixels and Figure 20 Each of the 800 pixels can have the same as Figure 1 Similar configuration and operation to the 100 pixel version.

[0106] In some embodiments, such as Figure 18As shown, the first initialization voltage VINT1 for gate initialization and the second initialization voltage VINT2 for diode initialization can be the same voltage provided to pixel 600 through the same line. However, the third initialization voltage VINT3 for drain initialization can be provided to pixel 600 through a different line than the first initialization voltage VINT1 / second initialization voltage VINT2, and can be a different voltage than the first initialization voltage VINT1 / second initialization voltage VINT2. Since the first initialization voltage VINT1 / second initialization voltage VINT2 for gate / diode initialization and the third initialization voltage VINT3 for drain initialization are different voltages from different lines, each of the gate / diode initialization and drain initialization can be performed sufficiently and appropriately.

[0107] In other embodiments, such as Figure 19 As shown, the first initialization voltage VINT1 for gate initialization and the third initialization voltage VINT3 for drain initialization can be the same voltage provided to pixel 700 through the same line. However, the second initialization voltage VINT2 for diode initialization can be provided to pixel 700 through a different line than the first initialization voltage VINT1 / third initialization voltage VINT3, and can be a different voltage than the first initialization voltage VINT1 / third initialization voltage VINT3. Since the first initialization voltage VINT1 / third initialization voltage VINT3 for gate / drain initialization and the second initialization voltage VINT2 for diode initialization are different voltages from different lines, each of the gate / drain initialization and diode initialization can be performed sufficiently and appropriately.

[0108] In other embodiments, such as Figure 20 As shown, the first initialization voltage VINT1 for gate initialization, the second initialization voltage VINT2 for diode initialization, and the third initialization voltage VINT3 for drain initialization can be different voltages provided to the pixel 800 via different lines. Since the first initialization voltage VINT1 for gate initialization, the second initialization voltage VINT2 for diode initialization, and the third initialization voltage VINT3 for drain initialization are different voltages from different lines, each of the gate initialization, diode initialization, and drain initialization can be performed sufficiently and appropriately.

[0109] Figure 21 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment, and Figure 22 This is a timing diagram used to describe the operation of pixels in an OLED display device according to an embodiment.

[0110] Reference Figure 21 According to an embodiment, the pixel 1100 of the OLED display device may include a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an organic light-emitting diode EL. Except that the seventh transistor T7 and the eighth transistor T8 can receive the same fourth scan signal SCAN4 through the same line, Figure 21 The 1100 pixels can have the same Figure 1 Similar configuration and operation to the 100 pixel version.

[0111] In some embodiments, such as Figure 21 As shown, the seventh transistor T7 and the eighth transistor T8 can receive the same fourth scan signal SCAN4, such as the same gate bypass signal GB. The operation of pixel 1100 in variable frequency mode can be substantially the same as the operation of pixel 1100 in normal mode. Furthermore, in some embodiments, although the frame period in variable frequency mode has a variable duration and the frame period in normal mode has a constant duration, each of the frame periods in variable frequency mode and normal mode can include substantially the same time period.

[0112] For example, such as Figure 22 As shown, each frame period FP in normal mode and variable frequency mode may include a gate initialization period GIP for initializing the gate of the first transistor T1, a threshold voltage compensation period VCP for compensating the threshold voltage of the first transistor T1, a diode and drain initialization period ADIP for initializing the organic light-emitting diode EL and the drain of the first transistor T1, a data write period DWP for applying the data voltage VDAT to the first node N1, and an emission period EMP for the organic light-emitting diode EL to emit light. The operation of pixel 1100 in the gate initialization period GIP, threshold voltage compensation period VCP, data write period DWP, and emission period EMP can be the same as described above. Figure 5 , Figure 6 , Figure 7 , Figure 9 and Figure 10 The operation of pixel 100 is basically the same.

[0113] During the diode and drain initialization period (ADIP), the seventh transistor T7 and the eighth transistor T8 can be turned on in response to a fourth scan signal SCAN4 having a conduction level. The seventh transistor T7 can apply an initialization voltage VINT (e.g., a second initialization voltage VINT2) to the anode of the organic light-emitting diode EL, and thus initialize the organic light-emitting diode EL. Furthermore, the eighth transistor T8 can apply an initialization voltage VINT (e.g., a third initialization voltage VINT3) to the drain of the first transistor T1, and thus initialize the drain of the first transistor T1. In some embodiments, the duration of the diode and drain initialization period (ADIP) can correspond to, but is not limited to, a horizontal time (or 1H time).

[0114] Figure 23 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment. Figure 24 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment, and Figure 25 This is a circuit diagram illustrating the pixels of an OLED display device according to an embodiment.

[0115] Reference Figure 23 , Figure 24 and Figure 25 According to an embodiment, the pixels 1200, 1300, and 1400 of the OLED display device may include a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and an organic light-emitting diode EL. Except that the second initialization voltage VINT2 applied via the seventh transistor T7 for diode initialization (or anode initialization) and the third initialization voltage VINT3 applied via the eighth transistor T8 for drain initialization can be different voltages provided to pixels 1200, 1300, and 1400 through different lines, Figure 23 1200 pixels Figure 24 1300 pixels and Figure 25 Each of the 1400 pixels can have the same as Figure 21 It has a similar configuration and operation to the 1100 pixel version.

[0116] In some embodiments, such as Figure 23As shown, the first initialization voltage VINT1 for gate initialization and the second initialization voltage VINT2 for diode initialization can be the same voltage provided to pixel 1200 through the same line. However, the third initialization voltage VINT3 for drain initialization can be provided to pixel 1200 through a different line than the first initialization voltage VINT1 / second initialization voltage VINT2, and can be a different voltage than the first initialization voltage VINT1 / second initialization voltage VINT2.

[0117] In other embodiments, such as Figure 24 As shown, the first initialization voltage VINT1 for gate initialization and the third initialization voltage VINT3 for drain initialization can be the same voltage provided to pixel 1300 through the same line. However, the second initialization voltage VINT2 for diode initialization can be provided to pixel 1300 through a different line than the first initialization voltage VINT1 / third initialization voltage VINT3, and can be a different voltage than the first initialization voltage VINT1 / third initialization voltage VINT3.

[0118] In other embodiments, such as Figure 25 As shown, the first initialization voltage VINT1 for gate initialization, the second initialization voltage VINT2 for diode initialization, and the third initialization voltage VINT3 for drain initialization can be different voltages provided to the pixel 1400 through different lines.

[0119] Figure 26 This is a block diagram illustrating an OLED display device according to an embodiment, and Figure 27 This is a diagram illustrating the operation of an OLED display device in a variable frequency mode according to an embodiment.

[0120] Reference Figure 26 According to an embodiment, the OLED display device 1500 may include a display panel 1510, a data driver 1520, a scan driver 1530, an emission driver 1540, and a controller 1550.

[0121] The display panel 1510 may include a plurality of pixels PX. In the OLED display device 1500 according to an embodiment, each pixel PX may include a voltage coupled to a first power supply voltage (e.g., ...). Figure 1 The first power supply voltage (ELVDD) in the line and the first node (e.g., Figure 1 The first capacitor between the first node N1 in the first capacitor (e.g., Figure 1 The first capacitor C1 in the middle), coupled to the first node (e.g., Figure 1 The first node N1) and the second node (e.g., Figure 1The second capacitor (e.g., between the second node N2) in the second node N2) Figure 1 The second capacitor C2 in the middle), configured based on the second node (e.g., Figure 1 The driving transistor (e.g., the driving current generated by the voltage of the second node N2) in the circuit. Figure 1 The first transistor T1 in the transistor is configured to respond to a gate write signal (e.g., Figure 1 The first scan signal SCAN1 in the signal transmits the data voltage VDAT to the first node (e.g., Figure 1 The switching transistor of the first node N1 in the process (e.g., Figure 1 The second transistor T2 in the transistor is configured to respond to a gate initialization signal (e.g., Figure 1 The third scan signal SCAN3 in the signal will initialize the gate voltage (e.g., Figure 1 The first initialization voltage VINT1 in the middle is transmitted to the second node (e.g., Figure 1 The gate initialization transistor of the second node N2 in the middle (e.g., Figure 1 The fourth transistor T4 in the transistor is configured to drive the transistor (e.g., in response to the transmit signal EM). Figure 1 The drain of the first transistor T1 and the organic light-emitting diode (e.g., Figure 1 The anode-coupled emitter transistor (e.g., organic light-emitting diode EL) in the organic light-emitting diode (EL) Figure 1 The sixth transistor T6 in the transistor is configured to respond to a gate-drain signal (e.g., Figure 1 The fifth scan signal (SCAN5) will initialize the drain voltage (e.g., Figure 1 The third initialization voltage VINT3 is transmitted to the driving transistor (e.g., Figure 1 The drain initialization transistor (e.g., the drain of the first transistor T1) in the transistor. Figure 1 The eighth transistor T8 in the middle) and the transistor containing the anode and coupled to the second power supply voltage (e.g., Figure 1 The organic light-emitting diode (e.g., the cathode of the line in the second power supply voltage ELVSS) is a second power supply voltage (ELVSS). Figure 1 Organic light-emitting diodes (ELs) in the display panel. For example, each pixel PX of the display panel 1510 can be an organic light-emitting diode (EL). Figure 1 100 pixels Figure 16 400 pixels Figure 17 500 pixels Figure 18 600 pixels Figure 19 700 pixels Figure 20 800 pixels Figure 21 1100 pixels Figure 23 1200 pixels Figure 24 1300 pixels or Figure 25Pixels 1400, etc. In the OLED display device 1500 according to an embodiment, each pixel PX may include a drain initialization transistor for drain initialization (e.g., Figure 1 (The eighth transistor T8 in the image). Therefore, the pixel PX according to the embodiment is applicable not only to the normal mode but also to the variable frequency mode.

[0122] Data driver 1520 can provide a data voltage VDAT to a plurality of pixels PX in response to a data control signal DCTRL received from controller 1550 and output image data ODAT. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a level start signal, and a load signal. Data driver 1520 can receive output image data ODAT as frame data at a drive frequency DF of display panel 1510. In some embodiments, data driver 1520 and controller 1550 can be embedded in a single integrated circuit chip, and the single integrated circuit chip may be referred to as a timing controller embedded data driver (TED). In other embodiments, data driver 1520 and controller 1550 can be implemented using separate integrated circuits.

[0123] The scan driver 1530 can provide a first scan signal SCAN1 (or gate write signal), a second scan signal SCAN2 (or gate compensation signal), a third scan signal SCAN3 (or gate initialization signal), a fourth scan signal SCAN4 (or gate bypass signal), and / or a fifth scan signal SCAN5 (or gate drain signal) to a plurality of pixels PX in response to a scan control signal SCTRL received from the controller 1550. In some embodiments, the scan control signal SCTRL may include, but is not limited to, a scan start signal and a scan clock signal. In some embodiments, the scan driver 1530 can sequentially provide the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3, the fourth scan signal SCAN4, and / or the fifth scan signal SCAN5 to the plurality of pixels PX on a line-by-line basis. In some embodiments, the scan driver 1530 may be integrated or formed in a peripheral portion of the display panel 1510. In other embodiments, the scan driver 1530 may be implemented using one or more integrated circuits.

[0124] The transmit driver 1540 can provide a transmit signal EM to a plurality of pixels PX in response to a transmit control signal EMCTRL received from the controller 1550. In some embodiments, the transmit control signal EMCTRL may include, but is not limited to, a transmit start signal and a transmit clock signal. In some embodiments, the transmit driver 1540 can provide the transmit signal EM sequentially to the plurality of pixels PX on a row-by-row basis. In some embodiments, the transmit driver 1540 may be integrated or formed in a peripheral portion of the display panel 1510. In other embodiments, the transmit driver 1540 may be implemented using one or more integrated circuits.

[0125] Controller 1550 (e.g., a timing controller (TCON)) can receive input image data IDAT and control signals CTRL from an external host processor (e.g., an application processor (AP), a graphics processing unit (GPU), or a graphics card). In some embodiments, the control signal CTRL may include a mode signal indicating whether the display panel 1510 is driven in a normal mode with a fixed frame rate or a variable frequency mode with a variable frame rate. In some embodiments, the control signal CTRL may also include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 1550 can generate output image data ODAT, a data control signal DCTRL, a scan control signal SCTRL, and a transmit control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 1550 can control the operation of the data driver 1520 by providing the output image data ODAT and the data control signal DCTRL to the data driver 1520, control the operation of the scan driver 1530 by providing the scan control signal SCTRL to the scan driver 1530, and control the operation of the transmit driver 1540 by providing the transmit control signal EMCTRL to the transmit driver 1540.

[0126] In normal mode, the host processor can provide input image data IDAT to the controller 1550 at a fixed input frame frequency (IFF), and can determine the drive frequency DF of the display panel 1510 as the fixed input frame frequency (IFF). Therefore, the controller 1550 can control the data driver 1520 and the scan driver 1530 to drive the display panel 1510 at either the fixed input frame frequency (IFF) or the fixed drive frequency DF.

[0127] In variable frequency mode, the host processor can provide input image data IDAT to the controller 1550 at a variable input frame frequency (IFF) by changing the length (or duration) of the blanking period in each frame segment, and can determine the drive frequency DF of the display panel 1510 based on the variable input frame frequency (IFF). Therefore, the controller 1550 can control the data driver 1520 and the scan driver 1530 to drive the display panel 1510 based on the variable input frame frequency (IFF) or the variable drive frequency DF. For example, the variable frequency mode can be, but is not limited to, Free-Sync mode, G-Sync mode, etc.

[0128] For example, such as Figure 27 As shown, the rendering periods 1610, 1620, and 1630 (rendering periods) or frequencies performed by the host processor (e.g., AP, GPU, or graphics card) may differ (especially in the case of rendering game image data), and the host processor may provide input image data IDAT or frame data FDAT1, FDAT2, and FDAT3 to the OLED display device 1500 synchronously with the inconsistent rendering periods 1610, 1620, and 1630 in variable frequency mode. Therefore, in variable frequency mode, each frame period FP1, FP2, and FP3 may include valid periods AP1, AP2, and AP3 with the same duration, but the host processor can provide frame data FDAT1, FDAT2, and FDAT3 to the OLED display device 1500 at a variable input frame frequency IFF by changing the duration (or duration) of the variable blanking periods VBP1, VBP2, and VBP3 of each frame period FP1, FP2, and FP3.

[0129] exist Figure 27In the example, if the rendering period 1610 for the second frame data FDAT2 is executed at a frequency of 120Hz during the first frame period FP1, the host processor can provide the first frame data FDAT1 to the OLED display device 1500 at an input frame frequency IFF of 120Hz during the first frame period FP1. During the first frame period FP1, the controller 1550 can provide the first frame data FDAT1 to the data driver 1520 at a drive frequency DF of 120Hz, driving the display panel 1510 at a drive frequency DF of 120Hz. Furthermore, the host processor can output the second frame data FDAT2 during the effective period AP2 of the second frame period FP2, and can continue the vertical blanking period VBP2 of the second frame period FP2 until the rendering period 1620 for the third frame data FDAT3 is completed. Therefore, in the second frame period FP2, if the rendering period 1620 for the third frame data FDAT3 is executed at a frequency of 60Hz, the host processor can provide the second frame data FDAT2 to the OLED display device 1500 at an input frame frequency IFF of 60Hz by increasing the duration of the variable blanking period VBP2 of the second frame period FP2. In the second frame period FP2, the controller 1550 can provide the second frame data FDAT2 to the data driver 1520 at a drive frequency DF of 60Hz, driving the display panel 1510 at the same frequency. Furthermore, in the third frame period FP3, if the rendering period 1630 for the fourth frame data FDAT4 is executed again at a frequency of 120Hz, the host processor can again provide the third frame data FDAT3 to the OLED display device 1500 at an input frame frequency IFF of 120Hz.

[0130] As described above, the OLED display device 1500 supporting variable frequency mode can prevent tearing caused by frame frequency mismatch by displaying images synchronously with the variable input frame frequency (IFF). Furthermore, as described above, each pixel PX of the OLED display device 1500 according to the embodiment can include not only a seventh transistor for diode initialization but also an eighth transistor for drain initialization. Therefore, the pixel PX can be used not only in normal mode but also in variable frequency mode, and the OLED display device 1500 according to the embodiment can display images with substantially uniform brightness not only in normal mode but also in variable frequency mode.

[0131] Figure 28 It is an electronic device including an OLED display device according to an embodiment.

[0132] Reference Figure 28The electronic device 2100 may include a processor 2110, a memory device 2120, a storage device 2130, an input / output (I / O) device 2140, a power supply 2150, and an OLED display device 2160. The electronic device 2100 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, and other electronic devices.

[0133] Processor 2110 can perform various computing functions or tasks. Processor 2110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. Processor 2110 may be coupled to other components via address buses, control buses, data buses, etc. Furthermore, in some embodiments, processor 2110 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0134] The memory device 2120 can store data for the operation of the electronic device 2100. For example, the memory device 2120 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0135] Storage device 2130 may be a solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc. I / O device 2140 may be an input device such as a keyboard, keypad, mouse, touchscreen, etc., and an output device such as a printer, speaker, etc. Power supply 2150 provides power for the operation of electronic device 2100. OLED display device 2160 may be coupled to other components via a bus or other communication link.

[0136] In the OLED display device 2160, each pixel may include an eighth transistor for drain initialization. Therefore, the pixel can be used not only in a normal mode but also in a variable frequency mode, and the OLED display device 2160 according to the embodiment can display an image with substantially uniform brightness not only in a normal mode but also in a variable frequency mode.

[0137] The present invention can be applied to any OLED display device 2160 and any electronic device 2100 including the OLED display device 2160. For example, the present invention can be applied to mobile phones, smartphones, wearable electronic devices, tablet computers, televisions (TVs), digital televisions, 3D televisions, personal computers (PCs), home appliances, portable computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0138] The foregoing is illustrative of the embodiments and should not be construed as limiting them. Although some embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A pixel in an organic light-emitting diode (OLED) display device, wherein, The pixels include: The first capacitor is coupled between the first power supply voltage line and the first node; A second capacitor is coupled between the first node and the second node; The first transistor is configured to generate a drive current based on the voltage of the second node; The second transistor is configured to transmit a data voltage to the first node in response to a first scan signal; The third transistor is configured to connect the diode of the first transistor in response to the second scan signal; The fourth transistor is configured to transmit an initialization voltage to the second node in response to a third scan signal; The fifth transistor is configured to transmit a reference voltage to the first node in response to the second scan signal; The sixth transistor is configured to couple the drain of the first transistor and the anode of the organic light-emitting diode in response to an emission signal; A seventh transistor is configured to transmit the initialization voltage to the anode of the organic light-emitting diode in response to a fourth scan signal; An eighth transistor, configured to transmit the initialization voltage to the drain of the first transistor in response to a fifth scan signal; and The organic light-emitting diode includes the anode and a cathode coupled to the second power supply voltage line. In the normal mode where the display panel is driven at a fixed frame rate, the eighth transistor is not turned on, and In the variable frequency mode where the display panel is driven at a variable frame rate, the eighth transistor is turned on to initialize the drain of the first transistor.

2. The pixel according to claim 1, wherein, The eighth transistor includes: a gate for receiving the fifth scan signal; a source coupled to the drain of the first transistor; and a drain coupled to an initialization voltage line.

3. The pixel according to claim 1, wherein, In the normal mode where the display panel is driven at the fixed frame frequency, the seventh transistor is turned on to initialize the organic light-emitting diode, and In the variable frequency mode where the display panel is driven at the variable frame frequency, the seventh transistor is not turned on.

4. The pixel according to claim 1, wherein, Each frame period in the normal mode of driving the display panel at the fixed frame frequency includes a gate initialization period for initializing the gate of the first transistor, a threshold voltage compensation period for compensating the threshold voltage of the first transistor, a diode initialization period for initializing the organic light-emitting diode, a data writing period for applying the data voltage to the first node, and an emission period for the organic light-emitting diode to emit light. Each frame period in the variable frequency mode of driving the display panel with the variable frame frequency includes the gate initialization period, the threshold voltage compensation period, the drain initialization period for initializing the drain of the first transistor, the data writing period, and the transmission period.

5. The pixel according to claim 4, wherein, During the drain initialization period, The transmitted signal has a cutoff level. The fifth scan signal has a conduction level. The first scan signal, the second scan signal, the third scan signal, and the fourth scan signal have the cutoff level, and The eighth transistor is turned on to apply the initialization voltage to the drain of the first transistor.

6. The pixel according to claim 4, wherein, The duration of the threshold voltage compensation period is longer than the duration of the data writing period.

7. The pixel according to claim 4, wherein, The diode initialization period overlaps with the gate initialization period or the threshold voltage compensation period.

8. The pixel according to claim 4, wherein, The drain initialization period is located between the data writing period and the transmission period.

9. The pixel according to claim 1, wherein, The second transistor, the third transistor, the fourth transistor, and the fifth transistor are dual transistors.

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