Operation circuit and operation method of resistive memory

Abstract

The present invention discloses an operating circuit and operating method for a resistive random access memory. The operating circuit includes at least one capacitor connected in series to a resistive random access memory so that the resistive random access memory is grounded through the capacitor. The operating method comprises connecting at least one capacitor in series to a resistive random access memory so that the resistive random access memory is grounded through the capacitor; and applying a forming or setting pulse voltage to the resistive random access memory to implement a forming or setting operation on the resistive random access memory. The present invention connects a capacitor in series to the bottom electrode end of each RRAM so that the RRAM is grounded through the capacitor, thereby enabling a fast and low-power batch forming or setting process of the RRAM array, accelerating the forming or setting process of the RRAM array, reducing energy consumption during the forming or setting process, and improving the performance of the RRAM device after forming or setting.

Description

[0001] This application is a divisional application, the application number of the parent application is: 201910715383.3, the application date is: August 2, 2019, and the name is: Operating circuit and operating method of resistive random access memory. Technical Field

[0002] The present invention belongs to the technical field of semiconductor devices and integrated circuits, and relates to an operating circuit and an operating method for a resistive random access memory, specifically an operating circuit and an operating method for realizing fast and low-power forming and setting of a resistive random access memory using a capacitor. Background Art

[0003] Resistive Random Access Memory (RRAM) is a promising new device for future storage and neural network acceleration due to its excellent performance, including fast, low-power programming, excellent durability, and reliable size reduction capabilities. However, after fabrication, RRAM generally requires a forming process before normal use. This process involves applying a voltage across the RRAM to change its resistance from high to low. Only after forming can the RRAM perform normal set or reset operations. This forming process consumes considerable time and energy, and as the size of the RRAM array increases, the energy and time implications of the forming process become more significant. Furthermore, this forming process significantly impacts the subsequent performance of the RRAM during normal use. Therefore, a forming method that can quickly and efficiently form RRAM in bulk and optimize subsequent RRAM performance is of great importance.

[0004] In addition, the process of setting up RRAM, like the forming process, also consumes a lot of time and energy. Summary of the Invention

[0005] In view of this, the main object of the present invention is to provide an operating circuit and an operating method of a resistive random access memory, so as to achieve fast and low-power formation and setting of the resistive random access memory.

[0006] To achieve the above-mentioned object, the present invention provides an operating circuit for a resistive random access memory, the circuit comprising: at least one capacitor connected in series to a resistive random access memory, so that the resistive random access memory is grounded through the capacitor; wherein the resistive random access memory is composed of a resistive random access memory cell, and the resistive random access memory cell is a 1R structure having a resistive random access memory (RRAM), a 1T1R structure having a transistor (transistor) and a resistive random access memory (RRAM), or a 1S1R structure having a selector (selector) and a resistive random access memory (RRAM); the resistive random access memory is an m×n RRAM array structure, where m and n are both natural numbers greater than or equal to 1, the top electrode terminals of multiple resistive random access memory cells in the column direction are connected to the same bit line, and the bottom electrode terminals of multiple resistive random access memory cells in the row direction are connected to the same word line, and the line resistance of the word line between any two resistive random access memory cells is R wire , the line capacitance is C wire , these line capacitances are connected in parallel, and the effect of line capacitance can be considered as a line capacitance of size n×C on the word line. wire The capacitor is grounded; at least one capacitor is connected in series to a resistive memory, and these parallel line capacitors are used as grounding capacitors; a forming or setting pulse voltage is applied to a bit line connected to the top electrode terminal of a plurality of resistive memory cells.

[0007] In one embodiment of the present invention, the capacitor is connected in series to the bottom electrode terminal of the resistive memory unit.

[0008] To achieve the above-mentioned object, the present invention further provides an operating method of a resistive random access memory, the method comprising: connecting at least one capacitor in series to a resistive random access memory, so that the resistive random access memory is grounded through the capacitor; applying a shaping or setting pulse voltage to the resistive random access memory to perform a shaping or setting operation on the resistive random access memory; wherein the resistive random access memory is composed of a resistive random access memory cell, the resistive random access memory cell being a 1R structure having a resistive random access memory (RRAM), a 1T1R structure having a transistor (transistor) and a resistive random access memory (RRAM), or a 1S1R structure having a selector (selector) and a resistive random access memory (RRAM); the resistive random access memory is an m×n RRAM array structure, where m and n are both natural numbers greater than or equal to 1, the top electrode terminals of the plurality of resistive random access memory cells in the column direction are connected to the same bit line, the bottom electrode terminals of the plurality of resistive random access memory cells in the row direction are connected to the same word line, and the line resistance of the word line between any two resistive random access memory cells is R wire , the line capacitance is C wire , these line capacitances are connected in parallel, and the effect of line capacitance can be considered as a line capacitance of size n×C on the word line. wireThe capacitor is grounded; at least one capacitor is connected in series to a resistive memory, and these parallel line capacitors are used as grounding capacitors; a forming or setting pulse voltage is applied to a bit line connected to the top electrode terminal of a plurality of resistive memory cells.

[0009] In one embodiment of the present invention, the capacitor is connected in series to the bottom electrode terminal of the resistive memory unit, and the shaping or setting pulse voltage is applied to the top electrode terminal of the resistive memory unit.

[0010] In one embodiment of the present invention, the shaped pulse voltage is applied to the bit lines connected to the top electrode terminals of the plurality of resistive memory cells, specifically comprising: selecting the first row bit line BL1 through the bit line terminal MUX, leaving the word line terminal MUX dangling, and making the column word lines WL1, WL2, ..., WL m Connect to ground through capacitor; apply shaping pulse of certain length on the first row bit line BL1 to complete the shaping process of m resistive memory cells connected to the first row bit line BL1; after the shaping process of m resistive memory cells connected to the first row bit line BL1 is completed, open the word line terminal MUX and connect to ground, reset the voltage on the capacitor to 0; then, close the word line terminal MUX, select the second row bit line BL2 through the bit line terminal MUX, apply shaping voltage of certain length on the second row bit line BL2 to complete the shaping process of m resistive memory cells connected to the second row bit line BL2; repeat the above process until the shaping process of m resistive memory cells connected to the nth row bit line BL1 is completed. n The formation process of the connected m resistive memory cells completes the formation process of the entire resistive memory array.

[0011] In one embodiment of the present invention, the setting pulse voltage is applied to the bit lines connected to the top electrode terminals of the plurality of resistive memory cells, specifically comprising: selecting the first row bit line BL1 through the bit line terminal MUX, leaving the word line terminal MUX dangling, and making the column word lines WL1, WL2, ..., WL m Grounded through the capacitor; a setting pulse of a certain length is applied to the first row bit line BL1 to complete the setting process of the m resistive memory cells connected to the first row bit line BL1; after the setting process of the m resistive memory cells connected to the first row bit line BL1 is completed, the word line terminal MUX is opened and grounded to reset the voltage on the capacitor to 0; then, the word line terminal MUX is closed, and the second row bit line BL2 is selected through the bit line terminal MUX, and a setting voltage of a certain length is applied to the second row bit line BL2 to complete the setting process of the m resistive memory cells connected to the second row bit line BL2; the above process is repeated until the setting process of the m resistive memory cells connected to the nth row bit line BL1 is completed. n The setting process of the connected m resistive memory cells completes the setting process of the entire resistive memory array.

[0012] The operating circuit and method of the resistive random access memory provided by the present invention connect a capacitor in series with the bottom electrode terminal of each RRAM, grounding the RRAM through the capacitor. This allows for rapid, low-power batch formation or setting of RRAM arrays, accelerates the formation or setting process of the RRAM arrays, reduces energy consumption during the formation or setting process, and improves the performance of the RRAM devices after formation or setting.

[0013] Figure Description

[0014] Figure 1a A schematic diagram of a connection between a capacitor and a resistive memory unit when the resistive memory is composed of a resistive memory unit according to an embodiment of the present invention;

[0015] Figure 1b A schematic diagram of voltage changes across a resistive memory cell during a forming process when the resistive memory according to an embodiment of the present invention is composed of a resistive memory cell;

[0016] Figure 1c A schematic diagram of changes in current in a circuit during a forming process when a resistive memory is composed of a resistive memory unit according to an embodiment of the present invention;

[0017] Figure 2a Schematic diagram of the connection between a capacitor and a resistive memory array when the resistive memory is an m×n RRAM array structure according to an embodiment of the present invention;

[0018] Figure 2b Schematic diagram of the change of total current in the circuit when the resistive random access memory is an m×n RRAM array structure according to an embodiment of the present invention;

[0019] Figure 3 A schematic diagram illustrating that the parasitic effects in the RRAM array are equivalent to grounding through a capacitor when the resistive random access memory is a large-scale RRAM array structure according to an embodiment of the present invention;

[0020] Figure 4a Schematic diagram of a circuit structure for batch forming or setting an RRAM array according to an embodiment of the present invention;

[0021] Figure 4b FIG. 4 is a flow chart of a method for batch forming or fixing RRAM arrays according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific embodiments and the accompanying drawings.

[0023] The present invention provides an operating circuit and method for a resistive random access memory. The operating circuit includes at least one capacitor connected in series with the resistive random access memory, grounding the resistive random access memory through the capacitor. The operating method comprises connecting at least one capacitor in series with the resistive random access memory, grounding the resistive random access memory through the capacitor, and applying a shaping or setting pulse voltage to the resistive random access memory to perform a shaping or setting operation on the resistive random access memory.

[0024] After applying the forming or setting pulse voltage, when the RRAM is in a high resistance state before forming or setting, the capacitor charges slowly. The applied forming or setting pulse voltage is primarily applied to the RRAM, allowing this voltage to complete the forming or setting of the RRAM. After forming or setting is complete, the RRAM resistance decreases, accelerating the charging of the capacitor, rapidly reducing the voltage across the RRAM and, in turn, reducing the current through the RRAM until it reaches zero.

[0025] Based on the above-mentioned method of using capacitors to complete forming or setting, the present invention also proposes a method that can complete the forming or setting operation of the RRAM array in parallel and with low power consumption. Because under this operation method, the time of the large current generated during the device forming process is relatively short, and the time when each RRAM device is formed is also different, even if a large number of devices are formed in parallel, the total current in the circuit can still be tolerated. Therefore, this method can complete low-energy, high-efficiency RRAM batch forming, significantly reducing the RRAM array forming time and energy consumption. At the same time, because the device passes through a large current for a short time, the resistance state achieved after forming is also higher, and the low resistance during the subsequent setting and reset operations is also higher, resulting in a reduction in the subsequent operating current, thereby reducing the power consumption of subsequent operations.

[0026] Figure 1a A schematic diagram illustrating the connection between a capacitor and a resistive memory cell when a resistive memory is composed of a resistive memory cell according to an embodiment of the present invention. In this embodiment, the resistive memory is composed of a resistive memory cell, the capacitor is connected in series to the bottom electrode terminal of the resistive memory cell, and the shaping or setting pulse voltage is applied to the top electrode terminal of the resistive memory cell. The resistive memory cell has a 1R structure having a resistive random access memory (RRAM), a 1T1R structure having a transistor and a resistive random access memory (RRAM), or a 1S1R structure having a selector and a resistive random access memory (RRAM).

[0027] In this embodiment, the RRAM device is connected in series with a capacitor, which is grounded through the capacitor. The voltage signal during forming is applied to the top electrode of the RRAM. Before the forming voltage is applied, no charge accumulates on the capacitor, and the voltage across the capacitor is zero. After the forming voltage is applied, before the RRAM is formed, due to the extremely large resistance of the RRAM and the low current flowing through the RRAM, the capacitor charges very slowly, and the voltage on the capacitor rises very slowly. The voltage is mainly applied to the RRAM, so the voltage can support the RRAM forming process. After the RRAM is formed, due to the reduced resistance, the current flowing through the RRAM increases, and the charging speed of the capacitor is accelerated. Therefore, the voltage on the capacitor rises rapidly, causing the current in the circuit to decay rapidly, eventually decreasing to zero. Therefore, during the forming process of a single device, the current distribution is concentrated in the short period after the forming is completed. This peak current can significantly reduce energy consumption compared to traditional forming methods.

[0028] Figure 1b A schematic diagram of voltage changes across a resistive memory cell during a forming process when the resistive memory according to an embodiment of the present invention is composed of a resistive memory cell; Figure 1c FIG. 1 is a schematic diagram showing changes in current in a circuit during a forming process when a resistive memory is composed of a resistive memory unit according to an embodiment of the present invention.

[0029] The same principle can also be used for the RRAM setting process. Simply by replacing the shaping pulse with the setting pulse, a fast and low-power setting process can be achieved in batches. The present invention uses the shaping process as an example, but the same principle applies to the setting process.

[0030] In another embodiment, Figure 2a As shown, Figure 2a A schematic diagram illustrating the connection between a capacitor and a resistive memory array when the resistive memory is an m×n RRAM array structure according to an embodiment of the present invention. The resistive memory is an m×n RRAM array structure, where m and n are both natural numbers greater than or equal to 1. The top electrodes of multiple resistive memory cells in the column direction are connected to the same bit line, and the bottom electrodes of multiple resistive memory cells in the row direction are connected to the same word line. Each word line is connected in series with a capacitor and grounded through the capacitor. In this embodiment, the series connection of at least one capacitor to the resistive memory involves connecting a capacitor in series to each word line, so that the bottom electrodes of multiple resistive memory cells connected to the same word line are grounded through the capacitor. The shaping or setting pulse voltage is applied to the bit line connected to the top electrodes of the multiple resistive memory cells.

[0031] exist Figure 2aIn this example, each RRAM in a row is connected to ground via a series capacitor. Applying a shaping pulse to the top electrode of the RRAM in this row allows simultaneous shaping of all devices in the row. Because the current flow during shaping of a single device is a very short spike, and shaping of different devices occurs at different times, the maximum total current during the entire shaping process significantly reduces the burden on the circuit. This allows simultaneous shaping of a large number of devices in an entire row without exceeding the maximum current limit of the circuit. Figure 2b A schematic diagram showing changes in the total current in a circuit when the resistive random access memory is an m×n RRAM array structure according to an embodiment of the present invention is shown.

[0032] Figure 3 FIG. 1 is a schematic diagram showing that the parasitic effects in the RRAM array are equivalent to grounding through a capacitor when the resistive random access memory is a large-scale RRAM array structure according to an embodiment of the present invention. Figure 3 As shown, this embodiment uses the line capacitance of the RRAM array itself as a series capacitor. The resistive memory is an m×n RRAM array structure, where m and n are both natural numbers greater than or equal to 1. The top electrode terminals of multiple resistive memory cells in the column direction are connected to the same bit line, and the bottom electrode terminals of multiple resistive memory cells in the row direction are connected to the same word line. In this embodiment, the line resistance of the word line between any two resistive memory cells is R wire , the line capacitance is C wire When the line resistance R wire When the resistance is much smaller than that of RRAM, the line resistance can be approximately ignored, so the parasitic effect of the wire can be simplified to only the line capacitance. These line capacitances are all connected in parallel, and the effect of the line capacitance can be considered as a line on the word line with a size of n×C wire The capacitor is grounded. This type of capacitor can play the same role as the capacitor in Figure 1. Therefore, when the RRAM array reaches a certain scale, for example, under the 22nm process, when n≥512, the parasitic capacitance is large enough to support the RRAM to complete the formation. At this time, the parasitic capacitance effect of the wire can be used to complete the formation process without the need to prepare additional capacitors in the circuit. In this embodiment, the series connection of at least one capacitor in a resistive memory utilizes these parallel line capacitances as grounding capacitors; the forming or setting pulse voltage is applied to the bit line connected to the top electrode terminal of multiple resistive memory cells.

[0033] Figure 4a FIG. 1 is a schematic diagram of a circuit structure for batch forming or setting an RRAM array according to an embodiment of the present invention. Figure 4b FIG. 4 is a flow chart of a method for batch forming or configuring RRAM arrays according to an embodiment of the present invention.

[0034] Reference Figure 4a and Figure 4bThe batch forming process of the RRAM array specifically includes: firstly, the first row bit line BL1 is selected through the bit line terminal MUX, and the word line terminal MUX is left floating, so that the column word lines WL1, WL2, ..., WL m Connect to ground through capacitor; apply shaping pulse of certain length on the first row bit line BL1 to complete the shaping process of m resistive memory cells connected to the first row bit line BL1; after the shaping process of m resistive memory cells connected to the first row bit line BL1 is completed, open the word line terminal MUX and connect to ground, reset the voltage on the capacitor to 0; then, close the word line terminal MUX, select the second row bit line BL2 through the bit line terminal MUX, apply shaping voltage of certain length on the second row bit line BL2 to complete the shaping process of m resistive memory cells connected to the second row bit line BL2; repeat the above process until the shaping process of m resistive memory cells connected to the nth row bit line BL1 is completed. n The formation process of the connected m resistive memory cells completes the formation process of the entire resistive memory array.

[0035] Reference Figure 4a and Figure 4b The batch setting process of the RRAM array specifically includes: firstly, the first row bit line BL1 is selected through the bit line terminal MUX, and the word line terminal MUX is left unconnected, so that the column word lines WL1, WL2, ..., WL m Grounded through the capacitor; a setting pulse of a certain length is applied to the first row bit line BL1 to complete the setting process of the m resistive memory cells connected to the first row bit line BL1; after the setting process of the m resistive memory cells connected to the first row bit line BL1 is completed, the word line terminal MUX is opened and grounded to reset the voltage on the capacitor to 0; then, the word line terminal MUX is closed, and the second row bit line BL2 is selected through the bit line terminal MUX, and a setting voltage of a certain length is applied to the second row bit line BL2 to complete the setting process of the m resistive memory cells connected to the second row bit line BL2; the above process is repeated until the setting process of the m resistive memory cells connected to the nth row bit line BL1 is completed. n The setting process of the connected m resistive memory cells completes the setting process of the entire resistive memory array.

[0036] It should be noted that the above embodiment mainly takes the forming process of RRAM as an example. In actual applications, the same principle can also be used for the setting process of RRAM. Simply by replacing the forming pulse with the setting pulse, a fast and low-power setting process can be implemented in batches.

[0037] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An operating circuit of a resistive random access memory, characterized in that: The circuit includes: At least one capacitor is directly connected in series with a resistive memory, so that the resistive memory is grounded through the capacitor; The resistive memory includes a resistive memory unit, wherein the resistive memory unit is a 1R structure having a resistive random access memory (RRAM), a 1T1R structure having a transistor and a resistive random access memory (RRAM), or a 1S1R structure having a selector and a resistive random access memory (RRAM); The resistive memory is an m×n RRAM array structure, where m and n are both natural numbers greater than or equal to 1. The top electrode terminals of multiple resistive memory cells in the column direction are connected to the same bit line, and the bottom electrode terminals of multiple resistive memory cells in the row direction are connected to the same word line. The line resistance of the word line between any two resistive memory cells is R wire , the line capacitance is C wire , these line capacitances are connected in parallel, and the effect of line capacitance can be considered as a line capacitance of size n×C on the word line. wire The capacitor is grounded; at least one capacitor is connected in series to a resistive memory, and these parallel line capacitors are used as grounding capacitors; a pulse voltage is formed or set to be applied to a bit line connected to the top electrode terminal of a plurality of resistive memory cells; The shaped pulse voltage is applied to the bit lines connected to the top electrode terminals of the plurality of resistive memory cells, specifically comprising: The first row bit line BL1 is selected by the bit line terminal MUX, and the word line terminal MUX is left floating, so that the word lines WL1, WL2, ..., WL m Grounding through a capacitor; applying a shaping pulse of a certain length on the first row bit line BL1 to complete the shaping process of m resistive memory cells connected to the first row bit line BL1; After the formation process of the m resistive memory cells connected to the first row of bit lines BL1 is completed, the word line terminal MUX is opened and grounded, resetting the voltage on the capacitor to 0; then, the word line terminal MUX is closed, and the second row of bit lines BL2 is selected through the bit line terminal MUX. A forming voltage is applied to the second row of bit lines BL2 for a certain period of time, completing the formation process of the m resistive memory cells connected to the second row of bit lines BL2; Repeat the above process until the nth row bit line BL is completed. n The formation process of the connected m resistive memory cells completes the formation process of the entire resistive memory array.

2. The operating circuit of the resistive random access memory according to claim 1, wherein: The capacitor is connected in series to the bottom electrode terminal of the resistive memory unit.

3. A method for operating a resistive random access memory, applied to the operating circuit of the resistive random access memory according to any one of claims 1 to 2, characterized in that: The method includes: Connect at least one capacitor in series with a resistive memory, so that the resistive memory is grounded through the capacitor; Applying a forming or setting pulse voltage to the resistive memory to implement a forming or setting operation on the resistive memory; The resistive memory includes a resistive memory unit, wherein the resistive memory unit is a 1R structure having a resistive random access memory (RRAM), a 1T1R structure having a transistor and a resistive random access memory (RRAM), or a 1S1R structure having a selector and a resistive random access memory (RRAM); The resistive memory is an m×n RRAM array structure, where m and n are both natural numbers greater than or equal to 1. The top electrode terminals of multiple resistive memory cells in the column direction are connected to the same bit line, and the bottom electrode terminals of multiple resistive memory cells in the row direction are connected to the same word line. The line resistance of the word line between any two resistive memory cells is R wire , the line capacitance is C wire , these line capacitances are connected in parallel, and the effect of line capacitance can be considered as a line capacitance of size n×C on the word line. wire The capacitor is grounded; at least one capacitor is connected in series to a resistive memory, and these parallel line capacitors are used as grounding capacitors; a pulse voltage is formed or set to be applied to a bit line connected to the top electrode terminal of a plurality of resistive memory cells; The shaped pulse voltage is applied to the bit lines connected to the top electrode terminals of the plurality of resistive memory cells, specifically comprising: The first row bit line BL1 is selected by the bit line terminal MUX, and the word line terminal MUX is left floating, so that the word lines WL1, WL2, ..., WL m Grounding through a capacitor; applying a shaping pulse of a certain length on the first row bit line BL1 to complete the shaping process of m resistive memory cells connected to the first row bit line BL1; After the formation process of the m resistive memory cells connected to the first row of bit lines BL1 is completed, the word line terminal MUX is opened and grounded, resetting the voltage on the capacitor to 0; then, the word line terminal MUX is closed, and the second row of bit lines BL2 is selected through the bit line terminal MUX. A forming voltage is applied to the second row of bit lines BL2 for a certain period of time, completing the formation process of the m resistive memory cells connected to the second row of bit lines BL2; Repeat the above process until the nth row bit line BL is completed. n The formation process of the connected m resistive memory cells completes the formation process of the entire resistive memory array.

4. The operating method of the resistive random access memory according to claim 3, wherein: The capacitor is connected in series to the bottom electrode terminal of the resistive memory unit, and the shaping or setting pulse voltage is applied to the top electrode terminal of the resistive memory unit.

5. The operating method of the resistive random access memory according to claim 3, wherein: The setting pulse voltage is applied to the bit lines connected to the top electrode terminals of the plurality of resistive memory cells, specifically comprising: The first row bit line BL1 is selected by the bit line terminal MUX, and the word line terminal MUX is left floating, so that the word lines WL1, WL2, ..., WL m Grounding through a capacitor; applying a set pulse of a certain length on the first row bit line BL1 to complete the setting process of m resistive memory cells connected to the first row bit line BL1; After the setting process of the m resistive memory cells connected to the first row bit line BL1 is completed, the word line terminal MUX is opened and grounded, resetting the voltage on the capacitor to 0; then, the word line terminal MUX is closed, and the second row bit line BL2 is selected through the bit line terminal MUX. A setting voltage is applied to the second row bit line BL2 for a certain period of time, completing the setting process of the m resistive memory cells connected to the second row bit line BL2; Repeat the above process until the nth row bit line BL is completed. n The setting process of the connected m resistive memory cells completes the setting process of the entire resistive memory array.

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