Method of selective trimming of fin structure dimensions

Abstract

The method for selectively trimming the size of a fin structure comprises: providing a substrate, a top of the substrate is formed with a fin structure comprising a channel region, a gate insulating layer, and a dummy gate covering the sidewall and top surface of the channel region; then, removing the dummy gate to expose the gate insulating layer on the channel region; then, performing etching selection ratio adjustment on the gate insulating layer to divide the gate insulating layer into a first part and a second part with different etching rates, the first part is located on the top surface of the channel region, and the second part is located on the sidewall of the channel region; then, performing a first etching process to remove the second part to expose the sidewall of the channel region while retaining the first part; and then, performing a second etching process to etch the channel region along the sidewall of the channel region to reduce the width of the channel region. In this way, the width of the channel region can be selectively reduced without losing the height of the channel region, which helps to reduce the short channel effect of the FinFET and can reduce the influence on the drive current of the FinFET and the performance of the alternating current device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for selectively trimming the size of a fin structure. BACKGROUND

[0002] With the continuous development of semiconductor technology, the traditional planar device has been difficult to meet the demand of people for high-performance devices. Fin-Field-Effect-Transistor (FinFET) is a three-dimensional device, including a fin structure (Fin) vertically formed on a substrate and a high-k metal gate (HKMG) covering the fin structure, which can greatly improve the circuit control and reduce the leakage current, and also can greatly shorten the gate length of the transistor. In the FinFET process, the smaller the size of the fin structure, the easier the channel region of the fin structure is depleted after the gate voltage is applied, which helps to reduce the short channel effect and thus reduce the off current Ioff of the FinFET.

[0003] In order to reduce the size of the fin structure, one method is to trim the fin structure as a whole (Global Fin Trim) to reduce the overall size of the fin structure. Although this method can reduce the short channel effect, the overall reduction of the size of the fin structure will reduce the epitaxy growth of the source-drain region of the fin structure, thereby increasing the resistance Rsd of the source-drain region; in addition, the overall reduction of the size of the fin structure will also result in a decrease in the number of channel carriers, thereby increasing the on voltage.

[0004] In order to reduce the size of the fin structure, another method is to selectively trim the size of the channel region of the fin structure (Selectivity Fin Trim). When the existing method for selectively trimming the size of the fin structure is used to trim the channel region of the fin structure, although the size of the channel region of the fin structure can be selectively reduced without affecting the size of the source-drain region of the fin structure, the height of the channel region of the fin structure will be lost, resulting in an increase in the capacitance between the metal gate and the source-drain region, thereby affecting the drive current and the AC device performance of the FinFET. SUMMARY

[0005] The present application provides a method for selectively trimming the size of a fin structure, which can reduce the width of the channel region of the fin structure without losing the height of the channel region and increasing the resistance of the source-drain region, thereby helping to reduce the short channel effect of the FinFET and reducing the impact on the drive current and the AC device performance of the FinFET.

[0006] In order to achieve the above-mentioned purpose, the method for selectively trimming the size of the fin structure provided by the present application comprises:

[0007] A substrate is provided, a top portion of the substrate is formed with a fin structure, the fin structure includes a channel region, a gate insulating layer and a dummy gate on the channel region, the gate insulating layer and the dummy gate cover the sidewall and the top surface of the channel region;

[0008] The dummy gate is removed to expose the gate insulating layer on the channel region;

[0009] The etching selectivity of the gate insulating layer is adjusted to divide the gate insulating layer into a first portion and a second portion with different etching rates, the first portion is on the top surface of the channel region, and the second portion is on the sidewall of the channel region;

[0010] A first etching process is performed to remove the second portion to expose the sidewall of the channel region while retaining the first portion; and

[0011] A second etching process is performed to reduce the channel region along the sidewall of the channel region to reduce the width of the channel region.

[0012] Optionally, the method of adjusting the etching selectivity of the gate insulating layer includes: performing a nitridation treatment on the gate insulating layer, and the nitrogen doping concentration of the gate insulating layer on the top surface of the channel region is greater than the nitrogen doping concentration of the gate insulating layer on the sidewall of the channel region, thereby forming the first portion and the second portion with different etching rates.

[0013] Optionally, the method of the nitridation treatment includes ion implantation or coupled plasma nitridation treatment.

[0014] Optionally, during the nitridation treatment, nitrogen dopants are implanted into the gate insulating layer in a direction perpendicular to the top surface of the fin structure.

[0015] Optionally, the second etching process adopts a single-crystal silicon isotropic dry etching process, and the etching rate of the second etching process on the channel region is greater than the etching rate on the first portion.

[0016] Optionally, the fin structure includes source / drain regions at both ends of the channel region; before the dummy gate is removed, the method of selectively trimming the size of the fin structure includes: forming a protective layer on the source / drain regions.

[0017] Optionally, before the protective layer is formed on the source / drain regions, epitaxial growth of the source / drain regions has been completed.

[0018] Optionally, after the second etching process is performed, the method of selectively trimming the size of the fin structure further includes: removing the first portion by using a dry etching process.

[0019] Optionally, the thickness of the gate insulating layer is 10-40 angstroms.

[0020] Optionally, the substrate comprises a Core device region and a high-voltage device region, and the Core device region and the high-voltage device region are both formed with the fin structure; the method for selectively trimming the size of the fin structure comprises: only trimming the channel region of the fin structure in the Core device region.

[0021] In the method for selectively trimming the size of the fin structure, after the dummy gate on the channel region of the fin structure is removed, the etching selectivity of the gate insulating layer is adjusted to divide the gate insulating layer into a first part and a second part with different etching rates, wherein the first part is located on the top surface of the channel region, and the second part is located on the sidewall of the channel region; then, a first etching process is performed to remove the second part to expose the sidewall of the channel region while retaining the first part; and then, a second etching process is performed to reduce (etch) the channel region along the sidewall of the channel region to reduce the width of the channel region. In this way, the width of the channel region of the fin structure can be selectively reduced without losing the height of the channel region and the size of the source / drain region of the fin structure, thereby not increasing the resistance of the source / drain region, which helps to reduce the short channel effect of the FinFET and can reduce the influence on the drive current and the AC device performance of the FinFET. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 It is a perspective view of a fin structure.

[0023] Figure 2 It is a flowchart of the method for selectively trimming the size of the fin structure according to an embodiment of the present application.

[0024] Figures 3 to 8 It is a process cross-sectional view of trimming a fin structure by using the method for selectively trimming the size of the fin structure according to an embodiment of the present application.

[0025] BRIEF DESCRIPTION OF DRAWINGS: 10-substrate; 101-fin structure; 101a-channel region; 101b-source / drain region; 101c-side wall covering region; 102-isolation structure; 103-gate insulating layer; 103a-first part; 103b-second part; 104-dummy gate. DETAILED DESCRIPTION

[0026] The method for selectively trimming the size of the fin structure according to the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are all very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0027] Figure 1A perspective structure of a fin structure is shown. As shown in Figure 1 The fin structure 101 is elongated along the X direction, and the fin structure 101 includes a channel area 101a, source-drain areas 101b at both ends of the channel area 101a, and a spacer area initial 101c between the channel area 101a and the source-drain areas 101b. A method for selectively trimming the size of the fin structure includes: removing a dummy gate on the channel area of the fin structure and a gate insulating layer under the dummy gate to expose the channel area of the fin structure; and trimming the channel area of the fin structure to reduce the size of the channel area.

[0028] As shown in Figure 1 When the channel area 101a is trimmed by the method, the width (size in the Y direction) of the channel area 101a is reduced, and at the same time, the height (size in the Z direction) of the channel area 101a is lost, which increases the capacitance between the metal gate and the source-drain area of the FinFET, thereby affecting the driving current and AC device performance of the FinFET.

[0029] In order to reduce the width of the channel area of the fin structure without losing the height of the channel area and increasing the resistance of the source-drain area of the fin structure, the embodiment provides a method for selectively trimming the fin structure. Figure 2 A flowchart of the method for selectively trimming the size of the fin structure according to an embodiment of the present application is shown. As shown in Figure 2 The method for selectively trimming the size of the fin structure includes:

[0030] Step S1, providing a substrate, a fin structure is formed on the top of the substrate, the fin structure includes a channel area, a gate insulating layer is formed on the channel area, and a dummy gate is formed on the gate insulating layer, the gate insulating layer and the dummy gate cover the sidewall and the top surface of the channel area;

[0031] Step S2, removing the dummy gate to expose the gate insulating layer on the channel area;

[0032] Step S3, adjusting the etching selectivity of the gate insulating layer to divide the gate insulating layer into a first part and a second part with different etching rates, the first part is located on the top surface of the channel area, and the second part is located on the sidewall of the channel area;

[0033] Step S4, performing a first etching process to remove the second part to expose the sidewall of the channel area, while retaining the first part;

[0034] Step S5, performing a second etching process to reduce the channel area along the sidewall of the channel area to reduce the width of the channel area.

[0035] Figures 3 to 8 A process cross-sectional view of a substrate for trimming a fin structure using the method of selectively trimming a fin structure according to an embodiment of the present application. In this embodiment, Figures 3 to 8 may be a cross-sectional view along a direction perpendicular to the elongated direction of the fin structure and perpendicular to the channel region. The following description is made in conjunction with Figures 2 to 8 The method of selectively trimming a fin structure according to the embodiment is described.

[0036] As shown in Figure 3 , the top of the substrate 10 is formed with a fin structure, which includes a channel region 101a, a gate insulating layer 103 formed on the channel region 101a, and a dummy gate 104 formed on the gate insulating layer 103, the gate insulating layer 103 and the dummy gate 104 covering the sidewalls and the top surface of the channel region 101a.

[0037] In this embodiment, the substrate 10 can be a silicon substrate. However, the substrate 10 can also be a silicon germanium substrate or a silicon-on-insulator (SOI) substrate.

[0038] In this embodiment, a plurality of fin structures can be formed on the substrate 10. The method of forming the substrate 10 can include, with reference to Figure 3 , etching the substrate 10 to form a plurality of trenches and a plurality of fin structures defined by the plurality of trenches; filling the bottoms of the plurality of trenches to form a plurality of isolation structures 102, the plurality of fin structures protruding from the plurality of isolation structures 102; forming a gate insulating layer 103 and a dummy gate 104 on the channel region 101a of the fin structure, the gate insulating layer 103 and the dummy gate 104 covering the sidewalls and the top surface of the channel region 101a, and covering the upper surface of the isolation structure between two adjacent channel regions 101a; and forming a sidewall (not shown in the figure) covering the sidewalls of the dummy gate 104 and the gate insulating layer 103, and covering part of the top surface and part of the sidewalls of the fin structure (i.e., covering the sidewall coverage region of the fin structure).

[0039] In this embodiment, the material of the dummy gate 104 can include polysilicon. The material of the gate insulating layer 103 can include silicon oxide. In order to ensure that the first part of the gate insulating layer 103 divided in the subsequent etching process has sufficient thickness to protect the top surface of the channel region 101a, in this embodiment, the thickness of the gate insulating layer 103 can be in the range of 10 angstroms to 40 angstroms. However, the thickness of the gate insulating layer 103 can be adjusted as needed.

[0040] With reference to Figure 1The fin structure further includes source-drain regions 101b at both ends of the channel region 101a, and a sidewall covering region 101c between the channel region 101a and the source-drain regions 101b. In this embodiment, the epitaxial growth of the source-drain regions 101b is completed before the fin structure is selectively trimmed (i.e. before the dummy gate 104 is removed), so that the size trimming of the fin structure does not affect the epitaxial growth of the source-drain regions 101b.

[0041] In order to avoid the subsequent trimming of the channel region 101a affecting the size of the source-drain regions 101b, in this embodiment, a protective layer (not shown in the figure) is formed on the source-drain regions 101b before the dummy gate 104 is removed. The material of the protective layer can include silicon oxide, but is not limited thereto, and the material of the protective layer can also include silicon nitride.

[0042] Step S2 is performed, as shown in Figure 4 The dummy gate 104 is removed to expose the gate insulating layer 103 on the channel region 101a. The dummy gate 104 can be removed by a method known in the art.

[0043] Step S3 is performed, as shown in Figure 5 The etching selectivity of the gate insulating layer 103 is adjusted to divide the gate insulating layer 103 into a first part 103a and a second part 103b with different etching rates, the first part 103a is located on the top surface of the channel region 101a, and the second part 103b is located on the sidewall of the channel region 101a.

[0044] In this embodiment, the method of adjusting the etching selectivity of the gate insulating layer 103 can include: performing a nitriding treatment on the gate insulating layer 103, and making the nitrogen doping concentration of the gate insulating layer on the top surface of the channel region 101a greater than the nitrogen doping concentration of the gate insulating layer on the sidewall of the channel region 101a, thereby forming the first part 103a and the second part 103b with different etching rates.

[0045] The nitrogenation process can include ion implantation or decoupled plasma nitridation. In the present embodiment, during the nitrogenation process, nitrogen dopants are implanted into the gate insulating layer in a direction perpendicular to the top surface of the fin structure, so that the gate insulating layer on the top surface of the channel region 101a is more easily nitrided, while the gate insulating layer on the sidewall of the channel region 101a is less or not nitrided, which helps to increase the difference in etching rate between the first portion 103a and the second portion 103b. However, the implantation angle of the nitrogen dopants can be appropriately increased, provided that the first etching process can remove the second portion 103b while retaining the first portion 103a.

[0046] It should be noted that, as shown in Figure 5 , during the nitrogenation process, the gate insulating layer on the upper surface of the isolation structure 102 between two adjacent channel regions 101a is also nitrided, and the nitrogen doping concentration thereof is similar to that of the gate insulating layer on the top surface of the channel region 101a (i.e., similar to the nitrogen doping concentration of the second portion 103b).

[0047] After adjusting the etching selectivity of the gate insulating layer 103, as shown in Figure 6 , a first etching process is performed to remove the second portion 103b to expose the sidewall of the channel region 101a, while retaining the first portion 103a. The etching rate of the first etching process on the second portion 103b is greater than that on the first portion 103a. In the present embodiment, the first etching process can employ an isotropic dry etching process. However, the first etching process can also employ a wet etching process.

[0048] It should be noted that, during the first etching process, as shown in Figure 6 , the nitrided gate insulating layer between two adjacent channel regions 101a is retained.

[0049] Next, as shown in Figure 7 , a second etching process is performed to reduce the channel region 101a along the sidewall thereof, so as to reduce the width (i.e., the horizontal dimension in Figure 7 ) of the channel region 101a. Due to the protection of the first portion 103a, in the second etching process, the channel region 101a can be etched inward along the sidewall thereof, and cannot be etched downward along the top surface thereof, so that the width of the channel region 101a can be reduced without losing the height (i.e., the vertical dimension in Figure 7 ) of the channel region 101a.

[0050] In the embodiment, the second etching process can be a single-crystal silicon isotropic dry etching process. The second etching process has a greater etching rate on the channel region 101a than on the first portion 103a.

[0051] After the width of the channel region 101a is trimmed, the method for selectively trimming the size of the fin structure can further include removing the first portion 103a by using a dry etching process. It should be noted that in the process of removing the first portion 103a, the nitrided gate insulation layer between the two adjacent channel regions 101a is also removed.

[0052] In an embodiment, the substrate 10 can include a Core device region and a high-voltage device region, and the Core device region and the high-voltage device region are both formed with fin structures, and the device operating voltage of the Core device region is less than the device operating voltage of the high-voltage device region. Since the devices of the Core device region are more sensitive to the size of the fin structure, especially the channel region 101a, in the embodiment, the method for selectively trimming the size of the fin structure can include trimming only the channel region of the fin structure of the Core device region. Specifically, in the step of removing the dummy gate 104, only the dummy gate on the channel region 101a of the fin structure of the Core device region is removed while the dummy gate of the high-voltage device region is retained, and after the width of the channel region 101a of the Core device region is reduced, the dummy gate on the high-voltage device region is removed.

[0053] In the embodiment, after the first portion 103a on the channel region 101a is removed, subsequent processes of the FinFET can be performed. The subsequent processes of the FinFET can include depositing a high-k dielectric layer on the trimmed channel region 101a, depositing a gate work function material layer (WFM) on the high-k dielectric layer, and forming a metal gate on the gate work function material layer.

[0054] In the method for selectively trimming the size of the fin structure of the embodiment, after the dummy gate 104 on the channel region 101a of the fin structure is removed, the etching selectivity of the gate insulating layer 103 is adjusted to divide the gate insulating layer 103 into a first part 103a and a second part 103b with different etching rates, wherein the first part 103a is located on the top surface of the channel region 101a, and the second part 103b is located on the sidewall of the channel region 101a; then, a first etching process is performed to remove the second part 103b to expose the sidewall of the channel region 101a, while the first part 103a is reserved; next, a second etching process is performed to reduce the channel region 101a along the sidewall of the channel region 101a to reduce the width of the channel region 101a. In this way, the width of the channel region 101a of the fin structure can be selectively reduced, and the height of the channel region 101a and the size of the source-drain region 101b of the fin structure are not lost, thereby not increasing the resistance of the source-drain region 101b, which helps to reduce the short channel effect of the FinFET and can reduce the impact on the drive current and AC device performance of the FinFET.

[0055] In this application, although the terms "first", "second" and the like can be used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Spatial relationship terms such as "under", "below", "lower", "underneath", "on", "upper", and the like can be used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that the spatial relationship terms are intended to include different orientations of the device in use and operation in addition to the orientation shown in the figure.

[0056] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, all belong to the protection scope of the present application.

Claims

1. A method for selectively adjusting the dimensions of a fin structure, characterized in that, include: A substrate is provided, on the top of which a fin structure is formed, the fin structure including a channel region, a gate insulating layer and a dummy gate located on the gate insulating layer are formed on the channel region, the gate insulating layer and the dummy gate cover the sidewalls and top surface of the channel region; Remove the dummy gate to expose the gate insulating layer on the channel region; The gate insulating layer is etched with a selective ratio adjustment to divide it into a first part and a second part with different etch rates. The first part is located on the top surface of the channel region, and the second part is located on the sidewall of the channel region. Perform a first etching process to remove the second portion to expose the sidewalls of the trench region, while retaining the first portion; as well as A second etching process is performed to cut the trench region along the sidewall of the trench region to reduce the width of the trench region.

2. The method for selectively adjusting the dimensions of the fin structure as described in claim 1, characterized in that, The method for adjusting the etching selectivity of the gate insulating layer includes: The gate insulating layer is nitrided, such that the nitrogen doping concentration of the gate insulating layer on the top surface of the channel region is greater than the nitrogen doping concentration of the gate insulating layer on the sidewall of the channel region, forming the first part and the second part with different etching rates.

3. The method for selectively adjusting the dimensions of the fin structure as described in claim 2, characterized in that, The nitriding treatment methods include ion implantation or coupled plasma nitriding treatment.

4. The method for selectively adjusting the dimensions of the fin structure as described in claim 2, characterized in that, During the nitriding process, nitrogen dopant is injected into the gate insulating layer in a direction perpendicular to the top surface of the fin structure.

5. The method for selectively adjusting the dimensions of the fin structure as described in claim 1, characterized in that, The second etching process employs isotropic dry etching of single-crystal silicon, and the etching rate of the second etching process on the channel region is greater than the etching rate on the first portion.

6. The method for selectively adjusting the dimensions of the fin structure as described in claim 1, characterized in that, The fin structure includes source and drain regions located at both ends of the channel region; The method for selectively trimming the fin structure dimensions before removing the dummy gate includes: A protective layer is formed on the source / drain region.

7. The method for selectively adjusting the dimensions of the fin structure as described in claim 6, characterized in that, The epitaxial growth of the source / drain region is completed before the protective layer is formed on the source / drain region.

8. The method for selectively adjusting the dimensions of the fin structure as described in claim 1, characterized in that, After performing the second etching process, the method for selectively trimming the fin structure dimensions further includes: The first part is removed using a dry etching process.

9. The method for selectively adjusting the dimensions of the fin structure as described in claim 1, characterized in that, The thickness of the gate insulation layer is 10 angstroms to 40 angstroms.

10. The method for selectively adjusting the dimensions of the fin structure as described in claim 1, characterized in that, The substrate includes a core device region and a high-voltage device region, and the fin structure is formed in both the core device region and the high-voltage device region; the method of selectively trimming the fin structure size includes trimming only the channel region of the fin structure in the core device region.

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