Display substrate, display panel, and display device

Abstract

Provided are a display substrate, a display panel, and a display device. The display substrate includes: a plurality of pixel units disposed on a base substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction to form multiple rows of pixel units and multiple columns of pixel units, at least one pixel unit including multiple sub-pixels, and at least one sub-pixel including a light-emitting element and a pixel driving circuit for driving the light-emitting element; and a plurality of scan signal lines disposed on the base substrate, the plurality of scan signal lines supplying scan signals to the multiple rows of pixel units, the plurality of scan signal lines being arranged at intervals along the second direction, and at least one scan signal line extending along the first direction. The orthographic projections of the pixel driving circuits of the multiple sub-pixels on the base substrate at least partially overlap with the orthographic projections of the light-emitting elements of the same sub-pixel on the base substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel, and a display device. Background Art

[0002] OLEDs (Organic Light-Emitting Diodes) are current-type organic light-emitting devices (OLEDs). They emit light through the injection and recombination of charge carriers, with the intensity of the light being proportional to the injected current. Under the influence of an electric field, holes generated at the anode and electrons generated at the cathode migrate, injecting into the hole transport layer and electron transport layer, respectively, before migrating to the light-emitting layer. When these two molecules meet in the light-emitting layer, they generate energy excitons, which in turn excite the luminescent molecules, ultimately producing visible light.

[0003] An OLED display device is a type of display device that uses light-emitting OLEDs to display information such as images. OLED display devices have characteristics such as low power consumption, high brightness, and high response speed.

[0004] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the Invention

[0005] In order to solve at least one aspect of the above problems, embodiments of the present disclosure provide a display substrate, a display panel, and a display device.

[0006] In one aspect, a display substrate is provided, comprising: a base substrate; a plurality of pixel units arranged on the base substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction to form multiple rows of pixel units and multiple columns of pixel units, at least one of the pixel units comprising multiple sub-pixels, at least one sub-pixel comprising a light-emitting element and a pixel driving circuit for driving the light-emitting element; and a plurality of scanning signal lines arranged on the base substrate, the plurality of scanning signal lines respectively supplying scanning signals to the multiple rows of pixel units, the plurality of scanning signal lines being arranged at intervals along the second direction, and at least one of the scanning signal lines extending along the first direction, wherein the orthographic projections of the pixel driving circuits of the plurality of sub-pixels on the base substrate at least partially overlap with the orthographic projections of the light-emitting elements of the same sub-pixel on the base substrate.

[0007] According to some exemplary embodiments, for at least one row of pixel units, the light-emitting elements of multiple sub-pixels located in the same row are arranged side by side along a first direction, and the pixel driving circuits of the multiple sub-pixels located in the same row are arranged into two rows along a second direction. In each of the two rows of pixel driving circuits, multiple pixel driving circuits are arranged side by side along the first direction.

[0008] According to some exemplary embodiments, the light-emitting element includes an anode. For the same sub-pixel, the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate and the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate have the following relationship:

[0009] The orthographic projection of the pixel driving circuit of the sub-pixel on the substrate exceeds the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate in the first direction; and / or,

[0010] The orthographic projection of the anode of the light-emitting element of the sub-pixel on the base substrate exceeds the orthographic projection of the pixel driving circuit of the sub-pixel on the base substrate in the second direction.

[0011] According to some exemplary embodiments, for the same sub-pixel, the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate and the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate have the following relationship:

[0012] The ratio of the size of the orthogonal projection of the pixel driving circuit of the sub-pixel on the substrate in the first direction to the size of the orthogonal projection of the anode of the light-emitting element of the sub-pixel on the substrate in the first direction is between 1.5 and 3; and / or,

[0013] The ratio of the size of the positive projection of the anode of the light-emitting element of the sub-pixel on the substrate in the second direction to the size of the positive projection of the pixel driving circuit of the sub-pixel on the substrate in the second direction is between 1.5-3.

[0014] According to some exemplary embodiments, the pixel driving circuit includes at least a driving transistor, which is electrically connected to the light-emitting element, and the driving transistor includes at least a third channel region, the orthographic projection of the third channel region on the substrate has a first side, a second side, a third side and a fourth side, the first side and the second side are located on opposite sides of the orthographic projection of the third channel region on the substrate in a first direction, the third side and the fourth side are located on opposite sides of the orthographic projection of the third channel region on the substrate in a second direction, and a first distance between the first side and the second side along the first direction is greater than a second distance between the third side and the fourth side along the second direction.

[0015] According to some exemplary embodiments, for pixel driving circuits located in the same row, orthographic projections of two adjacent pixel driving circuits in a first direction on the substrate have an axisymmetric relationship.

[0016] According to some exemplary embodiments, for pixel driving circuits of a plurality of sub-pixels located in the same row and arranged in two rows, orthographic projections of two adjacent pixel driving circuits in the second direction on the substrate have a rotationally symmetric relationship.

[0017] According to some exemplary embodiments, for pixel driving circuits for a plurality of sub-pixels located in the same row arranged in two rows, orthographic projections of third channel regions of driving transistors of two adjacent pixel driving circuits in the second direction only partially overlap along the second direction.

[0018] According to some exemplary embodiments, pixel driving circuits for a plurality of sub-pixels located in the same row and arranged in two rows share one scanning signal line.

[0019] According to some exemplary embodiments, the driving transistor includes a third active layer; the pixel driving circuits located in the same row include a first pixel driving circuit, a second pixel driving circuit and a third pixel driving circuit, the first pixel driving circuit is adjacent to the second pixel driving circuit, the third pixel driving circuit is adjacent to the first pixel driving circuit, and the second pixel driving circuit and the third pixel driving circuit are respectively located on both sides of the first pixel driving circuit along the first direction; the third active layer of the driving transistor of the first pixel driving circuit and the third active layer of the driving transistor of the second pixel driving circuit extend continuously.

[0020] According to some exemplary embodiments, the third active layer of the driving transistor of the first pixel driving circuit is spaced apart from the third active layer of the driving transistor of the third pixel driving circuit.

[0021] According to some exemplary embodiments, the display substrate further includes a plurality of first voltage lines, which respectively supply first voltages to a plurality of columns of pixel units, the plurality of first voltage lines are arranged at intervals along a first direction, and at least one first voltage line extends along a second direction; and the first pixel driving circuit and the second pixel driving circuit share one first voltage line.

[0022] According to some exemplary embodiments, an orthographic projection of at least a portion of an axis of symmetry of the pixel driving circuit having an axially symmetrical relationship on the substrate falls within an orthographic projection of the first voltage line on the substrate.

[0023] According to some exemplary embodiments, an orthographic projection of a symmetry center of the pixel driving circuit having a rotationally symmetric relationship on the substrate falls within an orthographic projection of the scanning signal line on the substrate.

[0024] According to some exemplary embodiments, for pixel driving circuits of a plurality of sub-pixels located in the same row and arranged in two rows, orthographic projections of two adjacent pixel driving circuits in the second direction on the substrate have a 180° rotational symmetry.

[0025] According to some exemplary embodiments, the display substrate further includes: a plurality of light-emitting control signal lines arranged on the base substrate, the plurality of light-emitting control signal lines respectively supplying light-emitting control signals to a plurality of rows of pixel units, the plurality of light-emitting control signal lines being arranged at intervals along the second direction, and at least one of the light-emitting control signal lines extending along the first direction; and two light-emitting control signal lines are respectively set for the pixel driving circuits arranged in two rows for a plurality of sub-pixels located in the same row, and in the second direction, a shared scanning signal line is located above one of the two light-emitting control signal lines, and a shared scanning signal line is located below the other of the two light-emitting control signal lines.

[0026] According to some exemplary embodiments, a spacing distance between the scan signal line and an adjacent one of the light emitting control signal lines along the second direction is equal to a spacing distance between the scan signal line and another adjacent one of the light emitting control signal lines along the second direction.

[0027] According to some exemplary embodiments, the display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer located on the base substrate, the semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer are sequentially arranged away from the base substrate, the driving transistor includes a third active layer and a third gate, the third active layer is located in the semiconductor layer, and the third gate is located in the first conductive layer; the pixel driving circuit also includes a storage capacitor, the storage capacitor includes a first plate and a second plate, the first plate includes the third gate, and the second plate is located in the second conductive layer; the display substrate also includes a plurality of data lines located on the base substrate, the data lines are located in the third conductive layer; the orthographic projection of the second plate on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate.

[0028] According to some exemplary embodiments, the data line and the first voltage line both extend along the second direction; in an adjacent area between two adjacent pixel driving circuits located in the same row, two of the data lines and one of the first voltage lines extend through, and in the adjacent area, the orthographic projection of the first voltage line on the substrate is located between the orthographic projections of the two data lines on the substrate.

[0029] According to some exemplary embodiments, the display substrate further includes a first conductive connection portion, which is located in the second conductive layer; the pixel driving circuit further includes a fourth transistor, which includes a first electrode and a second electrode; the first conductive connection portion is connected to a reference voltage, and one end of the first conductive connection portion is electrically connected to the first electrode of the fourth transistor through a second via hole to connect the reference voltage to the first electrode of the fourth transistor; the second electrode of the fourth transistor is electrically connected to the second electrode plate through a third via hole.

[0030] According to some exemplary embodiments, an orthographic projection of the third via hole on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate.

[0031] According to some exemplary embodiments, the orthographic projection of the second electrode plate on the base substrate has a first side portion close to the orthographic projection of the third via hole on the base substrate and a second side portion away from the orthographic projection of the third via hole on the base substrate, the first side portion of the orthographic projection of the second electrode plate on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate, and / or the second side portion of the orthographic projection of the second electrode plate on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate.

[0032] According to some exemplary embodiments, the display substrate further includes a second conductive connection portion, which is located in the second conductive layer; the pixel driving circuit further includes a second transistor, which includes a first electrode and a second electrode; one end of the second conductive connection portion is electrically connected to the third gate through a fourth via, and the other end of the second conductive connection portion is electrically connected to the first electrode of the second transistor through a fifth via.

[0033] According to some exemplary embodiments, the display substrate further includes a third electrode plate, which is located in the third conductive layer; the third electrode plate is electrically connected to the second conductive connection portion through a sixth via hole, and the orthographic projection of the third electrode plate on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate on the base substrate.

[0034] According to some exemplary embodiments, an orthographic projection of the sixth via hole on the base substrate at least partially overlaps with an orthographic projection of the fourth via hole on the base substrate.

[0035] According to some exemplary embodiments, the display substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the base substrate, and the first voltage line is located in the fourth conductive layer; the display substrate further includes a fourth electrode plate, which is located in the fourth conductive layer; the fourth electrode plate is electrically connected to the second electrode plate through a seventh via hole, and the orthographic projection of the fourth electrode plate on the base substrate at least partially overlaps with the orthographic projection of the third electrode plate on the base substrate.

[0036] According to some exemplary embodiments, the orthographic projections of any two of the first plate, the second plate, the third plate, and the fourth plate on the substrate at least partially overlap to form a first sub-capacitor between the first plate and the second plate, a second sub-capacitor between the second plate and the third plate, and a third sub-capacitor between the third plate and the fourth plate, and the storage capacitor includes the first sub-capacitor, the second sub-capacitor, and the third sub-capacitor.

[0037] According to some exemplary embodiments, for a sub-pixel, the pixel driving circuit of the sub-pixel is electrically connected to the light-emitting element through the anode connection hole; for the pixel driving circuits of two adjacent sub-pixels located in the same row arranged in two rows, the anode connection holes of the two sub-pixels are spaced apart by a first specified distance in the first direction, and the anode connection holes of the two sub-pixels are spaced apart by a second specified distance in the second direction.

[0038] According to some exemplary embodiments, the seventh via hole at least partially overlaps with an orthographic projection of the third via hole along the first direction; and / or the seventh via hole at least partially overlaps with an orthographic projection of the anode connection hole along the second direction.

[0039] According to some exemplary embodiments, in two rows of pixel units, the relative position of the anode connection hole of at least one sub-pixel in one row of pixel units relative to the third channel region of the driving transistor of the pixel driving circuit of the sub-pixel is different from the relative position of the anode connection hole of at least one sub-pixel of the same color in another row of pixel units relative to the third channel region of the driving transistor of the pixel driving circuit of the sub-pixel of the same color.

[0040] According to some exemplary embodiments, the pixel driving circuit further includes a first transistor, the first transistor including a gate and a first channel region, a portion of the scanning signal line overlapping with the semiconductor layer forms the gate of the first transistor; the data line is electrically connected to a portion of the semiconductor layer located on one side of the first channel region through an eighth via hole; any two of the orthographic projections of the second via hole, the third via hole, and the eighth via hole along the second direction at least partially overlap.

[0041] According to some exemplary embodiments, the pixel driving circuit further includes a fifth transistor, the fifth transistor including a gate and a fifth channel region, and a portion of the light-emitting control signal line overlapping with the semiconductor layer constitutes the gate of the fifth transistor; the light-emitting element is electrically connected to a portion of the semiconductor layer located on one side of the fifth channel region through an anode connection hole; for two adjacent pixel driving circuits located in the same row, any two of the orthographic projections of the first via hole, the second via hole and the anode connection hole along the first direction at least partially overlap.

[0042] In another aspect, a display panel is provided, comprising the display substrate as described above.

[0043] In yet another aspect, a display device is provided, comprising the display substrate as described above or the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0045] Figure 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure;

[0046] Figure 2A is a planar schematic diagram of multiple sub-pixels of a display substrate in the related art;

[0047] Figure 2B is a planar schematic diagram of a pixel driving circuit for multiple sub-pixels of a display substrate in the related art;

[0048] Figure 3A is a schematic plan view of a plurality of sub-pixels of a display substrate according to an embodiment of the present disclosure;

[0049] Figure 3B is a schematic plan view of a pixel driving circuit for a plurality of sub-pixels of a display substrate according to an embodiment of the present disclosure;

[0050] Figure 4 is a schematic diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0051] Figure 5 is a partial timing diagram of a pixel driving circuit of a display substrate according to an embodiment of the present disclosure;

[0052] Figures 6 to 17 is a partial plan view of a display substrate according to an embodiment of the present disclosure, which schematically shows a plan view of pixel driving circuits of several sub-pixels included in the display substrate, wherein: Figure 6is a partial plan view of a semiconductor layer included in a display substrate according to an embodiment of the present disclosure, Figure 7 is a partial plan view of a first conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 8 is a partial plan view of a first insulating layer included in a display substrate according to an embodiment of the present disclosure, Figure 9 is a partial plan view of a second conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 10 is a partial plan view of a second insulating layer included in a display substrate according to an embodiment of the present disclosure, Figure 11 is a partial plan view of a third conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 12 is a partial plan view of a third insulating layer included in a display substrate according to an embodiment of the present disclosure, Figure 13 is a partial plan view of a fourth conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 14 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, and a first insulating layer included in a display substrate according to an embodiment of the present disclosure. Figure 15 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a first insulating layer, and a second conductive layer included in a display substrate according to an embodiment of the present disclosure. Figure 16 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer included in a display substrate according to an embodiment of the present disclosure. Figure 17 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer included in a display substrate according to an embodiment of the present disclosure;

[0053] Figure 18 The display substrate according to the embodiment of the present disclosure is Figure 17 A cross-sectional view taken along line AA' in FIG.

[0054] Figure 19 Schematically shows Figure 4 Schematic diagram of the storage capacitor in .

[0055] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0056] The technical solution of the present disclosure is further described in detail below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of the present disclosure and should not be construed as limiting the present disclosure.

[0057] Furthermore, in the following detailed description, for ease of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent that one or more embodiments can be practiced without these specific details.

[0058] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0059] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0060] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0062] Those skilled in the art should understand that, herein, unless otherwise specified, the expressions "continuous extension", "integrated structure", "monolithic structure" or similar expressions mean that multiple elements, components, structures and / or parts are located on the same layer and are usually formed by the same patterning process during the manufacturing process. There are no spaces or breaks between these elements, components, structures and / or parts, but they are continuously extended structures.

[0063] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along the pixel region, for example, the longitudinal direction and the transverse direction of the pixel region. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0064] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the thin film transistors used here are symmetrical, their source and drain can be interchanged. In the embodiments of the present disclosure, the transistor may include a gate, a first electrode and a second electrode, wherein the first electrode can represent one of the source and the drain, and the second electrode can represent the other of the source and the drain. In the following examples, the case of a P-type thin film transistor used as a driving transistor is mainly described, and other transistors have the same or different types as the driving transistor according to the circuit design. Similarly, in other embodiments, the driving transistor may also be shown as an N-type thin film transistor.

[0065] Herein, the expression "PPI" (Pixels Per Inch) refers to pixel density, which represents the number of pixels set per inch. Generally, a higher PPI value represents that the display device can display images at a higher density.

[0066] Some exemplary embodiments of the present disclosure provide a display substrate, comprising: a base substrate; a plurality of pixel units disposed on the base substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction to form multiple rows of pixel units and multiple columns of pixel units, at least one of the pixel units comprising multiple sub-pixels, at least one sub-pixel comprising a light-emitting element and a pixel driving circuit for driving the light-emitting element; and a plurality of scanning signal lines disposed on the base substrate, the plurality of scanning signal lines respectively supplying scanning signals to the multiple rows of pixel units, the plurality of scanning signal lines being arranged at intervals along the second direction, and at least one of the scanning signal lines extending along the first direction, wherein the orthographic projections of the pixel driving circuits of the multiple sub-pixels on the base substrate at least partially overlap with the orthographic projections of the light-emitting elements of the same sub-pixel on the base substrate.

[0067] For example, for at least one row of pixel units, the light-emitting elements of multiple sub-pixels located in the same row are arranged side by side along the first direction, and the pixel driving circuits of the multiple sub-pixels located in the same row are arranged into two rows along the second direction. In each of the two rows of pixel driving circuits, multiple pixel driving circuits are arranged side by side along the first direction.

[0068] By adopting the layout provided by the embodiments of the present disclosure, it is beneficial to realize a high PPI display device and to improve the display quality of the display device.

[0069] Figure 1 : is a schematic plan view of a display substrate according to an embodiment of the present disclosure. Figure 1 , a display substrate according to an embodiment of the present disclosure may include a base substrate 100 and a pixel unit PX disposed on the base substrate 100 .

[0070] The display substrate may include a display area AA and a non-display area NA. The display area AA may be an area where pixel cells PX displaying an image are located. Each pixel cell PX will be described later. The non-display area NA is an area where pixel cells PX are not located, that is, an area where no image is displayed. The non-display area NA corresponds to the bezel in the final display device, and the width of the bezel is determined based on the width of the non-display area NA.

[0071] The display area AA can have various shapes. For example, the display area AA can be provided in various shapes, such as a closed polygon (e.g., a rectangle) with straight sides, a circle or an ellipse with curved sides, or a semicircle or a semiellipse with both straight and curved sides. In the embodiment of the present disclosure, the display area AA is provided as a quadrilateral with straight sides. It should be understood that this is merely an exemplary embodiment of the present disclosure and is not intended to limit the present disclosure.

[0072] The non-display area NA may be provided on at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in a first direction X and a longitudinal portion extending in a second direction Y.

[0073] The pixel unit PX is provided in the display area AA. The pixel unit PX is the smallest unit for displaying an image and may be provided in plurality. For example, the pixel unit PX may include a light emitting device that emits white light and / or colored light.

[0074] The pixel units PX may be provided in a plurality and arranged in a matrix along rows extending in the first direction X and columns extending in the first direction Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel units PX, and the pixel units PX may be arranged in various forms. For example, the pixel units PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0075] That is, the plurality of pixel units PX are arranged in an array along the first direction X and the second direction Y to form a plurality of rows of pixel units and a plurality of columns of pixel units.

[0076] A pixel unit PX may include multiple sub-pixels. For example, a pixel unit PX may include three sub-pixels, namely a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel.

[0077] It should be noted that, in the embodiment of the present disclosure, the number of sub-pixels included in a pixel unit is not particularly limited and is not limited to the above-mentioned three.

[0078] For example, in Figure 1 In the exemplary embodiment shown, scan signal lines 61 and data lines 64 are schematically illustrated. Specifically, the display substrate may further include: a plurality of scan signal lines 61 and a plurality of data lines 64 disposed on the base substrate. The plurality of scan signal lines 61 supply scan signals to multiple rows of pixel units, and the plurality of data lines 64 supply data signals to multiple columns of pixel units. The scan signal lines 61 extend along a first direction X and are spaced apart along a second direction Y. The data lines 64 extend along the second direction Y and are spaced apart along the first direction X.

[0079] For example, the scan signal line may be a representative of a horizontal line, and the data line may be a representative of a vertical line. It should be understood that the horizontal line may also include lines of other types or lines for supplying other signals, and the vertical line may also include lines of other types or lines for supplying other signals.

[0080] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, in an OLED display substrate or display panel, the light-emitting element of a sub-pixel may include a stacked anode, a light-emitting material layer, and a cathode. The anodes of the light-emitting elements of each sub-pixel are spaced apart and arranged in a matrix along rows extending in a first direction X and columns extending in a first direction Y.

[0081] Herein, for the convenience of description, in each plan view, the corresponding sub-pixel is represented by the orthographic projection of the anode of the light-emitting element of the sub-pixel on the base substrate.

[0082] Figure 2A is a planar schematic diagram of multiple sub-pixels of a display substrate in the related art, Figure 2B It is a planar schematic diagram of a pixel driving circuit for multiple sub-pixels of a display substrate in the related art.

[0083] Combined with reference Figure 2A and Figure 2B , a plurality of sub-pixels SP1 , SP2 , and SP3 located in the same row are arranged side by side along the first direction X, that is, arranged side by side in the horizontal direction.

[0084] The first sub-pixel SP1 may include a first light-emitting element located in the first light-emitting area and a first pixel driving circuit SPC1 for driving the first light-emitting element, and the first light-emitting element may emit red light; the second sub-pixel SP2 may include a second light-emitting element located in the second light-emitting area and a second pixel driving circuit SPC2 for driving the second light-emitting element, and the second light-emitting element may emit green light; the third sub-pixel SP3 may include a third light-emitting element located in the third light-emitting area and a third pixel driving circuit SPC3 for driving the third light-emitting element, and the third light-emitting element may emit blue light.

[0085] It should be noted that the light-emitting region of a sub-pixel may be the region where the light-emitting element of the sub-pixel is located. For example, the light-emitting region of a sub-pixel may be the region corresponding to the anode of the light-emitting element of the sub-pixel, or the light-emitting region of a sub-pixel may be the region corresponding to the portion of the light-emitting material layer sandwiched between the anode and the cathode.

[0086] In related art, the pixel driving circuits of the sub-pixels SP1, SP2, and SP3, namely the first pixel driving circuit SPC1, the second pixel driving circuit SPC2, and the third pixel driving circuit SPC3, are also arranged side by side along the first direction X, namely arranged side by side in the horizontal direction.

[0087] exist Figure 2B In the figure, the anode connection hole VHA is schematically shown by a dotted box, through which the anode of the light-emitting element of each sub-pixel can be electrically connected to the pixel driving circuit below, so that the pixel driving circuit of each sub-pixel can drive its own light-emitting element.

[0088] exist Figure 2A and Figure 2B In the example shown, the orthographic projections of the anodes of the light-emitting elements of each sub-pixel SP1, SP2, and SP3 on the substrate substantially coincide with the orthographic projections of the respective pixel driving circuits SPC1, SPC2, and SPC3 on the substrate. Thus, the sub-pixels SP1, SP2, and SP3 are arranged side by side along the first direction X, i.e., in a horizontally side-by-side layout. Correspondingly, the pixel driving circuits SPC1, SPC2, and SPC3 of each sub-pixel are also arranged side by side along the first direction X, i.e., in a horizontally side-by-side layout.

[0089] With the development of technology, the PPI of display devices continues to increase. As the PPI continues to increase, the width of the sub-pixel becomes narrower. Figure 2A and Figure 2B In the example shown, the width of the pixel driver circuit is directly related to the width of the sub-pixels. Specifically, when the pixel driver circuits are arranged side by side horizontally, the requirements for high PPI require a reduced width of the pixel driver circuit. Consequently, the size of each transistor included in the pixel driver circuit must be reduced, making it difficult to implement larger driver transistors. Consequently, the driving performance of the pixel driver circuit may not meet the requirements of a high-PPI display device, making it difficult to improve the display quality of the display device.

[0090] In addition, refer to Figure 2B In a high PPI display device, the width of each sub-pixel is relatively narrow. Usually, the size of the anode PAD (i.e., the electrical connection portion for electrically connecting the anode to the pixel driving circuit below) corresponding to the anode connection hole VHA is set larger to facilitate improving the electrical connection capability between the anode and the pixel driving circuit. Figure 2A and Figure 2B In the layout shown, the anode PADs of the sub-pixels are arranged side by side, which results in limited space for arranging longitudinal wiring on the display substrate, that is, it is not conducive to arranging longitudinal wiring on the display substrate.

[0091] Figure 3Ais a schematic plan view of a plurality of sub-pixels of a display substrate according to an embodiment of the present disclosure, Figure 3B 4 is a planar schematic diagram of a pixel driving circuit for a plurality of sub-pixels of a display substrate according to an embodiment of the present disclosure.

[0092] Combined with reference Figure 3A and Figure 3B , a plurality of sub-pixels SP1 , SP2 , and SP3 located in the same row are arranged side by side along the first direction X, that is, arranged side by side in the horizontal direction.

[0093] The first sub-pixel SP1 may include a first light-emitting element located in the first light-emitting area and a first pixel driving circuit SPC1 for driving the first light-emitting element, and the first light-emitting element may emit red light; the second sub-pixel SP2 may include a second light-emitting element located in the second light-emitting area and a second pixel driving circuit SPC2 for driving the second light-emitting element, and the second light-emitting element may emit green light; the third sub-pixel SP3 may include a third light-emitting element located in the third light-emitting area and a third pixel driving circuit SPC3 for driving the third light-emitting element, and the third light-emitting element may emit blue light.

[0094] It should be noted that the light-emitting region of a sub-pixel may be the region where the light-emitting element of the sub-pixel is located. For example, the light-emitting region of a sub-pixel may be the region corresponding to the anode of the light-emitting element of the sub-pixel, or the light-emitting region of a sub-pixel may be the region corresponding to the portion of the light-emitting material layer sandwiched between the anode and the cathode.

[0095] In the embodiment of the present disclosure, the orthographic projections of the pixel driving circuits of the plurality of sub-pixels on the substrate at least partially overlap with the orthographic projections of the light-emitting elements of the same sub-pixel on the substrate. Figure 3A and Figure 3B, the orthographic projections of the pixel driving circuits SPC1 and SPC2 of the multiple sub-pixels on the substrate at least partially overlap with the orthographic projections of the light-emitting element of the same sub-pixel SP1 on the substrate. The orthographic projections of the pixel driving circuits SPC1 and SPC2 of the multiple sub-pixels on the substrate at least partially overlap with the orthographic projections of the light-emitting element of the same sub-pixel SP2 on the substrate. The orthographic projections of the pixel driving circuits SPC3 and SPC1 of the multiple sub-pixels on the substrate at least partially overlap with the orthographic projections of the light-emitting element of the same sub-pixel SP3 on the substrate. The orthographic projections of the pixel driving circuits SPC3 and SPC1 of the multiple sub-pixels on the substrate at least partially overlap with the orthographic projections of the light-emitting element of the same sub-pixel SP1 on the substrate. The orthographic projections of the pixel driving circuits SPC2 and SPC3 of the multiple sub-pixels on the substrate at least partially overlap with the orthographic projections of the light-emitting element of the same sub-pixel SP2 on the substrate. The orthographic projections of the pixel driving circuits SPC2 and SPC3 of the plurality of sub-pixels on the base substrate respectively at least partially overlap with the orthographic projections of the light emitting element of the same sub-pixel SP3 on the base substrate.

[0096] For example, in an embodiment of the present disclosure, the pixel driving circuits of the plurality of sub-pixels SP1, SP2, and SP3 located in the same row, namely the first pixel driving circuit SPC1, the second pixel driving circuit SPC2, and the third pixel driving circuit SPC3, are arranged in two rows.

[0097] For example, for at least one row of pixel units, the light emitting elements of a plurality of sub-pixels SP1, SP2, and SP3 in the same row are arranged side by side along the first direction X, such as Figure 3A As shown. The pixel driving circuits SPC1, SPC2, and SPC3 of the multiple sub-pixels located in the same row are arranged into two rows along the second direction Y. In each of the two rows of pixel driving circuits SPC1, SPC2, and SPC3, the multiple pixel driving circuits SPC1, SPC2, and SPC3 are arranged side by side along the first direction X, as shown. Figure 3B shown.

[0098] It should be noted that, in the illustrated embodiment, the orthographic projection of the pixel driving circuits of two sub-pixels on the substrate substrate at least partially overlaps with the orthographic projection of the light-emitting element of the same sub-pixel on the substrate substrate, that is, the pixel driving circuits of two sub-pixels correspond to the light-emitting element of one sub-pixel, but the embodiments of the present disclosure are not limited to this. In other embodiments, pixel driving circuits of more than two sub-pixels can be set to correspond to the light-emitting element of one sub-pixel, for example, pixel driving circuits of three sub-pixels correspond to the light-emitting element of one sub-pixel, and pixel driving circuits of four sub-pixels correspond to the light-emitting element of one sub-pixel.

[0099] exist Figure 3B In the figure, the anode connection hole VHA is schematically shown by a dotted box, through which the anode of the light-emitting element of each sub-pixel can be electrically connected to the pixel driving circuit below, so that the pixel driving circuit of each sub-pixel can drive its own light-emitting element.

[0100] In the embodiment of the present disclosure, the layout of each sub-pixel remains unchanged and still adopts a horizontal side-by-side layout. The pixel driving circuits of the sub-pixels in the same row are arranged in two rows. The light-emitting elements of each sub-pixel can still be electrically connected to the pixel driving circuit below through the anode connection hole VHA, so that the pixel driving circuit of each sub-pixel can still drive its own light-emitting element.

[0101] In the embodiment of the present disclosure, in response to the demand for high PPI, the width of the area occupied by the pixel driving circuit can be increased while the layout of each sub-pixel remains unchanged. Figure 3A and Figure 3B In the illustrated embodiment, for the six sub-pixels, the six sub-pixels can still be arranged in the same row along the first direction X, and the pixel driving circuits of the six sub-pixels are arranged in two rows, that is, three pixel driving circuits are arranged in each row. For example, the width of the area occupied by one pixel driving circuit can be approximately twice the width of the area occupied by one sub-pixel. In this way, in a high PPI display device, a larger driving transistor can be implemented, which is beneficial to improving the driving performance of the pixel driving circuit. For example, when the size of the driving transistor is increased, its performance can be more stable, its data range can be larger, and the number of grayscales it supports can be greater. Therefore, by adopting the layout provided by the embodiments of the present disclosure, it is beneficial to realize a high PPI display device and to improve the display quality of the display device.

[0102] In addition, refer to Figure 3B The anode PAD corresponding to the anode connection hole VHA (i.e., the electrical connection portion for electrically connecting the anode and the pixel driving circuit below) can also be arranged in at least two rows. In this way, the space between each anode PAD will be larger, that is, the space for arranging the longitudinal wiring on the display substrate will be increased, which is conducive to arranging the longitudinal wiring on the display substrate.

[0103] For example, in Figure 3A In FIG, each rectangular frame may represent a schematic representation of the outline of the positive projection of the anode of the light-emitting element of each sub-pixel on the substrate; Figure 3B In the figure, each solid rectangular box may represent a schematic representation of the outline of the positive projection of the pixel driving circuit of each sub-pixel on the substrate.

[0104] It should be noted that in Figures 1 to 3BAlthough a rectangular frame is used to represent each sub-pixel and its pixel driving circuit, it should be understood that the rectangular frame only schematically represents the layout of each sub-pixel and its pixel driving circuit, and its shape does not limit the shape of the sub-pixel and its pixel driving circuit.

[0105] In an embodiment of the present disclosure, for the same sub-pixel, the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate and the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate have the following relationship: the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate exceeds the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate in a first direction X; and / or, the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate exceeds the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate in a second direction Y.

[0106] For example, for the same sub-pixel, the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate and the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate have the following relationship: the ratio of the dimension W1 of the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate in the first direction X to the dimension W2 of the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate in the first direction X is between 1.5-3, for example, between 1.8-2.5, for example, approximately 2; and / or, the ratio of the dimension H2 of the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate in the second direction Y to the dimension H1 of the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate in the second direction Y is between 1.5-3, for example, between 1.8-2.5, for example, approximately 2.

[0107] Figure 4 is a schematic diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Figure 4 The pixel driving circuit shown in FIG can be any one of the above-mentioned pixel driving circuits SPC1, SPC2, and SPC3. Figure 4 The pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a storage capacitor Cst. This pixel driving circuit may be referred to as a 5T1C structure.

[0108] It should be noted that the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is described here using the 5T1C structure as an example, but the pixel driving circuit included in the display substrate according to the embodiment of the present disclosure is not limited to the 5T1C structure.

[0109] Continue to refer to Figure 4The gate G1 of the first transistor T1 is electrically connected to the scan signal line 61 for receiving the scan signal Sn. The first electrode (e.g., source S1) of the first transistor T1 is electrically connected to the data line 64 for receiving the data signal Dm. The second electrode (e.g., drain D1) of the first transistor T1 is electrically connected to the node N1.

[0110] The gate G2 of the second transistor T2 is electrically connected to the scan signal line 61 for receiving the scan signal Sn. The first electrode (eg, source S2) of the second transistor T2 is electrically connected to the node N3. The second electrode (eg, drain D2) of the second transistor T2 is electrically connected to the node N2.

[0111] The gate G3 of the third transistor T3 (i.e., the driving transistor) is electrically connected to the node N2. A first electrode (e.g., the source S3) of the third transistor T3 is electrically connected to the first voltage line 65 for receiving the first voltage VDD. A second electrode (e.g., the drain D3) of the third transistor T3 is electrically connected to the node N3.

[0112] The gate G4 of the fourth transistor T4 is electrically connected to the light-emission control signal line 63 for receiving the light-emission control signal En. The first electrode (e.g., source S4) of the fourth transistor T4 is electrically connected to the reference voltage line 66 for receiving the reference voltage Vref. The second electrode (e.g., drain D4) of the fourth transistor T4 is electrically connected to the node N1.

[0113] A gate G5 of the fifth transistor T5 is electrically connected to the light-emission control signal line 63 for receiving the light-emission control signal En. A first electrode (e.g., source S5) of the fifth transistor T5 is electrically connected to the node N3. A second electrode (e.g., drain D5) of the fifth transistor T5 is electrically connected to an electrode, e.g., an anode, of the light-emitting element OLED.

[0114] Another electrode of the light emitting element OLED, for example, a cathode, is electrically connected to the second voltage line 67 for receiving the second voltage VSS.

[0115] A first electrode Cst1 of the storage capacitor Cst is electrically connected to the node N2 , and a second electrode Cst2 of the storage capacitor Cst is electrically connected to the node N1 .

[0116] Figure 5 This is a partial timing diagram of the pixel driving circuit of the display substrate according to the embodiment of the present disclosure. Figure 5 right Figure 4 The working principle of the pixel circuit shown is further explained.

[0117] Combined with reference Figure 4 and Figure 5 , in the data storage and threshold compensation stage t1, as Figure 5As shown, the scanning signal line 61 is enabled row by row, and the scanning signal S1...Sn is input into the scanning signal line 61 row by row. The first transistor T1 and the second transistor T2 are turned on, and the data signal line 64 inputs the data signal Dm. The data signal Dm transmits the required data voltage Vdata to each row of pixel driving circuits as the scanning signal line 61 is enabled; the fourth transistor T4 and the fifth transistor T5 are turned off.

[0118] Because one end of the storage capacitor Cst is electrically connected to the second electrode D1 of the first transistor T1, the data voltage Vdata is stored at node N1. At this time, the voltage of the storage capacitor Cst at node N1 is Vdata. The other end of the storage capacitor Cst is electrically connected to the gate of the third transistor T3 and the second electrode D2 of the second transistor T2. Since the second transistor T2 is on, the gate and drain of the third transistor T3 are directly connected. The storage capacitor Cst discharges through the third transistor T3 in a diode connection until the third transistor T3 is turned off. At this time, the voltage of the storage capacitor Cst at node N2 is VDD + Vth, thereby simultaneously storing the data voltage Vdata and acquiring the threshold voltage Vth of the driving transistor. That is, the storage capacitor Cst stores the data voltage Vdata and the threshold voltage Vth of the driving transistor T3. The voltage difference between nodes N1 and N2 includes the threshold voltage Vth of the driving transistor T3 and the data voltage Vdata.

[0119] During the light-emitting phase t2, the light-emitting control signal line 63 is enabled, the fourth transistor T4 and the fifth transistor T5 are turned on, the reference voltage Vref is written to the node N1, and the change in node N1 is fed back to the node N2, causing the potential of node N2 to become VDD + Vth + (Vref - Vdata). The source-gate voltage difference Vsg of the third transistor T3 can be calculated using the following formula: Vsg = VDD - Vref + Vdata - (VDD + Vth) + Vth = Vdata - Vref. From this, it can be concluded that the current flowing through the third transistor T3 (i.e., the current flowing through the OLED) Id = k(Vdata - Vref). 2 , where k is a constant coefficient, which is related to the mobility, aspect ratio and gate-source capacitance of the third transistor T3.

[0120] Figures 6 to 17 FIG is a partial plan view of a display substrate according to an embodiment of the present disclosure, which schematically shows a plan view of pixel driving circuits of several sub-pixels included in the display substrate. Figure 6 is a partial plan view of a semiconductor layer included in a display substrate according to an embodiment of the present disclosure, Figure 7 is a partial plan view of a first conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 8is a partial plan view of a first insulating layer included in a display substrate according to an embodiment of the present disclosure, Figure 9 is a partial plan view of a second conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 10 is a partial plan view of a second insulating layer included in a display substrate according to an embodiment of the present disclosure, Figure 11 is a partial plan view of a third conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 12 is a partial plan view of a third insulating layer included in a display substrate according to an embodiment of the present disclosure, Figure 13 is a partial plan view of a fourth conductive layer included in a display substrate according to an embodiment of the present disclosure, Figure 14 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, and a first insulating layer included in a display substrate according to an embodiment of the present disclosure. Figure 15 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a first insulating layer, and a second conductive layer included in a display substrate according to an embodiment of the present disclosure. Figure 16 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a third conductive layer included in a display substrate according to an embodiment of the present disclosure. Figure 17 is a partial plan view of a combination of a semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, and a fourth conductive layer included in a display substrate according to an embodiment of the present disclosure. Figure 18 The display substrate according to the embodiment of the present disclosure is Figure 17 A cross-sectional view taken along line AA' in FIG.

[0121] Combined with reference Figures 6 to 18 The display substrate may include at least one semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers. For example, at least one insulating layer may be disposed between adjacent semiconductor layers and conductive layers, and between adjacent conductive layers.

[0122] For example, Figure 6 A portion of the semiconductor layer 50 is shown. The semiconductor layer may include materials such as amorphous silicon, polycrystalline silicon or an oxide semiconductor, and may include, for example, a channel region, a source region and a drain region. The channel region may not be doped or may have a different doping type from the source region and the drain region, and thus have semiconductor properties. The source region and the drain region are respectively located on either side of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor. For example, in an embodiment of the present disclosure, each transistor may be an N-type thin film transistor.

[0123] For the sake of convenience, the plurality of insulating layers are described as a fourth insulating layer GI1, a first insulating layer GI2, a second insulating layer ILD1, and a third insulating layer ILD2. For example, these insulating layers may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The fourth insulating layer GI1 may be provided between the semiconductor layer 50 and the first conductive layer 10. For example, Figure 8 A portion of a first insulating layer GI2 is shown, and the first insulating layer GI2 may be disposed between the first conductive layer 10 and the second conductive layer 20 . Figure 10 A portion of the second insulating layer ILD1 is shown, and the second insulating layer ILD1 may be disposed between the second conductive layer 20 and the third conductive layer 30 . Figure 12 A portion of the third insulating layer ILD2 is shown, and the third insulating layer ILD2 may be disposed between the third conductive layer 30 and the fourth conductive layer 40 .

[0124] It should be noted that in Figures 6 to 18 In the figure, in order to better illustrate the electrical connection relationship between the various components located in the semiconductor layer and each conductive layer, only the vias located in each insulating layer are schematically shown. Generally, these vias pass through the corresponding insulating layer to electrically connect the semiconductor layer located on the upper and lower sides of the insulating layer and the various components in each conductive layer.

[0125] For example, the semiconductor layer 50, the fourth insulating layer GI1, the first conductive layer 10, the first insulating layer GI2, the second conductive layer 30, the second insulating layer IDL1, the third conductive layer 40, the third insulating layer IDL2 and the fourth conductive layer 40 are sequentially arranged on the base substrate of the display substrate.

[0126] The display substrate may include a plurality of signal lines disposed on the base substrate. Figure 4 The plurality of signal lines may include a scan signal line 61 , a light emitting control signal line 63 , a data line 64 , a first voltage line 65 and a second voltage line 67 .

[0127] For example, the scan signal line 61 and the light emitting control signal line 63 may extend substantially along the first direction X, ie, they are horizontal lines. The data line 64 and the first voltage line 65 may extend substantially along the second direction Y, ie, they are vertical lines.

[0128] Combined with reference Figure 4 and Figure 6 The active layers of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 may be arranged along the lines shown in FIG. Figure 6The semiconductor layer may have a curved or bent shape and may include a first active layer 20a corresponding to the first transistor T1, a second active layer 20b corresponding to the second transistor T2, a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, and a fifth active layer 20e corresponding to the fifth transistor T5.

[0129] The first active layer 20a includes a first source region 203a, a first drain region 205a, and a first channel region 201a connecting the first source region 203a and the first drain region 205a. The first source region 203a and the first drain region 205a extend in two opposite directions relative to the first channel region 201a.

[0130] The second active layer 20b includes a second source region 203b, a second drain region 205b, and a second channel region 201b connecting the second source region 203b and the second drain region 205b. The second source region 203b and the second drain region 205b extend in two opposite directions relative to the second channel region 201b.

[0131] The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in two opposite directions relative to the third channel region 201c.

[0132] The fourth active layer 20d includes a fourth source region 203d, a fourth drain region 205d, and a fourth channel region 201d connecting the fourth source region 203d and the fourth drain region 205d. The fourth source region 203d and the fourth drain region 205d extend in two opposite directions relative to the fourth channel region 201d.

[0133] The fifth active layer 20e includes a fifth source region 203e, a fifth drain region 205e, and a fifth channel region 201e connecting the fifth source region 203e and the fifth drain region 205e. The fifth source region 203e and the fifth drain region 205e extend in two opposite directions relative to the fifth channel region 201e.

[0134] Reference Figure 6For the driving transistor (i.e., the third transistor T3), its channel region (i.e., the third channel region 201c) extends along the first direction X, i.e., extends laterally. Specifically, the orthographic projection of the third channel region 201c on the substrate includes a first side 201c1, a second side 201c2, a third side 201c3, and a fourth side 201c4. The first side 201c1 and the second side 201c2 are located on opposite sides of the orthographic projection of the third channel region 201c on the substrate in the first direction X. That is, the first side 201c1 and the second side 201c2 serve as the left and right edges of the third channel region 201c. The third side 201c3 and the fourth side 201c4 are located on opposite sides of the orthographic projection of the third channel region 201c on the substrate in the second direction Y. That is, the third side 201c3 and the fourth side 201c4 serve as the upper and lower edges of the third channel region 201c. A first distance XC1 between the first side 201c1 and the second side 201c2 along the first direction X is greater than a second distance YC1 between the third side 201c3 and the fourth side 201c4 along the second direction Y.

[0135] In the embodiment of the present disclosure, the channel region of the driving transistor T3 can be extended laterally, thereby realizing a larger driving transistor, thereby making the performance of the driving transistor more stable, its data range larger, and the number of grayscales it supports more.

[0136] Reference Figures 6 to 18 , which schematically shows a plan view of a pixel driving circuit for 2 rows and 8 columns of sub-pixels. In the embodiment of the present disclosure, the pixel driving circuits of each sub-pixel can be arranged horizontally. The pixel driving circuits of multiple sub-pixels (for example, 8 sub-pixels) located in the same row can be arranged in 2 rows. Figure 17 As described above, the pixel driving circuits of the 8 sub-pixels in the first row can be arranged in 2 rows. For the convenience of description, the pixel driving circuits of the 8 sub-pixels are respectively represented as pixel driving circuits PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8. Figure 17 , the pixel driving circuits PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8 are schematically shown by dotted boxes respectively.

[0137] In the illustrated embodiment, the pixel driving circuits of the 2 rows and 8 columns of sub-pixels can be arranged in 4 rows and 4 columns. This arrangement can increase the size of each pixel driving circuit in the first direction, thereby facilitating the realization of a larger driving transistor.

[0138] In an embodiment of the present disclosure, for pixel driving circuits located in the same row, the orthographic projections of two adjacent pixel driving circuits in the first direction X on the substrate have an axisymmetric relationship. For example, pixel driving circuits PC1, PC2, PC3, and PC4 are located in the first row, that is, in the same row. The orthographic projections of two adjacent pixel driving circuits PC1 and PC2 in the first direction X on the substrate have an axisymmetric relationship, for example, they are axisymmetric with respect to the symmetry axis AX1; the orthographic projections of two adjacent pixel driving circuits PC2 and PC3 in the first direction X on the substrate have an axisymmetric relationship, for example, they are axisymmetric with respect to the symmetry axis AX2; and the orthographic projections of two adjacent pixel driving circuits PC3 and PC4 in the first direction X on the substrate have an axisymmetric relationship, for example, they are axisymmetric with respect to the symmetry axis AX3. For another example, the pixel driving circuits PC5, PC6, PC7, and PC8 are located in the second row, that is, in the same row, and the orthographic projections of the two adjacent pixel driving circuits PC5 and PC6 in the first direction X on the substrate have an axially symmetrical relationship, for example, they are axially symmetrical relative to the symmetry axis AX1; the orthographic projections of the two adjacent pixel driving circuits PC6 and PC7 in the first direction X on the substrate have an axially symmetrical relationship, for example, they are axially symmetrical relative to the symmetry axis AX2; the orthographic projections of the two adjacent pixel driving circuits PC7 and PC8 in the first direction X on the substrate have an axially symmetrical relationship, for example, they are axially symmetrical relative to the symmetry axis AX3.

[0139] It should be noted that, in the embodiments of the present disclosure, the axis of symmetry is an imaginary axis and is not intended to refer to a physical axis.

[0140] In an embodiment of the present disclosure, for pixel driving circuits arranged in two rows for a plurality of sub-pixels located in the same row, the orthographic projections of two adjacent pixel driving circuits in the second direction on the substrate have a rotationally symmetrical relationship. For example, pixel driving circuits PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8 are pixel driving circuits arranged in two rows for a plurality of sub-pixels located in the same row. For two adjacent pixel driving circuits in the second direction Y, such as pixel driving circuits PC1 and PC5, the orthographic projections on the substrate have a rotationally symmetrical relationship, for example, they are rotationally symmetrical relative to the rotational symmetry center OX1. Similarly, for two adjacent pixel driving circuits PC2 and PC6 in the second direction Y, the orthographic projections on the substrate have a rotationally symmetrical relationship, for example, they are rotationally symmetrical relative to the rotational symmetry center OX2. For two adjacent pixel driving circuits PC3 and PC7 in the second direction Y, the orthographic projections on the substrate have a rotationally symmetrical relationship, for example, they are rotationally symmetrical relative to the rotational symmetry center OX3. The orthographic projections of two adjacent pixel driving circuits PC4 and PC8 in the second direction Y on the base substrate have a rotationally symmetrical relationship, for example, a rotationally symmetrical relationship with respect to the rotationally symmetrical center OX4.

[0141] For example, for pixel driving circuits of a plurality of sub-pixels located in the same row arranged in two rows, the orthographic projections of two adjacent pixel driving circuits in the second direction on the substrate have a 180° rotational symmetry relationship.

[0142] It should be noted that, in the embodiments of the present disclosure, the rotational symmetry center is an imaginary symmetry center and is not intended to refer to a physical point.

[0143] In the embodiment of the present disclosure, by setting the above-mentioned axial symmetry relationship and rotational symmetry relationship, it is beneficial to the layout of the pixel driving circuit on the substrate and to the implementation of the manufacturing process of the pixel driving circuit.

[0144] Reference Figure 17 The pixel driving circuits located in the same row include a first pixel driving circuit PC3, a second pixel driving circuit PC2 and a third pixel driving circuit PC4, the first pixel driving circuit PC3 is adjacent to the second pixel driving circuit PC2, the third pixel driving circuit PC4 is adjacent to the first pixel driving circuit PC3, and the second pixel driving circuit PC2 and the third pixel driving circuit PC4 are respectively located on both sides of the first pixel driving circuit PC3 along the first direction X.

[0145] Combined with reference Figure 6 and Figure 17, the third active layer 201c of the driving transistor T3 of the first pixel driving circuit PC3 and the third active layer 201c of the driving transistor T3 of the second pixel driving circuit PC2 extend continuously. In the embodiment of the present disclosure, the active layers of the driving transistors of two adjacent pixel driving circuits can extend continuously along the first direction, thereby facilitating further increasing the size of the channel region of the driving transistor.

[0146] The third active layer 201c of the driving transistor T3 of the first pixel driving circuit PC3 is spaced apart from the third active layer 201c of the driving transistor T3 of the third pixel driving circuit PC4. In this way, other transistors of the pixel driving circuit can be formed between the spaced apart driving transistors, which is beneficial to improving the space utilization rate of the pixel driving circuit.

[0147] For example, for pixel driving circuits arranged in two rows for a plurality of sub-pixels located in the same row, the orthographic projections of the third channel regions of the driving transistors of two adjacent pixel driving circuits in the second direction only partially overlap along the second direction. Figure 14 and Figure 17 For the pixel driving circuits arranged in two rows for a plurality of sub-pixels located in the same row, the orthographic projections of the third channel regions (part of 201 c ) of the driving transistors of two adjacent pixel driving circuits PC1 and PC5 in the second direction Y only partially overlap along the second direction Y. Here, “only partially overlap” means that the two do not completely overlap or coincide, but rather there is a non-overlapping portion between them.

[0148] Reference Figure 7 The display substrate may include a scanning signal line 61, a light emission control signal line 63, and a gate structure 11 located in a first conductive layer 10. The first conductive layer 10 may be formed of a gate material. For example, the gate material may include a metal material, such as Mo, Al, Cu, or an alloy thereof.

[0149] In an embodiment of the present disclosure, pixel driving circuits for a plurality of sub-pixels located in the same row and arranged in two rows may share one scanning signal line 61. For example, in the illustrated embodiment, pixel driving circuits PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8 for a plurality of sub-pixels located in the same row and arranged in two rows may share one scanning signal line 61.

[0150] The pixel driving circuits arranged in two rows for the multiple sub-pixels located in the same row can each use the light emission control signal line 63. That is, the pixel driving circuits PC1, PC2, PC3, and PC4 located in the first row can use one light emission control signal line 63, and the pixel driving circuits PC5, PC6, PC7, and PC8 located in the second row can use another light emission control signal line 63.

[0151] That is, for the pixel drive circuits for the multiple sub-pixels located in the same row, which are arranged in two rows, two light-emission control signal lines are provided for each pixel drive circuit, and one scan signal line is located between the two light-emission control signal lines. In other words, in the second direction, the shared scan signal line 61 is located above one of the two light-emission control signal lines 63, and the shared scan signal line 61 is located below the other of the two light-emission control signal lines 63. In the embodiment of the present disclosure, the pixel drive circuits for the multiple sub-pixels located in the same row, which are arranged in two rows, share a scan signal line, which helps save wiring space.

[0152] For example, the spacing distance 61Y1 between the scanning signal line 61 and an adjacent light emitting control signal line 63 along the second direction Y is substantially equal to the spacing distance 61Y2 between the scanning signal line 61 and another adjacent light emitting control signal line 63 along the second direction Y.

[0153] Continue to refer to Figure 7 The orthographic projection of the gate structure 11 on the base substrate may be located between the scanning signal line 61 and an adjacent light emitting control signal line 63. For example, the orthographic projection of the gate structure 11 on the base substrate may be substantially L-shaped.

[0154] Reference Figure 14 The portions where the scanning signal line 61 overlaps the semiconductor layer 50 form the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2, respectively. The portions where the gate structure 11 overlaps the semiconductor layer 50 form the gate G3 of the third transistor T3. The portions where the light emission control signal line 63 overlaps the semiconductor layer 50 form the gate G4 of the fourth transistor T4 and the gate G5 of the fifth transistor T5, respectively. The gate structure 11 also forms the first plate of the storage capacitor.

[0155] Reference Figure 9 The display substrate may include a second electrode 21, a first conductive connection portion 22, and a second conductive connection portion 23 located in a second conductive layer 20. The second conductive layer 20 may be formed of a gate material. For example, the gate material may include a metal material, such as Mo, Al, Cu, and alloys thereof.

[0156] The second electrode 21 is electrically connected to the second electrode D1 of the first transistor T1 and the second electrode D4 of the fourth transistor T4 through the third via hole VH3 located in the first insulating layer GI2, that is, forming Figure 4The orthographic projection of the second plate 21 on the substrate at least partially overlaps with the orthographic projection of the first plate 11 on the substrate. In the embodiment of the present disclosure, the second plate 21 can extend along the first direction. In this way, the second plate can have a larger area, which is conducive to increasing the overlapping area between the second plate and the first plate, thereby facilitating increasing the capacitance value of the storage capacitor.

[0157] The first conductive connection portion 22 is connected to the reference voltage Vref, and one end of the first conductive connection portion 22 is electrically connected to the first electrode S1 of the fourth transistor T4 through a second via hole VH2 located in the first insulating layer GI2, so as to connect the reference voltage Vref to the first electrode S1 of the fourth transistor T4.

[0158] A portion of the second conductive connection portion 23 is electrically connected to the gate G3 through a fourth via hole VH4 located in the first insulating layer GI2, and another portion of the second conductive connection portion 23 is electrically connected to the second electrode D2 of the second transistor T2 through a fifth via hole VH5 located in the first insulating layer GI2. That is, the gate G3 (which is also the first electrode plate) of the third transistor T3 can be electrically connected to the second electrode D2 of the second transistor T2 through the second conductive connection portion 23, thereby forming Figure 4 Node N2 in .

[0159] Reference Figure 11 The display substrate may include a data line 64 and a third electrode 31 located in a third conductive layer 30. The third conductive layer 30 may be formed of a conductive material that forms a source and a drain of a thin film transistor, for example, the conductive material may include Ti, Al, etc. The third conductive layer 30 may have a stacked structure formed of Ti / Al / Ti.

[0160] The data line 64 is used to transmit the data signal Dm. The data line 64 can be electrically connected to the first electrode S1 of the first transistor T1 through an eighth via hole VH8 located in the second insulating layer ILD1. In this way, the data signal Dm can be supplied to the first electrode S1 of the first transistor T1.

[0161] For example, two data lines 64 may be provided between two adjacent columns of pixel driving circuits to supply data signals to the two columns of pixel driving circuits respectively.

[0162] In an embodiment of the present disclosure, the orthographic projection of the second electrode 21 on the base substrate at least partially overlaps with the orthographic projection of the data line 64 on the base substrate. From the perspective of the stacking relationship of the film layers, the second electrode 21 is located between the first electrode 11 and the data line 64. A reference voltage Vref is applied to the second electrode 21 via the fourth transistor T4. In this way, the second electrode 21 can protect the voltage at the node N2. For example, when a data signal is transmitted on the data line 64, the second electrode 21 can shield the data signal transmitted on the data line 64 from interfering with the voltage at the node N2, thereby facilitating the voltage at the node N2 to remain stable.

[0163] For example, the orthographic projection of the third via VH3 on the substrate at least partially overlaps with the orthographic projection of the data line 64 on the substrate. For example, the orthographic projection of the second electrode plate 21 on the substrate has a first side portion close to the orthographic projection of the third via VH3 on the substrate and a second side portion away from the orthographic projection of the third via VH3 on the substrate. The first side portion of the orthographic projection of the second electrode plate 21 on the substrate at least partially overlaps with the orthographic projection of the data line 64 on the substrate, and / or the second side portion of the orthographic projection of the second electrode plate 21 on the substrate at least partially overlaps with the orthographic projection of the data line 64 on the substrate. This position design ensures that the second electrode plate 21 can shield the voltage at the node N2 from interference caused by the data signal transmitted on the data line 64.

[0164] The third electrode plate 31 can be electrically connected to the second conductive connection portion 23 through the sixth via hole VH6 in the second insulating layer ILD1. In this way, the third electrode plate 31 is electrically connected to the first electrode plate 11, that is, the same voltage is applied to the third electrode plate 31 and the first electrode plate 11.

[0165] The orthographic projection of the third electrode plate 31 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 21 on the substrate. In the embodiment of the present disclosure, the orthographic projection of the third electrode plate 31 on the substrate and the orthographic projection of the second electrode plate 21 on the substrate both have a substantially Z-shaped shape. In this way, the second electrode plate and the third electrode plate can both have a larger area, which is beneficial for increasing the overlapping area between the second electrode plate and the third electrode plate, thereby facilitating an increase in the capacitance value of the storage capacitor.

[0166] For example, an orthographic projection of the sixth via hole VH6 on the base substrate at least partially overlaps with an orthographic projection of the fourth via hole VH4 on the base substrate.

[0167] Reference Figure 13The display substrate may include a first voltage line 65, a fourth electrode 41, and a third conductive connection portion 42 located in a fourth conductive layer 40. The fourth conductive layer 40 may be formed of a conductive material that forms a source and a drain of a thin film transistor, for example, the conductive material may include Ti, Al, etc. The fourth conductive layer 40 may have a stacked structure formed of Ti / Al / Ti.

[0168] The first voltage line 65 is used to transmit the first voltage VDD. The first voltage line 65 can be electrically connected to the first electrode S3 of the third transistor T3 through a first via hole VH1 located in the third insulating layer ILD2. In this way, the first voltage VDD can be supplied to the first electrode S3 of the third transistor T3.

[0169] In an embodiment of the present disclosure, the pixel driving circuits of multiple sub-pixels located in adjacent columns can share a first voltage line 65. For example, in the illustrated embodiment, the first pixel driving circuit PC3 and the second pixel driving circuit PC2 can share a first voltage line 65. This helps save wiring space.

[0170] For example, in an adjacent region between two adjacent pixel driving circuits located in the same row, two data lines 64 and one first voltage line 65 extend through the adjacent region. In this adjacent region, the orthographic projection of the first voltage line 65 on the substrate is located between the orthographic projections of the two data lines 64 on the substrate. This arrangement saves wiring space and facilitates a symmetrical layout of the pixel driving circuits.

[0171] The fourth plate 41 can be electrically connected to the second plate 21 through the seventh via hole VH7 in the third insulating layer ILD2. In this way, the fourth plate 41 is electrically connected to the second plate 21, that is, the same voltage is applied to the fourth plate 41 and the second plate 21.

[0172] The orthographic projection of the fourth electrode plate 41 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 31 on the substrate. In the embodiment of the present disclosure, the orthographic projection of the fourth electrode plate 41 on the substrate has a substantially T-shape. This allows the fourth electrode plate 41 to have a larger area, which helps increase the overlap area between the fourth electrode plate and the third electrode plate, thereby facilitating an increase in the capacitance of the storage capacitor.

[0173] The third conductive connection portion 42 can be electrically connected to the second electrode D5 of the fifth transistor T5 through the ninth via hole VH9 located in the third insulating layer ILD2. In the embodiment of the present disclosure, the third conductive connection portion 42 can serve as the anode PAD. For example, referring to Figure 17The anode located above the fourth conductive layer 40 can be electrically connected to the third conductive connection portion 42 through the anode connection hole VHA. In this way, the electrical connection between the second electrode D5 of the fifth transistor T5 and the anode can be achieved.

[0174] In an embodiment of the present disclosure, at least a portion of the symmetry axis (eg, symmetry axis AX1, AX2, AX3) of the pixel driving circuit having an axially symmetrical relationship has its orthographic projection on the substrate fall within the orthographic projection of the first voltage line 65 on the substrate.

[0175] The orthographic projections of the symmetry centers (eg, symmetry centers OX1, OX2, OX3, OX4) of the pixel driving circuits having a rotationally symmetrical relationship on the substrate fall within the orthographic projections of the scanning signal lines 61 on the substrate.

[0176] In this way, it is helpful to realize the axisymmetric layout and rotational symmetric layout of the pixel driving circuit.

[0177] For example, the orthographic projections of the seventh via hole VH7 and the third via hole VH3 along the first direction X at least partially overlap, that is, for pixel driving circuits located in the same row, the seventh via hole VH7 and the third via hole VH3 are basically located on the same straight line extending along the first direction X.

[0178] For example, the orthographic projections of the seventh via hole VH7 and the anode connection hole VHA along the second direction Y at least partially overlap. That is, for pixel driving circuits in the same column, the seventh via hole VH7 and the anode connection hole VHA are substantially located on the same straight line extending along the second direction Y.

[0179] For example, any two of the orthographic projections of the second via hole VH2, the third via hole VH3, and the eighth via hole VH8 along the second direction Y at least partially overlap. That is, for pixel driving circuits located in the same column, the second via hole VH2, the third via hole VH3, and the eighth via hole VH8 are substantially located on the same straight line extending along the second direction Y.

[0180] For example, for two adjacent pixel driving circuits located in the same row, any two of the orthographic projections of the first via hole VH1, the second via hole VH2, and the anode connection hole VHA along the first direction X at least partially overlap. That is, for two adjacent pixel driving circuits located in the same row, the first via hole VH1, the second via hole VH2, and the anode connection hole VHA are substantially located on the same straight line extending along the first direction X.

[0181] Figure 19 Schematically shows Figure 4Schematic diagram of the storage capacitor Cst in FIG. Figures 4 to 19 The first plate 11, the second plate 21, the third plate 31, and the fourth plate 41 are stacked sequentially on the substrate 100, with at least one insulating layer separating adjacent plates. The orthographic projections of any two of the first plate 11, the second plate 21, the third plate 31, and the fourth plate 41 on the substrate 100 at least partially overlap, forming a first sub-capacitor C1 between the first plate 11 and the second plate 21, a second sub-capacitor C2 between the second plate 21 and the third plate 31, and a third sub-capacitor C3 between the third plate 31 and the fourth plate 41. The storage capacitor Cst includes the first sub-capacitor C1, the second sub-capacitor C2, and the third sub-capacitor C3. For example, the first plate 11 and the third plate 31 are electrically connected and connected to the voltage at the node N2; the second plate 21 and the fourth plate 41 are electrically connected and connected to the voltage at the node N1. The capacitance of the storage capacitor Cst may be substantially equal to the sum of the capacitances of the first capacitor C1, the second capacitor C2, and the third capacitor C3. In this way, the capacitance of the storage capacitor Cst is increased, thereby improving the performance of the pixel driving circuit.

[0182] Reference Figure 3B and Figure 17 For a subpixel, the pixel driver circuit of that subpixel is electrically connected to the light-emitting element via the anode connection hole VHA. For the pixel driver circuits of two adjacent subpixels in the same row, arranged in two rows, the anode connection holes VHA of the two subpixels are spaced apart by a first predetermined distance in the first direction X, and by a second predetermined distance in the second direction Y. For example, the anode connection hole VHA of pixel driver circuit PC1 is spaced apart from the anode connection hole VHA of pixel driver circuit PC5 in both the first direction X and the second direction Y. The anode connection hole VHA of pixel driver circuit PC1 and the anode connection hole VHA of pixel driver circuit PC5 are spaced apart by a first predetermined distance AW1 in the first direction X, and by a second predetermined distance AY1 in the second direction Y. For example, the ratio of the second predetermined distance AY1 to the first predetermined distance AW1 is approximately between 1 and 20, or approximately between 2 and 10, or approximately between 2 and 8, or approximately between 3 and 6. Such an arrangement is conducive to leaving sufficient space for each anode PAD, that is, it is conducive to the arrangement of the anode PAD.

[0183] For example, in two rows of pixel units, the relative position of the anode connection hole of at least one sub-pixel in one row of pixel units relative to the third channel region of the driving transistor of the pixel driving circuit of the sub-pixel is different from the relative position of the anode connection hole of at least one sub-pixel of the same color in another row of pixel units relative to the third channel region of the driving transistor of the pixel driving circuit of the sub-pixel of the same color. Figure 17 In the illustrated embodiment, pixel driver circuits PC1 and PC6 may each correspond to a sub-pixel of the same color, for example, a green sub-pixel. The anode connection hole VHA of the sub-pixel corresponding to pixel driver circuit PC1 is located to the upper right of the third channel region of the driver transistor of the pixel driver circuit for that sub-pixel, while the anode connection hole VHA of the sub-pixel corresponding to pixel driver circuit PC6 is located to the lower right of the third channel region of the driver transistor of the pixel driver circuit for that sub-pixel. Thus, the relative positions of the two are different.

[0184] For example, the display substrate may further include a fifth insulating layer PVX disposed on the side of the fourth conductive layer 40 away from the base substrate 100, a fifth conductive layer disposed on the side of the fifth insulating layer PVX away from the base substrate 100, and a pixel defining layer PDL disposed on the side of the fifth conductive layer away from the base substrate 100.

[0185] It should be noted that each of the above-mentioned insulating layers may include a single-layer structure or a stacked-layer structure composed of multiple insulating layers. For example, the fifth insulating layer PVX may include two passivation layers, or may include one passivation layer and one planarization layer.

[0186] For example, the fifth conductive layer may include the first electrode 701 of the light-emitting element. The fifth conductive layer may include a conductive material such as ITO. The pixel definition layer (PDL) may include an opening 703. The display substrate may further include: a light-emitting material layer (EL) disposed on a side of the pixel definition layer (PDL) away from the base substrate 100 and within the opening 703; and a sixth conductive layer disposed on a side of the light-emitting material layer (EL) away from the base substrate 100. For example, the sixth conductive layer may include the second electrode 801 of the light-emitting element.

[0187] In some exemplary embodiments, the first electrode 701 may be an anode of a light-emitting element (eg, an OLED), and the second electrode 801 may be a cathode of the light-emitting element.

[0188] Optionally, embodiments of the present disclosure further provide a display device that may include the aforementioned display substrate. The display device may include, but is not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation systems, and any other product or component with a display function. It should be understood that this display device has the same beneficial effects as the display substrates provided in the aforementioned embodiments.

[0189] Although some embodiments of the present general inventive concept have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate comprises: substrate; a plurality of pixel units disposed on the substrate, the plurality of pixel units being arranged in an array along a first direction and a second direction to form a plurality of rows of pixel units and a plurality of columns of pixel units, at least one of the pixel units including a plurality of sub-pixels, at least one of the sub-pixels including a light-emitting element and a pixel driving circuit for driving the light-emitting element; and A plurality of scanning signal lines are provided on the substrate, the plurality of scanning signal lines respectively supplying scanning signals to a plurality of rows of pixel units, the plurality of scanning signal lines are arranged at intervals along the second direction, and at least one of the scanning signal lines extends along the first direction. The orthographic projections of the pixel driving circuits of the plurality of sub-pixels on the base substrate respectively overlap at least partially with the orthographic projections of the light-emitting elements of the same sub-pixel on the base substrate; For at least one row of pixel units, the light-emitting elements of multiple sub-pixels located in the same row are arranged side by side along the first direction, and the pixel driving circuits of the multiple sub-pixels located in the same row are arranged into two rows along the second direction. In each of the two rows of pixel driving circuits, multiple pixel driving circuits are arranged side by side along the first direction.

2. The display substrate according to claim 1, wherein The light-emitting element includes an anode. For the same sub-pixel, the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate and the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate have the following relationship: The orthographic projection of the pixel driving circuit of the sub-pixel on the substrate exceeds the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate in a first direction; and / or, The orthographic projection of the anode of the light-emitting element of the sub-pixel on the base substrate exceeds the orthographic projection of the pixel driving circuit of the sub-pixel on the base substrate in the second direction.

3. The display substrate according to claim 2, wherein: For the same sub-pixel, the orthographic projection of the pixel driving circuit of the sub-pixel on the substrate and the orthographic projection of the anode of the light-emitting element of the sub-pixel on the substrate have the following relationship: The ratio of the size of the orthogonal projection of the pixel driving circuit of the sub-pixel on the substrate in the first direction to the size of the orthogonal projection of the anode of the light-emitting element of the sub-pixel on the substrate in the first direction is between 1.5 and 3; and / or, The ratio of the size of the positive projection of the anode of the light-emitting element of the sub-pixel on the substrate in the second direction to the size of the positive projection of the pixel driving circuit of the sub-pixel on the substrate in the second direction is between 1.5-3.

4. The display substrate according to any one of claims 1 to 3, wherein: The pixel driving circuit includes at least a driving transistor, which is electrically connected to the light-emitting element. The driving transistor includes at least a third channel region, and the orthographic projection of the third channel region on the substrate has a first side, a second side, a third side, and a fourth side. The first side and the second side are located on opposite sides of the orthographic projection of the third channel region on the substrate in a first direction, and the third side and the fourth side are located on opposite sides of the orthographic projection of the third channel region on the substrate in a second direction. A first distance between the first side and the second side along the first direction is greater than a second distance between the third side and the fourth side along the second direction.

5. The display substrate according to claim 4, wherein: For the pixel driving circuits located in the same row, the orthographic projections of two adjacent pixel driving circuits in the first direction on the base substrate have an axisymmetric relationship.

6. The display substrate according to claim 4, wherein: For the pixel driving circuits of the plurality of sub-pixels located in the same row and arranged in two rows, the orthographic projections of two adjacent pixel driving circuits in the second direction on the substrate have a rotationally symmetric relationship.

7. The display substrate according to claim 4, wherein: For pixel driving circuits of a plurality of sub-pixels located in the same row arranged in two rows, orthographic projections of the third channel regions of the driving transistors of two adjacent pixel driving circuits in the second direction along the second direction only partially overlap.

8. The display substrate according to claim 6, wherein: Pixel driving circuits for a plurality of sub-pixels located in the same row and arranged in two rows share one scanning signal line.

9. The display substrate according to claim 4, wherein: The driving transistor includes a third active layer; The pixel driving circuits located in the same row include a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit, wherein the first pixel driving circuit is adjacent to the second pixel driving circuit, the third pixel driving circuit is adjacent to the first pixel driving circuit, and the second pixel driving circuit and the third pixel driving circuit are respectively located on both sides of the first pixel driving circuit along the first direction; The third active layer of the driving transistor of the first pixel driving circuit and the third active layer of the driving transistor of the second pixel driving circuit extend continuously.

10. The display substrate according to claim 9, wherein: The third active layer of the driving transistor of the first pixel driving circuit is spaced apart from the third active layer of the driving transistor of the third pixel driving circuit.

11. The display substrate according to claim 9, wherein: The display substrate further includes a plurality of first voltage lines, each of which supplies a first voltage to a plurality of columns of pixel units. The plurality of first voltage lines are arranged at intervals along a first direction, and at least one of the first voltage lines extends along a second direction. The first pixel driving circuit and the second pixel driving circuit share a first voltage line.

12. The display substrate according to claim 11, wherein: The orthographic projection of at least a portion of the symmetry axis of the pixel driving circuit having an axially symmetrical relationship on the base substrate falls within the orthographic projection of the first voltage line on the base substrate.

13. The display substrate according to claim 8, wherein: The orthographic projection of the symmetry center of the pixel driving circuit having a rotationally symmetrical relationship on the base substrate falls within the orthographic projection of the scanning signal line on the base substrate.

14. The display substrate according to claim 6, wherein: For pixel driving circuits of a plurality of sub-pixels located in the same row and arranged in two rows, orthographic projections of two adjacent pixel driving circuits in the second direction on the substrate have a 180° rotational symmetry relationship.

15. The display substrate according to claim 8, wherein The display substrate further comprises: a plurality of light-emitting control signal lines provided on the base substrate, the plurality of light-emitting control signal lines respectively supplying light-emitting control signals to a plurality of rows of pixel units, the plurality of light-emitting control signal lines being arranged at intervals along the second direction, and at least one of the light-emitting control signal lines extending along the first direction; and For the pixel driving circuits arranged in two rows of multiple sub-pixels located in the same row, two light-emitting control signal lines are respectively set. In the second direction, a shared scanning signal line is located above one of the two light-emitting control signal lines, and a shared scanning signal line is located below the other of the two light-emitting control signal lines.

16. The display substrate according to claim 15, wherein: A spacing distance between the scanning signal line and an adjacent light emitting control signal line along the second direction is equal to a spacing distance between the scanning signal line and another adjacent light emitting control signal line along the second direction.

17. The display substrate according to claim 11, wherein The display substrate includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer located on the base substrate, wherein the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer are sequentially arranged away from the base substrate, and the driving transistor includes a third active layer and a third gate electrode, wherein the third active layer is located in the semiconductor layer, and the third gate electrode is located in the first conductive layer; The pixel driving circuit further includes a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate including the third gate, and the second plate being located in the second conductive layer; The display substrate further comprises a plurality of data lines located on the base substrate, wherein the data lines are located in the third conductive layer; The orthographic projection of the second electrode plate on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate.

18. The display substrate according to claim 17, wherein: The data line and the first voltage line both extend along the second direction; In an adjacent area between two adjacent pixel driving circuits located in the same row, two of the data lines and one of the first voltage lines extend through, and in this adjacent area, the orthographic projection of the first voltage line on the substrate is located between the orthographic projections of the two data lines on the substrate.

19. The display substrate according to claim 17, wherein: The display substrate further includes a first conductive connection portion, wherein the first conductive connection portion is located in the second conductive layer; The pixel driving circuit further includes a fourth transistor, and the fourth transistor includes a first electrode and a second electrode; The first conductive connection portion is connected to a reference voltage, and one end of the first conductive connection portion is electrically connected to the first electrode of the fourth transistor through a second via hole, so as to connect the reference voltage to the first electrode of the fourth transistor; The second electrode of the fourth transistor is electrically connected to the second electrode plate through a third via hole.

20. The display substrate according to claim 19, wherein An orthographic projection of the third via hole on the base substrate at least partially overlaps with an orthographic projection of the data line on the base substrate.

21. The display substrate according to claim 19 or 20, wherein: The orthographic projection of the second electrode plate on the base substrate has a first side portion close to the orthographic projection of the third via hole on the base substrate and a second side portion away from the orthographic projection of the third via hole on the base substrate. The first side portion of the orthographic projection of the second electrode plate on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate, and / or the second side portion of the orthographic projection of the second electrode plate on the base substrate at least partially overlaps with the orthographic projection of the data line on the base substrate.

22. The display substrate according to claim 20, wherein: The display substrate further includes a second conductive connection portion, wherein the second conductive connection portion is located in the second conductive layer; The pixel driving circuit further includes a second transistor, wherein the second transistor includes a first electrode and a second electrode; One end of the second conductive connection portion is electrically connected to the third gate through a fourth via hole, and the other end of the second conductive connection portion is electrically connected to the first electrode of the second transistor through a fifth via hole.

23. The display substrate according to claim 22, wherein: The display substrate further includes a third electrode plate, and the third electrode plate is located in the third conductive layer; The third electrode plate is electrically connected to the second conductive connection portion through a sixth via hole, and an orthographic projection of the third electrode plate on the base substrate at least partially overlaps with an orthographic projection of the second electrode plate on the base substrate.

24. The display substrate according to claim 23, wherein: An orthographic projection of the sixth via hole on the base substrate at least partially overlaps with an orthographic projection of the fourth via hole on the base substrate.

25. The display substrate according to claim 24, wherein: The display substrate further comprises a fourth conductive layer located on a side of the third conductive layer away from the base substrate, and the first voltage line is located in the fourth conductive layer; The display substrate further includes a fourth electrode plate, and the fourth electrode plate is located in the fourth conductive layer; The fourth electrode plate is electrically connected to the second electrode plate through a seventh via hole, and an orthographic projection of the fourth electrode plate on the base substrate at least partially overlaps with an orthographic projection of the third electrode plate on the base substrate.

26. The display substrate according to claim 25, wherein: The orthographic projections of any two of the first plate, the second plate, the third plate and the fourth plate on the substrate at least partially overlap to form a first sub-capacitor between the first plate and the second plate, a second sub-capacitor between the second plate and the third plate, and a third sub-capacitor between the third plate and the fourth plate, and the storage capacitor includes the first sub-capacitor, the second sub-capacitor and the third sub-capacitor.

27. The display substrate according to claim 26, wherein: For a sub-pixel, the pixel driving circuit of the sub-pixel is electrically connected to the light-emitting element through the anode connection hole; For pixel driving circuits arranged in two rows for two adjacent sub-pixels in the same row, the anode connection holes of the two sub-pixels are spaced apart by a first prescribed distance in the first direction, and the anode connection holes of the two sub-pixels are spaced apart by a second prescribed distance in the second direction.

28. The display substrate according to claim 27, wherein: The seventh via hole at least partially overlaps with the orthographic projection of the third via hole along the first direction; and / or, The seventh via hole at least partially overlaps with an orthographic projection of the anode connection hole along the second direction.

29. The display substrate according to claim 27, wherein: In two rows of pixel units, the relative position of the anode connection hole of at least one sub-pixel in one row of pixel units relative to the third channel region of the driving transistor of the pixel driving circuit of the sub-pixel is different from the relative position of the anode connection hole of at least one sub-pixel of the same color in another row of pixel units relative to the third channel region of the driving transistor of the pixel driving circuit of the sub-pixel of the same color.

30. The display substrate according to claim 19, wherein The pixel driving circuit further includes a first transistor, the first transistor including a gate and a first channel region, and a portion of the scanning signal line overlapping the semiconductor layer forms the gate of the first transistor; The data line is electrically connected to a portion of the semiconductor layer located on one side of the first channel region through an eighth via hole; Any two of the orthographic projections of the second via hole, the third via hole, and the eighth via hole along the second direction at least partially overlap.

31. The display substrate according to claim 19, wherein The display substrate further comprises: a plurality of light-emitting control signal lines provided on the base substrate, the plurality of light-emitting control signal lines respectively supplying light-emitting control signals to a plurality of rows of pixel units, the plurality of light-emitting control signal lines being arranged at intervals along the second direction, and at least one of the light-emitting control signal lines extending along the first direction; The pixel driving circuit further includes a third transistor and a fifth transistor, the fifth transistor including a gate and a fifth channel region, and a portion of the light emitting control signal line overlapping with the semiconductor layer constitutes the gate of the fifth transistor; The first voltage line is electrically connected to the first electrode of the third transistor through the first via hole; The light emitting element is electrically connected to a portion of the semiconductor layer located on one side of the fifth channel region through the anode connection hole; For two adjacent pixel driving circuits located in the same row, any two of the orthographic projections of the first via hole, the second via hole, and the anode connection hole along the first direction at least partially overlap.

32. A display panel, characterized in that: The display panel includes the display substrate according to any one of claims 1 to 31.

33. A display device, characterized in that: The display device includes the display substrate according to any one of claims 1 to 31 or the display panel according to claim 32.

Images