Semiconductor Memory

Abstract

The embodiment of the present application relates to a semiconductor memory, including: multiple storage arrays; at least one verification module, each verification module corresponds to the multiple storage arrays, the verification module is used to verify whether the data information of the corresponding storage array is erroneous, and each verification module is connected to a group of global data buses; multiple gating circuits, the gating circuits are respectively connected to the storage arrays and the global data bus, and the gating circuits are used to control the on-off of the data transmission path between the connected global data bus and the storage array. The verification module of the embodiment of the present application only needs to verify the data information of the verification module that is read in real time. Therefore, the semiconductor memory of the embodiment of the present application can ensure that each reading of the data information is effectively verified when using a small number of verification modules, thereby providing a semiconductor memory with a verification module occupying a small space.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of memory devices, and in particular, to a semiconductor memory. Background Art

[0002] Semiconductor memory is a memory that uses semiconductor circuits for access. Among them, dynamic random access memory (DRAM) is widely used in various fields due to its fast storage speed and high integration.

[0003] In order to obtain higher data reading and writing reliability, a verification module needs to be set in the semiconductor memory to verify whether the read data is accurate. At present, the verification module needs to occupy a large amount of space in the semiconductor memory, so that the size of the memory cannot be further reduced. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor memory to address the problem that the verification module in the existing memory occupies a large space.

[0005] A semiconductor memory, comprising:

[0006] Multiple storage arrays;

[0007] At least one verification module, each of which corresponds to the plurality of storage arrays, and is used to verify whether data information of the corresponding storage array has errors, and each of which is connected to a set of global data buses;

[0008] A plurality of gating circuits are respectively connected to the storage array and the global data bus, and the gating circuits are used to control the on / off of a data transmission path between the connected global data bus and the storage array.

[0009] In one embodiment, the semiconductor memory includes two storage arrays and one verification module, the storage arrays correspond to the gating circuits one by one, and the storage arrays are connected to the verification module through the corresponding gating circuits and the global data bus.

[0010] In one embodiment, the semiconductor memory includes three storage arrays and one verification module, the storage arrays correspond to the gating circuits one by one, and the storage arrays are connected to the verification module through the corresponding gating circuits and the global data bus.

[0011] In one embodiment, the semiconductor memory includes three storage arrays and two verification modules, the three storage arrays include a first array, a second array and a third array, the second array is connected to two second gating circuits, and the second gating circuits are connected to the global data bus in a one-to-one correspondence.

[0012] In one embodiment, the second array includes a first bit line and a second bit line, the first bit line is connected to one of the two second gating circuits, and the second bit line is connected to the other of the two second gating circuits.

[0013] In one embodiment, the first array is connected to two first gating circuits, and the first gating circuits are connected to the global data bus in a one-to-one correspondence;

[0014] The third array is connected to two third gating circuits, and the third gating circuits are connected to the global data bus in a one-to-one correspondence;

[0015] The first gating circuit, the second gating circuit and the first gating circuit connected to the same global data bus are turned on in a time-sharing manner.

[0016] In one embodiment, the verification module includes:

[0017] an encoding unit connected to the storage array, configured to receive input data information, encode the data information to generate write verification information, and send the data information and the write verification information to the storage array;

[0018] An error detection unit is connected to the storage array and is used to synchronously read the data information and the write verification information from the storage array, and verify whether an error occurs in the read data information according to the write verification information.

[0019] In one embodiment, the error detection unit is also connected to the encoding unit, and the encoding unit is further used to encode the read data information to generate read verification information, and send the read verification information to the error detection unit;

[0020] The error detection unit is used to obtain the write verification information and the read verification information, and compare the write verification information with the read verification information to determine whether an error occurs in the read data information.

[0021] In one of the embodiments, the verification module further includes an error correction unit connected to the error detection unit, configured to receive the read data information and comparison result information of the error detection unit, and update the data information according to the comparison result information.

[0022] In one of the embodiments, the semiconductor memory further comprises a gating control module, wherein the gating control module is used to generate a plurality of gating signals;

[0023] The gating circuit includes a switch tube, a control end of the switch tube is connected to the gating control module, a first end of the switch tube is connected to the global data bus, and a second end of the switch tube is connected to the storage array. The switch tube is used to select to turn on or off the data transmission path between the first end and the second end under the control of the gating signal.

[0024] In one embodiment, the switch tube is a high-voltage switch tube.

[0025] In one of the embodiments, the switch tube is turned on at a high level.

[0026] In one of the embodiments, the semiconductor memory further includes at least one byte data port, which is connected to the verification module in a one-to-one correspondence and is used to receive the data information input from the outside or output the read data information to the outside.

[0027] In one embodiment, the semiconductor memory also includes a read-write control module, which is connected to the verification module and the global data bus respectively, and the read-write control module is used to receive a read-write enable signal and select the data transmission direction between the verification module and the corresponding global data bus under the control of the read-write enable signal.

[0028] The semiconductor memory includes: a plurality of storage arrays; at least one verification module, each of which corresponds to the plurality of storage arrays, the verification module is used to verify whether the data information of the corresponding storage array is erroneous, and each of which is connected to a group of global data buses; a plurality of gating circuits, the gating circuits are respectively connected to the storage arrays and the global data bus, and the gating circuits are used to control the on-off of the data transmission path between the connected global data bus and the storage array. The embodiment of the present application can control the on-off of the data transmission path between the global data bus and each storage array by controlling the gating circuit, so that the plurality of storage arrays connected to the same verification module read the data information in time-sharing, and the verification module only needs to verify the data information of the verification module that is read in real time. Therefore, the semiconductor memory of the embodiment of the present application can ensure that each reading of the data information is effectively verified when a relatively small number of verification modules are used, thereby providing a semiconductor memory with a relatively small space occupied by the verification module. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1A schematic structural diagram of a semiconductor memory having a half storage block structure according to an embodiment;

[0030] Figure 2 A schematic structural diagram of a semiconductor memory having a half storage block structure according to another embodiment;

[0031] Figure 3 A schematic structural diagram of a semiconductor memory having a half storage block structure according to another embodiment;

[0032] Figure 4 A schematic diagram of the structure of a semiconductor memory device with a complete storage block structure according to an embodiment;

[0033] Figure 5 A schematic structural diagram of a semiconductor memory device with a complete storage block structure according to another embodiment;

[0034] Figure 6 A schematic structural diagram of a semiconductor memory device with a complete storage block structure according to another embodiment;

[0035] Figure 7 The figure is a schematic diagram of the structure of a check module in a semiconductor memory according to an embodiment of the present invention.

[0036] Component number description:

[0037] Storage block: 10; storage array: 100; first array: 110; second array: 120; third array: 130; word line: 140; first word line: 141; second word line: 142; bit line: 150; first bit line: 151; second bit line: 152; column selection line: 160; check module: 200; encoding unit: 210; error detection unit: 220; error correction unit: 230; gating circuit: 300; first gating circuit: 310; second gating circuit: 320; third gating circuit: 330; gating control module: 400; read-write control module: 500; byte data port: 600; first byte data port: 610; second byte data port: 620; global data bus: 700 DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the embodiments of the present application. The terms used herein in the specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0040] Figure 1 FIG. 1 is a schematic diagram of a semiconductor memory having a half-storage block structure according to an embodiment of the present invention. Figure 1 In this embodiment, the semiconductor memory includes a plurality of memory arrays 100 , at least one check module 200 and a plurality of gating circuits 300 .

[0041] A plurality of memory arrays 100 are used to store data, thereby realizing the storage function of a semiconductor memory. Specifically, the memory array 100 includes a word line, a bit line, and a memory cell, and the memory cell further includes a storage capacitor and a transistor, the control end of the transistor is connected to the word line, the first end of the transistor is connected to the storage capacitor, and the second end of the transistor is connected to the bit line. When the word line control transistor is turned on, the storage capacitor and the bit line are turned on, thereby realizing the reading and writing of data information, that is, when reading data information, the storage capacitor transmits the stored data information to the bit line; when writing data information, the bit line sends the data information to be written to the storage capacitor.

[0042] Each verification module 200 corresponds to a plurality of storage arrays 100. The verification module 200 is used to verify whether data information of the corresponding storage array 100 is erroneous, that is, each verification module 200 is used to verify data information of a plurality of storage arrays 100, thereby optimizing the number of verification modules 200. Each verification module 200 is connected to a set of global data buses 700, and the verification module 200 sends and receives data information through the global data buses 700.

[0043] The gating circuit 300 is connected to the storage array 100 and the global data bus 700 respectively, and the gating circuit 300 is used to control the on-off of the data transmission path between the connected global data bus 700 and the storage array 100. Specifically, at the same time, the gating circuit 300 controls the global data bus 700 to be connected to at most one of the multiple storage arrays 100. Since in this embodiment, the global data bus 700 is connected to the verification module 200, the on-off condition of the data transmission path between the global data bus 700 and the storage array 100 is the on-off condition of the data transmission path between the verification module 200 and the storage array 100. Therefore, when the gating circuit 300 is turned on, the data transmission path between the global data bus 700 and the storage array 100 is turned on, and correspondingly, the data transmission path between the verification module 200 and the storage array 100 is turned on; when the gating circuit 300 is turned off, the data transmission path between the global data bus 700 and the storage array 100 is disconnected, and correspondingly, the data transmission path between the verification module 200 and the storage array 100 is disconnected.

[0044] In this embodiment, the semiconductor memory includes: a plurality of storage arrays 100; at least one check module 200, each of which corresponds to the plurality of storage arrays 100, and is used to check whether the data information of the corresponding storage array 100 is erroneous, and each of which is connected to a group of global data buses 700; and a plurality of strobe circuits 300, each of which is connected to the storage array 100 and the global data bus 700, and is used to control the on-off of the data transmission path between the connected global data bus 700 and the storage array 100. In this embodiment, by controlling the strobe circuit 300, the on-off of the data transmission path between the global data bus 700 and each storage array 100 can be controlled, so that the plurality of storage arrays 100 connected to the same check module 200 read the data information in a time-sharing manner, and the check module 200 only needs to check the data information of the check module 200 that is read in real time. Therefore, the semiconductor memory of this embodiment can ensure that each reading of data information is effectively verified while using a smaller number of verification modules 200, thereby providing a semiconductor memory in which the verification modules 200 occupy a smaller space.

[0045] Further, continue to refer to Figure 1 The semiconductor memory further includes at least one byte data port 600, which is connected to the verification module 200 in a one-to-one correspondence, and is used to receive external input data information or output read data information to the outside. Figure 1, two byte data ports 600 and two storage blocks 10 are shown, the two byte data ports 600 specifically include a first byte data port 610 and a second byte data port 620, each storage block 10 includes a plurality of storage arrays 100, and the byte data ports 600, the check module 200 and the storage block 10 are connected in a one-to-one correspondence, that is, the plurality of storage arrays 100 in each storage block 10 are connected to the same check module 200, and then connected to the same byte data port 600 via the check module 200. It should be noted that the above-mentioned byte data port 600 and the check module 200 are only used for illustration, and the embodiment of the present invention is not limited thereto. In other embodiments, the byte data port 600 may not correspond to the check module 200 in a one-to-one correspondence, for example, a plurality of byte data ports 600 correspond to a check module 200, and those skilled in the art may select as needed. In addition, the storage block 10 in this embodiment may be a complete storage body (bank), or half of a storage body (bank), or other, and this embodiment does not limit this.

[0046] Each byte data port 600 can be used to transmit 8-bit input data, that is, the first byte data port 610 is used to transmit DQ<0:7>, and the second byte data port 610 is used to transmit DQ<8:15>. The semiconductor memory can choose to use a half-storage block structure to store data information according to the parameter performance of the external device. Taking the first byte data port 610 as an example, when writing data information, the external device sends 8 bits of data to be written and transmits it to one of the two storage arrays 100 connected to it via the first byte data port 610; when reading data information, 8 bits of data are read from one of the two storage arrays 100 connected to the first byte data port 610, and transmitted to the external device via the first byte data port 610. The data transmission method of the second byte data port 620 is the same as that of the first byte data port 610, which will not be repeated here. It should be noted that due to the design of the pre-fetch (or burst) function of the current memory, multiple 8-bit data can be transmitted each time the external device communicates with each byte data port of the memory, and the embodiment of the present invention is not limited to this.

[0047] Figure 2 FIG. 1 is a schematic diagram of a semiconductor memory device with a half-storage block structure according to another embodiment. It should be noted that, since the connection modes of the check modules 200 and the storage array 100 corresponding to different byte data ports 600 are the same in this embodiment, in order to simplify the drawings, Figure 2 Only the check module 200 and the storage array 100 connected to one byte data port 600 are shown and described. The connection method of other byte data ports 600 can be referred to. Figure 2The same simplification is also performed in the drawings of other embodiments of the half storage block structure, and will not be repeated in other embodiments.

[0048] refer to Figure 2 In this embodiment, the semiconductor memory includes two memory arrays 100 and a check module 200. The memory arrays 100 correspond to the strobe circuits 300 one by one. The memory arrays 100 are connected to the check module 200 through the corresponding strobe circuits 300 and the global data bus 700. The two memory arrays 100 are respectively a first array 110 and a second array 120. The first array 110 is connected to the global data bus 700 through a first strobe circuit 310, and the second array 120 is connected to the global data bus 700 through a second strobe circuit 320. The check module 200 is connected to the byte data port 600 through a plurality of data transmission lines. Figure 2 Only three data transmission lines are shown, but it can be understood that the number of data transmission lines is not limited to three, for example, it can be one, or it can be eight, etc.

[0049] Specifically, at the same time, at most one of the first gating circuit 310 and the second gating circuit 320 is turned on. Figure 2 When the byte data port 600 corresponding to the check module 200 performs data transmission, data information is transmitted between the byte data port 600 and the check module 200 via the data transmission line, the check module 200 is turned on, and one of the first selection circuit 310 and the second selection circuit 320 is turned on, so that the first array 110 or the second array 120 reads and writes data information; when the corresponding byte data port 600 does not perform data transmission, the data transmission line is not used to transmit data information, the check module 200 is turned off, and the first selection circuit 310 and the second selection circuit 320 are both disconnected, so that the first array 110 or the second array 120 is in a standby state and does not read or write data information.

[0050] In this embodiment, the conduction check module 200 and one of the two storage arrays 100 are selected by the selection circuit 300 to realize the reading and writing of data information of different storage arrays 100, and when any storage array 100 reads and writes data, it is checked by the same connected check module 200, thereby reducing the number of check modules 200 that need to be set by improving the utilization rate of the check module 200, reducing the space occupied by the check module 200 in the semiconductor memory, and thus realizing a semiconductor memory with higher integration and smaller size.

[0051] Continue to refer Figure 2In one embodiment, the semiconductor memory further includes a gating control module 400, which is used to generate multiple gating signals; the gating circuit 300 includes a switch tube, the control end of the switch tube is connected to the gating control module 400, the first end of the switch tube is connected to the global data bus 700, and the second end of the switch tube is connected to the storage array 100, and the switch tube is used to select to turn on or off the data transmission path between the first end and the second end under the control of the gating signal. For the convenience of explanation, it is defined that the first gating circuit 310 includes a first switch tube, and the second gating circuit 320 includes a second switch tube.

[0052] Exemplarily, the first switch tube and the second switch tube can have the same conduction characteristics, for example, both switch tubes are turned on at a high level, if the strobe control module 400 outputs a high level signal to the first switch tube, and outputs a low level signal to the second switch tube, then the data transmission path between the first array 110 and the verification module 200 is turned on, and the data transmission path between the second array 120 and the verification module 200 is disconnected, so that the first array 110 reads and writes data information, and the data information read and written by the first array 110 is verified by the verification module 200. This example provides a setting method for switch tubes, so that the control logic of the switch tubes is relatively simple, and when it is necessary to continue to add storage arrays 100 in the storage block 10, corresponding expansion can also be performed according to the existing setting method of switch tubes.

[0053] Exemplarily, the first switch tube and the second switch tube may have different conduction characteristics, for example, the first switch tube is turned on at a high level, and the second switch tube is turned on at a low level. If the strobe control module 400 simultaneously outputs a high level signal to the first switch tube and the second switch tube, the data transmission path between the first array 110 and the verification module 200 is turned on, and the data transmission path between the second array 120 and the verification module 200 is disconnected, so that the first array 110 reads and writes data information, and the data information read and written by the first array 110 is verified by the verification module 200. This example provides another setting method of the switch tube, and the setting method of this example is applicable to the case where each storage block 10 includes two storage arrays 100. Compared with the previous example, this example can omit one strobe signal, thereby simplifying the wiring between the verification module 200 and the storage array 100.

[0054] In one embodiment, the switch is a high-voltage switch. Specifically, it can be a relatively higher-voltage transistor in the chip, usually with a thicker gate oxide layer and / or a higher threshold voltage, etc., but the embodiment of the present invention is not limited thereto, and the high-voltage switch mentioned here is only a concept relative to other transistors in the chip.

[0055] In the memory array 100, there are multiple memory cells, and each memory array 100 is connected to multiple word lines 140 (WL in the figure), multiple bit lines 150 (BL in the figure) and multiple column select lines 160 (column select, CS in the figure). The word line 140 connects multiple memory cells in the row direction, and the bit line 150 connects multiple memory cells in the column direction. When the word line 140 corresponding to the memory cell is turned on, the memory cell can realize data reading and writing, that is, the memory cell can obtain the data to be written from the corresponding bit line 150 or send the stored data to the corresponding bit line 150. It should be noted that Figure 2 The word line 140, column selection line 160, and bit line 150 shown in the figure are only for simple illustration and do not represent the connection relationship between them. The relationship between the three can refer to the conventional settings in the memory.

[0056] In one embodiment, the semiconductor memory further includes a read / write control module 500, which is connected to the verification module 200 and the global data bus 700, respectively. The read / write control module 500 is used to receive a read / write enable signal (a read enable signal RdEn and a write enable signal WrEn), and select the data transmission direction between the verification module 200 and the corresponding global data bus 700 under the control of the read / write enable signal. Specifically, the read / write control module 500 may include a plurality of read / write control units, and the number of the read / write control units matches the number of bits of the data information to be read / written. For example, eight read / write control units may be connected to each verification module 200.

[0057] Further, the read-write control unit can be a bidirectional driver, the data flow direction from the verification module 200 to the global data bus 700 is the write direction, and the data flow direction from the global data bus 700 to the verification module 200 is the read direction. A write control unit is provided on the output transmission path in the write direction, and a read control unit is provided on the output transmission path in the read direction, and the write control unit and the read control unit are not turned on at the same time. The write control unit receives a write enable signal WrEn, and turns on the data transmission path in the write direction under the control of the write enable signal WrEn, so that the verification module 200 sends the data information to be written to the global data bus 700; the read control unit receives a read enable signal RdEn, and turns on the data transmission path in the read direction under the control of the read enable signal RdEn, so that the verification module 200 obtains the read data information from the global data bus 700.

[0058] Figure 3 FIG. 1 is a schematic diagram of a semiconductor memory device having a half storage block structure according to another embodiment of the present invention. Figure 3In this embodiment, the semiconductor memory includes three memory arrays 100 and a check module 200. The memory arrays 100 correspond to the gating circuits 300 one by one. The memory arrays 100 are connected to the check module 200 through the corresponding gating circuits 300 and the global data bus 700. The three memory arrays 100 are respectively a first array 110, a second array 120 and a third array 130, and the three gating circuits 300 are respectively a first gating circuit 310, a second gating circuit 320 and a third gating circuit 330.

[0059] Specifically, at the same time, at most one of the first gating circuit 310, the second gating circuit 320 and the third gating circuit 330 is turned on. Figure 3 When the byte data port 600 corresponding to the check module 200 performs data transmission, data information is transmitted between the byte data port 600 and the check module 200 via the data transmission line, the check module 200 is turned on, and one of the first selection circuit 310, the second selection circuit 320 and the third selection circuit 330 is turned on, so that the storage array 100 corresponding to the turned-on selection circuit 300 reads and writes data information; when the corresponding byte data port 600 does not perform data transmission, the data transmission line is not used to transmit data information, the check module 200 is turned off, and the first selection circuit 310, the second selection circuit 320 and the third selection circuit 330 are all disconnected, so that the three storage arrays 100 are all in a standby state and no data information is read or written.

[0060] In this embodiment, three storage arrays 100 are arranged in each storage block 10, so as to obtain more optimized storage performance. Moreover, the conduction check module 200 and one of the three storage arrays 100 are selected through the selection circuit 300 to realize the reading and writing of data information of different storage arrays 100. When any storage array 100 reads and writes data, it is checked by the same connected check module 200. Therefore, by improving the utilization rate of the check module 200, the number of the check modules 200 to be arranged is reduced, and the space occupied by the check module 200 in the semiconductor memory is reduced, thereby realizing a semiconductor memory with higher integration and smaller volume.

[0061] Figure 4 A schematic diagram of the structure of a semiconductor memory with a complete storage block structure according to an embodiment of the present invention is shown. Figure 4, two byte data ports 600 and a storage block 10 are shown, the two byte data ports 600 specifically include a first byte data port 610 and a second byte data port 620, each storage block 10 includes a plurality of storage arrays 100, and at least part of the storage arrays 100 are respectively connected to two check modules 200 through corresponding selection circuits 300. That is, in a semiconductor memory with a complete storage block structure, each storage block 10 can correspond to two byte data ports 600. For example, if each byte data port 600 can transmit 8-bit data, each storage block 10 can synchronously read and write 16-bit data information, thereby achieving better storage performance.

[0062] Figure 5 FIG. 1 is a schematic diagram of a semiconductor memory having a complete storage block structure according to another embodiment. Figure 5 In this embodiment, the semiconductor memory includes three storage arrays 100 and two verification modules 200. The three storage arrays 100 include a first array 110, a second array 120 and a third array 130. The second array 120 is connected to two second selection circuits 320. The second selection circuits 320 are connected to the global data bus 700 in a one-to-one correspondence.

[0063] Each check module 200 is connected to a global data bus 700, and the second array 120 includes a first bit line 151 and a second bit line 152. The first bit line 151 is connected to one of the two second selection circuits 320, and the second bit line 152 is connected to the other of the two second selection circuits 320. It should be noted that the connection between the first bit line 151 and the second selection circuit 320 can be a direct connection, that is, the first bit line 151 and the second selection circuit 320 are connected via a routing line, and can also be an indirect connection. For example, other control devices or processing devices can be added between the first bit line 151 and the second selection circuit 320, and the first bit line 151 and the second selection circuit 320 are connected via the aforementioned additional devices, so as to achieve more abundant control functions or signal processing functions. Similarly, the connection between the second bit line 152 and the second selection circuit 320 can be a direct connection or an indirect connection, which will not be repeated here.

[0064] The second array 120 further includes a column selection line 160, a first word line 141 and a second word line 142. When writing data, the check module 200 synchronously transmits data information to the corresponding global data bus 700; when reading data, the two check modules 200 synchronously obtain data information from the corresponding global data bus 700. For example, Figure 5In the illustrated embodiment, the word lines 140 and the column selection lines 160 of the first array 110 are enabled, the word lines 140 and the column selection lines 160 of the third array 130 are enabled, and the first word lines 141, the second word lines 142, and the column selection lines 160 of the second array 120 are all disabled (as shown by the dotted lines). Then, a data transmission path between one check module 200 and the first array 110 is turned on, and a data transmission path between another check module 200 and the third array 130 is turned on. Each storage array 100 can read and write 8-bit data information, so that each storage block 10 can synchronously read and write 16-bit data information, thereby achieving better performance.

[0065] Figure 6 FIG. 1 is a schematic diagram of a semiconductor memory device having a complete storage block structure according to another embodiment of the present invention. Figure 6 In the present embodiment, in one of the embodiments, the first array 110 is connected to two first gating circuits 310, and the first gating circuits 310 are connected to the global data bus 700 in a one-to-one correspondence; the third array 130 is connected to two third gating circuits 330, and the third gating circuits 330 are connected to the global data bus 700 in a one-to-one correspondence; wherein the first gating circuit 310, the second gating circuit 320 and the first gating circuit 310 connected to the same global data bus 700 are turned on in a time-sharing manner.

[0066] Specifically, each memory array 100 has its own first word line 141, second word line 142, first bit line 151, second bit line 152 and column selection line 160. The first bit line 151 is connected to a global data bus 700 through a gating circuit 300, and the second bit line 152 is connected to another global data bus 700 through another gating circuit 300. In each data reading and writing process, each check module 200 can transmit data information with one of the three memory arrays 100, and two check modules 200 can synchronously transmit data information with the same memory array 100. For example, in Figure 6In the embodiment shown, the first word line 141, the second word line 142 and the column selection line 160 of the first array 110 are enabled, the first word line 141, the second word line 142 and the column selection line 160 of the second array 120 are all disabled (as shown by the dotted line), and the first word line 141, the second word line 142 and the column selection line 160 of the third array 130 are all disabled, then the data transmission path between the two check modules 200 and the first array 110 is connected, thereby realizing the transmission of data information. As can be seen from the figure, corresponding to different byte data ports, the same set of column selection signals CS can be used. If the word lines corresponding to different byte data ports are all turned on, when the column selection signal CS is turned on, the data corresponding to each word line will be respectively connected to the global data bus corresponding to the different byte data ports, thereby saving the number of turned-on column selection signals CS by sharing the same set of column selection signals CS, and saving the power consumption generated by turning on the column selection signal CS.

[0067] Figure 7 FIG. 2 is a schematic diagram of a structure of a check module 200 in a semiconductor memory according to an embodiment of the present invention. Figure 7 As shown, in one embodiment, the verification module 200 includes an encoding unit 210 and an error detection unit 220.

[0068] The encoding unit 210 is connected to the storage array 100, and is used to receive input data information, encode the data information to generate write verification information, and send the data information and the write verification information to the storage array 100;

[0069] The error detection unit 220 is connected to the storage array 100 and is used to synchronously read data information and write verification information from the storage array 100, and verify whether errors occur in the read data information according to the written verification information.

[0070] It can be understood that the encoding unit 210 encodes the data information according to the preset rules, so the generated write verification information is one-to-one corresponding to the data information. If the read data information is found to be inconsistent with the write verification information when reading the data, it means that the data information has changed during the reading and writing process of the data information, resulting in data information errors. Therefore, this embodiment can accurately detect whether the read data information has errors through the encoding unit 210 and the error detection unit 220, thereby improving the accuracy of the read data information.

[0071] Continue to refer Figure 7The error detection unit 220 is also connected to the encoding unit 210, and the encoding unit 210 is also used to encode the read data information to generate read verification information, and send the read verification information to the error detection unit 220; the error detection unit 220 is used to obtain write verification information and read verification information, and compare the write verification information and the read verification information to determine whether an error occurs in the read data information.

[0072] In one embodiment, the verification module 200 further includes an error correction unit 230, which is connected to the error detection unit 220, and is used to receive the read data information and the comparison result information of the error detection unit 220, and update the data information according to the comparison result information.

[0073] Specifically, the comparison result information includes whether the read data information is the same as the written data information. When the two are different, the comparison result information further includes a specific error data bit. For example, if the written data information is 10000000 and the read data information is 11000000, the error data bit is the 2nd bit. The error correction unit 230 is used to receive the comparison result information and directly perform error correction according to the comparison result information. For example, if the read data information is 11000000, and the 2nd bit is indicated as the error data bit in the comparison result information, the written data information must be 10000000, and the error correction unit 230 can update the data information to complete the error correction. By setting the error correction unit 230, the present embodiment can correct the read error data information, thereby outputting the correct read data information.

[0074] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The above embodiments only express several implementation methods of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application. Therefore, the protection scope of the patent of the embodiments of the present application shall be subject to the attached claims.

Claims

1. A semiconductor memory, characterized in that: include: Multiple storage arrays; At least one verification module, each of which corresponds to the plurality of storage arrays, and is used to verify whether data information of the corresponding storage array has errors, and each of which is connected to a set of global data buses; A plurality of gating circuits, each of which is connected to the storage array and the global data bus, and is used to control the on / off of a data transmission path between the connected global data bus and the storage array; The semiconductor memory comprises three storage arrays and two check modules. The three storage arrays comprise a first array, a second array and a third array. The second array is connected to two second gating circuits.

2. The semiconductor memory according to claim 1, wherein: The second gating circuits are connected to the global data buses in a one-to-one correspondence.

3. The semiconductor memory according to claim 1, wherein: The second array includes a first bit line and a second bit line, the first bit line is connected to one of the two second gating circuits, and the second bit line is connected to the other of the two second gating circuits.

4. The semiconductor memory according to claim 2, wherein: The first array is connected to two first gating circuits, and the first gating circuits are connected to the global data bus in a one-to-one correspondence; The third array is connected to two third gating circuits, and the third gating circuits are connected to the global data bus in a one-to-one correspondence; The first gating circuit, the second gating circuit and the first gating circuit connected to the same global data bus are turned on in a time-sharing manner.

5. The semiconductor memory according to claim 1, wherein: The verification module comprises: an encoding unit connected to the storage array, configured to receive input data information, encode the data information to generate write verification information, and send the data information and the write verification information to the storage array; An error detection unit is connected to the storage array and is used to synchronously read the data information and the write verification information from the storage array, and verify whether an error occurs in the read data information according to the write verification information.

6. The semiconductor memory according to claim 5, wherein: The error detection unit is also connected to the encoding unit, and the encoding unit is further used to encode the read data information to generate read verification information, and send the read verification information to the error detection unit; The error detection unit is used to obtain the write verification information and the read verification information, and compare the write verification information with the read verification information to determine whether an error occurs in the read data information.

7. The semiconductor memory according to claim 6, wherein: The verification module also includes an error correction unit connected to the error detection unit, configured to receive the read data information and comparison result information of the error detection unit, and update the data information according to the comparison result information.

8. The semiconductor memory according to claim 1, wherein: The semiconductor memory further comprises a gating control module, wherein the gating control module is used to generate a plurality of gating signals; The gating circuit includes a switch tube, a control end of the switch tube is connected to the gating control module, a first end of the switch tube is connected to the global data bus, and a second end of the switch tube is connected to the storage array. The switch tube is used to select to turn on or off the data transmission path between the first end and the second end under the control of the gating signal.

9. The semiconductor memory according to claim 8, characterized in that The switch tube is a high-voltage switch tube.

10. The semiconductor memory according to claim 8, wherein: The switch tube is turned on at a high level.

11. The semiconductor memory according to claim 1, wherein: The semiconductor memory also includes at least one byte data port, which is connected to the verification module in a one-to-one correspondence and is used to receive the data information input from the outside or output the read data information to the outside.

12. The semiconductor memory according to claim 1, wherein: The semiconductor memory also includes a read-write control module, which is connected to the verification module and the global data bus respectively. The read-write control module is used to receive a read-write enable signal and select a data transmission direction between the verification module and the corresponding global data bus under the control of the read-write enable signal.

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