Memory device and clock locking method thereof

Abstract

Disclosed are a memory device and a clock locking method thereof. The clock locking method of the memory device can include performing an initial locking operation in a delay-locked loop circuit before an internal voltage is stabilized, monitoring a clock skew between a reference clock and a feedback clock using a window detection circuit after the internal voltage is stabilized, and performing a re-locking operation in the delay-locked loop circuit using a dynamic delay control corresponding to the clock skew.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0118435, filed on September 15, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a memory device and a clock locking method thereof. Background Technology

[0003] Typically, as the speed of semiconductor devices (such as dynamic random access memory (DRAM)) increases, delay-locked loop (DLL) circuits can operate independently using coarse delay lines with low delay resolution and fine delay lines with high delay resolution. Summary of the Invention

[0004] One aspect of the present invention is to provide a memory device that performs relatively fast clock locking under power noise conditions, and a clock locking method for the memory device.

[0005] According to one aspect of the present invention, a memory device includes: a first delay line configured to delay a reference clock according to a first code value to output a first delayed clock; a second delay line configured to delay the first delayed clock according to a second code value to output a second delayed clock; a first delay line controller configured to generate the first code value according to a first phase difference value, or configured to generate the first code value according to a second phase difference value; a second delay line controller configured to generate the second code value according to the second phase difference value; and a demultiplexer configured to output the second phase difference value to the first delay line controller in response to a monitoring detection signal corresponding to a clock offset between the reference clock and a feedback clock. One of the second delay line controllers; a first phase detector configured to detect a first phase difference between a reference clock and a feedback clock; a second phase detector configured to detect a second phase difference between a reference clock and a feedback clock; a clock path configured to receive a second delayed clock and configured to generate an internal clock; an output buffer configured to synchronize with the internal clock to output a data strobe signal; a clock path copy configured to delay the second delayed clock by an amount equal to the delay of the clock path; and an output buffer copy configured to generate a feedback clock by delaying the clock output from the clock path copy by an amount equal to the delay of the output buffer.

[0006] According to one aspect of the present invention, a clock locking method for a memory device includes: performing an initial locking operation in a delay-locked loop circuit before the internal voltage is stabilized; using a window detection circuit to monitor the clock offset between a reference clock and a feedback clock after the internal voltage is stabilized; and performing a relocking operation in the delay-locked loop circuit using dynamic delay control corresponding to the clock offset.

[0007] According to one aspect of the present invention, a memory device includes: a memory cell array having a plurality of memory cells, a plurality of word lines and a plurality of bit lines intersecting in the plurality of memory cells; a row decoder configured to select a word line among the plurality of word lines in response to a row address; a bit line detection amplifier circuit configured to detect and amplify data from a memory cell connected to a selected bit line among the plurality of bit lines during a read operation; a column decoder configured to select a selected bit line among the plurality of bit lines in response to a column address; a data input / output device configured to receive data from the bit line detection amplifier circuit during a read operation and configured to output the received data to an external device in response to a data strobe signal synchronized with an internal clock; a delay-locked loop circuit configured to receive a reference clock and configured to generate an internal clock; and a window detection circuit configured to generate a monitoring detection signal corresponding to a clock offset between the reference clock and a feedback clock. Attached Figure Description

[0008] The above and other aspects, features and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 This is a figure illustrating a memory device 100 with a delay-locked loop (DLL) according to an exemplary embodiment of the present invention.

[0010] Figure 2A and Figure 2B This is a diagram illustrating a method for controlling phase detectors PD1 and PD2 of a DLL controller 120 according to an exemplary embodiment of the present invention.

[0011] Figure 3 This is a diagram illustrating a window detection circuit 125 according to an exemplary embodiment of the present invention.

[0012] Figure 4 This is a diagram illustrating the locking operation of a DLL 110 according to an example embodiment of the present invention.

[0013] Figure 5 This is a diagram illustrating the internal configuration of a window detection circuit 125 according to an exemplary embodiment of the present invention.

[0014] Figure 6and Figure 7 This is a diagram illustrating the operation of a clock offset monitor 125-1 according to an exemplary embodiment of the present invention.

[0015] Figure 8 and Figure 9 This is a diagram illustrating the operation of a clock synchronization circuit 125-2 according to an exemplary embodiment of the present invention.

[0016] Figure 10 and Figure 11 This is a diagram illustrating the operation of a monitoring and detection signal generator 125-3 according to an exemplary embodiment of the present invention.

[0017] Figure 12 This is a flowchart illustrating a method of operating a memory device 100 according to an exemplary embodiment of the present invention.

[0018] Figure 13 This is a diagram illustrating a memory device 700 according to an exemplary embodiment of the present invention.

[0019] Figure 14 This is a diagram illustrating a memory system performing at least one command / address calibration according to an exemplary embodiment of the concept of the present invention.

[0020] Figure 15 This is a diagram illustrating an electronic system 3000 for a vehicle according to an exemplary embodiment of the present invention.

[0021] Figure 16 This is a diagram illustrating a data center using a memory device applied according to an example embodiment of the concept of the present invention. Detailed Implementation

[0022] In the following, the content of the inventive concept will be clearly and in detail described to the extent that those skilled in the art can readily implement the inventive concept using the accompanying drawings.

[0023] Typically, a Delayed Locked Loop (DLL) of a memory device performs a coarse locking operation during the initial locking period, followed by a fine locking operation. Subsequently, when unlocking occurs due to a power drop, the DLL can perform a fine locking operation to relock the device. This increases the DLL's locking time and reduces the data valid window (tDV).

[0024] The DLL of the memory device according to an exemplary embodiment of the present invention can operate a window detection circuit after the initial locking period to monitor the delay difference between the reference clock and the feedback clock, and activate a coarse locking operation based on the monitoring results. As a result, the memory device according to an exemplary embodiment of the present invention can monitor the delay skew corresponding to dynamic power noise to enable rapid clock synchronization, thereby addressing the reduction in tDV.

[0025] Figure 1 This is a figure illustrating a memory device 100 with a delay-locked loop (DLL) according to an exemplary embodiment of the present invention. (Refer to...) Figure 1 The memory device 100 may include a DLL 110, a clock path 130, and / or an output buffer 140.

[0026] The memory device 100 can be implemented to store data received from an external controller or to output read data to the controller. The memory device 100 can be used as operational memory, working memory, or buffer memory in a computing system. In example embodiments, the memory device 100 can be implemented as a single in-line memory module (SIMM), a dual in-line memory module (DIMM), a small outline DIMM (SODIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FBDIMM), a rank-buffered DIMM (RBDIMM), a miniature DIMM, a micro DIMM, a register-based DIMM (RDIMM), or a low-load DIMM (LRDIMM).

[0027] In example embodiments, memory device 100 may be implemented as volatile memory. For example, volatile memory may include at least one of dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), low power double data rate SDRAM (LPDDRSDRAM), graphics double data rate SDRAM (GDDRSDRAM), rambus DRAM (RDRAM), and static RAM (SRAM). In other example embodiments, memory device 100 may be implemented as non-volatile memory. For example, non-volatile memory may include one of NAND flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and NOR flash memory.

[0028] DLL 110 may include a first delay line (coarse delay line (CDL)) 111, a second delay line (fine delay line (FDL)) 112, a first delay line controller (CDL CNTL) 113, a second delay line controller (FDL CNTL) 114, a clock path copy 115, an output buffer copy 116, a first phase detector (PD1) 117, a second phase detector (PD2) 118, and / or a demultiplexer (De-MUX) 119.

[0029] Although not shown, the memory device 100 may also include a clock buffer that buffers a clock (CK) from an external source to generate a reference clock REFCLK.

[0030] The first delay line (coarse delay line) 111 can be implemented to receive a reference clock REFCLK and delay the reference clock REFCLK according to a first code value to generate a first delayed clock DCLK1. In an example embodiment, the first delay line may include first delay units connected in series. In an example embodiment, each of the first delay units may have a first delay amount.

[0031] The second delay line (fine delay line) 112 can be implemented to receive a first delayed clock DCLK1 and delay the first delayed clock DCLK1 according to a second code value to generate a second delayed clock DCLK2. In an example embodiment, the second delay line may include second delay units connected in series. In an example embodiment, each of the second delay units may have a second delay amount. In some example embodiments, the second delay amount may be less than the first delay amount.

[0032] The first delay line controller (CDL CNTL) 113 can be implemented to generate a first code value corresponding to a first phase difference or a second phase difference.

[0033] The second delay line controller (FDL CNTL) 114 can be implemented to generate a second code value corresponding to the second phase difference.

[0034] Clock path copy 115 can be implemented to receive a second delayed clock DCLK2 and have the same or substantially the same delay as in clock path 130.

[0035] Output buffer copy 116 can be implemented such that the clock delay from clock path copy 115 to output buffer copy 116 is the same or substantially the same as the delay in output buffer 140, so as to have (e.g., generate) feedback clock FBCLK.

[0036] The first phase detector (PD1) 117 can be implemented to generate a first phase difference based on the feedback clock FBCLK.

[0037] The second phase detector (PD2) 118 can be implemented to generate a second phase difference based on the feedback clock FBCLK.

[0038] The demultiplexer (De-MUX) 119 can be implemented to output a second phase difference value to one of the first delay line controller 113 and the second delay line controller 114 in response to a monitoring detection signal CON. In some example embodiments, the monitoring detection signal CON may be a signal that monitors delay offsets caused by dynamic power noise.

[0039] Clock path 130 can be implemented to send the clock output from DLL 110 to the memory device 100 via an internal path to generate an internal clock.

[0040] The output buffer 140 can be implemented to use the clock PCLK output from the clock path 130 to output the data strobe signal DQS for output data.

[0041] The memory device 100 of an exemplary embodiment of the present invention may include a DLL 110, which performs a coarse locking operation in response to a monitoring detection signal CON for monitoring delay offset, so as to more quickly compensate for delay offset caused by power noise.

[0042] Figure 2A and Figure 2B This is a diagram illustrating a method for controlling phase detectors PD1 and PD2 of a DLL controller 120 according to an exemplary embodiment of the present invention.

[0043] like Figure 2A As shown, the DLL controller 120 can output a first activation signal PD1_EN and a second activation signal PD2_EN, causing the first phase detector (PD1) 117 and the second phase detector (PD2) 118 of the DLL 110 to operate complementaryly to each other. The first phase detector 117 can be activated in response to the first activation signal PD1_EN. The second phase detector 118 can be activated in response to the second activation signal PD2_EN.

[0044] like Figure 2BAs shown, before the internal voltage of the memory device 100 is stabilized (e.g., as determined using the internal voltage stabilization signal PICC2D), the first activation signal PD1_EN can initially be high to perform a coarse locking operation. Then, the second activation signal PD2_EN can be high to perform a fine locking operation. Afterward, once the internal voltage is stabilized, the memory device 100 can hold the second activation signal PD2_EN high and the first activation signal PD1_EN low. In other example embodiments, after the internal voltage is stabilized, in response to the monitoring detection signal CON, the DLL controller 120 can change the second activation signal PD2_EN low and the first activation signal PD1_EN high.

[0045] Figure 3 This is a diagram illustrating a window detection circuit 125 according to an exemplary embodiment of the concept of the present invention. (Refer to...) Figure 3 The window detection circuit 125 can receive the internal voltage stabilization signal PICC2D and can be implemented to generate a monitoring detection signal CON when the delay offset between the reference clock REFCLK and the feedback clock FBCLK exceeds a predetermined value (or optionally, an expected value).

[0046] Figure 4 This is a diagram illustrating the locking operation of a DLL 110 according to an exemplary embodiment of the present invention. (Refer to...) Figure 4 DLL 110 can perform coarse and fine locking operations during the initialization phase, and can also perform them during normal periods after the initialization phase (e.g., in...). Figure 4 During the "2N" period, fine locking operation can be maintained, and then unlocking can occur due to power noise (e.g., in...). Figure 4 A coarse locking operation is performed during the "3N-4R" period. Therefore, clock locking operations can be achieved faster than in the example embodiment where unlocking and relocking are performed through a conventional fine locking operation.

[0047] Figure 5 This is a diagram illustrating the internal configuration of a window detection circuit 125 according to an exemplary embodiment of the present invention. (Refer to...) Figure 5 The window detection circuit 125 may include a clock offset monitor 125-1, a clock synchronization circuit (or clock synchronizer) 125-2, and a monitoring detection signal (CON) generator 125-3.

[0048] The clock offset monitor 125-1 can be implemented to monitor the clock offset between the reference clock REFCLK and the feedback clock FBCLK, and output a phase detection signal PD_LH_B corresponding to the clock offset.

[0049] In an example embodiment, the clock skew monitor 125-1 can be activated in response to the internal voltage stabilization signal PICC2D. In an example embodiment, the clock skew monitor 125-1 can be forcibly deactivated via the Test Mode Register Set (TMRS).

[0050] The clock synchronization circuit 125-2 can be implemented to receive the phase detection signal PD_LH_B and output the phase detection signal PD_LH_BD synchronized with the internal clock.

[0051] The monitoring and detection signal generator 125-3 can be implemented to receive the synchronous phase detection signal PD_LH_BD and generate the monitoring and detection signal CON corresponding to the clock offset between the reference clock REFCLK and the feedback clock FBCLK.

[0052] Figure 6 and Figure 7 This is a diagram illustrating the operation of a clock offset monitor 125-1 according to an exemplary embodiment of the present invention. (Refer to...) Figure 6 and Figure 7 The clock offset monitor 125-1 can monitor the clock offset between the reference clock REFCLK and the feedback clock FBCLK, and can output the phase detection signal PD_LH_B corresponding to the clock offset.

[0053] Reference Figure 6 The clock offset monitor 125-1 can receive a reference clock REFCLK, a feedback clock FBCLK, a dynamic offset monitoring signal DYNSKEW_SCR_ON, an internal voltage stabilization signal PICC2D, and / or a row open signal ROW_OPEN. In some example embodiments, the dynamic offset monitoring signal DYNSKEW_SCR_ON can be a signal that monitors dynamic offset. The row open signal ROW_OPEN can be forcibly disabled (e.g., L; low state) via TMRS.

[0054] In an example embodiment, the clock deactivation signal CLKDIS can be generated by manipulating the internal voltage stabilization signal PICC2D, the row open signal ROW_OPEN, and the phase detection signal PD_LH. The monitoring activation signal SCR_EN can be a signal that defines the time period in which the first phase detector PD1 operates.

[0055] In an example embodiment, the monitoring activation signal SCR_EN can be generated by operating the dynamic offset monitoring signal DYNSKEW_SCR_ON and the clock deactivation signal CLKDIS. In an example embodiment, the internal voltage stabilization signal PICC2DD, provided to the trigger (SA_FF) of the sense amplifier, can be generated based on the operation result of the internal voltage stabilization signal PICC2D and the clock deactivation signal CLKDIS. In an example embodiment, the delayed reference clock REFCLKD can be generated by operating the reference clock REFCLK and the monitoring activation signal SCR_EN.

[0056] In an example embodiment, the delayed feedback clock FBCLKD can be generated by operating on the feedback clock FBCLK and the monitor activation signal SCR_EN. In another example embodiment, the phase detection signal PD_LH can be generated by operating on the delayed reference clock REFCLKD and the delayed feedback clock FBCLKD via delay units DCELL1 and DCELL0 and their corresponding flip-flops SAFF. The multiplexer can select either the phase detection signal PD_LH or the ground signal VSSIO in response to the monitor activation signal SCR_EN.

[0057] The clock offset monitor 125-1 can invert the output signal of the multiplexer to output the phase detection signal PD_LH_B.

[0058] Figure 8 and Figure 9 This is a diagram illustrating the operation of a clock synchronization circuit 125-2 according to an exemplary embodiment of the present invention. (Refer to...) Figure 8 and Figure 9 The clock synchronization circuit 125-2 can receive the phase detection signal PD_LH_B and output the phase detection signal PD_LH_BD synchronized with the internal clock.

[0059] The up-down signal UPDOWN and the complementary up-down signal UPDOWNB can be generated by manipulating the up signal UP and the down signal DOWN.

[0060] The flip-flop F / F can output signal A in response to the phase detection signal PD_LH_B and the up / down signal UPDOWN. Furthermore, the flip-flop F / F can output signal B in response to the phase detection signal PD_LH_B and the complementary up / down signal UPDOWNB. Signal C can be generated by manipulating signals A and B.

[0061] The flip-flop F / F can input / output the phase detection signal PD_LH_BD in response to the operation result signal CLKN2B between the operation result signals of signals C and D and the internal clock CLKN2. In some example embodiments, signal D may be a signal obtained by delaying the operation result signal obtained by operating the phase detection signal PD_LH_BD via the flip-flop F / F.

[0062] Figure 10 and Figure 11 This is a diagram illustrating the operation of a monitoring and detection signal generator 125-3 according to an exemplary embodiment of the present invention. (Refer to...) Figure 10 and Figure 11 The monitoring and detection signal generator 125-3 can receive the phase detection signal PD_LH_BD and generate the monitoring and detection signal CON.

[0063] The initialization load completion signal INIT_LOAD_DONE can be the signal that will be loaded, causing the first phase detector PD1 to set its code value to the coarse delay line (CDL) via a time-to-digital converter (TDC). For example, after the operation of the first phase detector PD1 is complete, the initialization load completion signal INIT_LOAD_DONE can be changed from low to high.

[0064] The reset signal RESETB, the load initialization completion signal INIT_LOAD_DONE, the phase detection signal PD_LH_BD, and the internal voltage stabilization signal PICC2D can be manipulated to generate the completion stage reset signal END_STATGE_RSTB.

[0065] The delayed lower signal DOWMD can be generated by manipulating the lower signal DOWN and the internal clock CLKN2. The delayed upper signal UPD can be generated by manipulating the upper signal UP and the internal clock CLKN2.

[0066] The first flip-flop, connected in series, can output the completion stage reset signal END_STATE_RSTB in response to the delayed up signal UPD. The second flip-flop, also connected in series, can output the completion stage reset signal END_STATE_RSTB in response to the delayed down signal DOWND.

[0067] The completion stage signal END_STAGE can be generated by manipulating the output signals of the first and second flip-flops. In some example embodiments, the completion stage signal END_STAGE may be a signal instructing the second phase detector PD2 to operate.

[0068] The phase detection signal PD_LH_BD can be generated in response to the clock offset between the reference clock REFCLK and the feedback clock FBCLK. For example... Figure 11 As shown, in response to the low level of the upper signal UP and the rising edge of the lower signal DOWN, a new completion stage signal NEW_END_STAGE corresponding to the phase detection signal PD_LH_BD can be generated. The newly generated new completion stage signal NEW_END_STAGE can be output as the monitoring detection signal CON of the window detection circuit 125.

[0069] Figure 12 This is a flowchart illustrating a method of operating a memory device 100 according to an exemplary embodiment of the present invention. (Refer to...) Figures 1 to 12 The memory device 100 can be operated as follows.

[0070] When the memory device 100 is powered on, the memory device 100 may perform an initial locking operation (S110). In some example embodiments, the initial locking operation may include a coarse locking operation and a fine locking operation. When the internal voltage is stabilized, the fine locking operation may be performed primarily.

[0071] The window detection circuit 125 of the memory device 100 can monitor the delay offset between the input clock (e.g., reference clock REFCLK) and the output clock (e.g., feedback clock FBCLK) of the DLL 110 (S120). When the delay offset exceeds a predetermined value (or optionally, a desired value), a monitoring detection signal CON can be generated.

[0072] DLL 110 can perform a coarse locking operation in response to the monitoring detection signal CON, to perform a relocking operation to convert the unlocked state to the locked state (S130).

[0073] The DLL of the exemplary embodiment of the present invention can be applied to a memory device.

[0074] Figure 13 This is a figure illustrating a memory device 700 according to an exemplary embodiment of the present invention. (Refer to...) Figure 13 The memory device 700 may include a DLL 701, a window detection circuit 702, a memory cell array 710, a row decoder 720, a column decoder 730, a sense amplifier circuit 740, an address register 750, a memory bank control logic 752, a refresh counter 754, a row address multiplexer 756, a column address latch 758, a control logic 760, a repair control circuit (not shown), a timing control circuit (not shown), an input / output (I / O) gating circuit 770, an error correction circuit 780, and / or a data input / output (I / O) buffer 782.

[0075] like Figures 1 to 12 As described above, DLL 701 can quickly perform a coarse locking operation in response to the monitoring detection signal CON. Furthermore, as... Figures 1 to 12 As described above, the window detection circuit 702 can monitor the delay offset between the reference clock REFCLK and the feedback clock FBCLK, and can output a monitoring detection signal CON based on the monitoring results.

[0076] The memory cell array 710 may include first memory banks 711 to eighth memory banks 718. It is understood that the number of memory banks in the memory cell array 710 is not limited to this. The row decoder 720 may include first memory bank row decoders 721 to eighth memory bank row decoders 728 respectively connected to the first memory banks 711 to eighth memory banks 718. The column decoder 730 may include first memory bank column decoders 731 to eighth memory bank column decoders 738 respectively connected to the first memory banks 711 to eighth memory banks 718. The sense amplifier circuit 740 may include first memory bank sense amplifiers 741 to eighth memory bank sense amplifiers 748 respectively connected to the first memory banks 711 to eighth memory banks 718.

[0077] The first memory bank 711 to the eighth memory bank 718, the first memory bank row decoder 721 to the eighth memory bank row decoder 728, the first memory bank column decoder 731 to the eighth memory bank column decoder 738, and the first memory bank sense amplifier 741 to the eighth memory bank sense amplifier 748 can be configured with the first memory bank to the eighth memory bank respectively. Each of the first memory bank 711 to the eighth memory bank 718 may include a plurality of memory cells MC formed at the point where the word line WL and the bit line BL intersect.

[0078] Address register 750 can receive and store address ADDR from the external memory controller. Address ADDR has a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR. Address register 750 can provide the received bank address BANK_ADDR to the bank control logic 752, the received row address ROW_ADDR to the row address multiplexer 756, and the received column address COL_ADDR to the column address latch 758.

[0079] The memory bank control logic 752 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, the memory bank row decoder corresponding to the memory bank address BANK_ADDR, from the first memory bank row decoder 721 to the eighth memory bank row decoder 728, can be activated. In response to the memory bank control signal, the memory bank column decoder corresponding to the memory bank address BANK_ADDR, from the first memory bank column decoder 731 to the eighth memory bank column decoder 738, can be activated.

[0080] The row address multiplexer 756 can receive the row address ROW_ADDR from the address register 750 and the refresh row address REF_ADDR from the refresh counter 754. The row address multiplexer 756 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 756 can be applied to the first memory bank row decoder 721 through the eighth memory bank row decoder 728, respectively.

[0081] Among the first to eighth bank row decoders 721, the bank row decoder activated by the bank control logic 752 can decode the row address RA output from the row address multiplexer 756 to activate the word line corresponding to the row address. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address. Furthermore, the activated bank row decoder can activate the word line corresponding to the row address and simultaneously activate the redundant word line corresponding to the redundant row address output from the repair control circuit.

[0082] Column address latch 758 can receive column address COL_ADDR from address register 750 and can temporarily store the received column address COL_ADDR. Furthermore, column address latch 758 can gradually increase the received column address COL_ADDR in burst mode. Column address latch 758 can apply the temporarily stored or gradually increased column address COL_ADDR to column decoders 731 through 738 of the first memory bank, respectively.

[0083] Among the first bank column decoders 731 to the eighth bank column decoders 738, the bank column decoder activated by the bank control logic 752 can activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output gating circuit 770. Furthermore, the activated bank column decoder can perform a column repair operation in response to a column repair signal output from the repair control circuit.

[0084] Control logic 760 can be implemented to control the operation of memory device 700. For example, control logic 760 can generate control signals that cause memory device 700 to perform write or read operations. Control logic 760 may include command decoder 761 and mode register group 762. Command decoder 761 decodes commands (CMD) received from memory controller, and mode register group 762 sets the operating mode of memory device 700.

[0085] For example, the command decoder 761 can decode the write enable signal / WE, the row address strobe signal / RAS, the column address strobe signal / CAS, and the chip select signal / CS to generate operation control signals ACT, PCH, WE, and RD corresponding to the command CMD. The control logic 760 can provide the operation control signals ACT, PCH, WE, and RD to the timing control circuit. The operation control signals ACT, PCH, WE, and RD can each include the valid signal ACT, the precharge signal PCH, the write signal WR, and the read signal RD, respectively.

[0086] The input / output gating circuit in the input / output gating circuit 770 may accordingly include input data masking logic, a read data latch for storing data output from the first memory bank 711 to the eighth memory bank 718, a write driver for writing data to the first memory bank 711 to the eighth memory bank 718, and circuitry for gating the input / output data.

[0087] The codeword CW to be read from one of the first to eighth memory banks 711 can be sensed by a sense amplifier corresponding to said memory bank and can be stored in a read data latch. The codeword CW stored in the read data latch can be ECC decoded by error correction circuit 780 and can be provided to the memory controller by data input / output buffer 782. The data DQ to be written to one of the first to eighth memory banks 711 can be ECC encoded by error correction circuit 780 and can be written to said memory bank by a write driver.

[0088] The data input / output buffer 782 can provide data DQ to the error correction circuit 780 based on the clock signal CLK provided from the memory controller during a write operation, and can provide data DQ from the error correction circuit 780 to the memory controller during a read operation.

[0089] Error correction circuit 780 can generate parity bits based on the data bits of data DQ provided from data input / output buffer 782 during write operations, and can provide a codeword CW including data DQ and parity bits to input / output gating circuit 770. Input / output gating circuit 770 can write codeword CW into memory. Furthermore, error correction circuit 780 can receive codeword CW read from memory from input / output gating circuit 770 during read operations. Error correction circuit 780 can perform ECC decoding on data DQ using the parity bits included in the read codeword CW, and can correct at least one erroneous bit included in data DQ to provide corrected data DQ to data input / output buffer 782.

[0090] The memory device 700 of the exemplary embodiment of the present invention can quickly control the delay offset caused by power noise under the internal voltage stabilization state.

[0091] Figure 14 This is a diagram illustrating a memory system performing at least one command / address calibration according to an exemplary embodiment of the concept of the present invention.

[0092] Reference Figure 14 The memory system 1000 may include a controller 1800 and a memory device 1900. The controller 1800 may include a clock generator 1801, a command / address (CA; or referred to as a command / address signal) generator 1802, a command / address reference generator (or CA_ref1 generator) 1803, a register (or CA_ref1 register) 1804, a comparator (or CA_ref comparator) 1806, a phase / timing controller (or CA phase / timing controller) 1808, and / or data input / output units 1810 and 1812. The controller 1800 may provide a clock signal CK generated by the clock generator 1801 to the memory device 1900 via a clock signal line.

[0093] In an example embodiment, the memory system 1000 may include a separate command / address reference signal CA_Ref line (or CA reference bus) in the interface. The command / address reference signal CA_Ref line can send / receive the command / address reference signal CA_Ref in calibration mode, and the command / address reference signal CA_Ref can be a reference value for the command / address.

[0094] The calibration result using the command / address reference value can be provided to the phase / timing controller 1808 to adjust the phase / timing of the command / address signal CA. Because a separate command / address reference signal CA_Ref line can exist, it is advantageous to perform a calibration operation that adjusts the phase / timing of the command / address signal CA simultaneously with the transmission of the command / address signal CA.

[0095] The CA generator 1802 can generate a command / address signal CA whose phase or timing response is adjusted by the control signal CTR of the phase / timing controller 1808, and can send the command / address signal CA to the memory device 1900 via the CA bus.

[0096] Command / address reference generator 1803 can be configured in the same way as command / address generator 1802, and can generate the same first command / address reference signal CA_Ref1 as the command / address signal CA generated from command / address generator 1802.

[0097] The first command / address reference signal CA_Ref1 can be provided to register 1804. Furthermore, the first command / address reference signal CA_Ref1 can be sent to the CA reference bus by data output unit 1812, and can be provided to memory device 1900 via the CA reference bus.

[0098] Register 1804 can store the first command / address reference signal CA_Ref1. Comparator 1806 can compare the first command / address reference signal CA_Ref1 stored in register 1804 with the third command / address reference signal CA_Ref3 output from data input unit 1810. Comparator 1806 can compare the data of the first command / address reference signal CA_Ref1 with the data of the third command / address reference signal CA_Ref3 to generate a pass or fail signal P / F.

[0099] The phase / timing controller 1808 can generate a control signal CTR indicating the phase offset of the command / address signal CA based on the pass / fail signal P / F of the comparator 1806. The control signal CTR can adjust the phase or timing of the command / address signal CA to generate a phase-adjusted command / address signal CA.

[0100] The data input unit 1810 can receive the second command / address reference signal CA_Ref2 sent from the memory device 1900 via the CA reference bus, and can send the received second command / address reference signal CA_Ref2 to the comparator 1806 as the third command / address reference signal CA_Ref3.

[0101] The data output unit 1812 can receive the first command / address reference signal CA_Ref1 generated by the command / address reference generator 1803, and can send the received first command / address reference signal CA_Ref1 to the CA reference bus.

[0102] The memory device 1900 may include a clock buffer 1902, a command / address (CA) receiver 1904, a command / address reference receiver (or CA_ref receiver) 1906, and / or data input / output units 1908 and 1910. The clock buffer 1902 may receive a clock signal CK transmitted via a clock signal line to generate an internal clock signal ICK. The CA receiver 1904 may receive a chip select signal / CS, a clock enable signal CKE, and a command / address signal CA transmitted via the CA bus in response to the internal clock signal ICK.

[0103] The clock enable signal CKE can be used as a pseudo-command, which functions as a read command for the command / address signal CA sent via the CA bus. When the clock enable signal CKE is activated, the CA receiver 1904 can receive the command / address signal CA.

[0104] Data input unit 1908 can receive the first command / address reference signal CA_Ref1 sent from controller 1800 via the CA reference bus, and send the first command / address reference signal CA_Ref1 to command / address reference receiver 1906. Command / address reference receiver 1906 can be configured in the same way as CA receiver 1904. Command / address reference receiver 1906 can receive chip select signal / CS, clock enable signal CKE, and the first command / address reference signal CA_Ref1 sent via the CA reference bus in response to internal clock signal ICK, to generate a second command / address reference signal CA_Ref2.

[0105] The second command / address reference signal CA_Ref2 can be the same as the signal that the CA receiver 1904 receives and outputs in response to the internal clock signal ICK, including the chip select signal / CS, the clock enable signal CKE, and the command / address signal CA transmitted via the CA bus. The second command / address reference signal CA_Ref2 can be sent to the CA reference bus via the data output unit 1910.

[0106] The CA calibration performed in the memory system 1000 can be as follows: The CA generator 1802 of the controller 1800 can adjust the phase or timing of the command / address signal CA in response to the control signal CTR of the phase / timing controller 1808, so as to send the command / address signal CA to the CA bus. The command / address reference generator 1803 can generate a first command / address reference signal CA_Ref1 that is the same as the command / address signal CA, and send the generated first command / address reference signal CA_Ref1 to the CA reference bus.

[0107] The command / address reference receiver 1906 of the memory device 1900 can receive the first command / address reference signal CA_Ref1 according to the internal clock signal ICK and the clock enable signal CKE, and can generate a second command / address reference signal CA_Ref2. The second command / address reference signal CA_Ref2 of the memory device 1900 can be sent to the CA reference bus.

[0108] Controller 1800 can send a second command / address reference signal CA_Ref2, transmitted via the CA reference bus, to comparator 1806 as a third command / address reference signal CA_Ref3. Comparator 1806 can compare the data of the first command / address reference signal CA_Ref1 with the data of the third command / address reference signal CA_Ref3 to generate a pass / fail signal P / F. Phase / timing controller 1808 can generate a control signal CTR indicating the phase offset of the command / address signal CA based on the pass / fail signal P / F from comparator 1806. CA generator 1802 can generate a command / address signal CA whose phase is adjusted according to the control signal CTR.

[0109] By repeating the CA calibration operation, the phase / timing controller 1808 of the controller 1800 can determine the center portion of the (pass, P) position as the center portion of the command / address signal CA window. The command / address signal CA can be generated and provided to the memory device 1900 such that the center portion of the command / address signal CA window arrives at the edge of the clock signal CK. Therefore, the memory device 1900 can receive the command / address signal CA in which the center portion of the effective window is located at the rising / falling edges of a pair of clock signals CK and CKB at the rising / falling edges of the clock signal CK.

[0110] like Figure 14As shown, the controller 1800 and memory device 1900 of the memory system 1000 may include corresponding transceivers (XCVRs) 1820 and 1920, respectively. Specifically, the memory device 1900 may include a DLL 1930 for generating DQS signals and a window detection circuit 1932. See reference... Figures 1 to 12 The memory device 1900 can perform DLL operations to quickly convert an unlocked state caused by power noise into a relocked state.

[0111] The memory device according to an example embodiment of the present invention can be applied to automotive systems.

[0112] Figure 15 This is a figure illustrating an electronic system 3000 for a vehicle according to an exemplary embodiment of the present invention. (Refer to...) Figure 15 The electronic system 3000 may include at least one electronic control unit (ECU) 3100, a memory device 3200, a dynamic range sensor (DVS) 3300, a display device (or display) 3400 and / or a communication processor 3500.

[0113] The electronic control unit (ECU) 3100 can be implemented to control overall operation. The ECU 3100 can process image data received from the DVS 3300. The ECU 3100 may include a neural processor (NPU). The NPU can quickly derive the optimal image for driving by comparing the images received from the DVS 3300 with a learned model.

[0114] The memory device 3200 can be implemented to store a learning model related to the operation of the NPU. The memory device 3200 can include a volatile memory device or a non-volatile memory device. For example, the memory device 3200 can be DRAM or PRAM. Specifically, the memory device 3200 can be implemented as described in reference... Figures 1 to 13 The description refers to the execution of DLL operations.

[0115] The DVS 3300 can be implemented to sense the external environment of a vehicle. The DVS 3300 can output event signals in response to changes in relative light intensity. The DVS 3300 may include a pixel array comprising multiple DVS pixels and multiple address event handlers.

[0116] The display device 3400 can be configured to display images processed by the ECU 3100 or images transmitted by the communication processor 3500.

[0117] The communication processor 3500 can be configured to send processed images to an external device (e.g., an external vehicle) or receive images from an external vehicle. For example, the communication processor 3500 can be configured to perform wired or wireless communication with an external device.

[0118] The memory device according to an example embodiment of the present invention can be applied to a data center.

[0119] Figure 16 This is a diagram illustrating a data center using an example embodiment of a memory device based on the concept of the present invention. (Refer to...) Figure 16 Data center 7000 can be a facility that collects various types of data and provides services, and can be referred to as a data storage center. Data center 7000 can be a system for operating search engines and databases, and can be a computing system used by a company (such as a bank) or government agency. Data center 7000 can include application servers 7100 to 7100n and storage servers 7200 to 7200m. The number of application servers 7100 to 7100n and the number of storage servers 7200 to 7200m can be selected differently according to example embodiments, and the number of application servers 7100 to 7100n can differ from the number of storage servers 7200 to 7200m.

[0120] Application server 7100 or storage server 7200 may include at least one of processors 7110 and 7210 and memories 7120 and 7220. When storage server 7200 is described by way of example, processor 7210 may control the overall operation of storage server 7200 and may access memory 7220 to execute commands or data loaded in memory 7220. Memory 7220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVMDIMM). According to the example embodiment, the number of processors 7210 and the number of memories 7220 included in storage server 7200 may be selected differently.

[0121] In an example embodiment, processor 7210 and memory 7220 may provide a processor-memory pair. In an example embodiment, the number of processors 7210 may differ from the number of memories 7220. Processor 7210 may include a single-core processor or a multi-core processor. The description of storage server 7200 can be similarly applied to application server 7100. According to an example embodiment, application server 7100 may not include storage device 7150. Storage server 7200 may include at least one storage device 7250. Storage device 7250 may be implemented as follows: Figures 1 to 15 The implementation clock locking described herein is used to control dynamic delays in power-noise environments.

[0122] Application servers 7100 to 7100n and storage servers 7200 to 7200m can communicate with each other via network 7300 through NICs 7140, NIC 7140n, NIC 7240, and NIC 7240m. Network 7300 can be implemented using Fibre Channel (FC), Ethernet, etc. In some example embodiments, FC can be a medium for relatively high-speed data transmission and can use optical switches that provide high performance / high availability. Depending on the access method of network 7300, storage servers 7200 to 7200m can be configured as file storage devices, block storage devices, or object storage devices.

[0123] In example embodiments, network 7300 may be a storage-only network (such as a storage area network (SAN)). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a TCP / IP network and according to the SCSI protocol via TCP / IP or the Internet SCSI (iSCSI) protocol. In other example embodiments, network 7300 may be a general-purpose network (such as a TCP / IP network). For example, network 7300 may be implemented according to protocols such as the FC (FCoE) protocol via Ethernet, the Network Connected Storage (NAS) protocol, the NVMe (NVMe-oF) protocol via a network, etc.

[0124] The following description will focus on application server 7100 and storage server 7200. The description of application server 7100 can be applied to other application servers 7100n, and the description of storage server 7200 can be applied to other storage servers 7200m.

[0125] Application server 7100 can store data requested by users or clients in one of storage servers 7200 to 7200m via network 7300. Furthermore, application server 7100 can retrieve data requested by users or clients from one of storage servers 7200 to 7200m via network 7300. For example, application server 7100 can be implemented as a web server, a database management system (DBMS), etc.

[0126] Application server 7100 can access memory 7120n or storage device 7150n included in other application servers 7100n via network 7300, or it can access memory 7220 to 7220m or storage device 7250 to 7250m included in storage servers 7200 to 7200m via network 7300. Therefore, application server 7100 can perform various operations on data stored in application servers 7100 to 7100n or storage servers 7200 to 7200m. For example, application server 7100 can execute commands for moving or copying data between application servers 7100 to 7100n or storage servers 7200 to 7200m. In some example embodiments, data can be moved from storage devices 7250 to 7250m of storage servers 7200 to 7200m to storage devices 7220 to 7220m of application servers 7100 to 7100n via storage devices 7220 to 7220m of storage servers 7200 to 7200m, or directly from storage devices 7250 to 7250m of storage servers 7200 to 7200m to storage devices 7120 to 7120n of application servers 7100 to 7100n. For security or privacy, data moved via network 7300 can be encrypted.

[0127] Referring to the storage server 7200 as an example, the interface (NIC) 7254 can provide a physical connection between the processor 7210 and the controller (CTRL) 7251, and a physical connection between the NIC 7240 and the controller 7251. For example, the interface 7254 can be implemented using a direct-attached storage (DAS) method, in which the storage device 7250 is directly connected via a dedicated cable. Furthermore, the interface 7254 can be implemented using various interface methods such as: Advanced Technology Attachment (ATA) interface, Serial ATA (SATA) interface, external SATA (e-SATA) interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI) interface, PCIe interface, NVM Fast (NVMe) interface, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, Universal Flash Memory (UFS) interface, Embedded Universal Flash Memory (eUFS) interface, Compact Flash Memory (CF) card interface, etc.

[0128] Storage server 7200 may also include switch 7230 and NIC 7240. Switch 7230 may selectively connect processor 7210 and storage device 7250, or selectively connect NIC 7240 and storage device 7250. Similarly, storage server 7200m and application servers 7100 to 7100n may also include switches 7230m and 7130 to 7130n, respectively.

[0129] In an example embodiment, NIC 7240 may include a network interface card, network adapter, etc. NIC 7240 can connect to network 7300 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 7240 may include internal memory, DSP, host bus interface, etc., and can connect to processor 7210, switch 7230, etc., via the host bus interface. The host bus interface can be implemented as one of the examples of interface 7254 described above. In an example embodiment, NIC 7240 can be integrated with at least one of processor 7210, switch 7230, and storage device 7250.

[0130] In storage servers 7200 to 7200m or application servers 7100 to 7100n, the processor can send commands to storage devices 7150 to 7150n and 7250 to 7250m or memories 7120 to 7120n and 7220 to 7220m to program or read data. In some example embodiments, the data may be data that has been corrected by an error-correcting code (ECC) engine. The data may be data that has been processed by Data Bus Inversion (DBI) or Data Masking (DM) and may include Cyclic Redundancy Check (CRC) information. For security or privacy, the data may be encrypted.

[0131] Storage devices 7150 to 7150n and 7250 to 7250m can send control signals and command / address signals to NAND flash memory devices 7252 to 7252m in response to a read command received from the processor. Therefore, when data is read from NAND flash memory devices 7252 to 7252m, a read enable (RE) signal can be input as a data output control signal and can be used to output data to the DQ bus. The RE signal can be used to generate a data strobe signal (DQS). Command and address signals can be latched in page buffers based on the rising or falling edge of the write enable (WE) signal.

[0132] Controller 7251 can control the operation of storage device 7250 as a whole. In an example embodiment, controller 7251 may include static random access memory (SRAM). Controller 7251 can write data to NAND flash memory device 7252 in response to a write command, or read data from NAND flash memory device 7252 in response to a read command. For example, write or read commands may be provided from processor 7210 of storage server 7200, processor 7210m of another storage server 7200m, or processors 7110 and 7110n of application servers 7100 and 7100n. DRAM 7253 can temporarily store (buffer) data to be written to NAND flash memory device 7252, or can temporarily store (buffer) data read from NAND flash memory device 7252. In addition, DRAM 7253 can store metadata. In some example embodiments, metadata may be user data, or it may be data generated by controller 7251 to manage NAND flash memory device 7252. Storage device 7250 may include a security element (SE) for security or privacy. Similarly, DRAM 7253m, controller 7251m, and NIC 7254m in storage server 7200m may be similar to DRAM 7253, controller 7251, and NIC 7254 in storage server 7200.

[0133] One or more of the elements disclosed above may include or be implemented as one or more processing circuits (such as hardware including logic circuits), hardware / software combinations (such as processors executing software), or combinations thereof. For example, more specifically, the processing circuits may include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers, field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0134] The above description of the inventive concept is merely a specific example for implementing the inventive concept. The inventive concept includes not only the specific and practically usable device itself, but also technical ideas that can serve as abstract and conceptual thoughts that can be used as future technologies.

[0135] The memory device and clock locking method of the present invention, according to an exemplary embodiment, can monitor changes in clock offset caused by power noise and can dynamically control the delay line based on the monitoring results to perform clock locking operations more quickly.

[0136] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: The first delay line is configured to delay the reference clock according to the first code value in order to output the first delayed clock; The second delay line is configured to delay the first delay clock according to the second code value in order to output the second delay clock; The first delay line controller is configured to generate a first code value based on a first phase difference, or to generate a first code value based on a second phase difference. The second delay line controller is configured to generate a second code value based on the second phase difference. The demultiplexer is configured to output a second phase difference value to one of the first delay line controller and the second delay line controller in response to a monitoring detection signal corresponding to the clock offset between the reference clock and the feedback clock. The first phase detector is configured to detect a first phase difference between the reference clock and the feedback clock. The second phase detector is configured to detect the second phase difference between the reference clock and the feedback clock. The clock path is configured to receive a second delayed clock and to generate an internal clock. The output buffer is configured to synchronize with the internal clock to output a data strobe signal; The clock path copy is configured to have a delay equal to the delay of the second delayed clock and the delay of the clock path. as well as The output buffer copy is configured to generate a feedback clock by a delay equal to the delay of the clock output from the clock path copy and the delay of the output buffer.

2. The memory device according to claim 1, wherein, The first phase detector and the second phase detector are activated complementaryly to each other.

3. The memory device of claim 1, further comprising a delay-locked loop controller configured to generate a first activation signal for activating a first phase detector and a second activation signal for activating a second phase detector.

4. The memory device according to claim 1, wherein, During the initial locking period, a coarse locking operation is performed by activating the first phase detector, and a fine locking operation is performed by activating the second phase detector after the coarse locking operation.

5. The memory device according to claim 4, wherein, After the fine-lock operation is performed, the second phase detector remains active.

6. The memory device according to any one of claims 1 to 5, further comprising a window detection circuit configured to detect a clock offset between a reference clock and a feedback clock to generate a monitoring detection signal.

7. The memory device according to claim 6, wherein, The window detection circuit is activated in response to an internal voltage stabilization signal.

8. The memory device according to claim 6, wherein, The window detection circuit includes: The clock skew monitor is configured to generate a phase detection signal corresponding to the clock skew between the reference clock and the feedback clock. A clock synchronization circuit is configured to synchronize the phase detection signal with an internal clock to generate a synchronized phase detection signal; and The monitoring and detection signal generator is configured to generate a monitoring and detection signal in response to a synchronized phase detection signal.

9. The memory device according to claim 8, wherein, The clock offset monitor is activated in response to an internal voltage stabilization signal.

10. The memory device according to claim 8, wherein, The clock skew monitor is forcibly deactivated via the test mode register group.

11. A clock locking method for a memory device, comprising: An initial locking operation is performed in the delay-locked loop circuit before the internal voltage is stabilized; After the internal voltage is stabilized, a window detection circuit is used to monitor the clock offset between the reference clock and the feedback clock. as well as A relocking operation is performed in the delay-locked loop circuit using dynamic delay control corresponding to the clock offset monitored by the window detection circuit.

12. The clock locking method according to claim 11, wherein, The steps for performing the initial locking operation include: The first coarse locking operation is performed by delaying the reference clock via the first delay line; and The first fine-lock operation is performed by delaying the clock signal via the second delay line by the clock signal delayed by the first delay line.

13. The clock locking method according to claim 12, further comprising: After performing the first coarse locking operation, the first phase detector is deactivated; as well as After performing the first fine-locking operation, the second phase detector remains active.

14. The clock locking method according to any one of claims 11 to 13, further comprising: When the internal voltage is stabilized, the internal voltage stabilization signal is received in the delay-locked loop circuit.

15. The clock locking method according to claim 14, wherein, The steps to perform a relock operation include: After receiving the internal voltage stabilization signal, a monitoring and detection signal corresponding to the clock offset is received in the delay-locked loop circuit; and In response to the monitoring detection signal, a second coarse locking operation is performed by delaying the reference clock via a first delay line.

16. A memory device, comprising: A memory cell array having multiple memory cells, with multiple word lines and multiple bit lines intersecting at the multiple memory cells; The line decoder is configured to select a word line from the plurality of word lines in response to a line address; The bit line detection amplifier circuit is configured to detect and amplify data from a memory cell connected to a selected bit line among the plurality of bit lines during a read operation. The column decoder is configured to select the selected bit line from the plurality of bit lines in response to a column address. The data input / output device is configured to receive data from the bit line detection amplifier circuit during a read operation and to output the received data to an external device in response to a data strobe signal synchronized with the internal clock. The delay-locked loop circuit is configured to receive a reference clock and generate an internal clock. as well as The window detection circuit is configured to generate a monitoring and detection signal corresponding to the clock offset between the reference clock and the feedback clock. The delay-locked loop circuit includes: The first delay line is configured to delay the reference clock according to the first code value in order to output the first delayed clock; The second delay line is configured to delay the first delay clock according to the second code value in order to output the second delay clock; The first delay line controller is configured to generate a first code value based on a first phase difference, or to generate a first code value based on a second phase difference. The second delay line controller is configured to generate a second code value based on the second phase difference. The demultiplexer is configured to output a second phase difference value to one of the first delay line controller and the second delay line controller in response to a monitoring detection signal; The first phase detector is configured to detect a first phase difference between the reference clock and the feedback clock. The second phase detector is configured to detect the second phase difference between the reference clock and the feedback clock. The clock path copy is configured to: delay the second delayed clock by the amount of the clock path delay; and The output buffer copy is configured to delay the clock output from the clock path copy by the amount of delay of the output buffer to generate a feedback clock.

17. The memory device of claim 16, further comprising a delay-locked loop controller configured to: generate a first activation signal activating a first phase detector and generate a second activation signal activating a second phase detector.

18. The memory device according to claim 16, wherein, The window detection circuit is activated in response to an internal voltage stabilization signal.

19. The memory device according to any one of claims 16 to 18, wherein, The delay-locked loop circuit is configured to perform dynamic delay control in response to a monitoring detection signal.

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