Integrated components

Abstract

Some embodiments include an integrated component having a memory stack above a substrate and having an array of memory cells along the memory stack. The array includes rows extending along a row direction and columns extending along a column direction. The word lines are along the rows and the digital lines are along the columns. The control circuit system is along the substrate and includes a word line driver circuit system coupled to the word lines. The control circuit system is subdivided into memory bodies. The memory bodies are elongated along the row direction. Each memory body is subdivided into a series of segments, which are arranged in segment rows extending along the row direction. Each segment includes a series of patches, which include input / output circuit systems. The patches are arranged in groups, and the groups share portions of the word line driver circuit system.

Description

Technical Field

[0001] A memory array (eg, a DRAM array) is an integrated assembly comprising vertically stacked layers. Background Art

[0002] Memory is used in modern computing architectures to store data. One type of memory is dynamic random access memory (DRAM). DRAM can offer advantages of simplicity, low cost, and high speed over alternative types of memory.

[0003] A memory cell having one capacitor combined with one transistor (so-called 1T-1C memory cell) can be utilized, where the capacitor is coupled to the source / drain region of the transistor. FIG. 1 shows an exemplary 1T-1C memory cell 2, with the transistor labeled T and the capacitor labeled C. One node of the capacitor is coupled to the source / drain region of the transistor, and the other node is coupled to the common plate CP. The common plate can be coupled to any suitable voltage, such as a voltage in the range from greater than or equal to ground to less than or equal to VCC (i.e., ground ≤ CP ≤ VCC). In some applications, the voltage of the common plate is about half of VCC (i.e., about VCC / 2). The gate of the transistor is coupled to the word line WL (i.e., access line, routing line, first linear structure, etc.), and the source / drain region is coupled to the bit line BL (i.e., digital line, sense line, second linear structure, etc.). In operation, during read / write operations, the electric field generated by the voltage along the word line can gate-couple the bit line to the capacitor.

[0004] FIG2 shows another prior art 1T-1C memory cell configuration. The configuration of FIG2 shows two memory cells 2a and 2b, memory cell 2a includes a transistor T1 and a capacitor C1, and memory cell 2b includes a transistor T2 and a capacitor C2. Word lines WL0 and WL1 are electrically coupled to the gates of transistors T1 and T2, respectively. Memory cells 2a and 2b share a connection to a bit line BL.

[0005] The above-described memory cells may be incorporated into a memory array, and in some applications, the memory array may have an open bit line arrangement. FIG. 3 shows an exemplary integrated component 9 having an open bit line architecture. Component 9 includes two laterally adjacent memory arrays ("array 1" and "array 2"), each of which includes memory cells of the type described in FIG. 2 (not labeled in FIG. 3 to simplify the drawing). Word lines WL0 to WL7 extend across the arrays and are coupled to word line drivers. Digit lines D0 to D8 are associated with the first array (array 1), and digit lines D0* to D8* are associated with the second array (array 2). Sense amplifiers SA0 to SA8 are provided between the first array and the second array. Digit lines at the same height are paired with each other and compared by sense amplifiers (e.g., digit lines D0 and D0* are paired with each other and compared using sense amplifier SA0). In a read operation, one of the paired digit lines can be used as a reference to determine an electrical characteristic (e.g., voltage) of another of the paired digit lines.

[0006] FIG. 4 illustrates the general relationship of a memory array within an integrated arrangement. Specifically, FIG. 4 illustrates a block diagram of a prior art device 1000 that includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns and access lines 1004 (e.g., word lines WL0 to WLm for conducting signals) and first data lines 1006 (e.g., bit lines BL0 to BLn for conducting signals). The access lines 1004 and the first data lines 1006 may be used to transfer information to and from the memory cells 1003. The row decoder 1007 and the column decoder 1008 decode the address signals A0 to AX on the address lines 1009 to determine which memory cells 1003 are to be accessed. The sense amplifier circuit 1015 operates to determine the value of the information read from the memory cells 1003. The I / O circuit 1017 transfers the value of the information between the memory array 1002 and the input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O line 1005 may represent the value of information to be read from or written to memory cell 1003. Other devices may communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 is used to control memory operations to be performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 may receive power supply voltage signals Vcc and Vss on first power supply line 1030 and second power supply line 1032, respectively. Device 1000 includes selection circuit 1040 and input / output (I / O) circuit 1017. Selection circuit 1040 may respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013, which may represent the value of information to be read from or programmed into memory cell 1003. Column decoder 1008 may selectively activate CSEL1 through CSELn signals based on A0 through AX address signals on address lines 1009. Selection circuit 1040 may select signals on first and second data lines 1006 and 1013 to provide communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0007] It is desirable to develop new memory architectures. Summary of the invention

[0008] In one aspect, the present application provides an integrated component, comprising: a memory stack above a substrate; an array of memory cells along the memory stack; the array comprising rows extending along a row direction and columns extending along a column direction; word lines extending along the rows of the array and along the row direction; digit lines extending along the columns of the array and along the column direction; each of the memory cells in the array is uniquely addressed by a combination of one of the word lines and one of the digit lines; a control circuit system along the substrate; the control circuit system includes a word line driver circuit system coupled to the word lines; the control circuit system is subdivided into memory bodies; the memory bodies are physically elongated along the row direction; each of the memory bodies is subdivided into a series of segments, the segments are arranged in segment rows extending along the row direction; and each of the segments includes a series of patches, the patches containing input / output circuit systems; the patches are arranged into groups, the groups share parts of the word line driver circuit system; the part of the word line driver circuit system within each group includes a first segment along one of the patches in the group and includes a second segment along an adjacent patch in the group, the first segment and the second segment are offset from each other along both the row direction and the column direction.

[0009] In another aspect, the present application provides an integrated component, which includes: a memory stack above a substrate; an array of memory cells along the memory stack; the array includes rows extending along a row direction and includes columns extending along a column direction; word lines extending along the rows of the memory array and along the row direction; digit lines extending along the columns of the memory array and along the column direction; each of the memory cells in the memory array is uniquely addressed by a combination of one of the word lines and one of the digit lines; a control circuit system along the substrate; the control circuit system includes a word line driver circuit system coupled to the word line; the control circuit system is subdivided into memory banks; the memory banks are physically elongated along the row direction; the substrate corresponds to A semiconductor die; the die has a first side extending along the row direction and a second side opposite to the first side; the die is subdivided into four quadrant areas; two of the quadrant areas are separated from each other along the first side and by a socket area; the two of the quadrant areas are a first quadrant area and a second quadrant area; the first quadrant area and the second quadrant area each include 8 memory cells; each of the memory cells is subdivided into a series of segments, which are arranged in segment rows extending along the row direction; each of the memory cells includes more than one of the segment rows; each of the segments includes a series of patches, which include input / output circuit systems; and wherein the patches are arranged in groups, which share part of the word line driver circuit system.

[0010] In another aspect, the present application provides an integrated component, which includes: a first memory stack above a substrate; a second memory stack above the first memory stack; a first group of memory cell arrays along the first memory stack; the first group includes a first row extending along a row direction and includes a first column extending along a column direction; a second group of memory cell arrays along the first memory stack; the second group includes a second row extending along the row direction and includes a second column extending along the column direction; a first word line extending along the first row and along the row direction; a second word line extending along the second row and along the row direction; a control circuit system along the substrate; the control circuit system includes a first word line driver subcircuit system coupled to the first word line and a second word line driver subcircuit system coupled to the second word line; the control circuit system is subdivided into memory bodies; the memory bodies are physically elongated along the row direction; each of the memory bodies is subdivided into a series of segments, and the segments are arranged in a segment row extending along the row direction; each of the segments includes a series of first patches, the first patches are connected to the memory bodies, and the second patches are connected to the memory bodies. A patch includes a first input / output circuit system; the first patches are arranged into a first group, the first group sharing a portion of the first word line driver subcircuit system; the portion of the first word line driver subcircuit system within each first group includes a first segment along one of the first patches of the first group and a second segment along an adjacent first patch of the first group, the first segment and the second segment being offset from each other along the row direction and the column direction; each of the segments includes a series of second patches, the second patches including a second input / output circuit system; the second patches are arranged into a second group, the second group sharing a portion of the second word line driver subcircuit system; the portion of the second word line driver subcircuit system within each second group includes a third segment along one of the second patches of the second group and a fourth segment along an adjacent second patch of the second group, the third segment and the fourth segment being offset from each other along the row direction and the column direction; and wherein the third segment and the fourth segment are shifted relative to the first segment and the second segment along the row direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 is a schematic diagram of a prior art memory cell having 1 transistor and 1 capacitor.

[0012] 2 is a schematic diagram of a pair of prior art memory cells, each having 1 transistor and 1 capacitor and sharing a bit line connection.

[0013] FIG. 3 is a schematic diagram of a prior art integrated component having an open bitline architecture.

[0014] FIG4 shows a block diagram of a prior art arrangement including a memory array.

[0015] Figure 5 is a schematic diagram of an exemplary integrated assembly having multiple stacks of layers that are vertically displaced relative to each other.

[0016] Figure 6 is a schematic plan view of an exemplary arrangement of exemplary regions across a semiconductor substrate.

[0017] Figure 7 is a schematic plan view of an exemplary arrangement of exemplary memory banks within an area of ​​a semiconductor substrate.

[0018] Figure 8 is a schematic plan view schematically illustrating an example arrangement of tiles within an example section of circuitry.

[0019] Fig. 9 is a schematic plan view schematically illustrating an exemplary arrangement of patches including circuits associated with upper and lower stackups of the exemplary arrangement.

[0020] Fig.10 is a schematic plan view schematically illustrating an exemplary arrangement of exemplary sections of an integrated circuit relative to an exemplary area including redundant circuitry.

[0021] Fig.11 is a schematic plan view of an exemplary arrangement of circuitry and a pair of exemplary memory banks within an area of ​​a semiconductor substrate.

[0022] Fig.11A yes Fig.11 Schematic side view of a portion of an exemplary arrangement. DETAILED DESCRIPTION

[0023] Some embodiments include an integrated assembly having a memory stack above a substrate and having control circuitry along the substrate. The control circuitry may include word line driver circuits and may be subdivided into banks. The banks may be subdivided into a series of segments, and the segments may be subdivided into a series of tiles. The tiles may include input / output circuitry. Reference Figures 5 to 11 Exemplary embodiments are described.

[0024] refer to Figure 5 , integrated component 10 includes substrate 12, first stack 14 on substrate, and second stack 16 on first stack. Structures 12, 14, and 16 are stacked vertically on each other. Substrate 12, first stack 14, and second stack 16 can be considered as examples of levels (layers) stacked on each other. The levels can be in different semiconductor dies, or at least two of the levels can be in the same semiconductor die.

[0025] The first stack 14 and the second stack 16 have memory areas 18 and 22, respectively. The first memory array and the second memory array (array 1 and array 2) are supported by the first stack 14 and the second stack 16, wherein each memory array has a first portion along the first (lower) stack 14 and a second portion along the second (upper) stack 16. The first memory array includes first memory cells 20a, and the second memory array includes second memory cells 20b. The memory cells are schematically shown as circles. The first memory array and the second memory array may include any suitable number of memory cells, and in some embodiments may include hundreds, thousands, millions, etc. of memory cells. The memory cells may be DRAM cells, and in some embodiments may be configured in an arrangement of the type described above with reference to prior art Figures 1 to 3 (i.e., array 1 and array 2 may be DRAM arrays). For simplicity Figure 5 , array 1 and array 2 are shown as being separated from each other. In some embodiments, an area of ​​array 1 may overlap laterally with an area of ​​array 2.

[0026] In some embodiments, the first stack 14 and the second stack 16 may be referred to as a first memory stack and a second memory stack, respectively.

[0027] Substrate 12 may include semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. Substrate 12 may be referred to as a semiconductor substrate. The term "semiconductive substrate" means any construction including semiconductor material, including but not limited to bulk semiconductive material such as a semiconductive wafer (alone or in an assembly including other materials) and a layer of semiconductive material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, substrate 12 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like. Each stack 14 and 16 may also include semiconductor material.

[0028] In the illustrated embodiment, substrate 12 includes sense amplifier circuitry (SA) and word line driver circuitry (WD).

[0029] The sense amplifier circuit system includes an area 26 labeled "SA-E" to identify it as being associated with the "even" portion of the circuit, and an area 28 labeled "SA-O" to identify it as being associated with the "odd" portion of the circuit. The terms "even" and "odd" are arbitrary and are used to distinguish different sense amplifier systems from each other. The configuration shown has sense amplifier circuit systems SA-O and SA-E that are paired with each other and distributed as structures (blocks) 24. The sense amplifier circuit systems SA-E and SA-O can be referred to as first sense amplifier circuit systems and second sense amplifier circuit systems, respectively. In some embodiments, the sense amplifier circuit system SA-E can be considered to correspond to a first group of sense amplifier circuit systems, while the sense amplifier circuit system SA-O can be considered to correspond to a second group of sense amplifier circuit systems; and vice versa.

[0030] The word line driver circuitry (i.e., row driver circuitry) includes an area labeled SWD-L (area 31) and an area SWD-U (area 33). The acronym SWD stands for sub-word line driver, and is used to emphasize that the components SWD-L and SWD-U are part of a common word line driver circuitry. The word line driver circuitry SWD-L is utilized during operation of the memory cells associated with the lower stack 14, and the word line driver circuitry SWD-U is utilized during operation of the memory cells associated with the upper stack 16.

[0031] The configuration shown has word line driver circuitry SWD-L and SWD-U paired with each other and distributed as a structure (block) 30 .

[0032] Blocks 24 and 30 may be considered to form a patchwork area. Together, the patchwork areas may be considered to form a patchwork arrangement of circuit subunits along substrate 12.

[0033] First digit lines D0, D1, and D2 are associated with a first memory array (array 1). The first digit lines D0, D1, and D2 extend along columns of the first memory array (array 1) and are coupled to first memory cells 20a of the first memory array. In some embodiments, the first digit lines may be considered to extend along a column direction associated with the first memory array. The bit lines D0, D1, and D2 are laterally spaced apart from one another and may represent a large number of substantially identical bit lines extending across the first memory array. The term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. The first digit lines alternate between even first digit lines and odd first digit lines, where digit lines D0 and D2 represent even first digit lines, and digit line D1 represents odd first digit lines. The even first digit lines (e.g., D0) are coupled to the first sense amplifier circuit system 26 (i.e., SA-E), and the odd first digit lines (e.g., D1) are coupled to the second sense amplifier circuit system 28 (i.e., SA-O). The first digit lines D0 , D1 , and D2 have a first portion along the first stack 14 , and have a second portion along the second stack 16 .

[0034] The second digit lines D0*, D1*, and D2* are associated with the second memory array (array 2). The second digit lines D0*, D1*, and D2* extend along the columns of the second memory array and are coupled to the second memory cells 20b of the second memory array (array 2). In some embodiments, the second digit lines can be considered to extend along the column direction associated with the second memory array. The bit lines D0*, D1*, and D2* are spaced laterally from each other and can represent a large number of substantially identical bit lines extending across the second memory array. The second digit lines alternate between even second digit lines and odd second digit lines, where the digit lines D0* and D2* represent even second digit lines, and the digit line D1* represents an odd second digit line. The even second digit lines (e.g., D0*) are coupled to the first sense amplifier circuit system 26 (i.e., SA-E), and the odd second digit lines (e.g., D1*) are coupled to the second sense amplifier circuit system 28 (SA-O). The second digit lines D0 *, D1 *, and D2 * have a first portion along the first stack 14 , and have a second portion along the second stack 16 .

[0035] Even first digit lines D0 and D2 are equally coupled to even second digit lines D0* and D2* through first sense amplifier circuitry 26 (SA-E); and odd first digit line D1 is equally coupled to odd second digit line D1* through second sense amplifier circuitry 28 (SA-O). For purposes of understanding the present disclosure and the claims that follow, a first digit line is “equally coupled” to a second digit line through sense amplifier circuitry if the sense amplifier circuitry is configured to compare electrical characteristics (e.g., voltages) of the first and second digit lines to one another.

[0036] Two digit lines coupled relative to each other by a sense amplifier circuit system can be considered to include a true digit line and a complementary digit line. For example, digit lines D0 and D0* can be considered to be a true digit line and a complementary digit line, respectively; and similarly, digit lines D1 and D1* can be considered to be a true digit line and a complementary digit line, respectively. The terms "real" and "complementary" are arbitrary. During read / write operations of the memory cells (e.g., 20a, 20b) associated with the set, the electrical values ​​of the true and complementary digit lines of this set are utilized together. For the purpose of describing the embodiments herein, the true digit lines will be those without an asterisk indication in the label (e.g., D0, D1, D2, etc.), and the complementary digit lines will be those with an asterisk indication in the label (e.g., D0*, D1*, D2*, etc.).

[0037] Still reference Figure 5 , word lines 32 extend along rows of the first memory array and the second memory array (array 1 and array 2). The digit lines can be considered to extend along the row direction associated with the memory array. In some embodiments, the memory cells 20a and 20b along the first memory stack 14 can be considered together as a first group of memory cells within a first array (arrangement) along the first memory stack, and the word lines 32 along the first memory stack 14 can be considered to extend along a first row associated with such a first array (arrangement). Similarly, the memory cells 20a and 20b along the second memory stack 16 can be considered together as a second group of memory cells within a second array (arrangement) along the second memory stack, and the word lines 32 along the second memory stack 16 can be considered to extend along a second row associated with such a first array (arrangement).

[0038] Each first memory cell (20a and 20b) is uniquely addressed by one of the digit lines (eg, D0) and one of the word lines (32).

[0039] Figure 5An advantage of the configuration is that all of the sense amplifier circuitry and all of the word line driver circuitry are located directly beneath the memory arrays (array 1 and array 2), which can enable dense packing of the memory array across the semiconductor substrate; or in other words, this can save valuable semiconductor substrate real estate compared to conventional configurations in which at least some of the sense amplifier circuitry and / or at least some of the word line driver circuitry are not located directly beneath the memory array. Vertical stacking of areas of the memory arrays (array 1 and array 2) can further save valuable semiconductor substrate real estate. Figure 5 In the illustrated embodiment, the digit lines D0, D0*, D1, D1*, D2 and D2* are all vertically shifted relative to the first sense amplifier circuit system SA-E and the second sense amplifier circuit system SA-0, and are vertically shifted relative to the word line driver circuit systems SWD-U and SWD-L.

[0040] The circuitry along substrate 12 may be referred to as control circuitry, and in the illustrated embodiment includes sense amplifier circuitry and word line driver circuitry. The word line driver circuitry is shown as being subdivided into a first word line driver sub-circuitry SWD-L and a second word line driver sub-circuitry SWD-U. The first word line driver sub-circuitry SWD-L may be considered to be coupled to a first word line (i.e., word line 32 along lower stack 14), and the second word line driver sub-circuitry SWD-U may be considered to be coupled to a second word line (i.e., word line 32 along upper stack 16).

[0041] Although the embodiments described herein indicate two memory stacks (14, 16) above the substrate 12, it should be understood that in other embodiments there may be more than two memory stacks above the substrate or only a single memory stack above the substrate.

[0042] refer to Figure 6 , the substrate 12 can be considered to be subdivided into four quadrant regions 34a-d. The quadrant regions are identified as Quadrant 1, Quadrant 2, Quadrant 3, and Quadrant 4.

[0043] A system of axes is disposed adjacent to the substrate 12 as shown to indicate row and column directions that would be aligned with axes disposed above the substrate (e.g., along which the Figure 5 The memory stacks 14 and 16 are arranged in association with the memory array.

[0044] In some embodiments, substrate 12 may correspond to a semiconductor die (e.g., a die comprising monocrystalline silicon). The die has a first side 35 extending in a row direction and has a second side 37 in an opposing relationship to the first side. Quadrant regions 34a and 34b are along first side 35 and are separated from each other by an intermediate socket region 36a. Such a socket region is shown as including "bank logic". The bank logic circuitry may include, for example, a row decoder circuitry.

[0045] Quadrant regions 34a and 34b may be referred to as first and second quadrant regions, respectively. The first and second quadrant regions each include eight banks, each bank being understood to correspond to a region associated with a memory that is accessed independently relative to memory associated with other banks in the bank.

[0046] Quadrant regions 34c and 34d may be referred to as the third and fourth quadrant regions, respectively. In the illustrated embodiment, the third and fourth quadrant regions also each include eight memory banks, and are separated from one another by a socket region 36b, which is indicated as including "memory bank logic." In other embodiments, a memory bank may be associated with one or more of quadrant regions 34a-d, but may not be associated with all quadrant regions.

[0047] An exemplary configuration of a memory bank is described with reference to quadrant region 34a. A memory bank is subdivided into sections 38. The lowest memory bank within quadrant 34a is shown to include eight of the sections 38 (labeled SEC-0, SEC-1 ... SEC-7). Such sections can be considered to be arranged in section rows 40, which extend in a row direction. Sections 38 are also each indicated to extend in a row direction.

[0048] The uppermost bank within quadrant region 34a is shown as including three of segment rows 40. In some embodiments, each bank may be considered to include multiple segment rows, Figure 6 An exemplary application is shown in which each memory bank includes three sector rows. The sectors 38 can be considered to be associated with blocks of memory, with the length of each sector corresponding to approximately one page. A page can be, for example, 8.5K bytes (i.e., 8704 bytes). The terms "page", "segment", "chunk", and "memory bank" can be understood to have conventional meanings relative to memory storage applications.

[0049] Figure 6 The uppermost memory bank of quadrant region 34a is shown separated from the next memory bank by a socket region 42. Socket region 42 may include a bus (eg, reference bus) for coupling local input / output circuitry to global input / output circuitry. Fig.11Socket region 42 may also include, for example, connections to row decoder circuitry, column decoder circuitry, etc. Region 42 may be referred to as the global throat. In some applications, "throat" may be understood as an area (location, place) of control circuitry, and "socket" may be understood as a means for feeding signals through a hierarchy to circuitry above or below the hierarchy (e.g., through Figure 5 The level 14 feeds the signal to the Figure 5 For the purpose of understanding the present disclosure and the claims that follow, the term "socket" should be understood as being generic to both the socket and the throat, unless expressly stated otherwise.

[0050] Figure 6 The upper regions 34a and 34b of the embodiment of FIG. 4 are separated from the lower two regions 34c and 34d by a central socket region 44. The central socket region may contain, for example, a bus for global input / output circuitry.

[0051] Figure 7 The memory banks within quadrant region 34a are shown in more detail. Specifically, Figure 7 Quadrant region 34 a is shown to include eight banks (bank 0 . . . bank 7 ), each bank including three of segment rows 40 , and each segment row 40 including eight of segments 38 .

[0052] refer to Figure 8 , the segment 38 is schematically shown as containing 17 tiles 45 or 34 tiles 47. Each tile includes an input / output (I / O) circuit system. Each tile includes a subset of the page within the segment 38. If the page includes approximately 8.5K bytes, and if there are 17 tiles 45, each tile 45 will include a number of bytes corresponding to approximately 8.5K / 17 (e.g., approximately 0.5K bytes). Alternatively, if the page includes 8.5K bytes, and if there are 34 tiles 47, each tile 47 will include a number of bytes corresponding to approximately 8.5K / 34 (e.g., approximately 0.25K bytes).

[0053] It should be noted that Figure 8 The upper configuration (17 patch configuration) is an exemplary arrangement of patches within an exemplary segment 38, while Figure 8 The lower configuration (34 patch configuration) is another exemplary configuration of patches within the exemplary section 38. As will be appreciated by those of ordinary skill in the art, Figure 8 The upper configuration (17 patch configuration) and Figure 8The example arrangements shown in the lower configuration (34-patch configuration) are just two of many possible arrangements. Other arrangements may be utilized in other embodiments.

[0054] In some aspects, the I / O circuitry along the page may be considered to be subdivided into discrete subunits, and each "patch" may be considered to correspond to a respective discrete subunit of the I / O circuitry. The I / O circuitry of some of the patches includes coupling to word line driver circuitry (such coupling is shown in hatched areas such as areas 48a, 48b, 52a, and 52b), and some or all of the I / O circuitry in the patches may include sense amplifier circuitry (not shown). The sense amplifier circuitry may include any suitable configuration, including conventional configurations and / or other configurations now known or to be developed. Figure 5 The schematic illustration of generally refers to word line driver circuitry disposed along substrate 12 in an arrangement including block 30 including SWD-L (31) and SWD-U (33). Figure 8 The patch may be considered a more specific illustration of an exemplary arrangement of word line driver circuitry along substrate 12, Fig. 9 Areas of SWD-U circuitry (circuitry associated with word lines along the upper stack 16) and SWD-L circuitry (circuitry associated with word lines along the lower stack 14) are shown (discussed below).

[0055] Still refer to Figure 8 , the tiles 45 of the 17-tile configuration are arranged in groups 46a-c. Group 46a contains two of the tiles 45, group 46b contains four of the tiles 45, and group 46c contains three of the tiles 45 out of the 17 tiles within the segment 38, and contains an additional tile 45c from another segment adjacent to the segment 38 shown. Group 46c will be shared between the segment 38 shown and another segment adjacent to the segment shown (the other segment containing the tile 45c).

[0056] Word lines 32 (only some of which are labeled) are schematically shown extending across tiles 45, with each group 46a-c comprising a pair of word lines. To simplify the drawings, digit lines relative to the tiles are not shown. The embodiments described herein are primarily directed to word line connections and circuitry, and unless otherwise noted, digit lines can be understood to include conventional configurations.

[0057] Each of the groups 46a-c includes portions of word line driver circuitry, such portions being labeled as segments 48a and 48b. Segments 48a and 48b may be referred to as first segments and second segments, respectively. The word line driver circuitry may be Figure 5The SWD-L circuit system 31 or the SWD-U circuit system 33.

[0058] The groups 46a-c share portions of the word line driver circuitry (e.g., segments 48a and 48b). Segments 48a and 48b are schematically shown coupled to word lines 32 extending across the groups. In the illustrated embodiment, groups 46b and 46c include a patch 45a having segment 48b, and include an adjacent patch 45b having segment 48a. The first segment 48a and the second segment 48b are offset from each other in both the row direction and the column direction.

[0059] Edge patch 45d contains segment 48a, and adjacent segment 48b is laterally offset from edge patch 45d. Such segment 48b may be referred to as an isolated segment, and will be laterally outside of the leftmost segment 38 within the memory bank. Similarly, isolated segment 48a (not shown) may be laterally outside of the farthest right segment 38 within the memory bank. Thus, each memory bank may include two isolated segments along each segment row 40. This is an improvement over conventional configurations, in which memory banks typically extend in the column direction rather than the row direction (and segments extend in the column direction rather than the row direction), and there are typically more than two isolated segments arranged along each column of segments.

[0060] Figure 8 Also shown are tiles 47 of a 34-tile configuration arranged in groups 50a and 50b. Group 50a contains ten of the tiles 47, and group 50b contains four of the tiles 47 out of the 34 tiles within segment 38, and contains an additional tile 47c from another segment adjacent to the segment 38 shown. Group 50b will be shared between the segment 38 shown and another segment adjacent to the segment shown.

[0061] Word lines 32 (only some of which are labeled) are schematically shown extending across tiles 47, with each set 50a and 50b comprising a pair of word lines. To simplify the drawing, the digit lines relative to the tiles are not shown.

[0062] Groups 50a and 50b each contain portions of word line driver circuitry, such portions being labeled as segments 52a and 52b. Segments 52a and 52b may be referred to as first segments and second segments, respectively. The word line driver circuitry may be Figure 5 The SWD-L circuit system or SWD-U circuit system.

[0063] The groups 50a and 50b share portions of the word line driver circuitry (e.g., segments 52a and 52b). The segments 52a and 52b are schematically shown coupled to the word line 32 extending across the groups. In the illustrated embodiment, the groups 50a and 50b include a patch 47a having a segment 52b, and include an adjacent patch 47b having a segment 52b. The first segment 52a and the second segment 52b are offset from each other in both the row direction and the column direction.

[0064] Figure 8 can be considered to show that Figure 5 The memory stack 14 and 16 of the memory stack 14 and 16 are associated with a patch (input / output circuit system). Fig. 9 As shown, additional patches (input / output circuitry) may be provided to be associated with another in the memory stack. Specifically, Fig. 9 shows the arrangement in the above reference Figure 8 The first series of patches 47 within the groups 50a and 50b are depicted and are shown with respect to the upper stack ( Figure 5 and showing a second series of patches 51 arranged within groups 54a, 54b and 54c, and showing the lower stack ( Figure 5 Such a group is associated with the word line 32 of the stack 14).

[0065] A dashed box 57 is provided to schematically illustrate the 34 tiles contained within the exemplary sections 38 a and 38 b including the tiles 47 and 51 .

[0066] Along Figure 5 The word line driver circuitry of substrate 12 of the embodiment of the present invention can be considered to be divided into a first word line driver sub-circuitry 33 (SWD-U circuitry) and a second word line driver sub-circuitry 31 (SWD-L circuitry). Segments 52a and 52b of groups 50a and 50b can be considered to be associated with the first word line driver sub-circuitry 33 (SWD-U) and, therefore, coupled to the word lines 32 of the upper stack 16. Groups 54a-c are shown to include similar segments 56a and 56b, which can be considered to be associated with the second word line driver sub-circuitry 31 (SWD-L) and, therefore, coupled to the word lines 32 of the lower stack 14.

[0067] The patch 47 of the first group 50a and 50b can be referred to as the first patch, and the patch 51 of the second group 54a-c can be referred to as the second patch. Segments 52a and 52b can be referred to as the first segment and the second segment, and segments 56a and 56b can be referred to as the third segment and the fourth segment. In the illustrated embodiment, the third segment 56a and the fourth segment 56b are shifted relative to the first segment 52a and the second segment 52b along the row direction. In the illustrated embodiment, the third segment 56a and the fourth segment 56b are shifted relative to the first segment 52a and the second segment 52b by a distance corresponding to about half the size of one of the 10-patch groups 50 and 52 (i.e., a distance corresponding to a distance across about 5 of the patches).

[0068] It should be noted that Fig. 9 The group 54a comprises an isolated segment 56a laterally outward from the left side of the segment 38b and comprises only five of the patches 51. It should also be noted that Fig. 9 The group 54c will be shared with another segment adjacent to the segment 38b shown and contain the patch 51a from the adjacent segment.

[0069] although Fig. 9 An application utilizing 10-tile groups 50 and 52 is shown (i.e., an application in which each segment 38a and 38b includes 34 tiles), but it should be understood that a similar application (i.e., an application in which each segment 38a and 38b includes 17 tiles) may include Figure 8 A four-patch group 46 may be included, or may include any other suitable arrangement of patch groups.

[0070] Figure 8 and 9 The shared groups (ie, groups 46c, 50b, and 54c) may be used to provide redundant circuitry. Fig.10 An exemplary region of an exemplary bank of memory is schematically shown. The bank row includes banks 38a-d, which are labeled bank 0, bank 1, bank 2, and bank 3, respectively. Banks 38a and 38b share a set of tiles (e.g., Figure 8 and 9 50b), and similarly, segments 38c and 38d share a set of tiles within overlap region 58b. A gap 60 is provided between segments 38b and 38c to indicate that there is no shared group between these segments. In other embodiments, there may be a shared group between segments 38b and 38c.

[0071] The sharing groups within overlapping regions 58a and 58b may be incorporated into redundancy within one or more of the segments that include overlapping regions 58a and 58b. Specifically, it is common practice during the manufacture of integrated circuit systems to include redundant circuitry that can be utilized in the event of a failure during the manufacture of a region of the integrated circuit system. In some embodiments, it may be convenient to incorporate redundant circuitry into overlapping regions (e.g., 58a and / or 58b). Such redundant circuitry may be utilized to compensate for errors that may occur in each of the segments that include overlapping circuitry (e.g., in either of the segments labeled as segment 0 and segment 1 that include overlapping circuitry 58a).

[0072] Figure 6 and 7 The advantage of the memory bank configuration is that this can make the connection between the socket area and the section of the memory bank shorter. Generally, it is easier to make a short connection than a long connection, which can make it cheaper and less error-prone to form a short connection.

[0073] Fig.11 A pair of banks (bank 0 and bank 1) are shown adjacent to each other (i.e., adjacent to each other) along the column direction. The banks share a socket area 42. Each bank includes three segment rows (40a-c for bank 0 and 40d-f for bank 1), each of which includes eight of the segments 38 (only some of which are shown and only some of which are labeled).

[0074] The bus (multiplexer) 62 extends along the socket area 42. The global input / output lines (global I / O interconnects) 64 (only some of which are labeled) extend along the column direction and extend from the bus 62 within the shared socket 42 to the local buses (multiplexers) 66 (only some of which are labeled) adjacent to the segment 38. The global input / output lines 64 within the upper memory bank (memory bank 0) can be referred to as the first group (first series) of global input / output lines, while the global input / output lines 64 within the lower memory bank (memory bank 1) can be referred to as the second group (second series) of global input / output lines. Similarly, the local buses 66 within the upper memory bank (memory bank 0) can be referred to as the first group (first series) of local buses, while the local buses 66 within the lower memory bank (memory bank 1) can be referred to as the second group (second series) of local buses.

[0075] The bus 62 may extend in the row direction along the full length of the memory bank, or may be subdivided into a plurality of segments, each segment extending in the row direction along only a portion of the full length of the memory bank.

[0076] The global input / output line 64 can be shorter than similar lines of conventional configurations. In some embodiments, the length of the global input / output line 64 can be less than Figure 6 Less than one quarter of the width of the tube core 12 (the width is the distance between the edge 35 and the edge 37), less than one eighth of the width of such a tube core 12, less than one sixteenth of the width of such a tube core 12, and so on.

[0077] In the illustrated embodiment, local bus 66 is arranged in the row direction (ie, Fig.11 The horizontal direction of the input / output line 64 extends in a substantially perpendicular direction and thus extends substantially orthogonally relative to the global input / output line 64. The term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances.

[0078] Local input / output lines (local I / O interconnects) 68 (only some of which are labeled) extend from local bus 66 to segments 38, and specifically to the patches within such segments (e.g., Figure 8 and 9 ). Fig.11 In the top view of FIG. 3 , local input / output lines 68 are shown as dashed lines to indicate that they may be underneath various components, materials, etc. The local input / output lines 68 within the upper memory bank (memory bank 0) may be referred to as a first group (first series) of local input / output lines, while the local input / output lines 68 within the lower memory bank (memory bank 1) may be referred to as a second group (second series) of local input / output lines. Although only one local input / output line 68 is shown as being associated with each segment 38, it should be understood that in other embodiments, there may be more than one local input / output line 68 associated with each segment.

[0079] In some embodiments, global input / output lines 64 may have an area above one or more of segments 38, while local input / output lines 68 may have an area below portions of segments 38. For example, Fig.11A Schematically shows the Fig.11 38 and shows an exemplary embodiment in which global input / output lines 64 extend over segments 38 and local input / output lines 68 extend under portions of segments 38. Local input / output lines 68 may feed into individual patches (e.g., Figure 8 and 9 The patch shown in FIG. 1 is associated with a socket to access a segment of the word line driver circuitry (eg, Figure 8 and 9 In some embodiments, local input / output lines (local I / O interconnects) 68 and global input / output lines (global I / O interconnects) 64 together connect segments of word line driver circuitry within a tile (e.g., Figure 8 and 9 Segments 48, 52, and 56 of FIG. 4 are coupled to control circuitry (e.g., row decoder circuitry similar to circuitry 1007 of FIG. 4).

[0080] Fig.11A The bus bars 62 and 66 include a conductive material. The conductive material may include any suitable conductive component; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing components (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0081] Fig.11A An insulating material 70 is shown adjacent to the conductive material of bus bars 62 and 66. Such insulating material may comprise any suitable composition; and in some embodiments, may comprise, consist essentially of, or consist of silicon dioxide.

[0082] Any suitable configuration may be used to logically address the above tiles in a segment. For example, in some applications, along a segment (e.g., Figure 6 The edge patches on each side of the segment 38) can be logically merged with each other along the segment row (e.g., Figure 6 The edge patches on each side of the segment row 40) can be logically merged with each other, etc.

[0083] In some applications, a global input / output (GIO) may include segments having a size extending along a digit line direction (i.e., a column direction). Conventional GIOs are configured to extend along a die (e.g., Figure 6 The embodiments described herein may have a GIO that is arranged to include segments extending 1 / 6 to 1 / 8 of the length of the die along the digit line direction (column direction). In some embodiments, the segments of the GIO may be considered to extend less than or equal to about 1 / 3 of the length of the die along the column direction, less than or equal to about 1 / 6 of the length of the die along the column direction, less than or equal to about 1 / 8 of the length of the die along the column direction, etc. Moreover, the GIO signal may have full-rail operation, meaning that the GIO signal swings from Vdd to ground. In contrast, the input / output (IO) of a conventional design includes GIO and GIOF as a pair of differential signals with only about 150mV to 200mV separation. The advantage of a full-rail GIO is that this can be buffered with a simple buffer, while the differential signal of a conventional design needs to be amplified by a sense amplifier circuit (e.g., a DSA circuit, where DSA stands for direct SA) in order to enter the full rail before being sent to the next stage.

[0084] The components and structures discussed above may be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a variety of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting devices, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0085] Unless otherwise stated, the various materials, substances, components, etc. described herein may be formed by any suitable method, now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0086] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In this disclosure, the terms are considered synonymous. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may provide language changes in the disclosure to simplify the premise basis in the following claims and is not intended to indicate any significant chemical or electrical differences.

[0087] The terms "electrically connected" and "electrically coupled" may both be utilized in this disclosure. The terms are considered synonymous. The use of one term in some cases and the other in other cases may provide language variation in this disclosure to simplify the premise basis in the following claims. The terms "couple, coupling, coupled, etc." may refer to an electrical connection.

[0088] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the claims below are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0089] Unless otherwise indicated, the cross-sectional views of the drawings only show features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0090] When a structure is referred to as being "on," "adjacent to," or "abutting against" another structure, it can be directly on the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent to," or "directly abutting against" another structure, there are no intervening structures present. The terms "directly below," "directly over," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0091] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may extend substantially orthogonally relative to an upper surface of the base, or may extend non-orthogonally.

[0092] Some embodiments include an integrated component having a memory stack above a substrate and an array of memory cells along the memory stack. The array includes rows extending along a row direction and columns extending along a column direction. Word lines extend along the rows of the array and along the row direction. Digit lines extend along the columns of the array and along the column direction. Each memory cell in the array is uniquely addressed by a combination of one of the word lines and one of the digit lines. The control circuit system is along the substrate and includes a word line driver circuit system coupled to the word line. The control circuit system is subdivided into memory bodies. The memory body is physically elongated along the row direction. Each memory body is subdivided into a series of segments, which are arranged in a segment row extending along the row direction. Each segment includes a series of patches, which include input / output circuit systems. The patches are arranged in groups, and the groups share portions of the word line driver circuit system. The portion of the word line driver circuit within each group includes a first segment along one of the patches of the group and a second segment along an adjacent patch of the group, and the first segment and the second segment are offset from each other along both the row direction and the column direction.

[0093] Some embodiments include an integrated component comprising a memory stack above a substrate. An array of memory cells is along the memory stack. The array includes rows extending along a row direction and includes columns extending along a column direction. Word lines are along the rows of the array and extend along the row direction. Digit lines are along the columns of the array and extend along the column direction. Each memory cell in the array is uniquely addressed by a combination of one of the word lines and one of the digit lines. A control circuit system is along the substrate. The control circuit system includes a word line driver circuit system coupled to the word line. The control circuit system is subdivided into memory bodies. The memory bodies are physically elongated along the row direction. The substrate corresponds to a semiconductor die. The die has a first side extending along the row direction and has a second side in a relative relationship to the first side. The die is subdivided into four quadrant regions. Two of the quadrant regions are spaced apart from each other along the first side and by a socket region. The two of the quadrant regions are a first quadrant region and a second quadrant region. The first quadrant region and the second quadrant region each include 8 memory bodies. Each memory bank is subdivided into a series of segments arranged in segment rows extending along a row direction. Each memory bank includes more than one of the segment rows. Each segment includes a series of tiles containing input / output circuitry. The tiles are arranged in groups that share portions of the wordline driver circuitry.

[0094] Some embodiments include an integrated component comprising a first memory stack above a substrate. A second memory stack is above the first memory stack. A first group of memory cell arrays is along the first memory stack. The first group includes a first row extending along a row direction and includes a first column extending along a column direction. A second group of memory cell arrays is along the second memory stack. The second group includes a second row extending along a row direction and includes a second column extending along a column direction. A first word line extends along the first row and along the row direction. A second word line extends along the second row and along the row direction. A control circuit system is along the substrate. The control circuit system includes a first word line driver subcircuit system coupled to the first word line and a second word line driver subcircuit system coupled to the second word line. The control circuit system is subdivided into memory banks; the memory banks are physically elongated along the row direction. Each memory bank is subdivided into a series of segments arranged in a row of segments extending along the row direction. Each segment includes a series of first patches, the first patches including a first input / output circuit system. The first patches are arranged into a first group, the first group sharing a portion of the first word line driver subcircuit system. The portion of the first word line driver subcircuit system within each first group includes a first segment along one of the first patches of the first group and a second segment along an adjacent first patch of the first group, the first segment and the second segment being offset from each other along the row direction and the column direction. Each segment includes a series of second patches, the second patches including a second input / output circuit system. The second patches are arranged into a second group, the second groups sharing a portion of the second word line driver subcircuit system. The portion of the second word line driver subcircuit system within each second group includes a third segment along one of the second patches of the second group and a fourth segment along an adjacent second patch of the second group, the third segment and the fourth segment being offset from each other along the row direction and the column direction. The third segment and the fourth segment are shifted relative to the first segment and the second segment along the row direction.

[0095] In accordance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, since the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims should be given the full scope in a literal sense and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated component comprising: a memory stack above the substrate; an array of memory cells along the memory stack; The array includes rows extending along a row direction and columns extending along a column direction; word lines extending along the rows of the array and in the row direction; digit lines extending along the columns of the array and in the column direction; Each of said memory cells in said array is uniquely addressed by a combination of one of said word lines and one of said digit lines; control circuitry along the substrate; the control circuitry including word line driver circuitry coupled to the word lines; the control circuitry being subdivided into memory banks; the memory banks being physically elongated along the row direction; Each of the memory banks is subdivided into a series of sectors, the sectors being arranged in sector rows extending along the row direction; and Each of said sections comprises a series of patches containing input / output circuitry; The patches are arranged into groups that share portions of the word line driver circuit system; the portion of the word line driver circuit system within each group includes a first segment along one of the patches of the group and a second segment along an adjacent patch of the group, the first segment and the second segment being offset from each other along both the row direction and the column direction.

2. An integrated assembly according to claim 1, comprising 8 of said segments within each of said memory banks.

3. The integrated assembly of claim 1 comprising 17 of said patches within each of said sections, and wherein each of said groups contains four of said patches.

4. The integrated assembly of claim 1 comprising 34 of said patches within each of said sections, and wherein each of said groups contains 10 of said patches.

5. The integrated component of claim 1, wherein an edge of a first one of the segments shares one or more patches within a group with an adjacent second one of the segments.

6. The integrated component of claim 5, wherein at least one of the one or more patches is incorporated into redundant circuitry of one or both of the first and second of the segments.

7. The integrated component of claim 1, wherein the control circuitry includes sense amplifier circuitry coupled to the digit line.

8. The integrated component of claim 1 , comprising two of the memory stacks above the substrate; wherein the word line driver circuitry is divided into a first word line driver subcircuitry and a second word line driver subcircuitry, the first word line driver subcircuitry being coupled to the word lines of one of the memory stacks and the second word line driver subcircuitry being coupled to the word lines of the other of the memory stacks.

9. The integrated assembly of claim 1, comprising: two or more of said sector rows within each said memory bank; a pair of the memory banks adjacent to each other along the column direction and spaced apart from each other by a shared socket region; as well as A global input / output bus within the shared socket area.

10. The integrated component of claim 9, wherein the global input / output bus extends the full length of the memory bank along the row direction.

11. The integrated component of claim 9, wherein the global input / output bus is subdivided into two or more segments, each segment extending along the row direction by a length that is less than a full length of the memory bank.

12. The integrated assembly of claim 1, comprising: three of said sector rows within each of said memory banks; a pair of the memory banks adjacent to each other along the column direction and spaced apart from each other by a shared socket region; a first series of first global input / output lines extending in the column direction and extending from the shared socket region to a first set of local buses adjacent to the segment of one of the memory banks of the pair of the memory banks; as well as A second series of second global input / output lines extends along the column direction and from the shared socket region to a second set of local buses adjacent to the segment of the other of the memory banks in the pair of the memory banks.

13. An integrated component according to claim 12, comprising a first local input / output line, which extends from the first group of local buses to the segment of the one of the memory bodies; and a second local input / output line, which extends from the second group of local buses to the segment of the other of the memory bodies.

14. The integrated assembly of claim 1, wherein edge tiles of respective sections are logically merged with each other.

15. The integrated assembly of claim 1, wherein edge tiles of respective segment rows are logically merged with each other.

16. The integrated component of claim 1, wherein the substrate corresponds to a semiconductor die; the integrated component includes a GIO coupled to the input / output circuitry; and wherein the GIO includes one or more segments extending less than 1 / 3 of the length of the die.

17. The integrated assembly of claim 16, wherein the one or more segments extend less than 1 / 6 of the length of the die.

18. The integrated assembly of claim 16, wherein the one or more segments extend less than 1 / 8 of the length of the die.

19. The integrated component of claim 16, wherein signals along the GIO have full rail operation.

20. An integrated assembly comprising: a memory stack above the substrate; an array of memory cells along the memory stack; The array comprises rows extending along a row direction and comprises columns extending along a column direction; word lines extending along the rows of the memory array and in the row direction; digit lines extending along the columns of the memory array and in the column direction; Each of said memory cells in said memory array is uniquely addressed by a combination of one of said word lines and one of said digit lines; control circuitry along the substrate; the control circuitry including word line driver circuitry coupled to the word lines; the control circuitry being subdivided into memory banks; the memory banks being physically elongated along the row direction; The substrate corresponds to a semiconductor die; the die has a first side extending along the row direction and a second side in an opposite relationship to the first side; The die is subdivided into four quadrant regions; Two of the quadrant regions are spaced apart from each other along the first side and by a socket region; the two of the quadrant regions are a first quadrant region and a second quadrant region; the first quadrant region and the second quadrant region each include 8 memory banks; each of the memory banks is subdivided into a series of segments, the segments being arranged in segment rows extending along the row direction; each of the memory banks includes more than one of the segment rows; each of the segments includes a series of patches, the patches containing input / output circuitry; and Wherein the tiles are arranged into groups, the groups sharing portions of the word line driver circuitry.

21. The integrated component of claim 20, wherein the first quadrant region and the second quadrant region are separated from each other by an intermediate region containing memory bank logic circuitry.

22. The integrated component of claim 21 wherein the bank logic circuitry includes row decoder circuitry.

23. The integrated assembly of claim 20, comprising eight of said segments within each of said memory banks.

24. The integrated assembly of claim 23 comprising 17 of said patches within each of said sections, and wherein each of said groups contains four of said patches.

25. The integrated assembly of claim 23, comprising 34 of said patches within each of said sections, and wherein each of said groups contains 10 of said patches.

26. The integrated component of claim 20, wherein an edge of a first one of the segments within one of the memory banks shares one or more tiles within a group with an adjacent second one of the segments within the one of the memory banks.

27. The integrated component of claim 26, wherein at least one of the one or more patches is incorporated into redundant circuitry of one or both of the first and second of the segments.

28. The integrated component of claim 20 , comprising two of the memory stacks above the substrate; wherein the word line driver circuitry is divided into a first word line driver subcircuitry and a second word line driver subcircuitry, the first word line driver subcircuitry being coupled to word lines of one of the memory stacks and the second word line driver subcircuitry being coupled to word lines of another of the memory stacks.

29. An integrated component according to claim 20, comprising another two of the quadrant regions along the second side; the other two of the quadrant regions are a third quadrant region and a fourth quadrant region; the third quadrant region and the fourth quadrant region each include 8 storage bodies, each of the storage bodies in the third quadrant region and the fourth quadrant region include segments arranged in a segment row extending along the row direction; and each of the segments in the third quadrant region and the fourth quadrant region include a series of patches, which contain input / output circuit systems.

30. The integrated assembly of claim 20, comprising: a pair of the memory banks adjacent to each other along the column direction and spaced apart from each other by a shared socket region; a first series of first global input / output lines extending in the column direction and extending from the shared socket region to a first set of local buses adjacent to the segment of one of the memory banks of the pair of the memory banks; as well as A second series of second global input / output lines extends along the column direction and from the shared socket region to a second set of local buses adjacent to the segment of the other of the memory banks in the pair of the memory banks.

31. The integrated component of claim 30, wherein the first series of first global input / output lines and the second series of second global input / output lines have areas over one or more of the segments of the one of the memory banks and the other of the memory banks.

32. An integrated assembly comprising: a first memory stack over the substrate; a second memory stack above the first memory stack; a first set of memory cell arrays along the first memory stack; The first group includes a first row extending along a row direction and includes a first column extending along a column direction; a second group of memory cell arrays along the first memory stack; the second group comprising a second row extending along the row direction and comprising a second column extending along the column direction; a first word line extending along the first row and along the row direction; a second word line extending along the second row and along the row direction; control circuitry along said substrate; The control circuitry includes a first wordline driver subcircuitry coupled to the first wordline and a second wordline driver subcircuitry coupled to the second wordline; The control circuit system is subdivided into memory banks; the memory banks are physically elongated along the row direction; Each of the memory banks is subdivided into a series of segments, the segments being arranged in segment rows extending along the row direction; Each of the sections includes a series of first patches, the first patches containing first input / output circuitry; The first tiles are arranged into first groups, the first groups sharing a portion of the first word line driver subcircuitry; the portion of the first word line driver subcircuitry within each first group comprises a first segment along one of the first tiles of the first group and comprises a second segment along an adjacent first tile of the first group, the first segment and the second segment being offset from each other along the row direction and the column direction; Each of said sections includes a series of second patches, said second patches containing second input / output circuitry; the second patches are arranged into second groups, the second groups sharing a portion of the second word line driver subcircuitry; the portion of the second word line driver subcircuitry within each second group comprises a third segment along one of the second patches of the second group and comprises a fourth segment along an adjacent second patch of the second group, the third segment and the fourth segment being offset from each other along the row direction and the column direction; and Wherein the third segment and the fourth segment are displaced relative to the first segment and the second segment along the row direction.

33. An integrated assembly according to claim 32, comprising 8 of said segments within each of said memory banks.

34. The integrated assembly of claim 32, comprising 17 of the first patches within each of the segments, and wherein each of the first groups contains four of the first patches.

35. The integrated assembly of claim 34, comprising 17 of said second patches within each of said sections, and wherein each of said second groups contains four of said second patches.

36. The integrated assembly of claim 32, comprising 34 of said first patches within each of said sections, and wherein each of said first groups contains 10 of said first patches.

37. The integrated assembly of claim 36, comprising 34 of said second patches within each of said sections, and wherein each of said second groups contains 10 of said second patches.

38. The integrated component of claim 32, wherein an edge of a first one of the segments shares one or more first patches within a first group with an adjacent second one of the segments.

39. The integrated component of claim 38, wherein at least one of the one or more first patches is incorporated into redundant circuitry of one or both of the first and second in the segment.

40. The integrated assembly of claim 32, wherein the third and fourth segments are displaced relative to the first and second segments along the row direction by a distance half of one of the groups.

41. The integrated assembly of claim 32, comprising: three of said sector rows within each of said memory banks; a pair of the memory banks adjacent to each other along the column direction and spaced apart from each other by a shared socket region; a first series of first global input / output lines extending in said column direction and extending from said shared socket region to a first set of local buses along said segment of one of said memory banks of said pair of said memory banks; as well as A second series of second global input / output lines extends along the column direction and from the shared socket region to a second set of local buses along the segment of the other of the pair of the memory banks.

42. The integrated component of claim 41, wherein the local buses of the first group and the second group extend along the row direction.

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