Display device

Abstract

According to various embodiments, a display device includes a display panel comprising a non-display area and a display area. The display area includes: a semiconductor layer formed on a substrate; a gate insulating film formed on the semiconductor layer; a gate conductive layer located on the gate insulating film; an interlayer insulating film located on the gate conductive layer; and a data conductive layer located on the interlayer insulating film. The non-display area includes: a pad portion; and an inorganic film removal portion, wherein at least one inorganic film is removed, and an electrically floating conductive pattern is formed in the inorganic film removal portion.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically, to display devices capable of confirming whether microcracks have occurred. Background Technology

[0002] Starting with structures using glass substrates that cannot be bent, various flexible display devices using plastic substrates have gradually been developed. Furthermore, while existing display devices have rectangular structures, currently developed and mass-produced display devices feature chamfered corners or bent or deformed areas, resulting in a variety of shapes. Summary of the Invention

[0003] The embodiments are used to detect microcracks generated in a display device and prevent the microcracks from propagating to the wiring.

[0004] The display device involved in the embodiment includes a display panel comprising a non-display area and a display area. The display area includes: a semiconductor layer formed on a substrate; a gate insulating film formed on the semiconductor layer; a gate conductive layer located on the gate insulating film; an interlayer insulating film located on the gate conductive layer; and a data conductive layer located on the interlayer insulating film. The non-display area includes: a pad portion; and an inorganic film removal portion, wherein at least one inorganic film is removed, and an electrically floating conductive pattern is formed in the inorganic film removal portion.

[0005] Alternatively, the inorganic film removal section may remove the inorganic film that is connected to and located on the signal line that is located in the display area and has a crack-resistant structure.

[0006] Alternatively, the signal line may be located in the gate conductive layer, the inorganic film removal section may remove the interlayer insulating film, and the conductive pattern may be located in the gate conductive layer.

[0007] Alternatively, the inorganic film removal section may remove the inorganic film adjacent to the signal line located in the display area and subject to cracking.

[0008] Alternatively, the signal line may be located in the gate conductive layer, and the inorganic film removal section may remove the electrode insulating film and the interlayer insulating film.

[0009] Alternatively, the conductive pattern may be formed by a metal layer that is closer to the substrate than the semiconductor layer.

[0010] Alternatively, the outer side of the inorganic membrane removal section may include a dam region having at least one dam, wherein the conductive pattern extends in a direction parallel to one side of the dam region.

[0011] Alternatively, the conductive pattern may be located at the corner portion of the display panel.

[0012] Alternatively, an intermediate region containing an unremoved inorganic film may be formed in the inorganic film removal section, and an additional metallic pattern may be formed in the intermediate region.

[0013] Alternatively, the conductive pattern may be covered by an organic film.

[0014] The display device involved in the embodiment includes: a display panel having flexible characteristics and including a main body portion having a display area and a connecting portion protruding from the main body portion; an integrated circuit chip attached to the connecting portion; a dam region formed along the outline of the display panel and including at least one dam; an inorganic film removal portion located inside the dam region and removing an inorganic film; and a conductive pattern located within the inorganic film removal portion and electrofloted.

[0015] Alternatively, the display device may further include: a wiring area, including signal lines connecting the integrated circuit chip and the display area.

[0016] Alternatively, the inorganic film removal section may remove the inorganic film that is connected to and located on the signal line that is in contact with the signal line located in the wiring area and is subject to cracking.

[0017] Alternatively, the signal line may be located in the gate conductive layer, the inorganic film removal section may remove the interlayer insulating film covering the signal line, and the conductive pattern may be located in the gate conductive layer.

[0018] Alternatively, the inorganic film removal section may remove the inorganic film adjacent to the signal line located above and below the wiring area and subject to cracking.

[0019] Alternatively, the inorganic film removal section may remove the gate insulating film located below the signal line and the interlayer insulating film located above the signal line.

[0020] Alternatively, the conductor pattern may be formed by a metal layer that is closer to the substrate than the semiconductor layer located below the gate insulating film.

[0021] Alternatively, the outer side of the inorganic membrane removal section may include a dam region having at least one dam, wherein the conductive pattern extends in a direction parallel to one side of the dam region.

[0022] Alternatively, an intermediate region containing an unremoved inorganic film may be formed in the inorganic film removal section, and an additional metallic pattern may be formed in the intermediate region.

[0023] Alternatively, the conductive pattern may be covered by an organic film.

[0024] (Invention Effects)

[0025] According to various embodiments, an inorganic film removal section is formed in a non-display area where the inorganic film is removed, and a metal pattern is formed in the inorganic film removal section, so that even though it is an inorganic film removal section, it is possible to detect the propagation of microcracks toward the display area side.

[0026] When inspecting for cracks, a camera is used to check for the presence of cracks. However, it may not be possible to observe fine cracks at the 1-2 μm level well with a camera. Therefore, fine cracks can be easily detected by forming a conductive pattern from the metal.

[0027] Furthermore, by collecting these test results, it is possible to confirm whether cracks have occurred in any process, and the generation of microcracks can be prevented by changing the corresponding process. Attached Figure Description

[0028] Figure 1 This is a schematic plan view of a display device according to one embodiment.

[0029] Figure 2 This is a perspective view of the rear of a display device according to an embodiment.

[0030] Figure 3 This is a plan view of a display device according to an embodiment before it is bent.

[0031] Figure 4 It is shown in magnification Figure 3 The diagram shows the connection part.

[0032] Figure 5 It is shown in magnification Figure 4 The diagram of the L region.

[0033] Figure 6 It is along Figure 5 A sectional view taken along line VI-VI.

[0034] Figure 7 This is an enlarged view of the L region in another embodiment.

[0035] Figure 8 This is a diagram illustrating a portion that may generate microcracks according to another embodiment.

[0036] Figure 9 This is an enlarged view of a corner portion of a display panel according to another embodiment.

[0037] Figure 10 This is an enlarged view of a portion of the outline of the connecting part according to another embodiment.

[0038] Figure 11 This is a circuit diagram of a pixel PX of a display panel according to one embodiment.

[0039] Figure 12This is a cross-sectional view of an organic light-emitting display panel according to one embodiment.

[0040] Figures 13 to 15 This is a cross-sectional view of the inorganic membrane removal section according to another embodiment.

[0041] Symbol explanation:

[0042] 1: Display device; 10: Display panel;

[0043] 11: Main body; 12: Connecting part;

[0044] 20: Printed circuit board; 25: Signal transmission unit;

[0045] 30: Integrated circuit chip; DA: Display area;

[0046] SLR: Wiring area; CSR: Inorganic membrane removal section;

[0047] DR: Dam Area; IPR: Intermediate Area;

[0048] CSP: CSP1, CSP2, CSP3: Conductive patterns;

[0049] CD, CD1, CD2, CD3, CD4, CD5: Crack propagation direction;

[0050] AP: Additional metallic pattern; SL: Signal line;

[0051] PS: Semiconductor layer; PX: Pixel;

[0052] 110: Substrate; 111: Barrier layer;

[0053] 112: Buffer layer; 126: Maintenance line;

[0054] 140, 141, 142: Gate insulating film; 151, 152, 154: Scan lines;

[0055] 153: Light emission control line; 155: Gate electrode;

[0056] 160: Interlayer insulating film; 131: Initialization voltage line;

[0057] 171: Data line; 172: Drive voltage line;

[0058] 180: Organic membrane; 190: Protective layer;

[0059] 195: Covering membrane; 62, 68: Openings. Detailed Implementation

[0060] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement them. The present invention can be implemented in various different forms and is not limited to the embodiments described herein.

[0061] To clearly illustrate the invention, irrelevant parts have been omitted, and the same or similar constituent elements have been given the same reference numerals throughout the specification.

[0062] Furthermore, the sizes and thicknesses of the components shown in the illustrations are arbitrary for ease of explanation, and the present invention is not necessarily limited to the illustrated cases. In the accompanying drawings, the thicknesses are exaggerated to clearly show each layer and region. Additionally, in the accompanying drawings, the thicknesses of some layers and regions are exaggerated for ease of explanation.

[0063] Furthermore, when a layer, membrane, region, plate, or other part is located on or above other parts, this includes not only the case where it is directly located on other parts, but also the case where other parts are interspersed between them. Conversely, when a part is directly located on other parts, it means that there are no other parts in between. In addition, being located on or above the part that serves as a reference means being located below or below the part that serves as a reference, and does not necessarily mean being located on or above in the direction of gravity.

[0064] Furthermore, when a certain component is included in a part of the specification, unless otherwise stated, it does not exclude the inclusion of other components, but rather means that other components may also be included.

[0065] Furthermore, throughout the instruction manual, "on a plane" refers to the view of the object from above, while "on a cross section" refers to the view of a vertically cut section of the object from the side.

[0066] Referring to the accompanying drawings, the display device involved in the embodiment is described using a light-emitting display device as an example.

[0067] Figure 1 This is a schematic plan view of a display device according to one embodiment. Figure 2 This is a perspective view of the rear of a display device according to an embodiment.

[0068] The display device 1 involved in this embodiment includes a display panel 10, which includes a display area DA having a plurality of pixels PX for displaying images and a non-display area NA surrounding the display area DA and not displaying images. For the display panel 10, the display area DA and the non-display area NA are formed on a substrate with flexible properties such as plastic or polyimide (PI).

[0069] Multiple pixels (PX) can be set in the display area DA, and a pixel PX can be divided into a light-emitting element (also called a light-emitting diode) and a pixel circuit section that supplies current to the light-emitting element.

[0070] Each pixel PX is connected to signal lines such as scan lines, data lines, and drive voltage lines. It is subjected to gate signals, data voltages, drive voltages, etc., so that the pixel circuit can transfer current to the light-emitting element and make the light-emitting element emit light.

[0071] The non-display area NA may extend and be configured with signal lines for transmitting various signals and voltages applied to multiple pixels PX, and according to an embodiment, a driving unit for generating signals applied to the pixels PX may also be provided. The driving unit may be formed by the same process as the pixels PX or may be formed by attaching a separate integrated circuit (IC) chip.

[0072] Specifically, the driving unit formed in the non-display area NA may include a data driver that applies data voltage to the data lines, a scan driver that applies scan signals to the scan lines, and a signal controller that controls the data driver and the scan driver. The scan driver may be integrated into the display panel 10 and may be located on the left and right sides or one side of the display area DA. The data driver and the signal controller are integrated circuit chips 30, which may be formed in the connection portion 12 at one end of the flexible printed circuit board 20 attached to the display panel 10, and the data driver and the signal controller may be bent to be located on the back side of the display panel 10. The integrated circuit chip 30 is the driving unit that receives signals applied from the outside, converts them into driving signals suitable for the pixel PX, and transmits them to the pixel PX.

[0073] Reference Figure 2 In the display device 1, a flexible printed circuit board 20 is attached to one end of the connection portion 12 of the display panel 10, which is connected to one end of the display panel 10 and bent toward the back of the display panel 10. The flexible printed circuit board 20 may also include a signal transmission portion 25 that protrudes and connects to external components and transmits external signals.

[0074] Double-sided adhesive (not shown) can be formed along the outline on the back of the display device 1, and the display device 1 can be attached to the frame (not shown) of the electronic device and fixed by the double-sided adhesive.

[0075] The following uses Figures 3 to 6 The structure of the connection portion 12 of the display panel 10 before it is bent is observed.

[0076] Figure 3 This is a plan view of a display device according to one embodiment before it is bent. Figure 4It is shown in magnification Figure 3 A diagram of the connection part. Figure 5 It is shown in magnification Figure 4 The graph of region L, and Figure 6 It shows along Figure 5 A sectional view taken along line VI-VI.

[0077] Reference Figure 3 The display panel 10 includes a main body 11 located on the front surface and a connection portion 12 protruding from the main body 11 and to which an integrated circuit chip 30 is attached. The connection portion 12 also includes a plurality of signal lines and a plurality of pads, and the plurality of pads have a structure for electrical connection with the flexible printed circuit board 20. The connection portion 12 is bent to the back side of the main body 11 and is therefore not visible from the front surface.

[0078] The main body 11 of the display panel 10 is provided with a display area DA including a plurality of pixels PX and a non-display area NA surrounding the display area DA and not displaying an image, and the non-display area NA also includes a connecting portion 12. Although the non-display area NA of the main body 11 is along the periphery of the display area DA, the connecting portion 12 is formed to protrude with a width smaller than the width of the main body 11.

[0079] Reference Figure 4 The connection portion 12 of the display panel 10 has multiple wirings and multiple pads connecting the multiple pixels PX to the integrated circuit chip 30. Furthermore, according to an embodiment, a touch sensor capable of sensing touch on the upper part of the display panel 10 may be formed. In this case, wiring connecting the integrated circuit chip 30 and the touch sensor may also be formed in the connection portion 12.

[0080] In addition, a plurality of pads located on the connection portion 12 are electrically connected to a plurality of pads on the flexible printed circuit board 20, and an anisotropic conductive film (ACF) is located between two pads to electrically connect the two pads.

[0081] On the outer side of the wiring formed in the connection portion 12, an inorganic film removal portion and a dam area are formed, the inorganic film of which has been removed, which will be shown by magnification. Figure 4 L region Figure 5 and Figure 6 We will conduct a detailed observation.

[0082] Reference Figure 5 At both ends of the connecting part 12, a dam area DR and an inorganic film removal part CSR are provided from the outside, thus having a structure that protects the wiring area SLR.

[0083] The wiring area SLR can be formed together with the pixel PX that forms the display area DA and the layer above the pixel PX (e.g., the encapsulation layer, etc.), so they can have the same layered structure.

[0084] The dam area DR is a structure formed by stacking inorganic and organic membranes. When an organic membrane is formed on the wiring area SLR, it not only prevents the organic matter constituting the organic membrane from leaking to the outside, but also protects the wiring area SLR from external impacts.

[0085] The layered structure of the dam region DR may include all the organic and inorganic films, excluding conductive or semiconductor layers, in the layered structures of the wiring region SLR and the display region DA. According to embodiments, the dam region DR can be formed while removing a portion of the organic or inorganic film. More than one dam may be located in the dam region DR, and multiple dams may also be formed.

[0086] An inorganic film removal section (CSR) is provided inside the dam region DR and outside the wiring region SLR, wherein at least a portion of the inorganic film has been removed from the layered structure of the dam region DR. The removed inorganic film may be a gate insulating film, an interlayer insulating film, a barrier layer, a buffer layer, etc. Here, the gate insulating film may be the first gate insulating film 141 and / or the second gate insulating film, described later.

[0087] To prevent cracks from propagating from the outside to the wiring area SLR, an inorganic film removal section CSR is formed based on the width of the dam area DR, or an inorganic film removal section CSR is formed with a width greater than or equal to the width of the dam area DR. Since it can be determined that the crack in the signal line propagating from the outside to the wiring area SLR has passed through an inorganic film rather than an organic film, a layered structure in which at least one inorganic film has been removed from the layered structure of the dam area DR can be provided.

[0088] If a crack occurs in the signal line of a specific conductive layer in the wiring area SLR, the inorganic film removal section CSR used to prevent cracking can be formed by removing the adjacent inorganic film of the corresponding conductive layer or removing the inorganic film located below the corresponding conductive layer. This structure of the inorganic film removal section CSR prevents the inorganic film that receives crack propagation from the outside from continuously forming to the corresponding conductive layer; therefore, the crack will not propagate to the wiring area SLR, and no breakage will occur in the corresponding conductive layer.

[0089] However, even with the presence of the inorganic film removal section (CSR), microcracks of 1–2 μm in size can still propagate to the wiring area's surface roughness (SLR). This is especially problematic in the current development landscape, where resolution is increasing and wiring widths are decreasing; even microcracks can cause defects such as wiring breaks. Therefore, it is necessary to confirm whether microcracks also propagate to the wiring area's SLR. However, current methods have the drawback of being unable to identify microcracks as small as 1–2 μm.

[0090] To eliminate this drawback, an additional conductive pattern CSP is further formed within the inorganic film removal section CSR. The conductive pattern CSP can be located in the same layer as the conductive layer where it is desired to monitor for the presence of microcracks, or in a layer lower than it. The conductive pattern CSP can be electrically floated and can have an island-shaped structure.

[0091] exist Figure 5 The direction of crack propagation, i.e., crack propagation direction CD, is shown. The crack propagates from the outer dam region DR to the wiring region SLR, and the crack propagates in a direction that intersects or is perpendicular to the extension direction of the inorganic film removal section CSR.

[0092] In addition, refer to Figure 5 In addition to the conductive pattern CSP, other additional metal patterns AP can be formed within the inorganic film removal section CSR. These additional metal patterns AP can be alignment marks.

[0093] The additional metal pattern AP can be located within the intermediate region IPR where the inorganic film has not been removed, within the inorganic film removal section CSR. That is, unlike the conductive pattern CSP which is not covered by an inorganic film, the additional metal pattern AP can be covered by at least one inorganic film. Furthermore, in order to form the inorganic film removal section CSR, a portion of the organic film is also removed along with the inorganic film, thereby removing a portion of the organic film on top of the conductive pattern CSP. However, a corresponding organic film is also formed on the additional metal pattern AP. The upper stacking relationship of the additional metal pattern AP corresponds to the stacking relationship of the dam region DR, where the upper stacking relationship of the conductive pattern CSP is such that no inorganic film is formed, and additionally, a portion of the organic film is also removed.

[0094] exist Figure 6 This allows for a more detailed observation of this layered relationship.

[0095] exist Figure 6 A layered relationship involving one embodiment is shown.

[0096] First, observe the layered relationship of the SLR in the wiring area.

[0097] The layered relationship of the wiring area SLR can be the same as that of the display area DA. A gate insulating film 140, which is an inorganic film, is provided on a flexible substrate 110 such as plastic or polyimide (PI). A signal line SL located on the gate conductive layer is included on the gate insulating film 140. An interlayer insulating film 160, which is an inorganic film, is provided on the signal line SL. An organic film 180 is formed on the interlayer insulating film 160. A protective layer 190, which is formed of organic material and covers the entire area, can be provided on the top of the organic film 180. Various organic or inorganic films can also be formed between the organic film 180 and the protective layer 190. For example, a pixel definition film that divides the light-emitting elements or an encapsulation layer that protects the light-emitting elements from moisture or air and includes organic and inorganic films can be formed. Here, the gate insulating film 140 may include a first gate insulating film 141 and / or a second gate insulating film 142, which will be described later. The gate conductive layer may include a first gate conductive layer and / or a second gate conductive layer, which will be described later.

[0098] The dam area DR can have the same layered structure as the wiring area SLR except for the conductive layer.

[0099] That is, a gate insulating film 140, which is an inorganic film, is disposed on a flexible substrate 110 such as plastic or polyimide (PI), an interlayer insulating film 160, which is an inorganic film, is disposed on the gate insulating film 140, an organic film 180 is formed on the interlayer insulating film 160, and a protective layer 190 is disposed on the organic film 180.

[0100] According to the embodiment, a pixel definition film or a portion of the encapsulation layer may also be provided between the organic film 180 and the protective layer 190.

[0101] The layered structure of the dam region DR can be the same as the layered structure of the intermediate region IPR located within the inorganic film removal section CSR. That is, in the intermediate region IPR, a gate insulating film 140, serving as an inorganic film, is provided on a flexible substrate 110 such as plastic or polyimide (PI), and an additional metal pattern AP is included on the gate insulating film 140. An interlayer insulating film 160, serving as an inorganic film, is provided on the additional metal pattern AP, an organic film 180 is formed on the interlayer insulating film 160, and a protective layer 190 is provided on the organic film 180.

[0102] The layered structure of the inorganic membrane removal section CSR has a structure in which the interlayer insulating film 160, which is an inorganic membrane, is removed, and also has a structure in which the organic membrane 180 located thereon is removed at the same time as the interlayer insulating film 160 is removed.

[0103] That is, a gate insulating film 140, which serves as an inorganic film, is disposed on a flexible substrate 110 such as plastic or polyimide (PI). A conductive pattern CSP is disposed on the gate insulating film 140, and a protective layer 190 is disposed on the conductive pattern CSP. The conductive pattern CSP is located in the gate conductive layer in the same manner as the signal line SL.

[0104] like Figure 6 As shown, a conductive pattern CSP is formed on the same layer as the signal line SL in the wiring area SLR where it is to be confirmed whether a microcrack has occurred. This allows it to be confirmed whether the microcrack has propagated to the wiring area SLR through the inorganic film removal section CSR.

[0105] According to an embodiment, in the inorganic membrane removal section CSR, as will be described later. Figure 13 As shown, since the gate insulating film 140 is also an inorganic film, it can also be removed, and as will be described later. Figure 14 As shown, the organic membrane 180 can also be continuously formed in the inorganic membrane removal section CSR.

[0106] It can have various deformable cross-sectional structures other than these.

[0107] Furthermore, according to the embodiment, the intermediate region IPR may not be provided within the inorganic film removal section CSR. In this case, the cross-sectional structures of the conductive pattern CSP and the additional metal pattern AP may be identical. Unlike the additional metal pattern AP, the conductive pattern CSP may have a structure extending in a direction perpendicular to the crack propagation direction CD to facilitate easier inspection of microcracks. Additionally, the conductive pattern CSP may extend in a direction parallel to one side of the dam region DR.

[0108] Although Figure 5 The conductive pattern CSP is shown in the image with a triangular structure, but it is not limited to this structure and will be used in conjunction with other methods. Figure 7 To observe various structures.

[0109] Figure 7 This is an enlarged view of the L region in another embodiment.

[0110] Figure 7 yes Figure 5 A modified embodiment shows conductive patterns CSP1, CSP2, and CSP3 formed on the portion where the additional metal pattern AP is not provided, and multiple sizes are formed. Figure 5 Examples of small conductive patterns CSP1, CSP2, and CSP3. For example... Figure 7 As shown, the conductive patterns CSP1, CSP2, and CSP3 can be formed in various shapes.

[0111] When the additional metal pattern AP is located in the inorganic film removal section CSR, microcracks may also occur in the additional metal pattern AP, which can be used to check whether microcracks have occurred. Therefore, the conductive pattern CSP can be formed in the portion of the inorganic film removal section CSR where the additional metal pattern AP does not exist along the crack propagation direction CD.

[0112] With Figure 5 The part with differences is the center of observation. Figure 7 When the structure is as follows:

[0113] In the dam region DR, multiple conductive patterns CSP1, CSP2, and CSP3 are arranged in a direction perpendicular to the crack propagation direction CD toward the wiring region SLR. That is, the multiple conductive patterns CSP1, CSP2, and CSP3 extend in a direction parallel to one side of the dam region DR.

[0114] Since microcracks will be generated together in the predetermined area around the microcracks, it is not necessary to form conductive patterns CSP1, CSP2, and CSP3 continuously. When a conductive pattern CSP1, CSP2, or CSP3 is located in each predetermined area, it is sufficient to confirm whether microcracks have been generated.

[0115] Especially in Figure 7 In the embodiments, since there are no other additional metal patterns AP in the inorganic film removal section CSR, conductive patterns CSP1, CSP2, and CSP3 may be needed to inspect for microcracks.

[0116] Figure 7 The cross-sectional structures of the conductive patterns CSP1, CSP2, CSP3 and the inorganic film removal section CSR involved in the embodiments can be compared with... Figure 6 Same. In addition, it may also have, as will be described later. Figures 13 to 15 The cross-sectional structure.

[0117] Although conductive patterns can also be formed over the entire area of ​​the inorganic film removal section CSR, this is not suitable in terms of efficiency. Therefore, conductive patterns are formed around areas where microcracks are prone to occur.

[0118] The inorganic film removal section CSR and the conductive patterns CSP or CSP1, CSP2, and CSP3 were observed with a focus on the structure of the display panel 10 using a flexible substrate, including the connection portion 12 which is prone to cracking and microcracks when bent to the back.

[0119] The following, such as Figure 8 and Figure 9 As shown, observation is conducted with the corner portion, which is prone to cracking, as the center.

[0120] Figure 8This is a diagram illustrating a portion that may generate microcracks according to another embodiment, and Figure 9 This is an enlarged view of a corner portion of a display panel according to another embodiment, specifically... Figure 8 A magnified view of region C.

[0121] Besides the connecting part 12, there are other parts in the display panel 10 that are prone to cracking. The main body 11 of the display panel 10 has a corner part with a chamfered shape.

[0122] While etching the corner portion into a chamfered shape, the corresponding part becomes a structure that is vulnerable to cracks or impacts, so the frequency of cracks occurring in the part adjacent to the corner portion is high.

[0123] In this regard, such as Figure 9 As shown, observe the inorganic film removal section CSR and the conductive pattern in the corner portion of the main body 11.

[0124] like Figure 9 As shown, the corner portion of the main body 11 also has a structure in which a dam area DR and an inorganic film removal section CSR are provided from the outside to protect the wiring area SLR. Here, the wiring area SLR corresponds to the display area DA in which multiple pixels PX are provided.

[0125] The dam region DR is a structure in which inorganic and organic films are stacked. When forming the organic film that will be formed on the display region DA, it not only prevents the organic matter constituting the organic film from leaking to the outside, but also protects the display region DA from external impacts.

[0126] The layered structure of the dam region DR may include all the organic and inorganic films, excluding the conductive or semiconductor layers, in the layered structure of the display region DA. According to embodiments, the dam region DR can be formed while removing a portion of the organic or inorganic film. More than one dam may be located in the dam region DR, and multiple dams may also be formed.

[0127] An inorganic membrane removal section CSR is provided inside the dam region DR and outside the display region DA, which removes at least a portion of the inorganic membrane from the layered structure of the dam region DR.

[0128] To prevent cracks from propagating from the outside to the display area DA, an inorganic film removal section CSR is formed based on or greater than the width of the dam area DR. Since it is determined that cracks in signal lines propagating from the outside to the display area DA will propagate via the inorganic film rather than the organic film, a layered structure in which at least one inorganic film has been removed from the layered structure of the dam area DR can be used.

[0129] If a crack occurs in the signal line of a specific conductive layer in the display area DA, the inorganic film removal section CSR used to prevent the crack can be formed by removing the adjacent inorganic film of the corresponding conductive layer or removing the inorganic film located below the corresponding conductive layer. This structure of the inorganic film removal section CSR prevents the inorganic film that receives the propagation of the crack from the outside from continuously forming to the corresponding conductive layer; therefore, the crack will not propagate to the wiring area SLR, and no breakage will occur in the corresponding conductive layer.

[0130] However, even with the presence of the inorganic film removal section (CSR), microcracks of 1–2 μm in size can still propagate to the display area (DA). This is especially problematic given the current development trend of increasing resolution and decreasing wiring width; even microcracks can cause defects such as broken wiring. Therefore, it is necessary to confirm whether microcracks also propagate to the display area (DA). However, current methods have the drawback of being unable to identify microcracks as small as 1–2 μm.

[0131] To eliminate this drawback, additional conductive patterns CSP1, CSP2, and CSP3 are further formed within the inorganic film removal section CSR. The conductive patterns CSP1, CSP2, and CSP3 can be located in the same layer as the conductive layer where it is desired to monitor whether microcracks have formed, or in a layer lower than it.

[0132] exist Figure 9 The diagram shows the various directions of crack propagation, i.e., crack propagation directions. Cracks propagate from the outer dam region DR to the display region DA, therefore, the corner portions may have crack propagation directions CD1, CD2, CD3, CD4, and CD5.

[0133] The conductive patterns CSP1, CSP2, and CSP3 have a structure extending in directions perpendicular to the crack propagation directions CD1, CD2, CD3, CD4, and CD5. In particular, the conductive pattern CSP3 located at the corner can be formed along the corner curve, resulting in the ability to examine microcracks corresponding to each crack propagation direction CD3, CD4, and CD5. The conductive patterns CSP1, CSP2, and CSP3 can extend in a direction parallel to one side of the dam region DR.

[0134] Although Figure 9 The illustration shows a case where no additional metal patterns other than the conductive patterns CSP1, CSP2, and CSP3 are formed in the inorganic film removal section CSR. However, according to the embodiment, various additional metal patterns AP, such as alignment marks, can be formed.

[0135] Figure 9 The cross-sectional structures of the conductive patterns CSP1, CSP2, CSP3 and the inorganic film removal section CSR involved in the embodiments can be compared with... Figure 6 Same. In addition, it may also have, as described later. Figures 13 to 15 The cross-sectional structure.

[0136] The following is through Figure 10 Observe the structure of the inorganic membrane removal section CSR in the connecting part 12 of another embodiment.

[0137] Figure 10 This is an enlarged view of a portion of the outline of the connecting part according to another embodiment.

[0138] exist Figure 10 The relative area of ​​the inorganic membrane removal section CSR can be identified, and the case where it can have a width wider than the dam region DR is shown.

[0139] Furthermore, it is known that an inorganic film removal section CSR, in which the inorganic film has been completely removed, is provided in the space between the wiring area SLR and the dam area DR, and an intermediate area IPR, in which the inorganic film has not been removed, is provided in a part of the interior of the inorganic film removal section CSR.

[0140] Although not in Figure 10 As shown, however, the conductive pattern CSP can be formed in a direction perpendicular to the crack propagation directions CD1, CD2 (i.e., in a direction parallel to one side of the dam region DR) at a location that is not the middle region IPR.

[0141] The display panel 10 having the structure described above may include, for example: Figure 11 and Figure 12 The structure shown is represented by the pixel PX.

[0142] First, through Figure 11 Observe the circuit structure of pixel PX.

[0143] Figure 11 This is a circuit diagram of a pixel PX of a display panel according to one embodiment.

[0144] First, refer to Figure 11 A pixel PX may include transistors T1, T2, T3, T4, T5, T6, T7, capacitor Cst, and light emitting diode ED connected to signal lines 151, 152, 153, 154, 131, 171, 172.

[0145] Signal lines 151, 152, 153, 154, 131, 171, and 172 may include scan lines 151, 152, and 154, light emission control line 153, data line 171, drive voltage line 172, and initialization voltage line 131.

[0146] Scan lines 151, 152, and 154 can transmit scan signals GWn, GIn, and GI(n+1), respectively. Scan signals GWn, GIn, and GI(n+1) can alternately apply the gate on-state voltage and gate off-state voltage of transistors T2, T3, T4, and T7.

[0147] Scan lines 151, 152, and 154 connected to a pixel PX may include a first scan line 151 capable of transmitting a first scan signal GWn, a second scan line 152 capable of transmitting a second scan signal GIn with a gate on-state voltage at a different timing than the first scan line 151, and a third scan line 154 capable of transmitting a third scan signal GI(n+1). The second scan line 152 may transmit the gate on-state voltage at an earlier timing than the first scan line 151. For example, if the first scan signal GWn is the nth scan signal among scan signals applied within a frame period, the second scan signal GIn may be a preceding scan signal such as the (n-1)th scan signal, and the third scan signal GI(n+1) may be the nth scan signal. The third scan signal GI(n+1) may also be a scan signal different from the nth scan signal.

[0148] The light emission control line 153 can transmit a light emission control signal EM that controls the light emission of the light-emitting diode ED. The light emission control signal EM may include the gate on-state voltage and gate off-state voltage that turn transistors T5 and T6 on and off.

[0149] Data line 171 can transmit a data voltage Dm. Drive voltage line 172 can transmit a drive voltage ELVDD. The data voltage Dm can be generated based on an externally input image signal and can have different voltage levels depending on the desired brightness of the light-emitting element. On the other hand, the drive voltage ELVDD can have a substantially constant level. Initialization voltage line 131 can be applied with an initialization voltage Vint, and the initialization voltage Vint can have a constant voltage level.

[0150] The display device 1 may include a driving device (e.g., a scanning driving unit, a light-emitting driving unit, a data driving unit, a signal control unit, etc.) that generates signals to be transmitted to signal lines 151, 152, 153, 154, 131, 171, 172.

[0151] A pixel PX may include transistors T1, T2, T3, T4, T5, T6, and T7, which may include a first transistor T1 (also known as a driving transistor), a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0152] The first scan line 151 can transmit the first scan signal GWn to the second transistor T2 and the third transistor T3. The second scan line 152 can transmit the second scan signal GIn to the fourth transistor T4. The third scan line 154 can transmit the third scan signal GI(n+1) to the seventh transistor T7. The light emission control line 153 can transmit the light emission control signal EM to the fifth transistor T5 and the sixth transistor T6. Each transistor T1, T2, T3, T4, T5, T6, and T7 can respectively include source electrodes S1, S2, S3, S4, S5, S6, and S7, drain electrodes D1, D2, D3, D4, D5, D6, and D7, and gate electrodes G1, G2, G3, G4, G5, G6, and G7, and may include a polycrystalline semiconductor with a channel formed.

[0153] The data voltage Dm transmitted from the second transistor T2 to the source electrode S1 of the first transistor T1 is transmitted to the gate node GN via the third transistor T3. Here, the gate node GN is the node where the gate electrode G1 of the first transistor T1 and the capacitor Cst are connected. The first transistor T1 serves to output a drive current Id according to the voltage of the gate node GN when the drive voltage ELVDD is applied and transmit it to the light-emitting diode ED.

[0154] The second transistor T2 is turned on according to the first scan signal GWn transmitted through the first scan line 151, thereby transmitting the data voltage Dm transmitted from the data line 171 to the source electrode S1 of the first transistor T1.

[0155] The third transistor T3 is turned on according to the first scan signal GWn transmitted through the first scan line 151, thereby connecting the gate electrode G1 and the drain electrode D1 of the first transistor T1 to each other to form a diode connection for the first transistor T1. As a result, the data voltage Dm applied to the source electrode S1 of the first transistor T1 is transmitted to the gate node GN.

[0156] The fourth transistor T4 is turned on according to the second scan signal GIn received through the second scan line 152, thereby passing the initialization voltage Vint to the gate node GN, thereby performing an initialization operation to initialize the voltage of the gate electrode G1 of the first transistor T1 and the capacitor Cst.

[0157] When the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emission control signal EM transmitted through the light emission control line 153, such that the driving voltage ELVDD is applied to the source electrode S1 of the first transistor T1, the output current of the first transistor T1 is generated according to the pre-stored voltage of the gate node GN, and then transmitted to the light emission diode ED.

[0158] The seventh transistor T7 is turned on according to the third scan signal GI(n+1) transmitted through the third scan line 154, thereby changing the anode of the light-emitting diode ED to the initialization voltage Vint.

[0159] Transistors T1, T2, T3, T4, T5, T6, and T7 can be P-type transistors, and at least one of transistors T1, T2, T3, T4, T5, T6, and T7 can also be an N-type channel transistor.

[0160] One end of capacitor Cst can be connected to the gate electrode G1 of the first transistor T1, and the other end can be connected to the drive voltage line 172.

[0161] The anode of the light-emitting diode ED can be connected to the sixth transistor T6 to receive the drive current Id, and the cathode can be connected to the common voltage terminal of the common voltage ELVSS to receive the application of the common voltage ELVSS.

[0162] The number of transistors and capacitors included in a pixel PX, as well as their interconnections, can be varied in various ways.

[0163] The following is a brief explanation of how this pixel PX operation works.

[0164] The pixel PX operates in three phases: initialization, data programming and compensation, and emission.

[0165] During initialization, when a second scan signal GIn (which can be the (n-1)th scan signal) is supplied with a gate turn-on voltage level through the second scan line 152, the fourth transistor T4 is turned on, and the initialization voltage Vint is passed to the gate electrode G1 of the first transistor T1. The first transistor T1 is initialized by the initialization voltage Vint.

[0166] Next, during data programming and compensation, when a first scan signal GWn (which may be the nth scan signal) with a gate turn-on voltage level is supplied through the first scan line 151, the second transistor T2 and the third transistor T3 are turned on. The first transistor T1 is diode-connected through the turned-on third transistor T3. Thus, while the data voltage Dm supplied through the data line 171 is transmitted to the gate electrode G1 of the first transistor T1 via the diode-connected path, the voltage of the gate electrode G1 of the first transistor T1 gradually increases. Then, when the voltage of the gate electrode G1 of the first transistor T1 changes from the data voltage Dm to a small value equivalent to the threshold voltage of the first transistor T1, the first transistor T1 is turned off, and the voltage at this time (Dm - Vth; here, Vth is the threshold voltage value of the first transistor T1) is stored in the capacitor Cst.

[0167] Next, during the light emission period, based on the light emission control signal EM transmitted via the light emission control line 153, the fifth transistor T5 and the sixth transistor T6 are turned on. As a result, based on the voltage difference between the voltage at the gate electrode G1 of the first transistor T1 and the driving voltage ELVDD, a driving current Id is output from the first transistor T1 and transmitted to the light-emitting diode ED. Upon receiving the transmitted driving current Id, the light-emitting diode ED emits light according to the magnitude of the current.

[0168] On the other hand, during the data programming and compensation period, the seventh transistor T7 is turned on by receiving the third scan signal GI(n+1) through the third scan line 154. As a result, the anode of the light-emitting diode ED is initialized simultaneously with the initialization voltage Vint. The third scan signal GI(n+1) can be the nth scan signal. However, according to an embodiment, the seventh transistor T7 can also be turned on during the initialization period, at which time the same signal as the second scan line 152 can be applied to the third scan line 154.

[0169] According to the embodiment, in addition to the pixel PX having this circuit structure, various pixels can be formed on the display panel 10.

[0170] The following is through Figure 12 Observe the cross-sectional structure of the display area DA formed on the display panel 10.

[0171] Figure 12 This is a cross-sectional view of an organic light-emitting display panel according to one embodiment.

[0172] A barrier layer 111 is provided on the substrate 110, and a buffer layer 112 is provided on the barrier layer 111. A semiconductor layer PS is provided on the buffer layer 112.

[0173] The organic light-emitting display panel 10 of this embodiment is formed on a flexible substrate 110 using a plastic or polyimide (PI) substrate.

[0174] The barrier layer 111 and the buffer layer 112 may be inorganic films, and as an example, they may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y Inorganic insulating materials such as barrier layer 111 and buffer layer 112 can be single-layer or multi-layer structures of the aforementioned materials.

[0175] According to an embodiment, when using a polyimide (PI) substrate, the entire substrate up to the barrier layer 111, which serves as an inorganic film, can be referred to as a flexible substrate. Furthermore, according to an embodiment, multiple substrates 110 and barrier layers 111 made of polyimide (PI) can be formed. That is, a barrier layer 111 is provided on a substrate 110, and a substrate 110 and a barrier layer 111 are further provided on the barrier layer 111. A buffer layer 112 can be provided on the substrate 110 and barrier layer 111 after repeatedly forming the unit structure described above.

[0176] A semiconductor layer PS, including a channel with multiple transistors, a first electrode, and a second electrode, is disposed on the buffer layer 112.

[0177] The semiconductor layer PS can be formed from polycrystalline semiconductors, or from amorphous silicon or oxide semiconductors. For example, the semiconductor layer PS may include low-temperature polycrystalline silicon (LTPS), or may include an oxide semiconductor material containing at least one of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and mixtures thereof. For example, the semiconductor layer PS may include IGZO (Indium-Gallium-Zinc Oxide).

[0178] The portions of the semiconductor layer PS that form the first and second electrodes can be formed by plasma processing to have properties comparable to those of a conductor.

[0179] The semiconductor layer PS may be covered by a first gate insulating film 141, and the first gate insulating film 141 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y Inorganic insulating materials such as ) and . The first gate insulating film 141 may be a single layer or multiple layers of the material.

[0180] A first gate conductive layer is formed on the first gate insulating film 141. The first gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be a single layer or multiple layers of said material.

[0181] exist Figure 12 In the diagram, scan line 151 and gate electrode 155 are shown as the first gate conductive layer. Scan line 151 includes the gate electrode of the second transistor T2, and gate electrode 155 is the gate electrode of the driving transistor T1.

[0182] A second gate insulating film 142 is disposed on the first gate conductive layer, covering it. The second gate insulating film 142 may include silicon nitride (SiN). x ), silicon dioxide (SiO)x ), silicon oxynitride (SiO) x N y Inorganic insulating materials such as )

[0183] A second gate conductive layer is formed on the second gate insulating film 142. The second gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti), and may be a single layer or multiple layers of said material.

[0184] exist Figure 12 The image shows a sustaining line 126 in the second gate conductive layer. The sustaining line 126 forms a capacitor Cst while overlapping with the gate electrode 155.

[0185] An interlayer insulating film 160 is disposed on the second gate conductive layer, covering it. The interlayer insulating film 160 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y Inorganic insulating materials such as )

[0186] A data conductive layer is formed on the interlayer insulating film 160. The data conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multiple layers of said material.

[0187] Openings 62 and 68 are formed in the interlayer insulating film 160. Opening 62 serves to open a portion of the semiconductor layer PS to connect the data line 171 and the second transistor T2. In addition, opening 68 serves to connect the sustaining line 126 and the driving voltage line 172.

[0188] An organic film 180 is formed on the data conductive layer, covering it. The organic film 180 may be formed of an organic insulating material and may include general polymers such as PMMA (polymethylmethacrylate) or PS (polystyrene), polymer derivatives with phenol groups, acrylic polymers, imide polymers, polyimides, acrylic polymers, siloxane polymers, etc. In this embodiment, the organic film 180 is formed of polyimide (PI).

[0189] Although not shown, a pixel electrode (not shown) is disposed on the organic film 180. The pixel electrode receives the output current of the driving transistor T1 through an opening formed in the organic film 180.

[0190] Separator walls (not shown) and spacers (not shown) are provided on the organic film 180 and the pixel electrode.

[0191] The separator has an open portion that overlaps with the pixel electrode, and an organic light-emitting layer is disposed in the open portion. A common electrode (not shown) is disposed on the organic light-emitting layer and the separator. The pixel electrode, the organic light-emitting layer, and the common electrode constitute an organic light-emitting diode (ED).

[0192] The partition walls and spacers can be formed from various organic materials; in this embodiment, they are formed from polyimide (PI). The partition walls and spacers can be formed from the same material and can be formed together using a single mask, in which case a halftone mask is used. As a result, the spacers are formed from halftone regions, thereby reducing the number of masks required. However, in the case of forming high-resolution pixel PXs, it may be possible that the partition walls and spacers cannot be formed together using a halftone mask. In this case, the partition walls and spacers are formed using separate masks.

[0193] The following is through Figures 13 to 15 Observe the modified embodiments of the inorganic film removal section CSR and the conductive pattern CSP.

[0194] Figures 13 to 15 This is a cross-sectional view of the inorganic membrane removal section according to another embodiment.

[0195] first, Figure 13 and Figure 14 yes Figure 6 The deformed diagram.

[0196] exist Figure 13 In, with Figure 6 In contrast, the inorganic membrane removal section CSR does not include an embodiment of the gate insulating film 140, which is an inorganic membrane.

[0197] At this time, the conductor pattern CSP can be formed by a conductor disposed on a layer closer to the substrate 110 than the signal line SL located in the gate conductive layer. That is, a semiconductor layer can be formed below the gate conductive layer and below the gate insulating film 140, and a metal layer can be formed below the semiconductor layer, and the conductor pattern CSP can be formed from the same layer as the metal layer. At this time, the inorganic insulating film (refer to...) Figure 12 The buffer layer 112) can be located between the metal layer and the semiconductor layer of the display area DA, but this inorganic insulating film can also be removed from the inorganic film removal section CSR.

[0198] According to an embodiment, the conductor pattern CSP can also be formed from the gate conductive layer.

[0199] On the other hand, Figure 14An embodiment is shown in which the organic membrane 180 is also continuously formed in the inorganic membrane removal section CSR. Since the inorganic membrane is removed from the inorganic membrane removal section CSR, the presence of the organic membrane 180 formed of organic matter is not a problem.

[0200] Figure 15 The embodiments illustrate applications with Figure 12 An example of the inorganic film removal section CSR and conductive pattern CSP in the embodiment of the display area DA.

[0201] exist Figure 15 In this structure, the dam region DR is a structure formed by stacking inorganic and organic films, originally comprising inorganic and organic films formed on the display region DA, and formed to include portions other than the conductive or semiconductor layer of the display region DA. According to embodiments, a portion of the conductive layer may also be included. More than one dam may be located in the dam region DR, and multiple dams may also be formed.

[0202] An inorganic membrane removal section (CSR) is provided inside the dam area DR, where at least a portion of the inorganic membrane is removed.

[0203] exist Figure 15 In one embodiment, the structure is such that all layers are removed except for the substrate 110 and the barrier layer 111, which is an inorganic film directly connected to the substrate 110 formed of polyimide (PI), and a conductive pattern CSP is directly formed on the barrier layer 111.

[0204] The conductive pattern CSP can be formed by a conductive layer located lower than the buffer layer 112 and formed on the surface of the buffer layer 112. Figure 13 The conductive layer is located at the same position as the conductive pattern CSP.

[0205] The conductive pattern CSP is covered by a cover film 195, which serves as an additional organic film. The cover film 195 has a structure that does not form in the dam region DR and the display region DA, but only in the inorganic film removal section CSR. However, according to an embodiment, the cover film 195 can be formed from the same material in the same process as an organic film formed in the display region DA.

[0206] The conductive pattern described above can be used to inspect and detect microcracks. This allows for the detection of cracks at the corners of the display panel 10 or when it is bent, providing guidance to modify manufacturing or bending processes to prevent the formation of microcracks. Specifically, when the display panel 10 is bent, it is pressed with a certain pressure; if microcracks are detected, the bending can be performed with weaker pressure to prevent even microcracks as small as 1–2 μm from forming.

[0207] Typically, since the layer formed by the signal lines is either a gate conductive layer or a data conductive layer, the conductor pattern CSP can be a gate conductive layer, a data conductive layer, or a metal layer located below the semiconductor layer. According to an embodiment, the data conductive layer can also be composed of two or more conductive layers, just like the gate conductive layer, in which case an insulating layer (organic insulating layer or inorganic insulating layer) can be located between the two data conductive layers.

[0208] Furthermore, the inorganic film removed from the inorganic film removal section CSR is mainly the inorganic film between the substrate 110 and the interlayer insulating film 160. The corresponding layers may be the barrier layer 111, the buffer layer 112, the gate insulating films 140 / 141 and 142, and the interlayer insulating film 160. Other inorganic films (e.g., the inorganic film of the encapsulation layer) may not be removed even in the inorganic film removal section CSR.

[0209] The embodiments of the present invention have been described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art that utilize the basic concepts of the present invention as defined in the claims are all within the scope of the present invention.

Claims

1. A display device comprising a display panel including a non-display area and a display area, The display area includes: A semiconductor layer is formed on the substrate; A gate insulating film is formed on the semiconductor layer; A gate conductive layer is located on the gate insulating film; An interlayer insulating film is located on the gate conductive layer; as well as The data conductive layer is located on the interlayer insulating film. The non-display area includes: solder pad area; as well as In the inorganic film removal section, at least one of the gate insulating film and the interlayer insulating film is removed. An electrically floated conductive pattern is formed within the inorganic membrane removal section. The gate insulating film and the interlayer insulating film are inorganic films. The conductive pattern is covered by an organic film. The organic film fills the inorganic film removal section and covers the interlayer insulating film of the display area, thus forming a continuous structure.

2. The display device according to claim 1, wherein, The inorganic film removal section removes the inorganic film that is connected to and located on the signal line that is located in the display area and is subject to cracking.

3. The display device according to claim 2, wherein, The signal line is located in the gate conductive layer. The inorganic film removal section removes the interlayer insulating film. The conductor pattern is located in the gate conductive layer.

4. The display device according to claim 1, wherein, The inorganic film removal section removes the inorganic film adjacent to the signal line located above and below the display area and which should prevent cracking.

5. The display device according to claim 4, wherein, The signal line is located in the gate conductive layer. The inorganic film removal section removes the gate insulating film and the interlayer insulating film.

6. The display device according to claim 5, wherein, The conductive pattern is formed by a metal layer that is closer to the substrate than the semiconductor layer.

7. The display device according to claim 1, wherein, The outer side of the inorganic membrane removal section also includes a dam region having at least one dam. The conductive pattern extends in a direction parallel to one side of the dam region.

8. The display device according to claim 7, wherein, The conductive pattern is located at the corner portion of the display panel.

9. The display device according to claim 1, wherein, An intermediate region containing unremoved inorganic membrane is formed in the inorganic membrane removal section. An additional metallic pattern is formed in the central region.

10. A display device, comprising: The display panel is flexible and includes a main body having a display area and a connecting part protruding from the main body. An integrated circuit chip is attached to the connection portion; A dam area is formed along the outer contour of the display panel and includes at least one dam. An inorganic film removal section is located inside the dam region and removes one of the gate insulating film located below the signal line and the interlayer insulating film located above the signal line, wherein the signal line is the line connecting the integrated circuit chip and the display area; as well as The conductive pattern is located within the inorganic film removal section and is electrically floated. The gate insulating film and the interlayer insulating film are inorganic films. The conductive pattern is covered by an organic film. The organic film fills the inorganic film removal section and covers the interlayer insulating film of the display area, thus forming a continuous structure.

11. The display device according to claim 10, further comprising: The wiring area includes the signal lines.

12. The display device according to claim 11, wherein, The inorganic film removal section removes the inorganic film that is connected to and located on the signal line that is in the wiring area and should prevent cracking.

13. The display device according to claim 12, wherein, The signal line is located in the gate conductive layer. The inorganic film removal section removes the interlayer insulating film covering the signal line. The conductor pattern is located in the gate conductive layer.

14. The display device according to claim 11, wherein, The inorganic film removal section removes the inorganic film adjacent to the signal line located above and below the wiring area and which should prevent cracking.

15. The display device according to claim 14, wherein, The signal line is located in the gate conductive layer. The inorganic film removal section removes the gate insulating film located below the signal line and the interlayer insulating film located above the signal line.

16. The display device according to claim 15, wherein, The conductive pattern is formed by a metal layer that is closer to the substrate than the semiconductor layer located below the gate insulating film.

17. The display device according to claim 11, wherein, The outer side of the inorganic membrane removal section also includes a dam region having at least one dam. The conductive pattern extends in a direction parallel to one side of the dam region.

18. The display device according to claim 10, wherein, An intermediate region containing unremoved inorganic membrane is formed in the inorganic membrane removal section. An additional metallic pattern is formed in the central region.

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