Tiled display

Abstract

The video wall display includes: a first display device including a first display area and a first pad area having a groove; and a second display device including a second display area and a second pad area overlapping the second display area, the second pad area having a protrusion, wherein the protrusion is inserted into the groove to connect the first pad area and the second pad area.

Description

Technical Field

[0001] This disclosure relates to a video wall display. Background Technology

[0002] With the development of the information society, the demand for display devices is constantly increasing. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and organic light-emitting diode (OLED) displays. In such flat panel displays, the light-emitting element can include a light-emitting element capable of emitting light itself, allowing each pixel in the display panel to emit its own light. Therefore, the light-emitting display device can display images without a backlight portion that provides light to the display panel.

[0003] For display devices with large screens, a large number of pixels can be set, which may increase the defect rate of the light-emitting elements and reduce productivity or reliability. To overcome these problems, video wall displays can provide a large screen by connecting multiple display devices with relatively small dimensions. However, such video wall displays may include boundaries between multiple display devices because non-display areas or bezels may exist between multiple adjacent display devices. These boundaries between display devices can result in visible seams, thus hindering the viewer's immersion in the image.

[0004] It should be understood that this background section is partly intended to provide useful background for understanding the art. However, this background section may also include ideas, concepts, or knowledge that were not known or understood by a person skilled in the art prior to the corresponding valid application date of the subject matter disclosed herein. Summary of the Invention

[0005] This disclosure provides a video wall display that eliminates visible seams between multiple display devices by preventing the boundaries between display devices from being identified, allowing viewers to immerse themselves in the displayed images.

[0006] It should be noted that the aspects of this disclosure are not limited to those described above. Other aspects of this disclosure will be apparent to those skilled in the art from the following description.

[0007] According to embodiments of this disclosure, a video wall display can be formed by connecting a first display device having a recess and a second display device having a protrusion. Therefore, the video wall display can immerse the viewer in the image by suppressing the perception of the boundaries between the display areas of the display devices.

[0008] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent to those skilled in the art from the following description.

[0009] According to embodiments of the present disclosure, a splicing display may include: a first display device including a first display area and a first pad area having a groove; and a second display device including a second display area and a second pad area overlapping the second display area, the second pad area having a protrusion, wherein the protrusion can be inserted into the groove to connect the first pad area and the second pad area.

[0010] In one embodiment, the first pad region may include a first connection pattern inside a contact groove. The second pad region may include a second connection pattern forming a protrusion.

[0011] In one implementation, the first pad area may include a first signal line extending from the first display area. A recess may expose the first signal line. A first connection pattern may contact the first signal line through the recess.

[0012] In one embodiment, the second pad area may include a second signal line extending from the second display area and a hole exposing the second signal line.

[0013] In one implementation, the second connection pattern can contact the second signal line through a hole.

[0014] In one embodiment, the diameter of the second connecting pattern can be equal to the diameter of the hole, and the diameter of the second connecting pattern is smaller than the diameter of the groove.

[0015] In one embodiment, the second display device may include a substrate, the second connection pattern may protrude beyond the substrate, and the height of the second connection pattern protruding from the substrate may be greater than the depth of the groove in the first pad region.

[0016] In an implementation, each of the first connection patterns may include at least one of ITO, IZO, and ITZO.

[0017] In an implementation, the second connection pattern may include at least one of a metal layer, a metal pin, and a silver (Ag) dot.

[0018] In this implementation, the first pad area may not overlap with the first display area, but may overlap with the second pad area.

[0019] According to embodiments of this disclosure, a video wall display may include: a first display device including a first display area and a first pad area having a groove; and a second display device including a second display area and a second pad area overlapping the second display area, the second pad area having a protrusion. The second display device may include a substrate and a step in the second pad area, the step may include a thinner portion of the substrate, and the protrusion may be inserted into the groove to connect the first pad area and the second pad area.

[0020] In an implementation, the substrate may include a first base substrate, a barrier layer disposed on the first base substrate, and a second base substrate disposed on the barrier layer. The step may be formed by removing at least a portion of the first base substrate, the barrier layer, and the second base substrate in the second pad region, by removing at least a portion of the first base substrate in the second pad region, or by removing at least a portion of the barrier layer and the first base substrate in the second pad region.

[0021] In one embodiment, the first pad region may include a first connection pattern inside a contact groove. The second pad region may include a second connection pattern forming a protrusion.

[0022] In one implementation, the first pad area may include a first signal line extending from the first display area, the groove may expose the first signal line, and the first connection pattern may contact the first signal line through the groove.

[0023] In one embodiment, the second pad area may include a second signal line extending from the second display area and a hole exposing the second signal line, and the second connection pattern may contact the second signal line through the hole. Attached Figure Description

[0024] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0025] Figure 1 This is a schematic plan view of a video wall display according to an embodiment of the present disclosure.

[0026] Figure 2 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0027] Figure 3 It is along Figure 2 A schematic cross-sectional view taken from line I-I'.

[0028] Figure 4 This is a schematic plan view showing the pixels of a display device according to an embodiment of the present disclosure.

[0029] Figure 5 It is along Figure 4 A schematic cross-sectional view taken from line II-II'.

[0030] Figure 6 This is a schematic view of a light-emitting element according to an embodiment of the present disclosure.

[0031] Figure 7 This is a plan view schematically illustrating the connection structure of a video wall display according to an embodiment of the present disclosure.

[0032] Figure 8 This is a schematic plan view of a first display device according to an embodiment of the present disclosure.

[0033] Figure 9 This is a schematic cross-sectional view of a first display device according to an embodiment of the present disclosure.

[0034] Figure 10 It is shown schematically. Figure 9 A magnified view of region A.

[0035] Figure 11 This is a schematic plan view of a second display device according to an embodiment of the present disclosure.

[0036] Figure 12 This is a schematic cross-sectional view of a second display device according to an embodiment of the present disclosure.

[0037] Figure 13 It is shown schematically. Figure 12 A magnified view of region B.

[0038] Figure 14 This is a schematic cross-sectional view showing a first display device and a second display device connected to each other according to an embodiment of the present disclosure.

[0039] Figure 15 It is shown schematically. Figure 14 A magnified view of region C.

[0040] Figure 16 It is along Figure 7 The schematic cross-sectional view of the first display device is shown by line III-III'.

[0041] Figure 17 It is along Figure 7 The schematic cross-sectional view of the second display device is shown by line IV-IV'.

[0042] Figure 18 This is a schematic cross-sectional view of a second display device according to another embodiment.

[0043] Figure 19 It is shown schematically. Figure 18 A magnified view of region D.

[0044] Figure 20 This is a schematic cross-sectional view of a first display device and a second display device connected to each other according to another embodiment.

[0045] Figure 21 and Figure 22 This is a schematic plan view of a video wall display according to other embodiments of the present disclosure. Detailed Implementation

[0046] This disclosure will now be described more fully below with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0047] Throughout the specification, the same reference numerals indicate the same components.

[0048] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0049] Each of the features of the various embodiments of this disclosure can be combined or integrated with each other in part or in whole, and technical interconnection and driving are possible. Each embodiment can be implemented independently of each other or can be implemented together in association.

[0050] In the specification and claims, for purposes of meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood as equivalent to "and / or".

[0051] In the specification and claims, for purposes of meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0052] When the terms “comprised,” “comprising,” “includes,” and / or “including,” “has,” “have,” and / or “having,” and variations thereof are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0053] The term "overlap" or "overlapped" means that a first object may be above or below a second object, or to one side of a second object, or vice versa. Furthermore, the term "overlap" may include layering, stacking, facing, extending above, extending below, covering, or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. When an element is described as "not overlapping" or "to not overlap," this may include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art.

[0054] When a component is referred to as being in contact with another component or in contact with another component, the component may be in “electrical contact” or “physical contact” with the other component. This contact can be “direct contact” where there is no intermediate component, or “indirect contact” where there is an intermediate component.

[0055] When a layer is referred to as being "on" another layer or substrate, it can be directly on another layer or substrate, or it can be an intermediate layer.

[0056] As used herein, “about,” “approximately,” and “substantially” include the value and the average of the specific value within an acceptable range of deviations determined by a person skilled in the art, considering the measurement under discussion and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the value.

[0057] Unless otherwise defined or implied herein, all terms used (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted as having an ideal or overly formal meaning, unless expressly defined herein.

[0058] Figure 1 This is a schematic plan view of a video wall display according to an embodiment of the present disclosure.

[0059] Reference Figure 1 The video wall display TD may include multiple display devices 10. The display devices 10 may be arranged in a grid pattern, but are not limited thereto. The display devices 10 may be connected in a first direction (X-axis direction) or a second direction (Y-axis direction), and the video wall display TD may have a specific shape. For example, the display devices 10 may all have the same size. However, it should be understood that this disclosure is not limited thereto. As another example, the display devices 10 may have different sizes.

[0060] Each of the display devices 10 may have a rectangular shape including a longer side and a shorter side. The display devices 10 may be arranged such that the longer or shorter sides of the display devices 10 can be connected to each other. Some of the display devices 10 may be disposed on the edge of the video wall display TD to form the side of the video wall display TD. Others of the display devices 10 may be disposed at the corners of the video wall display TD and may form two adjacent side of the video wall display TD. Still other displays 10 may be disposed on the inner side of the video wall display TD and may be surrounded by other display devices 10.

[0061] Each of the display devices 10 may include a display area DA and a non-display area NDA. The display area DA may include pixels to display an image. The non-display area NDA may be disposed around the display area DA to surround the display area DA and may not display an image.

[0062] The video wall display TD can have, but is not limited to, a generally planar shape. The video wall display TD can also have a three-dimensional shape, giving viewers a three-dimensional experience. For example, in the case where the video wall display TD has a three-dimensional shape, at least some of the display devices 10 can have a curved shape. As another example, the display devices 10 can have a flat shape and can be connected to each other at an angle, allowing the video wall display TD to have a three-dimensional shape.

[0063] A video wall display TD can be formed by connecting the non-display areas NDA of adjacent display devices 10 to each other. The display devices 10 can be connected to each other using bonding or adhesive components. Therefore, the non-display areas NDA between display devices 10 can be surrounded by adjacent display areas DA. The display areas DA of the display devices 10 can be very close to each other, making it impossible for a viewer to perceive the non-display areas NDA or the boundaries between the display devices 10. The reflectivity of external light at the display areas DA of the display devices 10 can be substantially equal to the reflectivity of external light at the non-display areas NDA between the display devices 10. Therefore, the video wall display TD can eliminate the seams between the display devices 10 by preventing the non-display areas NDA or the boundaries between the display devices 10 from being perceived, thereby immersing the viewer in the image.

[0064] Figure 2 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0065] Reference Figure 2 The display device 10 may include pixels arranged in rows and columns in a display area DA. Each pixel may include a light-emitting area LA defined by a pixel defining layer, and may emit light having a peak wavelength through the light-emitting area LA. For example, the display area DA of each of the display devices 10 may include a first light-emitting area LA1, a second light-emitting area LA2, and a third light-emitting area LA3. In each of the first light-emitting area LA1, the second light-emitting area LA2, and the third light-emitting area LA3, light generated by the light-emitting element of the display device 10 may be emitted from the display device 10.

[0066] The first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 can emit light with peak wavelengths to the outside of the display device 10. The first light-emitting region LA1 can emit light of a first color, the second light-emitting region LA2 can emit light of a second color, and the third light-emitting region LA3 can emit light of a third color. For example, the first color light can be red light with a peak wavelength in the range of about 610 to about 650 nm, the second color light can be green light with a peak wavelength in the range of about 510 to about 550 nm, and the third color light can be blue light with a peak wavelength in the range of about 440 to about 480 nm. However, it should be understood that this disclosure is not limited thereto.

[0067] The first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 can be arranged repeatedly and sequentially along the first direction (X-axis direction) of the display area DA. For example, the width of the first light-emitting region LA1 in the first direction (X-axis direction) can be greater than the width of the second light-emitting region LA2 in the first direction. The width of the second light-emitting region LA2 in the first direction can be greater than the width of the third light-emitting region LA3 in the first direction. As another example, the widths of the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3 in the first direction can all be substantially equal.

[0068] The area of ​​the first luminous region LA1 can be larger than the area of ​​the second luminous region LA2, and the area of ​​the second luminous region LA2 can be larger than the area of ​​the third luminous region LA3. As another example, the areas of the first luminous region LA1, the second luminous region LA2, and the third luminous region LA3 can all be substantially equal.

[0069] The display area DA of the display device 10 may include a light-shielding area BA surrounding the light-emitting area LA. For example, the display area DA may include a first light-shielding area BA1, a second light-shielding area BA2, and a third light-shielding area BA3. The first light-shielding area BA1, the second light-shielding area BA2, and the third light-shielding area BA3 may be respectively disposed on one side of the first light-emitting area LA1, the second light-emitting area LA2, and the third light-emitting area LA3, thereby preventing the mixing of light emitted from the first light-emitting area LA1, the second light-emitting area LA2, and the third light-emitting area LA3.

[0070] Figure 3 It is along Figure 2 A schematic cross-sectional view taken from line I-I'.

[0071] Reference Figure 3 Each of the display devices 10 may include a first light-emitting area LA1, a second light-emitting area LA2, and a third light-emitting area LA3 in its display area DA. In each of the first light-emitting area LA1, the second light-emitting area LA2, and the third light-emitting area LA3, light generated by the light-emitting diode ED of the display device 10 may be emitted from the display device 10.

[0072] The display device 10 may include a substrate SUB, a buffer layer BF, a thin film transistor layer TFTL, an emitter element layer EML, a wavelength conversion layer WLCL, a color filter layer CFL, and an encapsulation layer TFE.

[0073] The substrate SUB may include a first base substrate PI1, a barrier layer BAR, and a second base substrate PI2. The first base substrate PI1 and the second base substrate PI2 may be formed of an insulating material such as a polymer resin. For example, the first base substrate PI1 and the second base substrate PI2 may be flexible substrates capable of being bent, folded, and / or rolled. The first base substrate PI1 and the second base substrate PI2 may include, but are not limited to, polyimide (PI). The barrier layer BAR may be disposed between the first base substrate PI1 and the second base substrate PI2, and may be implemented as an inorganic layer capable of preventing the penetration of air or moisture. For example, the barrier layer BAR may include inorganic films alternately stacked on top of each other.

[0074] A buffer layer BF can be disposed on a substrate SUB. The buffer layer BF can be formed of an inorganic membrane capable of preventing the penetration of air or moisture. For example, the buffer layer BF may comprise inorganic membranes that are stacked alternately on top of each other.

[0075] The thin-film transistor layer (TFTL) may include a thin-film transistor (TFT), a gate insulator (GI), an interlayer dielectric (ILD), a connection electrode (CNE), a first passivation layer (PAS1), and a first planarization layer (OC1).

[0076] Thin-film transistors (TFTs) can be disposed on a buffer layer (BF) and can form pixel circuits for each of multiple pixels. For example, a TFT can be a driving transistor or a switching transistor for a pixel circuit. A TFT may include a semiconductor region (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0077] The semiconductor region ACT, source electrode SE, and drain electrode DE can be disposed on the buffer layer BF. The semiconductor region ACT can overlap with the gate electrode GE in the thickness direction and can be insulated from the gate electrode GE by the gate insulator GI. The source electrode SE and drain electrode DE can be formed by converting the material of the semiconductor region ACT into a conductor.

[0078] The gate electrode GE can be disposed on the gate insulator GI. The gate electrode GE can overlap with the semiconductor region ACT, and the gate insulator GI is inserted between the gate electrode GE and the semiconductor region ACT.

[0079] A gate insulator GI can be disposed on the semiconductor region ACT, the source electrode SE, and the drain electrode DE. For example, the gate insulator GI can cover the semiconductor region ACT, the source electrode SE, the drain electrode DE, and the buffer layer BF, and can insulate the semiconductor region ACT from the gate electrode GE. The gate insulator GI may include a contact hole through which the connection electrode CNE passes.

[0080] An interlayer dielectric layer (ILD) can be disposed above the gate electrode GE. For example, the ILD may include a contact hole through which a connection electrode CNE passes. The contact hole of the ILD may be connected to the contact hole of the gate insulator GI.

[0081] The connection electrode CNE can be disposed on the interlayer dielectric layer (ILD). The connection electrode CNE can connect the drain electrode DE of the thin-film transistor (TFT) to the first electrode AE ​​of the light-emitting element (EL). The connection electrode CNE can contact the drain electrode DE through contact holes formed in the gate insulator (GI) and the interlayer dielectric layer (ILD).

[0082] The first passivation layer PAS1 can be disposed above the connection electrode CNE to protect the thin-film transistor TFT. For example, the first passivation layer PAS1 may include a contact hole through which the first electrode AE ​​of the light-emitting element EL passes.

[0083] A first planarization layer OC1 may be disposed on a first passivation layer PAS1 to provide a flat surface above a thin-film transistor layer TFTL. For example, the first planarization layer OC1 may include a contact hole through which a first electrode AE ​​of a light-emitting element EL passes. The contact hole in the first planarization layer OC1 may be connected to a contact hole in the first passivation layer PAS1.

[0084] The emitting element layer EML may include a light-emitting element EL, a first dam BNK1, a second dam BNK2, a second passivation layer PAS2, and a second planarization layer OC2.

[0085] The light-emitting element EL can be disposed on a thin-film transistor (TFT). The light-emitting element EL may include a first electrode AE, a second electrode CE, and a light-emitting diode ED.

[0086] The first electrode AE ​​can be disposed on the first planarization layer OC1. For example, the first electrode AE ​​can be disposed on the first embankment BNK1 disposed on the first planarization layer OC1 to cover the first embankment BNK1. The first electrode AE ​​can be disposed to overlap with one of the first light-emitting regions LA1, LA2, and LA3 defined by the second embankment BNK2. The first electrode AE ​​can be connected to the drain electrode DE of the thin-film transistor TFT. The first electrode AE ​​can be, but is not limited to, the anode electrode of the light-emitting element EL.

[0087] The second electrode CE can be disposed on the first planarization layer OC1, such that the second electrode CE can be spaced apart from the first electrode AE. For example, the second electrode CE can be disposed on the first embankment BNK1 disposed on the first planarization layer OC1 to cover the first embankment BNK1. The second electrode CE can be configured to overlap with one of the first light-emitting regions LA1, LA2, and LA3 defined by the second embankment BNK2. For example, the second electrode CE can receive a common voltage applied to all pixels. The second electrode CE can be, but is not limited to, the cathode electrode of the light-emitting element EL.

[0088] The first insulating layer IL1 can cover a portion of the first electrode AE ​​and a portion of the second electrode CE that are adjacent to each other, and can insulate the first electrode AE ​​and the second electrode CE from each other.

[0089] A light-emitting diode (LED) can be disposed above a first planarization layer OC1 between a first electrode AE ​​and a second electrode CE. The LED can be disposed on a first insulating layer IL1. One end of the LED can be connected to the first electrode AE, and the other end can be connected to the second electrode CE. For example, the LED may include active layers of the same material, such that they can emit light of the same wavelength or the same color. Light emitted from each of the first emitting region LA1, the second emitting region LA2, and the third emitting region LA3 can have the same color. For example, the LED can emit light of a third color or blue light with a peak wavelength in the range of about 440 nm to about 480 nm. Therefore, the emitting element layer EML can emit light of a third color or blue light.

[0090] The second dam portion BNK2 can be disposed on the first planarization layer OC1 to define the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3. For example, the second dam portion BNK2 can surround each of the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3. However, it should be understood that this disclosure is not limited thereto. The second dam portion BNK2 can separate and insulate the first electrode AE ​​or the second electrode CE of the light-emitting element EL from the first electrode AE ​​or the second electrode CE of the adjacent light-emitting element EL. The second dam portion BNK2 can be disposed in the first light-shielding region BA1, the second light-shielding region BA2, and the third light-shielding region BA3.

[0091] The second passivation layer PAS2 can be disposed on the light-emitting element EL and the second embankment BNK2. The second passivation layer PAS2 can cover the light-emitting element EL to protect it. The second passivation layer PAS2 can prevent impurities such as moisture and air from penetrating from the outside to prevent damage to the light-emitting element EL.

[0092] The second planarization layer OC2 may be disposed on the second passivation layer PAS2 to provide a flat surface above the emitter element layer EML. The second planarization layer OC2 may include an organic material. For example, the second planarization layer OC2 may be at least one selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0093] The wavelength conversion layer (WLCL) may include a first capping layer (CAP1), a first light-shielding member (BK1), a first wavelength conversion section (WLC1), a second wavelength conversion section (WLC2), a light-transmitting section (LTU), a second capping layer (CAP2), and a third planarization layer (OC3).

[0094] The first capping layer CAP1 can be disposed on the second planarization layer OC2 of the emitter element layer EML. The first capping layer CAP1 can seal the lower surface of the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU. The first capping layer CAP1 can include inorganic materials. For example, the first capping layer CAP1 can include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride.

[0095] The first light-shielding member BK1 can be disposed in the first light-shielding area BA1, the second light-shielding area BA2, and the third light-shielding area BA3 on the first cover layer CAP1. The first light-shielding member BK1 can overlap with the second embankment BNK2 in the thickness direction. The first light-shielding member BK1 can block the transmission of light. The first light-shielding member BK1 can improve the color gamut by preventing light from intruding and mixing between the first light-emitting area LA1, the second light-emitting area LA2, and the third light-emitting area LA3. When viewed from above, the first light-shielding member BK1 can be arranged in a lattice shape around the first light-emitting area LA1, the second light-emitting area LA2, and the third light-emitting area LA3.

[0096] The first light-shielding member BK1 may include an organic light-shielding material and a hydrophobic component. Herein, the hydrophobic component may consist of a fluorinated monomer or a fluorinated polymer, and specifically, may include a fluorinated aliphatic polycarbonate. For example, the first light-shielding member BK1 may be formed from a black organic material including the hydrophobic component. The first light-shielding member BK1 may be formed via a coating and exposure process for the organic light-shielding material containing the hydrophobic component, etc.

[0097] Since the first light-shielding member BK1 may include a hydrophobic component, the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU can be separated so that they correspond to their respective light-emitting regions LA. For example, if the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU can be formed by an inkjet method, the ink composition can flow on the upper surface of the first light-shielding member BK1. In this respect, the first light-shielding member BK1 may include a hydrophobic component, and therefore can guide the ink composition to flow towards the light-emitting region. Thus, the first light-shielding member BK1 can prevent the ink composition from mixing.

[0098] The first wavelength conversion unit WLC1 can be disposed on the first capping layer CAP1 in the first light-emitting region LA1. The first wavelength conversion unit WLC1 can be surrounded by the first light-shielding member BK1. The first wavelength conversion unit WLC1 may include the first base resin BS1, the first scatterer SCT1, and the first wavelength converter WLS1.

[0099] The first base resin BS1 may include a material having relatively high light transmittance. The first base resin BS1 may be formed from a transparent organic material. For example, the first base resin BS1 may include at least one organic material selected from epoxy resin, acrylic resin, calorie resin, and imide resin.

[0100] The first scatterer SCT1 may have a refractive index different from that of the first base resin BS1 and may form an optical interface with the first base resin BS1. For example, the first scatterer SCT1 may include light-scattering materials or light-scattering particles that scatter at least a portion of the transmitted light. For example, the first scatterer SCT1 may include metal oxides such as titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), and tin oxide (SnO2), or may include organic particles or combinations thereof such as acrylic resin and polyurethane resin. Regardless of the incident direction of the incident light, the first scatterer SCT1 can scatter light in any direction without substantially changing the peak wavelength of the incident light.

[0101] The first wavelength converter WLS1 can convert or transform the peak wavelength of the incident light into a first peak wavelength. For example, the first wavelength converter WLS1 can convert blue light provided from the display device 10 into red light having a single peak wavelength in the range of about 610 nm to about 650 nm, and emit that light. The first wavelength converter WLS1 can be a quantum dot, a quantum rod, or a phosphor. A quantum dot can be a particulate material that emits a color when an electron transitions from the conduction band to the valence band.

[0102] For example, quantum dots can be semiconductor nanocrystal materials. Quantum dots can have specific band gaps depending on their composition and size, and can absorb light and emit light with an inherent wavelength. Examples of semiconductor nanocrystals containing quantum dots can include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI compound nanocrystals, or combinations thereof.

[0103] For example, quantum dots can have a core-shell structure, which includes a core containing nanocrystals and a shell surrounding the core. The shell of a quantum dot can serve as a protective layer to maintain semiconductor properties by preventing chemical denaturation of the core, and can also serve as a charging layer to impart electrophoretic properties to the quantum dot. The shell can be a single layer or multiple layers. At the interface between the core and the shell, the concentration gradient of atoms in the shell can decrease towards the center. The shell of a quantum dot can be formed from oxides of metals or non-metals, semiconductor compounds, or combinations thereof.

[0104] The light emitted from the first wavelength converter WLS1 can have a full width at half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, about 40 nm or less, or about 30 nm or less. In this way, the color purity and color gamut of the colors displayed by the display device 10 can be further improved. Regardless of the incident direction of the incident light, the light emitted from the first wavelength converter WLS1 can propagate in different directions. Therefore, the lateral visibility of red displayed in the first emitting region LA1 can be improved.

[0105] A portion of the blue light emitted from the emitting element layer EML can pass through the first wavelength conversion section WLC1 without being converted into red light by the first wavelength converter WLS1. If this blue light is incident on the first color filter CF1, it can be blocked by the first color filter CF1. On the other hand, the red light converted from blue light by the first wavelength conversion section WLC1 can pass through the first color filter CF1 and exit to the outside. Therefore, the first emitting region LA1 can emit red light.

[0106] The second wavelength conversion unit WLC2 can be disposed on the first capping layer CAP1 within the second light-emitting region LA2. The second wavelength conversion unit WLC2 can be surrounded by the first light-shielding member BK1. The second wavelength conversion unit WLC2 may include a second base resin BS2, a second scatterer SCT2, and a second wavelength converter WLS2.

[0107] The second base resin BS2 may include a material with relatively high light transmittance. The second base resin BS2 may be formed from a transparent organic material. For example, the second base resin BS2 and the first base resin BS1 may be formed from the same material, or the second base resin BS2 may be formed from one of the aforementioned materials of the first base resin BS1.

[0108] The second scatterer SCT2 may have a refractive index different from that of the second base resin BS2, and may form an optical interface with the second base resin BS2. For example, the second scatterer SCT2 may include light-scattering material or light-scattering particles that scatter at least a portion of the transmitted light. For example, the second scatterer SCT2 and the first scatterer SCT1 may be formed of the same material, or the second scatterer SCT2 may be formed of one of the materials listed above for the first scatterer SCT1. Regardless of the incident direction of the incident light, the second scatterer SCT2 can scatter light in any direction without substantially changing the peak wavelength of the incident light.

[0109] The second wavelength converter WLS2 can convert or transform the peak wavelength of the incident light into a second peak wavelength, which may be different from the first peak wavelength of the first wavelength converter WLS1. For example, the second wavelength converter WLS2 can convert blue light provided from the display device 10 into green light having a single peak wavelength in the range of about 510 nm to about 550 nm, and emit such light. The second wavelength converter WLS2 may be a quantum dot, a quantum rod, or a phosphor. The second wavelength converter WLS2 may include the materials listed above for the first wavelength converter WLS1. The second wavelength converter WLS2 may be formed of quantum dots, quantum rods, phosphors, or combinations thereof, such that the wavelength conversion range of the second wavelength converter WLS2 may be different from the wavelength conversion range of the first wavelength converter WLS1.

[0110] The light-transmitting portion LTU can be disposed in the third light-emitting region LA3 on the first capping layer CAP1. The light-transmitting portion LTU can be surrounded by the first light-shielding member BK1. The light-transmitting portion LTU can transmit incident light without changing its peak wavelength. The light-transmitting portion LTU may include a third base resin BS3 and a third diffuser SCT3.

[0111] The third base resin BS3 may include a material with relatively high light transmittance. The third base resin BS3 may be formed from a transparent organic material. For example, the third base resin BS3, the first base resin BS1, and / or the second base resin BS2 may be formed from the same material, or the third base resin BS3 may be formed from one of the materials listed above, namely the first base resin BS1 and / or the second base resin BS2.

[0112] The third scatterer SCT3 may have a refractive index different from that of the third base resin BS3 and may form an optical interface with the third base resin BS3. For example, the third scatterer SCT3 may include light-scattering material or light-scattering particles that scatter at least a portion of the transmitted light. For example, the third scatterer SCT3, the first scatterer SCT1, and / or the second scatterer SCT2 may be formed of the same material, or the third scatterer SCT3 may be formed of one of the materials listed above for the first scatterer SCT1 and / or the second scatterer SCT2. Regardless of the incident direction of the incident light, the third scatterer SCT3 can scatter light in any direction without substantially changing the peak wavelength of the incident light.

[0113] The wavelength conversion layer WLCL can be disposed (e.g., directly disposed) on the second planarization layer OC2 of the emitting element layer EML, so that the display device 10 does not require separate substrates for the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU. Therefore, the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU can be easily aligned with the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3, respectively, so that the thickness of the display device 10 can be relatively reduced.

[0114] The second capping layer CAP2 can cover the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, the light-transmitting section LTU, and the first light-shielding member BK1. For example, the second capping layer CAP2 can seal the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU, thereby preventing damage or contamination to the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU. The second capping layer CAP2 and the first capping layer CAP1 can be formed of the same material, or the second capping layer CAP2 can be formed of the material of the first capping layer CAP1 listed above.

[0115] The third planarization layer OC3 may be disposed on the second capping layer CAP2 to provide a flat top surface for the first wavelength conversion section WLC1, the second wavelength conversion section WLC2, and the light-transmitting section LTU. The third planarization layer OC3 may include an organic material. For example, the third planarization layer OC3 may be at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0116] The color filter layer CFL may include a second light-shielding member BK2, a first color filter CF1, a second color filter CF2 and a third color filter CF3, and a third passivation layer PAS3.

[0117] The second light-shielding member BK2 can be disposed on the third planarization layer OC3 of the wavelength conversion layer WLCL within the first light-shielding region BA1, the second light-shielding region BA2, and the third light-shielding region BA3. The second light-shielding member BK2 can overlap with the first light-shielding member BK1 or the second embankment BNK2 in the thickness direction. The second light-shielding member BK2 can block light transmission. The second light-shielding member BK2 can improve the color gamut by preventing light from intruding and mixing between the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3. When viewed from above, the second light-shielding member BK2 can be arranged in a lattice shape surrounding the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3.

[0118] A first color filter CF1 may be disposed on the third planarization layer OC3 within the first light-emitting region LA1. The first color filter CF1 may be surrounded by a second light-shielding member BK2. The first color filter CF1 may overlap with the first wavelength conversion section WLC1 in the thickness direction. The first color filter CF1 may selectively transmit light of a first color (e.g., red light) and may block and absorb light of a second color (e.g., green light) and a third color (e.g., blue light). For example, the first color filter CF1 may be a red color filter and may include a red colorant. The red colorant may be formed from a red dye or red pigment.

[0119] A second color filter CF2 can be disposed on the third planarization layer OC3 within the second light-emitting region LA2. The second color filter CF2 can be surrounded by a second light-shielding member BK2. The second color filter CF2 can overlap with the second wavelength conversion section WLC2 in the thickness direction. The second color filter CF2 can selectively transmit light of a second color (e.g., green light) and can block and absorb light of a first color (e.g., red light) and a third color (e.g., blue light). For example, the second color filter CF2 can be a green color filter and can include a green colorant. The green colorant can be formed from a green dye or green pigment.

[0120] A third color filter CF3 can be disposed on the third planarization layer OC3 within the third light-emitting region LA3. The third color filter CF3 can be surrounded by a second light-shielding member BK2. The third color filter CF3 can overlap with the light-transmitting portion LTU in the thickness direction. The third color filter CF3 can selectively transmit light of a third color (e.g., blue light) and can block and absorb light of a first color (e.g., red light) and a second color (e.g., green light). For example, the third color filter CF3 can be a blue color filter and can include a blue colorant. The blue colorant can be formed from a blue dye or blue pigment.

[0121] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of the light introduced from the outside of the display device 10 to reduce the reflection of external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent color distortion caused by the reflection of external light.

[0122] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed (e.g., directly disposed) on the third planarization layer OC3 of the wavelength conversion layer WLCL, and therefore the display device 10 does not require separate substrates for the first color filter CF1, the second color filter CF2, and the third color filter CF3. Therefore, the thickness of the display device 10 can be relatively reduced.

[0123] The third passivation layer PAS3 can cover the first color filter CF1, the second color filter CF2, and the third color filter CF3. The third passivation layer PAS3 can protect the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0124] The encapsulation layer TFE can be disposed on the third passivation layer PAS3 of the color filter layer CFL. The encapsulation layer TFE can cover the upper surface and side surfaces of the display device 10. For example, the encapsulation layer TFE may include at least one inorganic layer to prevent the penetration of oxygen or moisture. The encapsulation layer TFE may include at least one organic layer to protect the display device 10 from impurities such as dust.

[0125] Figure 4 This is a schematic plan view showing the pixels of a display device according to an embodiment of the present disclosure.

[0126] Reference Figure 4 Each pixel PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may correspond to a first light-emitting region LA1, a second light-emitting region LA2, and a third light-emitting region LA3, respectively. The light-emitting diodes ED of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may emit light through the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3, respectively.

[0127] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can emit light of the same color. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can all include the same type of light-emitting diode (LED) and can emit light of a third color or blue light. As another example, the first sub-pixel SP1 can emit light of a first color or red light, the second sub-pixel SP2 can emit light of a second color or green light, and the third sub-pixel SP3 can emit light of a third color or blue light.

[0128] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a first electrode AE ​​and a second electrode CE, a light-emitting diode ED, a contact electrode CTE, and a second embankment BNK2.

[0129] The first electrode AE ​​and the second electrode CE can be electrically connected to a light-emitting diode ED to receive voltage, and the light-emitting diode ED can emit light of a certain wavelength band. At least a portion of the first electrode AE ​​and at least a portion of the second electrode CE can form an electric field in the pixel PX, and the light-emitting diode ED can be aligned by the electric field.

[0130] For example, the first electrode AE ​​can be a separate pixel electrode for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and the second electrode CE can be a common electrode extending across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. One of the first electrode AE ​​and the second electrode CE can be the anode electrode of the light-emitting diode ED, and the other can be the cathode electrode of the light-emitting diode ED.

[0131] The first electrode AE ​​may include a first electrode trunk AE1 extending in a first direction (X-axis direction) and at least one first electrode branch AE2 branching from the first electrode trunk AE1 and extending in a direction opposite to the second direction (Y-axis direction).

[0132] The first electrode AE1 of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be separated from the first electrode AE1 of the adjacent sub-pixel, and the first electrode AE1 can be arranged on an imaginary extension line with the first electrode AE1 of the sub-pixel adjacent in the first direction (X-axis direction). The first electrode AE1 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can receive different signals and can be driven individually.

[0133] The first electrode branch AE2 can branch from the first electrode trunk AE1 and can extend in a direction opposite to the second direction (Y-axis direction). One end of the first electrode branch AE2 can be connected to the first electrode trunk AE1, while the other end of the first electrode branch AE2 can be separated from the second electrode trunk CE1, which is opposite to the first electrode trunk AE1.

[0134] The second electrode CE may include a second electrode trunk CE1 extending in a first direction (X-axis direction) and a second electrode branch CE2 branching from the second electrode trunk CE1 and extending in a second direction (Y-axis direction). The second electrode trunk CE1 of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be connected to the second electrode trunk CE1 of the adjacent sub-pixel. The second electrode trunk CE1 may extend in the first direction (X-axis direction) to traverse the sub-pixels in pixel PX. The second electrode trunk CE1 may be connected to a portion extending in one direction at the outer portion of the display area DA or in the non-display area NDA.

[0135] The second electrode branch CE2 can be separated from the first electrode branch AE2 and face the first electrode branch AE2. One end of the second electrode branch CE2 can be connected to the second electrode trunk CE1, while the other end of the second electrode branch CE2 can be separated from the first electrode trunk AE1.

[0136] The first electrode AE ​​can be electrically connected to the thin-film transistor layer TFTL of the display device 10 through the first contact hole CNT1, and the second electrode CE can be electrically connected to the thin-film transistor layer TFTL of the display device 10 through the second contact hole CNT2. For example, the first contact hole CNT1 can be formed in each of the first electrodes AE1, and the second contact hole CNT2 can be formed in the second electrode CE1. However, it should be understood that this disclosure is not limited thereto.

[0137] The second dam portion BNK2 can be disposed at the boundary between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first electrode AE1 can be spaced apart from each other relative to the second dam portion BNK2. The second dam portion BNK2 can extend in a second direction (Y-axis direction) and can be disposed at the boundary of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 arranged in a first direction (X-axis direction). The second dam portion BNK2 can also be disposed at the boundary of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 arranged in a second direction (Y-axis direction). The second dam portion BNK2 can define the boundary of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0138] When ink containing dispersible light-emitting diodes (LEDs) is sprayed during the manufacturing process of the display device 10, the second dike portion BNK2 prevents the ink from flowing out of the boundaries of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The second dike portion BNK2 can separate the ink containing different LEDs, preventing the ink from mixing.

[0139] A light-emitting diode (LED) can be disposed between a first electrode AE ​​and a second electrode CE. One end of the LED can be connected to the first electrode AE, and the other end of the LED can be connected to the second electrode CE. For example, the LED can be connected to the first electrode AE ​​via a first contact electrode CTE1, and to the second electrode CE via a second contact electrode CTE2.

[0140] Light-emitting diodes (LEDs) can be spaced apart from each other and aligned substantially parallel to each other. In this document, the spacing between LEDs is not particularly limited. Some LEDs can be arranged adjacent to each other, some other LEDs can be spaced apart at a constant interval, and still others can be aligned in a certain direction with non-uniform density. For example, LEDs can be arranged in a direction perpendicular to the direction in which the first electrode branch AE2 or the second electrode branch CE2 can extend. As another example, LEDs can be arranged in a direction inclined relative to the direction in which the first electrode branch AE2 or the second electrode branch CE2 can extend.

[0141] Light-emitting diodes (EDs) may include active layers of the same material, enabling them to emit light within the same wavelength range or the same color. First sub-pixels SP1, second sub-pixels SP2, and third sub-pixels SP3 may emit light of the same color. For example, an ED may emit light of a third color or blue light having a peak wavelength in the range of approximately 440 nm to approximately 480 nm. Therefore, the emitting element layer EML of the display device 10 may emit light of a third color or blue light. As another example, first sub-pixels SP1, second sub-pixels SP2, and third sub-pixels SP3 may include EDs with different active layers and may emit light of different colors.

[0142] The contact electrode CTE may include a first contact electrode CTE1 and a second contact electrode CTE2. The first contact electrode CTE1 may cover a portion of the first electrode branch AE2 and the light-emitting diode ED, and may electrically connect the first electrode branch AE2 and the light-emitting diode ED. The second contact electrode CTE2 may cover another portion of the second electrode branch CE2 and the light-emitting diode ED, and may electrically connect the second electrode branch CE2 and the light-emitting diode ED.

[0143] The first contact electrode CTE1 can be disposed on the first electrode branch AE2 and extend in the second direction (Y-axis direction). The first contact electrode CTE1 can contact the first end of the light-emitting diode ED. The light-emitting diode ED can be electrically connected to the first electrode AE ​​through the first contact electrode CTE1.

[0144] The second contact electrode CTE2 can be disposed on the second electrode branch CE2 and extend in the second direction (Y-axis direction). The second contact electrode CTE2 can be spaced apart from the first contact electrode CTE1 in the first direction (X-axis direction). The second contact electrode CTE2 can contact the second terminal of the light-emitting diode ED. The light-emitting diode ED can be electrically connected to the second electrode CE through the second contact electrode CTE2.

[0145] For example, the widths of the first contact electrode CTE1 and the second contact electrode CTE2 can be greater than the widths of the first electrode branch AE2 and the second electrode branch CE2, respectively. As another example, the first contact electrode CTE1 and the second contact electrode CTE2 can cover one side of the first electrode branch AE2 and the second electrode branch CE2, respectively.

[0146] Figure 5 It is along Figure 4 A schematic cross-sectional view taken from line II-II'.

[0147] Reference Figure 5 The emission element layer EML of the display device 10 can be disposed on the thin film transistor layer TFTL, and can include a first insulating layer IL1, a second insulating layer IL2 and a third insulating layer IL3.

[0148] The first embankment BNK1 can be respectively disposed in the first light-emitting region LA1, the second light-emitting region LA2, and the third light-emitting region LA3. Each of the first embankment BNK1 can correspond to the first electrode AE ​​or the second electrode CE. Each of the first electrode AE ​​and the second electrode CE can be disposed on the corresponding first embankment BNK1. For example, each of the first electrode branch AE2 and the second electrode branch CE2 can be disposed on the corresponding first embankment BNK1. The first embankment BNK1 can include, but is not limited to, polyimide (PI).

[0149] The first dam portion BNK1 may be disposed on the first planarization layer OC1, and the side surface of each of the first dam portions BNK1 may be inclined from the first planarization layer OC1. For example, each of the first electrode AE ​​and the second electrode CE may contain a material with high reflectivity and may be disposed on the inclined surface of the first dam portion BNK1 to reflect light emitted from the light-emitting element EL toward the upper side of the display device 10.

[0150] Combination Figure 4 Reference Figure 5 The first electrode AE1 may include a first contact hole CNT1 penetrating the first planarization layer OC1. The first electrode AE1 can be electrically connected to the thin-film transistor TFT through the first contact hole CNT1. Therefore, the first electrode AE ​​can receive electrical signals from the thin-film transistor TFT.

[0151] The second electrode CE1 can extend in the first direction (X-axis direction) and can also be disposed in a non-emitting area where no light-emitting diode ED is disposed. The second electrode CE1 may include a second contact hole CNT2 penetrating the first planarization layer OC1. The second electrode CE1 can be electrically connected to the power electrode through the second contact hole CNT2. The second electrode CE can receive electrical signals from the power electrode.

[0152] The first electrode AE ​​and the second electrode CE may comprise a transparent conductive material. For example, each of the first electrode AE ​​and the second electrode CE may comprise, but is not limited to, at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO).

[0153] The first electrode AE ​​and the second electrode CE may comprise conductive materials with high reflectivity. For example, the first electrode AE ​​and the second electrode CE may comprise metals with high reflectivity, such as silver (Ag), copper (Cu), aluminum (Al), or combinations thereof. The first electrode AE ​​and the second electrode CE may reflect light incident from the light-emitting diode ED toward the upper side of the display device 10.

[0154] The first electrode AE ​​and the second electrode CE can be composed of a stack of one or more transparent conductive materials and one or more metals with high reflectivity, or a single layer comprising both. For example, the first electrode AE ​​and the second electrode CE can have a stacked structure of ITO / silver (Ag) / ITO / IZO, or can be an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc. However, it should be understood that this disclosure is not limited thereto.

[0155] A first insulating layer IL1 may be disposed on the first planarization layer OC1, the first electrode AE, and the second electrode CE. The first insulating layer IL1 may partially cover each of the first electrode AE ​​and the second electrode CE. For example, the first insulating layer IL1 may expose the portions of the first electrode AE ​​and the second electrode CE corresponding to the upper surface of the first embankment BNK1, and may cover other portions of the first electrode AE ​​and the second electrode CE that do not correspond to said upper surface. Therefore, the first insulating layer IL1 may include openings that expose the portions of the first electrode AE ​​and the second electrode CE corresponding to the upper surface of the first embankment BNK1.

[0156] For example, the first insulating layer IL1 may include an inorganic insulating material and may include a recessed portion between the first electrode AE ​​and the second electrode CE. The recessed portion of the first insulating layer IL1 may be filled by the second insulating layer IL2. Therefore, the second insulating layer IL2 can make the upper surface of the first insulating layer IL1 uniform, and thus the light-emitting diode ED can be disposed on the first insulating layer IL1 and the second insulating layer IL2.

[0157] The first insulating layer IL1 protects the first electrode AE ​​and the second electrode CE, and also insulates the first electrode AE ​​and the second electrode CE from each other. The first insulating layer IL1 prevents the light-emitting diode ED from directly contacting and being damaged by other components.

[0158] A light-emitting diode (LED) can be disposed on a first insulating layer IL1 and a second insulating layer IL2 between a first electrode AE ​​and a second electrode CE. One end of the LED can be connected to the first electrode AE, and the other end of the LED can be connected to the second electrode CE. For example, the LED can be connected to the first electrode AE ​​through a first contact electrode CTE1, and to the second electrode CE through a second contact electrode CTE2.

[0159] The third insulating layer IL3 can be partially disposed on the light-emitting diode ED located between the first electrode AE ​​and the second electrode CE. The third insulating layer IL3 can partially cover the outer surface of the light-emitting diode ED. The third insulating layer IL3 can protect the light-emitting diode ED.

[0160] The contact electrode CTE may include a first contact electrode CTE1 and a second contact electrode CTE2. The first contact electrode CTE1 may cover a portion of the first electrode branch AE2 and the light-emitting diode ED, and may electrically connect the first electrode branch AE2 and the light-emitting diode ED. The second contact electrode CTE2 may cover another portion of the second electrode branch CE2 and the light-emitting diode ED, and may electrically connect the second electrode branch CE2 and the light-emitting diode ED.

[0161] The contact electrode CTE may include conductive materials. For example, the contact electrode CTE may include, but is not limited to, ITO, IZO, ITZO, aluminum (Al), or combinations thereof.

[0162] Figure 6 This is a schematic view of a light-emitting element according to an embodiment of the present disclosure.

[0163] Reference Figure 6Light-emitting diodes (LEDs) can have micrometer or nanometer dimensions and can be inorganic LEDs containing inorganic materials. Inorganic LEDs can be aligned between two electrodes facing each other because they can generate polarity by forming an electric field in a specific direction between the two electrodes.

[0164] A light-emitting diode (LED) can have a shape that extends in one direction. An LED can have the shape of a rod, wire, tube, etc. For example, an LED can have a cylindrical or rod-shaped shape. As another example, an LED can have various shapes, including polygonal prism shapes such as cubes, cuboids, and hexagonal prisms, or shapes having a portion that extends in one direction and has a partially inclined section. The semiconductors included in the LED can have a structure in which they are arranged or stacked sequentially along one direction.

[0165] The light-emitting diode (ED) may include a first semiconductor layer 111, a second semiconductor layer 113, an active layer 115, an electrode layer 117, and an insulating layer 118.

[0166] The first semiconductor layer 111 may be an n-type semiconductor. For example, in the case where the light-emitting element EL emits blue light, the first semiconductor layer 111 may include a semiconductor material having the following chemical formula: Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). The first semiconductor layer 111 can be at least one of the following semiconductor materials selected from n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer 111 can be doped with n-type dopants such as Si, Ge, and Sn. The first semiconductor layer 111 can be n-GaN doped with n-type Si. The length of the first semiconductor layer 111 can be in the range of about 1.5 μm to about 5 μm, but is not limited thereto.

[0167] The second semiconductor layer 113 may be disposed on the active layer 115. For example, in the case where the light-emitting element EL emits blue or green light, the second semiconductor layer 113 may comprise a semiconductor material having the following chemical formula: Al x Ga y In 1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer 113 can be at least one of the following semiconductor materials selected from p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer 113 can be doped with p-type dopants such as Mg, Zn, Ca, Se, and Ba. The second semiconductor layer 113 can be p-GaN doped with p-type Mg. The length of the second semiconductor layer 113 can be in the range of about 0.05 μm to about 0.10 μm, but is not limited thereto.

[0168] Each of the first semiconductor layer 111 and the second semiconductor layer 113 may be composed of a single layer, but is not limited thereto. For example, each of the first semiconductor layer 111 and the second semiconductor layer 113 may have multiple layers including a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0169] An active layer 115 may be disposed between a first semiconductor layer 111 and a second semiconductor layer 113. The active layer 115 may comprise a material having a single quantum well structure or a multi-quantum well structure. When the active layer 115 comprises a material having a multi-quantum well structure, the quantum layers and well layers may be stacked alternately on top of each other. The active layer 115 may emit light when electron-hole pairs recombine in the active layer 115 in response to an electrical signal applied through the first semiconductor layer 111 and the second semiconductor layer 113. For example, when the active layer 115 emits blue light, it may comprise materials such as AlGaN and AlGaInN. When the active layer 115 has a multi-quantum well structure with quantum layers and well layers stacked alternately on top of each other, the quantum layers may comprise AlGaN, AlGaInN, etc., and the well layers may comprise GaN, AlInN, etc., or combinations thereof. The active layer 115 may comprise AlGaInN as a quantum layer and AlInN as a well layer to emit blue light.

[0170] In other embodiments, the active layer 115 may have a structure that includes group III to group V semiconductor materials depending on the wavelength range of the emitted light, in which semiconductor materials with large bandgap energy and semiconductor materials with small bandgap energy may be stacked alternately. The light emitted from the active layer 115 is not limited to blue light. In some embodiments, the active layer 115 may emit red or green light. The length of the active layer 115 may be in the range of about 0.05 μm to about 0.10 μm, but is not limited thereto.

[0171] Light emitted from the active layer 115 can exit in the longitudinal direction of the light-emitting diode (ED) and through both side surfaces. The directionality of the light emitted from the active layer 115 is unrestricted.

[0172] Electrode layer 117 may be an ohmic contact electrode. As another example, electrode layer 117 may be a Schottky contact electrode. A light-emitting diode (ED) may include at least one electrode layer 117. When the ED is electrically connected to an electrode or contact electrode CTE, electrode layer 117 may reduce the resistance between the ED and the electrode or contact electrode CTE. Electrode layer 117 may include a conductive metal. For example, electrode layer 117 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). Electrode layer 117 may include a semiconductor material doped with n-type or p-type impurities.

[0173] The insulating layer 118 may surround the outer surfaces of the semiconductor layer and the electrode layer. The insulating layer 118 may surround the outer surface of the active layer 115 and may extend in the direction in which the light-emitting diode ED can extend. The insulating layer 118 may protect the light-emitting diode ED. For example, the insulating layer 118 may surround the side surfaces of the light-emitting diode ED and may expose both ends of the light-emitting diode ED in the longitudinal direction.

[0174] Insulating layer 118 may include silicon oxide (SiO2) x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The insulating layer 118 is a material with insulating properties, such as aluminum nitride (AlN), aluminum oxide (Al2O3), or a combination thereof. Therefore, the insulating layer 118 can prevent electrical short circuits that may occur when the active layer 115 comes into contact with the electrodes through which electrical signals can be transmitted to the light-emitting element EL. Since the insulating layer 118 protects the outer surface of the light-emitting diode ED, including the active layer 115, a reduction in luminous efficiency can be prevented.

[0175] The connection structure used for the aforementioned video wall display TD will be described in detail below.

[0176] Figure 7 This is a plan view schematically illustrating the connection structure of a video wall display according to an embodiment of the present disclosure.

[0177] Reference Figure 7 A video wall display (TD) may include multiple display devices 10. Each display device 10 may include a first display device PA1 and a second display device PA2. Each of the first display device PA1 and the second display device PA2 may include a display area DA and a pad area PDA. The display area DA may include pixels PX to display an image. The pad area PDA may extend from the display area DA to surround or overlap with the display area DA, and may not display an image.

[0178] Specifically, each of the first display devices PA1 may include a first display area DA1 and a first pad area PDA1. The first pad area PDA1 may extend from the first display area DA1 to surround the first display area DA1. For example, the first pad area PDA1 may be respectively disposed on the four sides of the first display area DA1. Each of the second display devices PA2 may include a second display area DA2 and a second pad area PDA2. The second pad area PDA2 may be disposed to overlap with the second display area DA2 in the third direction (Z-axis direction) and may be disposed below the second display area DA2. The second pad area PDA2 may surround the second display area DA2. For example, the second pad area PDA2 may be respectively disposed on the four sides of the second display area DA2.

[0179] A video wall display TD can be formed by connecting adjacent display devices 10 to each other. The display devices 10 can be connected to each other using connecting or adhesive components. The pad areas PDA of each of the adjacent display devices 10 can overlap each other in the thickness direction (or Z-axis direction) of their respective display areas DA. Therefore, the display areas DA of the display devices 10 can be very close to each other, making the space between the display areas DA imperceptible to the viewer. Thus, the video wall display TD can eliminate the seams between the display devices 10 by preventing the space between them from being perceived, thereby immersing the viewer in the image.

[0180] The video wall display TD may include four first display devices PA1 and five second display devices PA2. The number and connection relationship of the display devices 10 are not limited to... Figure 7 The number and connection relationships of the implementation methods. The number of display devices 10 can be determined according to the size of the display devices 10 and the video wall display TD.

[0181] A flexible film FPCB can be disposed on the pad area PDA of each of the display devices 10. The flexible film FPCB can be attached to the pads disposed on the base component of each of the display devices 10. One side of the flexible film FPCB can be connected to the pad area PDA, while the other side of the flexible film FPCB can be connected to the source circuit board (not shown). The flexible film FPCB can transmit signals from the source driver SiC to the display device 10.

[0182] The source driver SICs can be individually disposed on the flexible film FPCB and can be connected to the pixels PX of the display device 10. For example, each of the source driver SICs can be an integrated circuit (IC). The source driver SICs can convert digital video data into analog data voltages based on source control signals from a timing controller, and can provide the analog data voltages to the data lines of the display area DA through the flexible film FPCB. In addition, the gate driver GIC can also be disposed on the flexible film FPCB, and the gate driver GIC can provide gate control signals to the gate lines of the display area DA.

[0183] The flexible film FPCB can be disposed on the pad area PDA along the edge of the video wall display TD. For example, the flexible film FPCB can be disposed on the first pad area PDA1 of each of the first display devices PA1 and the second pad area PDA2 of each of the second display devices PA2. However, it should be understood that this disclosure is not limited thereto.

[0184] Figure 8 This is a schematic plan view of a first display device according to an embodiment of the present disclosure. Figure 9 This is a schematic cross-sectional view of a first display device according to an embodiment of the present disclosure. Figure 10 It is shown schematically. Figure 9 A magnified view of region A.

[0185] Reference Figure 8 According to an embodiment of the present disclosure, a first display device PA1 may include a first display area DA1 and a first pad area PDA1 surrounding the first display area DA1. The first pad area PDA1 may extend from the longer side of the first display area DA1 extending in a first direction (X-axis direction) and the shorter side of the first display area DA1 extending in a second direction (Y-axis direction).

[0186] Each of the first pad areas PDA1 may include a recess HO. Signal lines extending from the first display area DA1 may be exposed through the recess HO and may be used as connecting components between adjacent second display devices PA2 and / or flexible film FPCB.

[0187] The recesses HO can be spaced apart from each other in each of the first pad areas PDA1. Each recess HO can correspond to at least one first signal line. For example, signal lines can extend from the first display area DA1 to the first pad area PDA1 and can be combined into first signal lines in the first pad area PDA1 such that the first signal lines can be exposed through a recess HO. However, it should be understood that this disclosure is not limited thereto. One first signal line can correspond to one recess HO. The gap and number of recesses HO can be adjusted in various ways according to the size of the first display device PA1.

[0188] Reference Figure 9 The first display device PA1 may include a substrate SUB, a thin film transistor layer TFTL, an emitter element layer EML, a wavelength conversion layer WLCL, a color filter layer CFL, and an encapsulation layer TFE.

[0189] In the first display area DA1, the substrate SUB, thin film transistor layer TFTL, emitter element layer EML, wavelength conversion layer WLCL, color filter layer CFL, and encapsulation layer TFE can overlap each other. In the first pad area PDA1, the substrate SUB and thin film transistor layer TFTL can overlap each other, while the emitter element layer EML, wavelength conversion layer WLCL, color filter layer CFL, and encapsulation layer TFE can be omitted.

[0190] Each of the first pad regions PDA1 may include a recess HO. The recess HO may be formed in at least some layers of the thin-film transistor layer TFTL.

[0191] Reference Figure 10 In the first pad area PDA1 of the first display device PA1, a substrate SUB and a thin film transistor layer TFTL can be disposed.

[0192] Specifically, the substrate SUB may include a first base substrate PI1, a barrier layer BAR, and a second base substrate PI2. A thin-film transistor layer (TFTL) may be disposed on the substrate SUB. In the TFTL, a gate insulator GI may be disposed on a buffer layer BF, and an interlayer dielectric layer (ILD) may be disposed on the gate insulator GI. A first signal line SSL1 may be disposed on the interlayer dielectric layer ILD. The first signal line SSL1 may be connected to a data line of the first display area DA1. A first passivation layer PAS1 may be disposed on the first signal line SSL1, and a first planarization layer OC1 may be disposed on the first passivation layer PAS1.

[0193] According to embodiments of this disclosure, the groove HO can penetrate the first passivation layer PAS1 and the first planarization layer OC1 to expose the first signal line SSL1. The groove HO may include a portion penetrating the first passivation layer PAS1. First through hole PH1A second via PH2 penetrates the first planarization layer OC1. When viewed from the top, the groove HO can have, but is not limited to, a circular shape, an elliptical shape, a polygonal shape, etc. The diameter W1 of the groove HO can range from about 3 μm to about 500 μm and can be adjusted in various ways according to the size of the video wall display TD. The groove HO can be formed by laser drilling technology. Green lasers, infrared lasers, ultraviolet lasers, etc., can be used for laser drilling technology. However, it should be understood that this disclosure is not limited thereto. The groove HO can be formed by photolithography.

[0194] The recess HO may include a first connection pattern MTP1 to facilitate connection with the second display device PA2. The first connection pattern MTP1 may be disposed on the first planarization layer OC1 and may contact the interior of the recess HO. Specifically, the first connection pattern MTP1 may contact the upper surface of the first planarization layer OC1, the side surface of the first planarization layer OC1, the side surface of the first passivation layer PAS1, and the upper surface of the first signal line SSL1.

[0195] The first connection pattern MTP1 may be exposed to the outside and therefore may be susceptible to corrosion or oxidation. Therefore, the first connection pattern MTP1 may be formed of a metal oxide to prevent corrosion or oxidation. For example, the first connection pattern MTP1 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or combinations thereof, but is not limited thereto.

[0196] Figure 11 This is a schematic plan view of a second display device according to an embodiment of the present disclosure. Figure 12 This is a schematic cross-sectional view of a second display device according to an embodiment of the present disclosure. Figure 13 It is shown schematically. Figure 12 A magnified view of region B.

[0197] Reference Figure 11 According to embodiments of the present disclosure, the second display device PA2 may include a second display area DA2 and a second pad area PDA2 surrounding the second display area DA2. The second pad areas PDA2 may be configured such that they overlap with the longer side of the second display area DA2 extending in a first direction (X-axis direction) and the shorter side of the second display area DA2 extending in a second direction (Y-axis direction), respectively.

[0198] Each of the second pad areas PDA2 may include a hole HOL. A second signal line extending from the second display area DA2 may be exposed through the hole HOL, and the second signal line extending from the second display area DA2 may be used as a connection component between the adjacent first display device A1 and / or the flexible film FPCB.

[0199] Hole holes (HOLs) can be spaced apart from each other in each of the second pad areas (PDA2). Each hole hole (HOL) can correspond to at least one second signal line. For example, second signal lines can extend from the second display area (DA2) to the second pad area (PDA2) and can be combined in the second pad area (PDA2) to form a second signal line that can be exposed through a hole hole (HOL). However, it should be understood that this disclosure is not limited thereto. One second signal line can correspond to one hole hole (HOL). The spacing and number of hole holes (HOLs) can be adjusted in various ways according to the size of the second display device (PA2).

[0200] Reference Figure 12 The second display device PA2 may include a substrate SUB, a thin film transistor layer TFTL, an emitter element layer EML, a wavelength conversion layer WLCL, a color filter layer CFL, and an encapsulation layer TFE.

[0201] In the second display area DA2, the substrate SUB, thin-film transistor layer TFTL, emitter element layer EML, wavelength conversion layer WLCL, color filter layer CFL, and encapsulation layer TFE can overlap each other. The second pad area PDA2 can overlap with the second display area DA2 and can be the edge of the second display area DA2. For example, in the second pad area PDA2, the substrate SUB, thin-film transistor layer TFTL, emitter element layer EML, wavelength conversion layer WLCL, color filter layer CFL, and encapsulation layer TFE can overlap each other.

[0202] The second pad region PDA2 may include multiple holes HOL. The holes HOL may be formed in at least some layers of the substrate SUB and the thin-film transistor layer TFTL.

[0203] Reference Figure 13 In the second pad area PDA2 of the second display device PA2, a substrate SUB, a thin film transistor layer TFTL, an emitter element layer EML, a wavelength conversion layer WLCL, a color filter layer CFL, and an encapsulation layer TFE can be disposed.

[0204] Specifically, the substrate SUB may include a first base substrate PI1, a barrier layer BAR, and a second base substrate PI2. A thin-film transistor layer (TFTL) may be disposed on the substrate SUB. In the TFTL, a gate insulator GI may be disposed on a buffer layer BF, and an interlayer dielectric layer (ILD) may be disposed on the gate insulator GI. A second signal line SSL2 may be disposed on the interlayer dielectric layer ILD. The second signal line SSL2 may be connected to the data line of the second display area DA2. A first passivation layer PAS1 may be disposed on the second signal line SSL2, and a first planarization layer OC1 may be disposed on the first passivation layer PAS1. An emitter element layer (EML), a wavelength conversion layer (WLCL), a color filter layer (CFL), and a packaging layer (TFE) may be disposed on the first planarization layer OC1.

[0205] According to embodiments of this disclosure, a hole HOL can be formed in at least a portion of a substrate SUB and a thin-film transistor layer TFTL. Specifically, the hole HOL can penetrate the first base substrate PI1, the barrier layer BAR, the second base substrate PI2, the buffer layer BF, the gate insulator GI, and the interlayer dielectric layer ILD to expose the second signal line SSL2. The hole HOL may include a third via PH3 penetrating the first base substrate PI1, a fourth via PH4 penetrating the barrier layer BAR, a fifth via PH5 penetrating the second base substrate PI2, a sixth via PH6 penetrating the buffer layer BF, a seventh via PH7 penetrating the gate insulator GI, and an eighth via PH8 penetrating the interlayer dielectric layer ILD. The hole HOL can be formed using laser drilling technology in the same manner as the aforementioned groove HO, but this disclosure is not limited thereto. It can be formed via photolithography.

[0206] When viewed from above, the hole HOL can have, but is not limited to, a circular shape, an elliptical shape, a polygonal shape, etc. When viewed from above, the shape of the hole HOL can correspond to the shape of the groove HO described above. The diameter W2 of the hole HOL can be in the range of approximately 3 μm to approximately 500 μm, and can be smaller than the diameter W1 of the groove HO.

[0207] The hole HOL may include a second connection pattern MTP2 to facilitate connection with the first display device PA1. The hole HOL may be filled with the second connection pattern MTP2, which may be a protrusion connected to the second signal line SSL2 and protruding to the outside of the first base substrate PI1. Specifically, the second connection pattern MTP2 may contact the side surface of the first base substrate PI1, the side surface of the barrier layer BAR, the side surface of the second base substrate PI2, the side surface of the buffer layer BF, the side surface of the gate insulator GI, the side surface of the interlayer dielectric layer ILD, and the lower surface of the second signal line SSL2.

[0208] The diameter of the second connection pattern MTP2 can be equal to the diameter W2 of the hole HOL. The second connection pattern MTP2 can protrude beyond the first base substrate PI1 to be inserted into the recess HO of the first display device PA1. The diameter of the second connection pattern MTP2 can be smaller than the diameter W1 of the recess HO, allowing it to be easily inserted into the recess HO. The height H1 of the second connection pattern MTP2 protruding beyond the first base substrate PI1 can be greater than the depth of the recess HO of the first display device PA1. Therefore, the second connection pattern MTP2 can be easily inserted into the recess HO.

[0209] The second connection pattern MTP2 can be formed of a conductive material, such that the hole HOL can be filled by the second connection pattern MTP2, and the second connection pattern MTP2 can be connected to the first connection pattern MTP1 of the recess HO. For example, the conductive material can be a metal, and can be a metal layer on which metals can be stacked, a metal pin with a pin shape, or a silver (Ag) dot. However, it should be understood that this disclosure is not limited thereto.

[0210] The connection structure between the first display device PA1 and the second display device PA2 according to the above embodiment will be described below.

[0211] Figure 14 This is a schematic cross-sectional view showing a first display device and a second display device connected to each other according to an embodiment of the present disclosure. Figure 15 It is shown schematically. Figure 14 A magnified view of region C.

[0212] Reference Figure 14 The first display device PA1 and the second display device PA2 can be electrically connected to each other. The first pad area PDA1 of the first display device PA1 can overlap with the second pad area PDA2 of the second display device PA2. Although the first display area DA1 of the first display device PA1 and the second display area DA2 of the second display device PA2 can contact each other, this disclosure is not limited thereto. They can be separated from each other by a minimum distance. The upper surface of the first pad area PDA1 of the first display device PA1 can contact the lower surface of the second pad area PDA2 of the second display device PA2. The second connection pattern MTP2 provided in the second pad area PDA2 of the second display device PA2 can be inserted into the groove HO formed in the first pad area PDA1 of the first display device PA1, so that the second connection pattern MTP2 and the groove HO can be connected to each other.

[0213] Specifically, refer to Figure 15In the first display device PA1, a first signal line SSL1 may be disposed on the interlayer dielectric layer ILD. A first passivation layer PAS1 may be disposed on the first signal line SSL1, and a first planarization layer OC1 may be disposed on the first passivation layer PAS1. A groove HO may penetrate the first passivation layer PAS1 and the first planarization layer OC1 to expose the first signal line SSL1. A first connection pattern MTP1 may be disposed on the first planarization layer OC1 and may contact the interior of the groove HO.

[0214] In the second display device PA2, the second signal line SSL2 can be disposed on the interlayer dielectric layer ILD, the first passivation layer PAS1 can be disposed on the second signal line SSL2, and the first planarization layer OC1 can be disposed on the first passivation layer PAS1. A via HOL can penetrate the first base substrate PI1, the barrier layer BAR, the second base substrate PI2, the buffer layer BF, the gate insulator GI, and the interlayer dielectric layer ILD to expose the second signal line SSL2. The via HOL can be filled with a second connection pattern MTP2, which can be connected to the second signal line SSL2 and protrude beyond the first base substrate PI1.

[0215] The second connection pattern MTP2 of the second display device PA2 can be inserted into the groove HO of the first display device PA1. Specifically, the second connection pattern MTP2 can be disposed adjacent to the first connection pattern MTP1 disposed in the groove HO of the first display device PA1. An anisotropic conductive film ACF can be disposed between the first connection pattern MTP1 of the first pad area PDA1 of the first display device PA1 and the second connection pattern MTP2 of the second pad area PDA2 of the second display device PA2. In the anisotropic conductive film ACF, conductive balls can be mixed in the adhesive resin. Therefore, electricity can be transmitted through the conductive balls, and the connection pattern can be attached.

[0216] An anisotropic conductive film (ACF) can electrically connect the first connection pattern MTP1 and the second connection pattern MTP2. The ACF can contact each of the first connection pattern MTP1 and the second connection pattern MTP2, and can also contact the surface of the first planarization layer OC1 of the first display device PA1 and the surface of the first base substrate PI1 of the second display device PA2. The first connection pattern MTP1 of the first display device PA1 can be connected to the second connection pattern MTP2 of the second display device PA2 via a thermo-pressing process using the ACF.

[0217] Therefore, since the first connection pattern MTP1 can be connected to the second connection pattern MTP2, the data line of the first display device PA1 can be connected to the data line of the second display device PA2. Similarly, the first connection pattern MTP1 connected to the gate line can be formed in another first pad area PDA1 of the first display device PA1, so that the gate line can be connected to each other through the second connection pattern MTP2 connected to the gate line in the second pad area PDA2 of the second display device PA2 and the first connection pattern MTP1 connected to the gate line in the other first pad area PDA1 of the first display device PA1.

[0218] The first display device PA1 and the second display device PA2 connected in this way can be connected to the flexible film FPCB through other first pad areas PDA1 and second pad areas PDA2.

[0219] Figure 16 It is schematically shown along Figure 7 The first display device is a cross-sectional view taken by line III-III'. Figure 17 It is schematically shown along Figure 7 The image shows a cross-sectional view of the second display device taken by line IV-IV'. In the following description, elements identical to those described above will be briefly described or omitted.

[0220] Reference Figure 16 The first display device PA1 may include a first pad region PDA1 extending from the first display area DA1. A flexible film FPCB may be connected to the first pad region PDA1. Specifically, the first pad region PDA1 may include a groove HO formed in a thin-film transistor layer TFTL, and a first connection pattern MTP1 may be disposed in the groove HO. The flexible film FPCB may be connected to the first connection pattern MTP1 via an anisotropic conductive film ACF to transmit external data or gate signals to the first display area DA1.

[0221] Reference Figure 17 The second display device PA2 may include a second pad region PDA2 located at an edge overlapping with the second display area DA2. A flexible film FPCB may be connected to the second pad region PDA2. Specifically, the second pad region PDA2 may include a hole HOL formed in the substrate SUB and the thin film transistor layer TFTL, and a second connection pattern MTP2 may be disposed in the hole HOL. The flexible film FPCB may be connected to the second connection pattern MTP2 via an anisotropic conductive film ACF to transmit external data or gate signals to the second display area DA2.

[0222] As described above, according to embodiments of the present disclosure, the first display device PA1 may have a recess HO, and the second display device PA2 may have a protrusion, and therefore the video wall display TD can be formed by connecting the recess HO and the protrusion. Thus, the video wall display TD can immerse the viewer in the image by suppressing the perception of the boundary between the display areas DA of the display device 10.

[0223] Figure 18 This is a schematic cross-sectional view of a second display device according to another embodiment. Figure 19 It is shown schematically. Figure 18 A magnified view of region D. Figure 20 This is a schematic cross-sectional view of a first display device and a second display device connected to each other according to another embodiment.

[0224] according to Figure 18 and Figure 19 The second display device PA2 in the embodiment may include a plurality of holes HOL formed in the second pad area PDA2. Figure 18 and Figure 19 The implementation method is the same as described above. Figures 11 to 17 The implementation may differ in that the substrate SUB of the second pad region PDA2 may have a step ST. In the following description, the description will focus on the differences and redundant descriptions will be omitted.

[0225] Reference Figure 18 The second display device PA2 may include a substrate SUB, a thin film transistor layer TFTL, an emitter element layer EML, a wavelength conversion layer WLCL, a color filter layer CFL, and an encapsulation layer TFE.

[0226] The second pad region PDA2 may include vias HOL. The vias HOL may be formed in at least some layers of the substrate SUB and the thin-film transistor layer TFTL. Each of the second pad regions PDA2 may include a step ST. The step ST may be a portion of the substrate SUB in each of the second pad regions PDA2 that is thinner than another portion. The step ST may be formed in at least a portion of the second pad region PDA2, or it may be formed throughout the entire second pad region PDA2. Multiple vias HOL may be formed in the step ST, and a second connection pattern MTP2 may be provided.

[0227] Reference Figure 19 In the second pad area PDA2 of the second display device PA2, a substrate SUB, a thin film transistor layer TFTL, an emitter element layer EML, a wavelength conversion layer WLCL, a color filter layer CFL, and an encapsulation layer TFE can be disposed.

[0228] A step ST can be formed in the second pad region PDA2. The step ST can be formed by removing at least a portion of the first base substrate PI1, the barrier layer BAR, and the second base substrate PI2. The step ST can reduce the horizontal plane difference in the second direction (Y-axis direction) between the first display area PA1 and the second display area PA2 that may be formed when the first display device PA1 and the second display device PA2 can be connected to each other.

[0229] Although, according to embodiments, the step ST can be formed by partially removing the first base substrate PI1, the barrier layer BAR, and the second base substrate PI2, this disclosure is not limited thereto. The step ST can be formed by removing at least a portion of the first base substrate PI1, or at least a portion of the barrier layer BAR and the first base substrate PI1. In other embodiments, the step ST can be formed by completely removing the first base substrate PI1, the barrier layer BAR, and the second base substrate PI2. In the step ST, the side surfaces of the first base substrate PI1 and the barrier layer BAR can overlap with the lower surface of the second base substrate PI2.

[0230] Reference Figure 20 The first display device PA1 and the second display device PA2 can be connected to each other and can be electrically connected to each other. The first pad area PDA1 of the first display device PA1 can overlap with the second pad area PDA2 of the second display device PA2.

[0231] A step ST formed in the second pad area PDA2 of the second display device PA2 can contact the first pad area PDA1 of the first display device PA1. Specifically, the side surface of the step ST can contact the side surface of the first pad area PDA1 of the first display device PA1, and the surface of the step ST located in the second direction (Y-axis direction) can contact the upper surface of the first pad area PDA1. A second connection pattern MTP2 provided in the hole HOL of the second pad area PDA2 of the second display device PA2 can be inserted into the groove HO formed in the first pad area PDA1 of the first display device PA1, so that they can be connected to each other.

[0232] In this way, the difference in horizontal plane between the upper surface of the first display device PA1 and the upper surface of the second display device PA2 in the second direction (Y-axis direction) can be reduced, thereby avoiding the seam of the spliced ​​display TD from being detected.

[0233] Figure 21 and Figure 22 This is a schematic plan view of a video wall display according to other embodiments of the present disclosure.

[0234] Reference Figure 21 ,and Figure 7 Unlike the flat, tiled display TD, according to Figure 21 The splicing display TD of the embodiment can be applied to a three-dimensional splicing display TD. When the splicing display TD has a pentagonal prism shape, the second display device PA2 can be positioned at the center, and the first display devices PA1 can be respectively positioned on the five sides of the second display device PA2. Each side of the first display device PA1 can contact the side of an adjacent first display device PA1. The flexible film FPCB can be removed from the sides of the first display devices PA1 that can contact each other, thus allowing the first display devices PA1 to contact each other.

[0235] according to Figure 22 In this implementation, each of the display devices 10 in the tiled display TD can have a hexagonal shape. In this example, the second display device PA2 can be located at the center, and the first display devices PA1 can be respectively located on the sides of the second display device PA2. Figure 21 Similarly, the flexible film FPCB can be removed from the sides of the first display devices PA1 that can contact each other, and thus the first display devices PA1 can contact each other.

[0236] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of this disclosure. Therefore, the embodiments of this disclosure are intended for general and descriptive purposes only and not for limiting purposes.

Claims

1. A tiled display comprising: a first display device including a first display area and a first pad area having a recess; a second display device including a second display area and a second pad area overlapping the second display area, the second pad area having a protrusion; and an anisotropic conductive film disposed between the first pad area and the second pad area, wherein the protrusion is inserted into the recess to connect the first pad area and the second pad area, the first pad area includes a first connection pattern contacting an inside of the recess, the second pad area includes a second connection pattern forming the protrusion, and the anisotropic conductive film is disposed between the first connection pattern and the second connection pattern. 2.The tiled display of claim 1, wherein the first pad area includes a first signal line extending from the first display area, the recess exposes the first signal line, and the first connection pattern contacts the first signal line through the recess.

3. The tiled display of claim 1, wherein, the second pad area includes: a second signal line extending from the second display area; and a hole exposing the second signal line.

4. The tiled display of claim 3, wherein, the second connection pattern contacts the second signal line through the hole. 5.The tiled display of claim 3, wherein a diameter of the second connection pattern is equal to a diameter of the hole, and the diameter of the second connection pattern is smaller than a diameter of the recess. 6.The tiled display of claim 1, wherein the second display device includes a substrate, the second connection pattern protrudes to an outside of the substrate, and a height of the second connection pattern protruding from the substrate is greater than a depth of the recess of the first pad area.

7. The tiled display of claim 1, wherein, each of the first connection patterns includes at least one of ITO, IZO, and ITZO.

8. The tiled display of claim 1, wherein, the second connection pattern includes at least one of a metal layer, a metal pin, and a silver dot.

9. The tiled display of claim 1, wherein, the first pad area does not overlap the first display area and overlaps the second pad area. 10.A tiled display comprising: a first display device including a first display area and a first pad area having a recess; a second display device including a second display area and a second pad area overlapping the second display area, the second pad area having a protrusion; and an anisotropic conductive film disposed between the first pad area and the second pad area, wherein the second display device includes a substrate and a step in the second pad area, the step including a thinner portion of the substrate, and the protrusion is inserted into the recess to connect the first pad area and the second pad area, the first pad area includes a first connection pattern contacting an inside of the recess, the second pad area includes a second connection pattern forming the protrusion, and 11. The tiled display of claim 10, wherein, the anisotropic conductive film is disposed between the first connection pattern and the second connection pattern. the substrate includes: a first base substrate; a barrier layer disposed on the first base substrate; and a second base substrate disposed on the barrier layer, wherein the step is formed by removing at least a portion of the first base substrate, the barrier layer, and the second base substrate in the second pad area, is formed by removing at least a portion of the first base substrate in the second pad area, or is formed by removing at least a portion of the barrier layer and the first base substrate in the second pad area.

12. The tiled display of claim 11, wherein, the first pad area includes a first signal line extending from the first display area, the recess exposes the first signal line, and the first connection pattern contacts the first signal line through the recess.

13. The tiled display of claim 12, wherein, the second pad area includes: a second signal line extending from the second display area; and an aperture exposing the second signal line, and the second connection pattern contacts the second signal line through the aperture.

14. The tiled display of claim 13, wherein, the first signal line is a first gate line, the second signal line is a second gate line, and the first connection pattern is a first gate connection pattern.

15. The tiled display of claim 14, wherein, the first gate line extends from a first gate driver on the first display area, the second gate line extends from a second gate driver on the second display area, the first gate connection pattern contacts the first gate line through the aperture, and the second gate connection pattern contacts the second gate line through the aperture.

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