Semiconductor memory device and system including semiconductor memory device

Abstract

A semiconductor memory device and a system including the same are disclosed. The semiconductor memory device includes an interface semiconductor wafer, at least one memory semiconductor wafer, and a silicon through-hole device connecting the interface semiconductor wafer and the memory semiconductor wafer. The interface semiconductor wafer includes a command pin for receiving command signals transmitted from a memory controller and an interface command decoder for decoding the command signals. The memory semiconductor wafer includes a memory integrated circuit configured to store data and a memory command decoder for decoding the command signals transmitted from the interface semiconductor wafer. The interface semiconductor wafer does not include a clock enable pin for receiving a clock enable signal from the memory controller. The interface command decoder and the memory command decoder generate an interface clock enable signal and a memory clock enable signal to control the clock supply of the interface semiconductor wafer and the memory semiconductor wafer based on power mode commands transmitted from the memory controller via multiple command pins.

Description

[0001] Cross-reference to related applications

[0002] Korean Patent Application No. 10-2020-0119732, entitled "Semiconductor Memory Device and System Including Semiconductor Memory Device", filed on September 17, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments relate to semiconductor integrated circuits, and more specifically, to semiconductor memory devices and systems including semiconductor memory devices. Background Technology

[0004] Integrated circuits can be integrated within a limited area to achieve high capacity, miniaturization, and high operating speed. The storage capacity and speed of semiconductor memory devices can be increased by increasing hardware speed and software complexity. Multiple semiconductor chips can be stacked in a memory chip package to increase the memory capacity of the same area. Summary of the Invention

[0005] An embodiment relates to a semiconductor memory device, comprising: an interface semiconductor wafer including a plurality of command pins configured to receive a plurality of command signals transmitted from a memory controller, and an interface command decoder configured to decode the plurality of command signals; a memory semiconductor wafer stacked with the interface semiconductor wafer, the memory semiconductor wafer including a memory integrated circuit configured to store data, and a memory command decoder configured to decode the plurality of command signals transmitted from the interface semiconductor wafer; and a plurality of silicon through-holes electrically connecting the interface semiconductor wafer and the memory semiconductor wafer. The interface semiconductor wafer may not include a clock enable pin for receiving a clock enable signal from the memory controller. The interface command decoder may be configured to generate an interface clock enable signal to control a first clock supply relative to the interface semiconductor wafer based on power mode commands transmitted from the memory controller via the plurality of command pins. The memory command decoder may be configured to generate a memory clock enable signal to control a second clock supply relative to the memory semiconductor wafer based on power mode commands transmitted from the interface semiconductor wafer via the plurality of silicon through-holes.

[0006] The embodiments also relate to a system including: a semiconductor memory device; and a host device including a memory controller configured to control the semiconductor memory device. The semiconductor memory device may include: an interface semiconductor wafer including a plurality of command pins configured to receive a plurality of command signals transmitted from the memory controller, and including an interface command decoder configured to decode the plurality of command signals; a memory semiconductor wafer stacked with the interface semiconductor wafer, the memory semiconductor wafer including a memory integrated circuit configured to store data, and including a memory command decoder configured to decode the plurality of command signals transmitted from the interface semiconductor wafer; and a plurality of silicon through-holes electrically connecting the interface semiconductor wafer and the memory semiconductor wafer. The interface semiconductor wafer may not include a clock enable pin for receiving a clock enable signal from the memory controller. The interface command decoder may be configured to generate an interface clock enable signal to control a first clock supply relative to the interface semiconductor wafer based on power mode commands transmitted from the memory controller via the plurality of command pins. The memory command decoder may be configured to generate a memory clock enable signal to control a second clock supply relative to the memory semiconductor wafer based on power mode commands transmitted from the interface semiconductor wafer via the plurality of silicon through-holes.

[0007] The embodiments also relate to a semiconductor memory device, comprising: an interface semiconductor wafer including a plurality of command pins configured to receive a plurality of command signals transmitted from a memory controller, and including an interface command decoder configured to decode the plurality of command signals; a memory semiconductor wafer including a memory integrated circuit configured to store data, and including a memory command decoder configured to decode the plurality of command signals transmitted from the interface semiconductor wafer; and a plurality of internal command paths electrically connecting the interface semiconductor wafer to the memory semiconductor wafer. The interface semiconductor wafer may not include a clock enable pin for receiving a clock enable signal from the memory controller. The interface command decoder may be configured to generate an interface clock enable signal to control a first clock supply relative to the interface semiconductor wafer based on power mode commands transmitted from the memory controller via the plurality of command pins. The memory command decoder may be configured to generate a memory clock enable signal to control a second clock supply relative to the memory semiconductor wafer based on power mode commands transmitted from the interface semiconductor wafer via the plurality of internal command paths. Attached Figure Description

[0008] The features will become clear to those skilled in the art from a detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an example embodiment;

[0010] Figure 2 This is a diagram illustrating an example embodiment of a clock enable signal generator included in a semiconductor memory device according to an example embodiment;

[0011] Figure 3 It is shown Figure 2 Timing diagram of the operation of the clock enable signal generator;

[0012] Figure 4 This is a diagram illustrating an example embodiment of a clock gating circuit included in a semiconductor memory device according to an example embodiment;

[0013] Figure 5 It is shown Figure 4 The timing diagram of the operation of the clock gating circuit;

[0014] Figure 6 This is a diagram illustrating an example embodiment of a memory integrated circuit included in a semiconductor memory device according to an example embodiment;

[0015] Figure 7 This is an exploded perspective view of a system including a stacked memory device according to an example embodiment;

[0016] Figure 8 This is a diagram illustrating a high-bandwidth memory (HBM) device according to an example embodiment;

[0017] Figure 9 This is a diagram illustrating an example interface of a system including an HBM device according to an example embodiment;

[0018] Figure 10 and Figure 11 This is a diagram illustrating an example embodiment of commands for an HBM device according to an example embodiment;

[0019] Figure 12 , Figure 13 and Figure 14 It is shown Figure 10 A diagram illustrating the power mode commands included in the commands;

[0020] Figure 15 and Figure 16 This is a timing diagram illustrating the entry and exit of power modes in an HBM device according to an example embodiment;

[0021] Figure 17 This is a diagram illustrating the switching of operating modes in an HBM device according to an example embodiment;

[0022] Figure 18 This is a diagram illustrating an example embodiment of the decoding logic included in the command decoder of HBM according to an example embodiment;

[0023] Figure 19 This is a diagram illustrating the operation of the power mode in an HBM device according to an example embodiment;

[0024] Figure 20 This is a diagram illustrating an example embodiment of the decoding logic included in the command decoder of HBM according to an example embodiment;

[0025] Figure 21 It is shown Figure 2 Timing diagram of the operation of the clock enable signal generator;

[0026] Figure 22 This is a diagram illustrating the operation of the power mode in an HBM device according to an example embodiment;

[0027] Figure 23 and Figure 24 This is a diagram illustrating the package structure of a stacked memory device according to an example embodiment;

[0028] Figure 25 It is a perspective view including a semiconductor package of a stacked memory device according to an example embodiment; and

[0029] Figure 26 This is a block diagram illustrating a system including a semiconductor memory device according to an example embodiment. Detailed Implementation

[0030] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0031] Reference Figure 1 The semiconductor memory device 100 may include an interface semiconductor chip 200, one or more memory semiconductor chips 300, and multiple internal command paths PTH1 to PTHn for communication between the interface semiconductor chip and one or more memory semiconductor chips 300.

[0032] The interface semiconductor chip 200 may include multiple command pins CPN1 to CPNn, which are configured to receive multiple command signals SCM1 to SCMn transmitted from a memory controller or a host device. The interface semiconductor chip 200 may include an interface command decoder ICDEC, which is configured to decode the multiple command signals SCM1 to SCMn.

[0033] The interface semiconductor chip 200 may include an interface clock gating circuit ICG, a clock pin CKPN, a clock buffer ICB, and multiple command receivers IRX. The clock pin CKPN is configured to receive an external clock signal CK transmitted from the memory controller, the clock buffer ICB is configured to buffer and output the external clock signal CK, and the multiple command receivers IRX are configured to sample and output multiple command signals SCM1 to SCMn.

[0034] Although Figure 1 Although not shown, the interface semiconductor chip 200 may also include data pins configured to exchange data with the memory controller and control pins configured to receive control signals from the memory controller.

[0035] In some example embodiments, the multiple command signals SCM1 to SCMn may include commands instructing the operation of the semiconductor memory device 100 and addresses for accessing the memory integrated circuit. In this case, the command signals may be referred to as command-address signals, and the command pins may be referred to as command-address pins. In some example embodiments, the multiple command signals SCM1 to SCMn may only include commands, while addresses may be provided through address pins different from the command pins.

[0036] The interface clock gating circuit ICG can receive the external clock signal CK transmitted from the memory controller, and can gating the external clock signal CK based on the interface clock enable signal ICKE to provide the interface clock signal ICK for the operation of the interface semiconductor wafer 200.

[0037] The memory semiconductor chip 300 may include a memory integrated circuit MEM configured to store data. The memory semiconductor chip 300 may include a memory command decoder MCDEC configured to decode a plurality of command signals SCM1 to SCMn transmitted from the interface semiconductor chip 200.

[0038] The memory semiconductor chip 300 may include a memory clock gating circuit MCG and a clock buffer MCB configured to buffer and output an external clock signal CK transmitted from the interface semiconductor chip 200. The memory semiconductor chip 300 may include multiple command receivers MRX configured to sample and output multiple command signals SCM1 to SCMn.

[0039] The memory clock gating circuit MCG can receive the external clock signal CK transmitted from the interface semiconductor chip 200, and can gating the external clock signal CK based on the memory clock enable signal MCKE to provide the memory clock signal MCK for the operation of the memory semiconductor chip 300.

[0040] In this example embodiment, as Figure 1As shown, the interface semiconductor chip 200 does not include a clock enable pin for receiving a clock enable signal from the memory controller. The interface command decoder ICDEC and the memory command decoder MCDEC can control the clock supply relative to the interface semiconductor chip 200 and the memory semiconductor chip 300 respectively based on multiple command signals SCM1 to SCMn transmitted from the memory controller. Therefore, the interface command decoder ICDEC can generate an interface clock enable signal ICKE to control the clock supply relative to the interface semiconductor chip 200 based on multiple command signals SCM1 to SCMn, and the memory command decoder MCDEC can generate a memory clock enable signal MCKE to control the clock supply relative to the memory semiconductor chip 300 based on multiple command signals SCM1 to SCMn.

[0041] In this way, by removing the clock enable pin and controlling the clock supply based on the command signal, the semiconductor memory device 100 according to the example embodiment can improve the design margin and reduce the size of the semiconductor memory device 100.

[0042] The internal command paths PTH1 to PTHn can electrically connect the interface semiconductor chip 200 and the memory semiconductor chip 300, and multiple command signals SCM1 to SCMn can be transmitted from the interface semiconductor chip 200 to the memory semiconductor chip 300 through the internal command paths PTH1 to PTHn.

[0043] Additionally, the internal clock path PTHC can electrically connect the interface semiconductor chip 200 and the memory semiconductor chip 300. The external clock signal CK can be transmitted from the interface semiconductor chip 200 to the memory semiconductor chip 300 through the internal clock path PTHC.

[0044] In some example embodiments, the semiconductor memory device 100 may be a stacked memory device consisting of a memory semiconductor wafer 300 and an interface semiconductor wafer 200. In this case, each of the plurality of internal command paths PTH1 to PTHn and the internal clock path PTHC may include a substrate pass-through or a silicon pass-through (TSV). According to this example embodiment, the interface semiconductor wafer 200 does not include a clock enable pin for receiving a clock enable signal, therefore the silicon pass-through electrically connecting the interface semiconductor wafer 200 and the memory semiconductor wafer 300 does not include a silicon pass-through for transmitting the clock enable signal.

[0045] Typically, in stacked memory devices, stacked semiconductor wafers exchange clock signals and signals aligned with those clock signals. If interface semiconductor wafer 200 decodes command signals and transmits internal control signals to memory semiconductor wafer 300, aligning the internal control signals with the clock signal can be difficult. The relative delay of the clock signal relative to the internal clock signal can vary depending on manufacturing processes, operating voltages, temperatures, command decoder performance, decoding time, etc., and the probability of errors may increase.

[0046] According to this example embodiment, the interface semiconductor chip 200 transmits multiple undecoded command signals SCM1 to SCMn to the memory semiconductor chip 300, and in the memory semiconductor chip 300, the memory command decoder MCDEC can decode the multiple command signals SCM1 to SCMn independently of the interface command decoder ICDEC.

[0047] The interface semiconductor chip 200 can focus on aligning command signals SCM1 to SCMn with clock signals, and each of the interface semiconductor chip 200 and the memory semiconductor chip 300 can decode command signals SCM1 to SCMn using each of the interface command decoder ICDEC and the memory command decoder MCDEC. Therefore, additional circuitry for signal alignment can be eliminated, and the performance of the semiconductor memory device 100 can be improved.

[0048] Thus, the semiconductor memory device 100 according to the example embodiment can effectively implement signal synchronization by transmitting undecoded command signals from the interface semiconductor chip 200 to the memory semiconductor chip 300 and decoding the transmitted command signals in the memory semiconductor chip 300.

[0049] Figure 2 This is a diagram illustrating an example embodiment of a clock enable signal generator included in a semiconductor memory device according to an example embodiment.

[0050] Available Figure 1 Each of the interface semiconductor chip 200 and the memory semiconductor chip 300 includes Figure 2 The clock enable signal generator 10 in the interface semiconductor chip 200 can generate an interface clock enable signal ICKE, and the clock enable signal generator 10 in the memory semiconductor chip 300 can generate a memory clock enable signal MCKE.

[0051] In some example embodiments, a clock enable signal generator 10 may be included in each of the interface command decoder (ICDEC) and the memory command decoder (MCDEC). In some example embodiments, the clock enable signal generator 10 may be located outside the interface command decoder (ICDEC) and the memory command decoder (MCDEC).

[0052] Reference Figure 2 The clock enable signal generator 10 can be implemented through a set-reset latch circuit, which may include a first NAND gate 11 and a second NAND gate 12.

[0053] The first NAND gate 11 performs a NAND logic operation on the output of the set signal SET and the second NAND gate 12 to generate the interface clock enable signal ICKE (or the memory clock enable signal MCKE). The second NAND gate 12 performs a NAND logic operation on the reset signal RST and the output of the first NAND gate 11.

[0054] (It can be used as follows, please refer to the following) Figure 18 and Figure 20 The described decoding logic generates a set signal SET and a reset signal RST by decoding a selected command signal corresponding to a portion of multiple command signals SCM1 to SCMn (e.g., by decoding line command-address signals R0, R1, and R2).

[0055] The decoding logic included in the interface command decoder ICDEC can generate a set signal SET and a reset signal RST based on a selected command signal transmitted from the memory controller via a selected command pin. The clock enable signal generator 10 included in the interface semiconductor chip 200 can generate an interface clock enable signal ICKE based on the set signal SET and the reset signal RST.

[0056] The decoding logic included in the memory command decoder MCDEC can generate a set signal SET and a reset signal RST based on a selected command signal transmitted from the interface semiconductor chip 200 via a selected internal command path. The clock enable signal generator 10 included in the memory semiconductor chip 300 can generate a memory clock enable signal MCKE based on the set signal SET and the reset signal RST.

[0057] The interface command decoder ICDEC and the memory command decoder MCDEC can generate the interface clock enable signal ICKE and the memory clock enable signal MCKE independently of each other.

[0058] Figure 3 It is shown Figure 2 The timing diagram of the operation of the clock enable signal generator.

[0059] Reference Figure 3 The set signal SET can be activated in response to the power mode enter command PME (which can be one of the command CMDs corresponding to a combination of multiple command signals SCM1 to SCMn), and the reset signal RST can be activated in response to the power mode exit command PMX in the command CMD. For example, the set signal SET can be activated at a logic low level, and the reset signal RST can be activated at a logic high level, such as... Figure 3 As shown below, power modes may include power-off mode and / or self-refresh mode.

[0060] Figure 2 The set-reset latch circuit 10 can deactivate each of the interface clock enable signal ICKE and the memory clock enable signal MCKE from logic low to logic high at a first time point Te corresponding to the falling edge of the set signal SET. The set-reset latch circuit 10 can also activate each of the interface clock enable signal ICKE and the memory clock enable signal MCKE from logic high to logic low at a second time point Tx corresponding to the rising edge of the reset signal RST. Figure 2 and Figure 3 In the example embodiment, the interface clock enable signal ICKE and the memory clock enable signal MCKE are activated at a logic low level, but the example embodiment is not limited thereto. As will be referred to below... Figures 18 to 22 The description states that the set signal SET and the reset signal RST can be generated by decoding the command signal.

[0061] Each of the interface semiconductor chip 200 and the memory semiconductor chip 300 includes a set-reset latch circuit 10 that can deactivate each of the interface clock enable signal ICKE and the memory clock enable signal MCKE in response to a timed set signal SET indicating a power mode enter command PME, and activate each of the interface clock enable signal ICKE and the memory clock enable signal MCKE in response to a timed reset signal RST indicating a power mode exit command PMX.

[0062] Figure 4 This is a diagram illustrating an example embodiment of a clock gating circuit included in a semiconductor memory device according to an example embodiment.

[0063] Figure 4 Both clock gating circuits 20 and 30 in the diagram can be implemented as... Figure 1 The interface clock gating circuit (ICG) and the memory clock gating circuit (MCG) are used in the circuit.

[0064] The interface clock gating circuit ICG can receive the external clock signal CK transmitted from the memory controller through the clock pin CKPN, and can gating the external clock signal CK based on the interface clock enable signal ICKE to provide the interface clock signal ICK for the operation of the interface semiconductor chip 200.

[0065] The memory clock gating circuit MCG can receive the external clock signal CK transmitted from the interface semiconductor chip 200 through the internal clock path PTHC, and can gating the external clock signal CK based on the memory clock enable signal MCKE to provide the memory clock signal MCK for the operation of the memory semiconductor chip 300.

[0066] In some example embodiments, the clock gating circuit 20 can be implemented using an AND gate 21. The AND gate 21 can perform an AND logic operation on the input of the external clock signal CK and the input of the inverted signal of the interface clock enable signal ICKE (or the inverted signal of the memory clock enable signal MCKE) to provide the output of the interface clock signal ICK (or the memory clock signal MCK).

[0067] In some example embodiments, the clock gating circuit 30 can be implemented using a transmission gate 31 and an inverter 32. The transmission gate 31 can enable an external clock signal CK based on an interface clock enable signal ICKE (or a memory clock enable signal MCKE) to provide and output an interface clock signal ICK (or a memory clock signal MCK).

[0068] Figure 5 It is shown Figure 4 The timing diagram of the operation of the clock gating circuit.

[0069] Reference Figure 5 Refer to the above usage Figure 4 One of the described clock gating circuits deactivates the interface clock enable signal ICKE (or memory clock enable signal MCKE) for a duration Te to Tx (e.g., when the interface clock enable signal ICKE (or memory clock enable signal MCKE) is at a logic high level), during which the external clock signal CK can be blocked. That is, when the interface clock enable signal ICKE (or memory clock enable signal MCKE) is deactivated, the interface clock signal ICK (or memory clock signal MCK) can stop switching; in other words, it can be deactivated.

[0070] In this way, the interface clock enable signal ICKE and the memory clock enable signal MCKE can be generated based on the set signal SET and the reset signal RST generated by decoding the command signal, and clock strobing can be performed based on the interface clock enable signal ICKE and the memory clock enable signal MCKE.

[0071] As a result, the interface command decoder ICDEC and the memory command decoder MCDEC can control the clock supply relative to the interface semiconductor chip 200 and the memory semiconductor chip 300 respectively based on the command signal.

[0072] Figure 6 This is a diagram illustrating an example embodiment of a memory integrated circuit included in a semiconductor memory device according to an example embodiment.

[0073] Although reference Figure 6 Dynamic random access memory (DRAM) is described as an example of a semiconductor memory device, but a semiconductor memory device can be any of a variety of memory cell structures, including but not limited to volatile memory structures such as DRAM, thyristor RAM (TRAM) and static RAM (SRAM), or non-volatile memory structures such as read-only memory (ROM), flash memory, phase-change RAM (PRAM), ferroelectric RAM (FRAM), magnetic RAM (MRAM), etc.

[0074] Reference Figure 6 The memory integrated circuit 400 may include control logic 410, address register 420, block control logic 430, row address multiplexer (RA MUX) 440, refresh counter 445, column address (CA) latch 450, row decoder 460, column decoder 470, memory cell array 480, sense amplifier unit 485, input / output (I / O) gating circuit 490, data input / output (I / O) buffer 495, and memory clock gating circuit MCG.

[0075] The memory cell array 480 may include multiple block memory arrays 480a to 480h. The row decoder 460 may include multiple block row decoders 460a to 460h respectively coupled to the block memory arrays 480a to 480h. The column decoder 470 may include multiple block column decoders 470a to 470h respectively coupled to the block memory arrays 480a to 480h. The sense amplifier unit 485 may include multiple block sense amplifiers 485a to 485h respectively coupled to the block memory arrays 480a to 480h.

[0076] Address register 420 can receive address ADDR, including block address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the memory controller. Address register 420 can provide the received block address BANK_ADDR to block control logic 430, the received row address ROW_ADDR to row address multiplexer 440, and the received column address COL_ADDR to column address latch 450.

[0077] Block control logic 430 can generate a block control signal in response to the block address BANK_ADDR. The block row decoders 460a to 460h corresponding to the block address BANK_ADDR can be activated in response to the block control signal, and the block column decoders 470a to 470h corresponding to the block address BANK_ADDR can be activated in response to the block control signal.

[0078] The row address multiplexer 440 can receive the row address ROW_ADDR from the address register 420 and the refresh row address REF_ADDR from the refresh counter 445. The row address multiplexer 440 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 can be applied to the block row decoders 460a to 460h.

[0079] An activated block line decoder among block line decoders 460a-460h can decode the line address RA output from the line address multiplexer 440 and can activate the word line corresponding to the line address RA. For example, the activated block line decoder can apply a word line drive voltage to the word line corresponding to the line address RA.

[0080] Column address latch 450 can receive column address COL_ADDR from address register 420 and can temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, column address latch 450 can generate a column address incremented from the received column address COL_ADDR. Column address latch 450 can apply the temporarily stored or generated column address to block column decoders 470a-470h.

[0081] One of the block column decoders 470a to 470h, when activated, can decode the column address COL_ADDR output from the column address latch 450 and can control the I / O strobe circuit 490 to output data corresponding to the column address COL_ADDR.

[0082] The I / O strobe circuit 490 may include circuitry for strobing input / output data. The I / O strobe circuit 490 may also include a read data latch for storing data output from the block memory arrays 480a to 480h and a write driver for writing data to the block memory arrays 480a to 480h.

[0083] A block read amplifier coupled to one of the block memory arrays 480a-480h (from which data will be read) can sense data DQ to be read from that block memory array, and data DQ can be stored in a read data latch. The data stored in the read data latch can be provided to the memory controller via a data I / O buffer 495. Data DQ to be written to one of the block memory arrays 480a-480h can be provided from the memory controller to the data I / O buffer 495. A write driver can write data DQ to one of the block memory arrays 480a-480h.

[0084] Control logic 410 can control the operation of memory integrated circuit 400. For example, control logic 410 can generate control signals for memory integrated circuit 400 to perform write or read operations. Control logic 410 may include command decoder 411 and mode register group 412. Command decoder 411 decodes commands (CMD) received from memory controller, and mode register group 412 sets the operating mode of memory integrated circuit 400. For example, command decoder 411 can generate control signals corresponding to commands (CMD) by decoding command signals.

[0085] According to the example embodiment, the command decoder 411 can generate a memory clock enable signal MCKE based on the command signal described above. The memory clock gating circuit MCG can receive an external clock signal CK transmitted from the interface semiconductor wafer, and can gating the external clock signal CK based on the memory clock enable signal MCKE to provide a memory clock signal MCK for the operation of the memory integrated circuit 400.

[0086] Figure 7 This is an exploded perspective view of a system including a stacked memory device according to an example embodiment.

[0087] Reference Figure 7 The system 500 may include a stacked memory device 1000 and a host device 2000.

[0088] The stacked memory device 1000 may include an interface semiconductor wafer 1010 (which may be referred to as a buffer semiconductor wafer or a logic semiconductor wafer), a plurality of memory semiconductor wafers 1070 and 1080 stacked with the buffer semiconductor wafer 1010, and silicon through-hole devices (TSVs) electrically connecting the semiconductor wafers 1010, 1070, and 1080. The memory semiconductor wafers 1070 and 1080 may include memory integrated circuits MEM 1071 and 1081, respectively.

[0089] Figure 7 A non-limiting example of an interface semiconductor wafer and two memory semiconductor wafers is shown. However, Figure 7 The stacked structure may include two or more logic semiconductor wafers and one, three or more memory semiconductor wafers. Additionally, Figure 7 The non-limiting example shown is that memory semiconductor wafers 1070 and 1080 are stacked vertically with interface semiconductor wafer 1010. However, reference will be made below. Figure 23 According to the description, memory semiconductor wafers 1070 and 1080 can be stacked vertically, and interface semiconductor wafer 1010 can be electrically connected to memory semiconductor wafers 1070 and 1080 via an intermediary and / or a substrate, instead of being stacked with memory semiconductor wafers 1070 and 1080.

[0090] The interface semiconductor chip 1010 may include a memory interface MIF 1020, a control circuit CTRL 1030, an interface command decoder ICDEC 1040, and a data buffer (BUFF) 1050.

[0091] The memory interface 1020 can communicate with external devices such as the host device 2000 via the interconnect device 520. The control circuitry 1030 can control the overall operation of the stacked memory device 1000. The interface command decoder 1040 can generate internal control signals by decoding multiple command signals transmitted from the host device 2000. In this example embodiment, the memory interface 1020 does not include a clock enable pin, but may include command pins, data pins, and control pins. The data buffer 1050 can temporarily store data exchanged with the host device 2000. Additionally, the data buffer 1050 can store information used to control the stacked memory device 1000.

[0092] The host device 2000 may include a host interface HIF 2110 and processor cores CR1 2120 and CR2 2130. The host interface 2110 may perform communication with external devices such as the stacked memory device 1000 via interconnect device 520. The host interface 2110 may include a memory controller for controlling the stacked memory device 1000.

[0093] Figure 8 This is a diagram illustrating a high-bandwidth memory (HBM) device according to an example embodiment.

[0094] Reference Figure 8 The HBM device 1001 may include a stack of multiple DRAM semiconductor wafers 1100, 1200, 1300, and 1400. The HBM device 1001 with its stacked structure can be optimized through multiple independent interfaces called channels. According to the HBM standard, each DRAM stack can support up to eight channels. Figure 8 An example stack is shown comprising four DRAM semiconductor wafers 1100, 1200, 1300, and 1400, with each DRAM semiconductor wafer supporting four channels, namely, channel 0 through channel 3. For example, as Figure 8 As shown, the fourth DRAM semiconductor wafer 1400 may include four memory integrated circuits 1401 to 1404, each corresponding to one of the four channels, namely, channel 0 to channel 3. The four memory integrated circuits 1401 to 1404 may each include the aforementioned four memory command decoders MCDEC0 to MCDEC3.

[0095] In some example embodiments, each of the four channels, namely channels 0 through 3, can be divided into two pseudo-channels. In this case, a memory semiconductor wafer may include eight memory command decoders, each corresponding to one of the eight pseudo-channels.

[0096] Each channel of the HBM device 1001 can provide access to a set of independent DRAM blocks. Requests from one channel cannot access data attached to different channels. Channels can be timed independently without synchronization.

[0097] HBM device 1001 may also include an interface semiconductor chip 1010 disposed at the bottom of the stacked structure to provide signal routing and / or other functions.

[0098] Figure 9 This is a diagram illustrating an example interface of a system including an HBM device according to an example embodiment.

[0099] Reference Figure 9 System 600 may include an HBM device 1001 and a host device 2000 connected via multiple channels CH0 to CHn. Each of the channels CH0 to CHn may include two pseudo-channels PC0 and PC1. For example, as Figure 9As shown, the signal lines corresponding to a channel CH0 may include the data line PC0 DQ of the first pseudo channel PC0, the data line PC1DQ of the second pseudo channel PC1, and the command address line CA. The command address line CA may include the row command address line ROW CA (used to transmit activation commands, precharge commands, etc.) and the column command address line COLUMN CA (used to transmit read commands, write commands, etc.).

[0100] Typical memory channels include a command address (CA) interface and a data (DQ) interface, which can be controlled independently of the interfaces of other channels. Pseudo-channels may include independent DQ interfaces and shared CA interfaces, such as... Figure 9 As shown. A time-division multiplexing scheme can be used to select pseudo-channels, and corresponding commands and addresses can be transmitted through pseudo-channels corresponding to the same memory channel. In this disclosure, "channel" refers to an independently controllable "pseudo-channel".

[0101] For example, in a 4H-HBM device comprising four stacked memory semiconductor wafers, each memory semiconductor wafer may include four channels or eight pseudo-channels, and each pseudo-channel may include 16 memory blocks. Therefore, each memory semiconductor wafer may include 128 memory blocks, which can be divided into eight pseudo-channels. The 4H-HBM device may include 16 memory command decoders corresponding to the 16 channels or 32 memory command decoders corresponding to the 32 pseudo-channels.

[0102] Figure 10 and Figure 11 This is a diagram illustrating an example embodiment of commands for an HBM device according to an example embodiment.

[0103] Figure 10 It shows the way Figure 9 The row command - address line ROW CA transmits the row no-operation command RNOP, activation or activation command ACT, power-down enter command PDE, self-refresh enter command SRE, power-down exit command PDX, and self-refresh exit command SRX.

[0104] Figure 11 It shows the way Figure 9 The column commands in the address line CA pass the column no-operation command CNOP, the read command RD, the write command WR, and the mode register set command MRS.

[0105] Reference Figure 10 and Figure 11 , refer to Figure 1The described multiple command signals SCM1 to SCMn may include multiple row CA signals R0 to R9 and multiple column CA signals C0 to C7. Commands and addresses transmitted from the host device to the HBM device can be represented by combinations of row CA signals R0 to R9 and column CA signals C0 to C7. 'H' represents a logic high level, 'L' represents a logic low level, RA0 to RA15 represent the row address bits, BA0 to BA3 represent the block address bits, 'V' represents a logic high level or a logic low level, CA0 to CA4 represent the column address bits, SID represents the identifier of the memory semiconductor chip, and PC represents a pseudo-channel.

[0106] For example, the activation command ACT can be transmitted over 1.5 clock cycles, including two rising edges R and one falling edge F, while the read command RD and write command WR can be transmitted within one clock cycle. The activation command ACT may include block address bits BA0–BA3 and row address bits RA0–RA15. The read command RD and write command WR may include block address bits BA0–BA3 and column address bits CA0–CA4.

[0107] Figure 10 and Figure 11 The combination of command-address signals shown is a non-limiting example, and various combinations can be used.

[0108] Figure 12 , Figure 13 and Figure 14 It is shown Figure 10 The diagram shows the power mode commands included in the commands.

[0109] Figure 12 The power-off entry command PDE is shown. Figure 13 The self-refresh entry command SRE is shown. Figure 14 The power-off exit command PDX and the self-refresh exit command SRX are shown. Figure 10 and Figure 14 As shown, the power-off exit command PDX and the self-refresh exit command SRX can be the same.

[0110] By (synchronizing with the edge of the external clock signal CK_t) and Figure 1 Sampling the logic levels of the row CA signals R0 to R3 corresponding to a portion of the multiple command signals SCM1 to SCMn can decode the power mode commands PDE, SRE, PDX, and SRX. An external clock signal CK_t can be provided from the memory controller using a complementary clock signal CK_c as a differential signal pair, but the example embodiment is not limited to this.

[0111] Figure 15 and Figure 16This is a timing diagram illustrating the entry and exit of power modes in an HBM device according to an example embodiment.

[0112] Figure 15 This shows how to enter and exit power-off mode. Figure 16 This shows how to enter and exit self-refresh mode. Figure 15 and Figure 16 In this context, RNOP indicates no operation command on the row, CNOP indicates no operation command on the column, and VCMD indicates any valid command.

[0113] Reference Figure 15 The aforementioned power mode commands may include the power outage entry command (PDE) and the power outage exit command (PDX).

[0114] Figure 1 The interface command decoder ICDEC can deactivate the interface clock enable signal ICKE in response to the timing of the power-down entry command PDE (i.e., at time point Te), and activate the interface clock enable signal ICKE in response to the timing of the power-down exit command PDX.

[0115] Figure 1 The memory command decoder MCDEC can deactivate the memory clock enable signal MCKE in response to the timing of the power-down entry command PDE (i.e., at time point Te), and activate the memory clock enable signal MCKE in response to the timing of the power-down exit command PDX.

[0116] A valid command VCMD can be delivered from the memory controller after a predetermined time period tXP following the timing of the power-off exit command PDX. In some example embodiments, the timing of the power-off exit command PDX may correspond to a time point Tx, i.e., the rising edge of the power-off exit command PDX. In some example embodiments, the timing of the power-off exit command PDX may correspond to a time point Tx', i.e., the rising edge of the external clock signal CK_t that samples the power-off exit command PDX.

[0117] Reference Figure 16 The aforementioned power mode commands may include the self-refresh entry command SRE and the self-refresh exit command SRX.

[0118] Figure 1 The interface command decoder ICDEC can deactivate the interface clock enable signal ICKE in response to the timing of the self-refresh enter command SRE (i.e., at time point Te), and activate the interface clock enable signal ICKE in response to the timing of the self-refresh exit command SRX.

[0119] Figure 1The memory command decoder MCDEC can deactivate the memory clock enable signal MCKE in response to the timing of the self-refresh enter command SRE (i.e., at time point Te), and activate the memory clock enable signal MCKE in response to the timing of the self-refresh exit command SRX.

[0120] A valid command VCMD can be passed from the memory controller after a predetermined time period tXS following the timing of the self-refresh exit command SRX. In some example embodiments, the timing of the self-refresh exit command SRX may correspond to a time point Tx, i.e., the rising edge of the self-refresh exit command SRX. In some example embodiments, the timing of the self-refresh exit command SRX may correspond to a time point Tx', i.e., the rising edge of the external clock signal CK_t that samples the self-refresh exit command SRX.

[0121] exist Figure 16 In this context, tXSMRS represents the delay time from the self-refresh exit command SRX to the mode register set command MRS, and tMRD represents the time period required to write the information of the mode register set command MRS into the mode register.

[0122] Figure 17 This is a diagram illustrating the switching of operating modes in an HBM device according to an example embodiment.

[0123] Reference Figure 17 The HBM device can enter power-down mode from activation mode in response to the power-down entry command PDE, and exit power-down mode from activation mode in response to the power-down exit command PDX.

[0124] In power-down mode, the clock signal supplied to the internal circuitry of the memory semiconductor chip in the HBM device can be deactivated, and power supplied to most of the internal circuitry can be blocked.

[0125] In some example embodiments, the HBM device can enter self-refresh mode from active mode in response to the self-refresh enter command SRE, and exit self-refresh mode back to active mode in response to the self-refresh exit command SRX.

[0126] In self-refresh mode, the clock signal provided to the internal circuitry of the memory semiconductor chip in the HBM device can be deactivated, and the memory semiconductor chip can perform refresh operations on its own without receiving refresh commands and refresh addresses from the memory controller.

[0127] Figure 18 This is a diagram illustrating an example embodiment of the decoding logic included in the command decoder of HBM according to an example embodiment.

[0128] Figure 1Each of the interface command decoder (ICDEC) and memory command decoder (MCDEC) in the system may include, for example: Figure 18 The decoding logic shown is 40.

[0129] The decoding logic 40 included in the interface command decoder ICDEC can be based on... Figure 1 The set signal SET and reset signal RST are generated by transmitting selected command signals from a subset of the multiple command pins CPN1 to CPNn. Additionally, the decoding logic 40 included in the memory command decoder MCDEC can be based on... Figure 1 The selected command signal, corresponding to a portion of the multiple internal command paths PTH1 to PTHn, is used to generate the set signal SET and the reset signal RST. Therefore, the selected command signal corresponds to a portion of the multiple command signals SCM1 to SCMn. In this way, the interface command decoder ICDEC and the memory command decoder MCDEC can generate the set signal SET and the reset signal RST independently of each other.

[0130] Reference Figure 18 The decoding logic 40 may include a first logic gate 41, a second logic gate 42, a first flip-flop 43, and a second flip-flop 44.

[0131] The first logic gate 41 can be used with, for example Figure 10 and Figure 11 The selected command signals R0, R1, and R2, corresponding to a portion of the multiple command signals R0 to R9 and C0 to C7 shown, perform a first logic operation. The second logic gate 42 can perform a second logic operation on the selected command signals R0, R1, and R2. For example, the first logic gate 41 can be implemented using a NAND gate, and the second logic gate 42 can be implemented using an AND gate.

[0132] The first flip-flop 43 can latch the output of the first logic gate 41 in response to the external clock signal CK transmitted from the memory controller to generate a set signal SET. The second flip-flop 44 can latch the output of the second logic gate 42 in response to the external clock signal CK to generate a reset signal RST. The decoding logic 40 can generate the set signal SET and the reset signal RST, as shown in the reference. Figure 3 The description is as follows. As a result, the interface command decoder ICDEC can generate the interface clock enable signal ICKE based on selected command signals R0, R1, and R2 corresponding to a portion of multiple command signals, and the memory command decoder MCDEC can generate the memory clock enable signal MCKE based on the selected command signals R0, R1, and R2.

[0133] Figure 19This is a diagram illustrating the operation of the power mode in an HBM device according to an example embodiment.

[0134] Reference Figure 19 The interface semiconductor chip can deactivate the command pins of the multiple command pins corresponding to the row CA signals R0-R9 in response to the deactivation of the interface clock enable signal ICKE, except for the selected command pins corresponding to the selected command signals R0, R1, and R2. For example... Figure 19 As shown, other command pins corresponding to the row CA signals R3 to R9 can be deactivated by disabling command receivers RX3 to RX9 and not disabling command receivers RX0 to RX2 corresponding to the selected command pin.

[0135] The interface semiconductor chip can reactivate other command pins corresponding to command signals R3 to R9 in response to the activation of the interface clock enable signal ICKE.

[0136] Figure 20 This is a diagram illustrating an example embodiment of the decoding logic included in the command decoder of HBM according to an example embodiment.

[0137] Figure 1 Each of the interface command decoder (ICDEC) and memory command decoder (MCDEC) in the system may include, for example: Figure 20 The decoding logic shown is 50.

[0138] The decoding logic 50 included in the interface command decoder ICDEC can be based on... Figure 1 The selected command signal is transmitted through a portion of the multiple command pins CPN1 to CPNn to generate the set signal SET and the reset signal RST.

[0139] The decoding logic 50 included in the memory command decoder MCDEC can be based on... Figure 1 The selected command signal is transmitted through a portion of the selected internal command paths PTH1 to PTHn to generate the set signal SET and the reset signal RST.

[0140] The selected command signal corresponds to a portion of multiple command signals SCM1 to SCMn.

[0141] The interface command decoder ICDEC and the memory command decoder MCDEC can generate the set signal SET and the reset signal RST independently of each other.

[0142] The decoding logic 50 may include logic gate 51 and flip-flop 52. Logic gate 51 can be used with, for example... Figure 10 and Figure 11The selected command signals R0, R1, and R2, corresponding to a portion of the multiple command signals R0-R9 and C0-C7 shown, perform logical operations. Logic gate 51 can be implemented using NAND gates. Flip-flop 52 can latch the output of logic gate 51 in response to an external clock signal CK passed from the memory controller to generate a set signal SET. Additionally, decoding logic 50 can provide one of the selected command signals R0, R1, and R2, R0, as a reset signal RST.

[0143] Figure 21 It is shown Figure 2 The timing diagram of the operation of the clock enable signal generator.

[0144] Reference Figure 21 The set signal SET can be activated in response to the power mode entry command PME being activated (corresponding to a combination of multiple command signals in the command CMD), and the reset signal RST can be activated in response to a command signal R0, as shown in the reference. Figure 20 The description. For example, such as Figure 21 As shown, the set signal SET can be activated by a logic low level. As mentioned above, the power mode can include a power-down mode and / or a self-refresh mode.

[0145] Figure 2 The set-reset latch circuit 10 can deactivate the interface clock enable signal ICKE (or memory clock enable signal MCKE) from logic low to logic high at a first time point Te corresponding to the falling edge of the set signal SET. The set-reset latch circuit 10 can activate the interface clock enable signal ICKE (or memory clock enable signal MCKE) from logic high to logic low at a second time point Tx corresponding to the rising edge of the reset signal RST.

[0146] In this way, the interface command decoder ICDEC and the memory command decoder MCDEC can deactivate the interface clock enable signal ICKE and the memory clock enable signal MCKE respectively in response to selected command signals R0, R1 and R2 corresponding to a portion of multiple command signals, and can activate the interface clock enable signal ICKE and the memory clock enable signal MCKE respectively in response to one of the selected command signals R0, R1 and R2.

[0147] Figure 22 This is a diagram illustrating the operation of the power mode in an HBM device according to an example embodiment.

[0148] Reference Figure 22The interface semiconductor chip can deactivate the command pins (excluding the one command pin corresponding to command signal R0) from among the multiple command pins corresponding to the row CA signals R0-R9 in response to the deactivation of the interface clock enable signal ICKE. For example... Figure 22 As shown, by disabling the command receivers RX1 to RX9 (except for the command receiver RX0 corresponding to a command pin), the other command pins corresponding to the row CA signals R1 to R9 can be deactivated.

[0149] The interface semiconductor chip can reactivate other command pins corresponding to command signals R1 to R9 in response to the activation of the interface clock enable signal ICKE.

[0150] Figure 23 and Figure 24 This is a diagram illustrating the package structure of a stacked memory device according to an example embodiment.

[0151] Reference Figure 23 The memory chip 1002 may include an inserter ITP and a stacked memory device stacked on the inserter ITP. The stacked memory device may include an interface semiconductor wafer ISD and multiple memory semiconductor wafers MSD1 to MSD4. Figure 23 The diagram shows a structure in which memory semiconductor wafers MSD1 to MSD4, excluding the interface semiconductor wafer ISD, are stacked vertically, and the interface semiconductor wafer ISD is electrically connected to the memory semiconductor wafers MSD1 to MSD4 via an inserter ITP or a substrate.

[0152] Reference Figure 24 The memory chip 1003 may include a substrate BSUB and a stacked memory device on the substrate BSUB. The stacked memory device may include an interface semiconductor wafer ISD and multiple memory semiconductor wafers MSD1 to MSD4. Figure 24 The structure of the interface semiconductor wafer ISD and the memory semiconductor wafers MSD1 to MSD4 stacked vertically is shown.

[0153] Reference Figure 23 and Figure 24 The interface semiconductor chip ISD may include an interface command decoder ICDEC, and the memory semiconductor chips MSD1 to MSD4 may each include memory command decoders MCDEC1 to MCDEC4. The interface command decoder ICDEC generates an interface clock enable signal ICKE for controlling the clock supply to the interface semiconductor chip ISD. The memory command decoders MCDEC1 to MCDEC4 generate memory clock enable signals MCKE1 to MCKE4 for controlling the clock supply to the memory semiconductor chips MSD1 to MSD4, respectively.

[0154] Figure 23 and Figure 24 An example embodiment is shown with one channel corresponding to a memory semiconductor wafer, but the example embodiment is not limited thereto. As mentioned above, one memory semiconductor wafer may correspond to two or more channels, and the number of memory command decoders may vary depending on the number of channels in each memory semiconductor wafer.

[0155] The substrate BSUB can be the same as or may include the inserter ITP. The substrate BSUB can be a printed circuit board (PCB). External connection elements, such as conductive bumps (BMPs), can be formed on the lower surface of the substrate BSUB, and internal connection elements, such as conductive bumps (uBMPs), can be formed on the upper surface of the substrate BSUB. Figure 25 In an example embodiment, the interface semiconductor wafer ISD and the memory semiconductor wafers MSD1 to MSD4 can be electrically connected via silicon through-hole (STO). The stacked semiconductor wafers BSD and MSD1 to MSD4 can be packaged using resin RSN.

[0156] Figure 25 It is a perspective view including a semiconductor package of a stacked memory device according to an example embodiment.

[0157] Reference Figure 25 The semiconductor package 3000 may include one or more stacked memory devices 3100, a central processing unit (CPU) 3200, and a graphics processing unit (GPU) 3250.

[0158] The stacked memory device 3100, CPU 3200, and GPU 3250 can be mounted on the inserter 3300. The inserter 3300, on which the stacked memory device 3100, CPU 3200, and GPU 3250 are mounted, can be mounted on a package substrate 3400. The CPU 3200 or GPU 3250 can be configured to perform the functions of the aforementioned host device. The CPU 3200 and GPU 3250 can respectively correspond to... Figure 7 The processor cores in it are 2120 and 2130.

[0159] The stacked memory device 3100 can be implemented in various forms, and can be a high-bandwidth memory (HBM) memory device with multiple layers stacked. Therefore, the stacked memory device 3100 may include an interface semiconductor wafer and multiple memory semiconductor wafers. The stacked memory device 3100 may include a configuration for controlling the clock supply as described above.

[0160] Each of the stacked memory device 3100, CPU 3200, and GPU 3250 may include a physical layer (PHY) through which communication can be performed between the stacked memory device 3100, CPU 3200, and GPU 3250. When the stacked memory device 3100 includes a direct access region, test signals can be provided to the stacked memory device 3100 via conductive means (e.g., solder balls 3500) mounted beneath the package substrate 3400 and the direct access region.

[0161] Figure 26 This is a block diagram illustrating a system including a semiconductor memory device according to an example embodiment.

[0162] Reference Figure 26 System 4000 may include an application processor (AP) 4100, a connectivity unit 4200, a volatile memory device (VM) 4300, a non-volatile memory device (NVM) 4400, a user interface 4500, and a power supply 4600. System 4000 may be a mobile system such as a mobile phone, smartphone, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation system, etc.

[0163] Application processor 4100 can execute applications such as web browsers, games, and video players. Application processor 4100 may include a single processor core or multiple processor cores. Application processor 4100 may also include a cache.

[0164] The connectivity unit 4200 can perform wired or wireless communication with external devices. For example, the connectivity unit 4200 can be implemented to perform Ethernet communication, Near Field Communication (NFC), Radio Frequency Identification (RFID) communication, mobile telecommunications, memory card communication, Universal Serial Bus (USB) communication, etc. For example, the connectivity unit 4200 may include a baseband chipset and support GSM, GPRS, WCDMA, or HSxPA communication, etc.

[0165] The volatile memory device 4300 can store data processed by the application processor 4100, or it can operate as working memory. For example, the volatile memory device 4300 can be dynamic random access memory (DRAM), such as DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, etc.

[0166] The non-volatile memory device 4400 can store a boot image for the boot system 4000. For example, the non-volatile memory device 4400 can be an EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), etc.

[0167] User interface 4500 may include at least one input device (such as a keyboard, touchscreen, etc.) and at least one output device (such as a speaker, display device, etc.). Power supply 4600 may provide power voltage to system 4000. In some example embodiments, system 4000 may also include a camera image processor (CIS) and / or storage devices, such as memory cards, solid-state drives (SSDs), hard disk drives (HDDs), CD-ROMs, etc.

[0168] The components of System 4000 can be integrated using various packages, such as PoP (PoP, stacked package), BGA (Ball Grid Array), CSP (Chip Scale Package), PLCC (Plastic Wire Carrier), PDIP (Plastic Dual In-line Package), Waffle Package, wafer-level chip, COB (Chip on Board), CERDIP (Ceramic Dual In-line Package), MQFP (Plastic Metric Quad Flat Package), TQFP (Thin Quad Flat Package), SOIC (Small Outline Integrated Circuit), SSOP (Shrink Small Outline Package), TSOP (Thin Small Outline Package), TQFP (Thin Quad Flat Package), SIP (System in Package), MCP (Multi-Chip Package), WFP (Wafer Scale Package), WSP (Wafer Scale Stacked Package), etc.

[0169] At least one of the volatile memory device 4300 and the non-volatile memory device 4400 may include a configuration for controlling the clock supply, which removes a dedicated clock enable signal while providing a clock enable signal based on a command signal.

[0170] The example embodiments can be applied to a variety of electronic devices and systems. For example, the example embodiments can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash storage (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptops, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Things (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, and so on.

[0171] In summary, as the number of stacked semiconductor wafers increases, the number of input-output pins in a semiconductor memory device can also increase. This increase in the number of input-output pins reduces design margins and limits the reduction in the size of semiconductor memory devices.

[0172] As described above, embodiments can provide semiconductor memory devices and systems including semiconductor memory devices that can effectively control clock supply. The semiconductor memory devices and systems according to example embodiments can increase design margin and reduce size by removing the clock enable pin and controlling the clock supply based on command signals. Furthermore, the semiconductor memory devices and systems according to exemplary embodiments can effectively implement signal synchronization by transmitting undecoded command signals from the interface semiconductor wafer to the memory semiconductor wafer and decoding the transmitted command signals in the memory semiconductor wafer.

[0173] This document discloses exemplary embodiments. Although specific terminology is used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, it will be apparent to one of ordinary skill in the art that, unless expressly indicated otherwise, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, along with the filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A semiconductor memory device, comprising: An interface semiconductor chip includes a plurality of command pins configured to receive a plurality of command signals transmitted from a memory controller, and includes an interface command decoder configured to decode the plurality of command signals. A memory semiconductor wafer stacked with the interface semiconductor wafer, the memory semiconductor wafer including a memory integrated circuit configured to store data, and a memory command decoder configured to decode the plurality of command signals transmitted from the interface semiconductor wafer; as well as Multiple silicon through-hole components electrically connect the interface semiconductor wafer to the memory semiconductor wafer, wherein... The interface semiconductor chip does not include a clock enable pin for receiving clock enable signals from the memory controller. The interface command decoder is configured to generate an interface clock enable signal to control a first clock supply relative to the interface semiconductor wafer based on power mode commands transmitted from the memory controller via the plurality of command pins, and The memory command decoder is configured to generate a memory clock enable signal to control a second clock supply relative to the memory semiconductor wafer based on the power mode command transmitted from the interface semiconductor wafer through the plurality of silicon pass-throughs.

2. The semiconductor memory device according to claim 1, wherein, The interface command decoder is configured to generate the interface clock enable signal based on a selected command signal corresponding to a portion of the plurality of command signals, and The memory command decoder is configured to generate the memory clock enable signal based on the selected command signal.

3. The semiconductor memory device according to claim 1, wherein, The interface command decoder is configured to deactivate the interface clock enable signal based on a selected command signal corresponding to a portion of the plurality of command signals, and to activate the interface clock enable signal based on one of the selected command signals. The memory command decoder is configured to deactivate the memory clock enable signal based on the selected command signal, and to activate the memory clock enable signal based on the selected command signal.

4. The semiconductor memory device according to claim 1, wherein, The interface semiconductor chip also includes an interface clock gating circuit configured to receive an external clock signal from the memory controller and gating the external clock signal based on the interface clock enable signal to provide an interface clock signal for operation of the interface semiconductor chip. The memory semiconductor wafer also includes a memory clock gating circuit configured to receive the external clock signal transmitted from the interface semiconductor wafer and to gating the external clock signal based on the memory clock enable signal to provide a memory clock signal for operation of the memory semiconductor wafer.

5. The semiconductor memory device according to claim 1, wherein, The power mode commands include a power-off entry command and a power-off exit command. The interface command decoder is configured to deactivate the interface clock enable signal in response to the power-down enter command, and to activate the interface clock enable signal in response to the power-down exit command. The memory command decoder is configured to deactivate the memory clock enable signal in response to the power-down enter command, and to activate the memory clock enable signal in response to the power-down exit command.

6. The semiconductor memory device according to claim 1, wherein, The power mode commands include a self-refresh entry command and a self-refresh exit command. The interface command decoder is configured to deactivate the interface clock enable signal in response to the self-refresh enter command, and to activate the interface clock enable signal in response to the self-refresh exit command. The memory command decoder is configured to deactivate the memory clock enable signal in response to the self-refresh enter command, and to activate the memory clock enable signal in response to the self-refresh exit command.

7. The semiconductor memory device according to claim 1, wherein, The interface semiconductor chip includes a set-reset latch circuit configured to deactivate the interface clock enable signal in response to a timed set signal indicating a power mode enter command, and to activate the interface clock enable signal in response to a timed reset signal indicating a power mode exit command. The memory semiconductor wafer includes a set-reset latch circuit having the same configuration as the set-reset latch circuit of the interface semiconductor wafer, and is configured to deactivate the memory clock enable signal in response to the set signal and activate the memory clock enable signal in response to the reset signal.

8. The semiconductor memory device according to claim 7, wherein, The set-reset latch circuit includes a first NAND gate and a second NAND gate. The first NAND gate performs a NAND logic operation on the set signal and the output of the second NAND gate to generate the interface clock enable signal or the memory clock enable signal, and The second NAND gate performs NAND logic operations on the reset signal and the output of the first NAND gate.

9. The semiconductor memory device according to claim 7, wherein, Each of the interface command decoder and the memory command decoder includes decoding logic, the decoding logic comprising: A first logic gate is configured to perform a first logic operation on a selected command signal corresponding to a portion of the plurality of command signals; A second logic gate is configured to perform a second logic operation on the selected command signal; A first flip-flop, configured to latch the output of the first logic gate in response to an external clock signal transmitted from the memory controller, to generate the set signal; and The second flip-flop is configured to latch the output of the second logic gate in response to the external clock signal to generate the reset signal.

10. The semiconductor memory device of claim 9, wherein, The interface semiconductor chip is configured as follows: In response to the deactivation of the interface clock enable signal, all command pins among the plurality of command pins except for the selected command pin corresponding to the selected command signal are deactivated, and In response to the activation of the interface clock enable signal, the other command pins are activated.

11. The semiconductor memory device according to claim 7, wherein, Each of the interface command decoder and the memory command decoder includes decoding logic, the decoding logic comprising: Logic gates configured to perform logical operations on a selected command signal corresponding to a portion of the plurality of command signals; and A flip-flop, configured to latch the output of the logic gate in response to an external clock signal passed from the memory controller, to generate the set signal, and The decoding logic provides one of the selected command signals as the reset signal.

12. The semiconductor memory device of claim 11, wherein, The interface semiconductor chip is configured as follows: In response to the deactivation of the interface clock enable signal, all command pins except the one corresponding to the command signal are deactivated. In response to the activation of the interface clock enable signal, the other command pins are activated.

13. The semiconductor memory device of claim 1, wherein, The memory integrated circuits included in each memory semiconductor wafer form multiple channels that are accessed independently of each other by the memory controller.

14. The semiconductor memory device of claim 13, wherein, Each memory command decoder is assigned to each channel.

15. The semiconductor memory device of claim 1, wherein, The semiconductor memory device is a high-bandwidth memory device.

16. The semiconductor memory device of claim 15, wherein, The interface semiconductor chip is configured as follows: When the semiconductor memory device enters a first power mode where at least the first clock supply is blocked, one of the plurality of command pins is activated and the other command pins are deactivated. The interface semiconductor chip is configured as follows: When the semiconductor memory device exits the first power mode, the other command pins are activated.

17. A system comprising: Semiconductor memory devices; as well as The host device includes a memory controller configured to control the semiconductor memory device, wherein, The semiconductor memory device includes: An interface semiconductor chip includes a plurality of command pins configured to receive a plurality of command signals transmitted from the memory controller, and includes an interface command decoder configured to decode the plurality of command signals. A memory semiconductor wafer stacked with the interface semiconductor wafer, the memory semiconductor wafer including a memory integrated circuit configured to store data and a memory command decoder configured to decode the plurality of command signals transmitted from the interface semiconductor wafer; and Multiple silicon through-hole components electrically connect the interface semiconductor wafer to the memory semiconductor wafer. The interface semiconductor chip does not include a clock enable pin for receiving clock enable signals from the memory controller. The interface command decoder is configured to generate an interface clock enable signal to control a first clock supply relative to the interface semiconductor wafer based on power mode commands transmitted from the memory controller via the plurality of command pins, and The memory command decoder is configured to generate a memory clock enable signal to control a second clock supply relative to the memory semiconductor wafer based on the power mode command transmitted from the interface semiconductor wafer through the plurality of silicon pass-throughs.

18. The system according to claim 17, wherein, The memory controller does not transmit the clock enable signal to the semiconductor memory device, and The interface command decoder and the memory command decoder are configured to control the clock supply relative to the interface semiconductor wafer and the memory semiconductor wafer, respectively, based on the plurality of command signals.

19. A semiconductor memory device, comprising: An interface semiconductor chip includes a plurality of command pins configured to receive a plurality of command signals transmitted from a memory controller, and includes an interface command decoder configured to decode the plurality of command signals. A memory semiconductor wafer includes a memory integrated circuit configured to store data, and a memory command decoder configured to decode the plurality of command signals transmitted from the interface semiconductor wafer. as well as Multiple internal command paths electrically connect the interface semiconductor chip to the memory semiconductor chip, wherein, The interface semiconductor chip does not include a clock enable pin for receiving clock enable signals from the memory controller. The interface command decoder is configured to generate an interface clock enable signal to control a first clock supply relative to the interface semiconductor wafer based on power mode commands transmitted from the memory controller via the plurality of command pins, and The memory command decoder is configured to generate a memory clock enable signal to control a second clock supply relative to the memory semiconductor wafer based on the power mode command transmitted from the interface semiconductor wafer through the plurality of internal command paths.

20. The semiconductor memory device of claim 19, wherein, The semiconductor memory device is a stacked memory device consisting of the memory semiconductor wafer and the interface semiconductor wafer stacked together. Each of the plurality of internal command paths includes a silicon through-hole.

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