Calibration method of ic chip, related system and device

Abstract

This application relates to a calibration method, system, and apparatus for IC chips. The IC to be calibrated is assembled onto a finished PCB, and then voltage calibration is performed by connecting a calibration circuit to a port on the PCB. This allows for direct voltage and current calibration of the IC on the finished product, eliminating calibration deviations caused by test fixtures and PCB traces in traditional calibration methods. This effectively improves calibration accuracy and avoids the risk of damage to the IC during disassembly and assembly, ensuring higher quality ICs. Furthermore, by utilizing the on-board ports for calibration of mass-produced ICs, disassembly is unnecessary, making the operation simple and easy, significantly reducing costs and shortening the development cycle.

Description

Technical Field

[0001] This application belongs to the field of chip technology, specifically relating to a calibration method, related system and apparatus for IC chips. Background Technology

[0002] Due to variations in wafer manufacturing, integrated circuit (IC) chips require calibration of various internal parameters before leaving the factory. For DC-DC converter chips and protocol chips in automotive fast charging systems, output voltage and output current are key parameters that must be calibrated. The output current is generally understood to correspond to the overcurrent protection (OCP) point.

[0003] However, the applicant discovered that the current standard for IC chip calibration before leaving the factory is to install the IC to be calibrated onto a test fixture and then connect an external calibration circuit for calibration. Because the test fixture can introduce deviations in contact impedance, it may even weaken after prolonged testing, thus causing greater deviations in the IC. When the IC is soldered onto the finished printed circuit board (PCB) after leaving the factory, the impedance and differences in the PCB wiring will also introduce deviations in various parameters of the IC, which cannot meet the requirements for high precision. Summary of the Invention

[0004] This application provides a calibration method, related system, and apparatus for IC chips, aiming to eliminate calibration deviations caused by test fixtures and PCB traces in traditional calibration methods, effectively improve calibration accuracy, and avoid the risk of damage to ICs during disassembly and assembly in traditional calibration methods, thus ensuring better quality of ICs after delivery. At the same time, by utilizing the ports built into the finished product to calibrate the mass-produced product, there is no need to disassemble the casing, making the operation simple and easy, greatly reducing costs and shortening the development cycle.

[0005] In a first aspect, embodiments of this application provide a calibration method for an IC chip, characterized by a calibration circuit applied in a chip calibration system. The chip calibration system includes the IC chip mounted on a finished printed circuit board (PCB) and the calibration circuit. The calibration circuit includes an analog-to-digital converter (ADC) sampling module, switches K1 and K2, load resistors RL1 and RL2, a system communication module, and a processor. The voltage output port of the IC chip is connected to a first terminal of the ADC sampling module, a first terminal of switch K1, and a first terminal of switch K2. The second terminal of switch K1 is connected to a first terminal of load resistor RL1, and the second terminal of switch K2 is connected to a first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module. The method includes:

[0006] Disconnect switches K1 and K2 to make the output unloaded;

[0007] The system communication module sets the value of the internal output voltage register of the IC chip to VREG1, and then the ADC sampling module obtains the current actual output voltage VO1.

[0008] The system communication module sets the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module obtains the current actual output voltage as VO2.

[0009] The calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated are calculated using the following formulas:

[0010] Vstep=(VO2-VO1)÷(VREG2-VREG1),

[0011] Voffset=VO1-[(VO2-VO1)÷(VREG2-VREG1)]×VREG1,

[0012] The actual output voltage Vo of the IC chip and the value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship. The value of the internal output voltage register corresponds to the internal reference voltage of the IC chip. The first linear relationship satisfies the following formula:

[0013] VO = Voffset + Vstep × VREG

[0014] Wherein, Voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register.

[0015] Secondly, embodiments of this application provide a calibration circuit applied in a chip calibration system. The chip calibration system includes the IC chip mounted on a finished printed circuit board (PCB) and the calibration circuit. The calibration circuit includes an analog-to-digital converter (ADC) sampling module, switches K1 and K2, load resistors RL1 and RL2, a system communication module, and a processor.

[0016] The voltage output port of the IC chip is connected to the first terminal of the ADC sampling module, the first terminal of switch K1, and the first terminal of switch K2. The second terminal of switch K1 is connected to the first terminal of load resistor RL1, and the second terminal of switch K2 is connected to the first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module.

[0017] The calibration circuit is used to control the switches K1 and K2 to disconnect, so that the output is unloaded;

[0018] And for setting the value of the internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtaining the current actual output voltage VO1 through the ADC sampling module;

[0019] And the system communication module is used to set the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module obtains the current actual output voltage as VO2.

[0020] And the calibration values ​​for the voltage parameters Voffset and Vstep to be calibrated, which are calculated using the following formulas:

[0021] Vstep=(VO2-VO1)÷(VREG2-VREG1),

[0022] Voffset=VO1-[(VO2-VO1)÷(VREG2-VREG1)]×VREG1,

[0023] The actual output voltage Vo of the IC chip and the value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship. The value of the internal output voltage register corresponds to the internal reference voltage of the IC chip. The first linear relationship satisfies the following formula:

[0024] VO = Voffset + Vstep × VREG

[0025] Wherein, Voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register.

[0026] Thirdly, embodiments of this application provide a calibration circuit applied in a chip calibration system. The chip calibration system includes the IC chip mounted on a finished printed circuit board (PCB) and the calibration circuit. The calibration circuit includes an analog-to-digital converter (ADC) sampling module, switches K1 and K2, load resistors RL1 and RL2, a system communication module, and a processor. The voltage output port of the IC chip is connected to the first terminal of the ADC sampling module, the first terminal of switch K1, and the first terminal of switch K2. The second terminal of switch K1 is connected to the first terminal of load resistor RL1, and the second terminal of switch K2 is connected to the first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module. The device includes:

[0027] The disconnection unit is used to control the switches K1 and K2 to disconnect, so that the output is unloaded.

[0028] The sampling unit is used to set the value of the internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtain the current actual output voltage VO1 through the ADC sampling module; and to set the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtain the current actual output voltage VO2 through the ADC sampling module.

[0029] The calculation unit is used to calculate the calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated using the following formula:

[0030] Vstep=(VO2-VO1)÷(VREG2-VREG1),

[0031] Voffset=VO1-[(VO2-VO1)÷(VREG2-VREG1)]×VREG1,

[0032] The actual output voltage Vo of the IC chip and the value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship. The value of the internal output voltage register corresponds to the internal reference voltage of the IC chip. The first linear relationship satisfies the following formula:

[0033] VO = Voffset + Vstep × VREG

[0034] Wherein, Voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register.

[0035] Fourthly, embodiments of this application provide a calibration circuit including a processor, a memory, a communication interface, and one or more programs, the one or more programs being stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps in the first aspect of embodiments of this application.

[0036] Fifthly, embodiments of this application provide a computer storage medium, characterized in that it stores a computer program for electronic data interchange, wherein the computer program causes a computer to perform some or all of the steps described in the first aspect of this embodiment.

[0037] In a sixth aspect, this application provides a fast charging chip, which is an IC chip and is used in some or all of the steps described in the first aspect of this embodiment.

[0038] In a seventh aspect, embodiments of this application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in the first aspect of embodiments of this application. The computer program product may be a software installation package.

[0039] As can be seen, in this embodiment of the application, voltage calibration of IC is performed directly on the finished PCB, which can eliminate the calibration deviation caused by test fixtures and PCB traces in traditional calibration methods, effectively improve calibration accuracy, and avoid the risk of damage to IC during the disassembly and assembly process of traditional calibration methods. The quality of ICs leaving the factory is more guaranteed. At the same time, by using the ports built into the finished product to calibrate the mass-produced finished product, there is no need to disassemble the casing. The operation is simple and easy, greatly reducing costs and shortening the development cycle. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the circuit structure of an IC chip calibration system provided in an embodiment of this application;

[0041] Figure 2 This is a schematic flowchart of a calibration method for an IC chip provided in an embodiment of this application;

[0042] Figure 3 This is a functional unit block diagram of an IC chip calibration device provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram of the circuit structure of a calibration circuit for an IC chip provided in an embodiment of this application. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0045] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] This application describes a method for calibrating an IC chip. The IC to be calibrated is assembled onto a finished PCB, and then a calibration circuit is connected to the ports on the PCB for voltage and current calibration. During voltage and current calibration, the IC's internal output voltage and current registers are set, and different loads in the calibration circuit are switched. The actual output voltage of the PCB is then sampled, and the voltage and current calibration values ​​are calculated and input to the IC to achieve the calibration.

[0048] like Figure 1As shown in the embodiment of this application, the chip calibration system includes a finished PCB1 with an IC under test mounted thereon and a calibration circuit 2; wherein, the calibration circuit 2 includes an analog-to-digital converter (ADC) sampling module, a switch K1, a switch K2, a load resistor RL1, a load resistor RL2, a system communication module, and a processor;

[0049] The voltage output port of the IC chip is connected to the first terminal of the ADC sampling module, the first terminal of switch K1, and the first terminal of switch K2. The second terminal of switch K1 is connected to the first terminal of load resistor RL1, and the second terminal of switch K2 is connected to the first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module.

[0050] The IC chip includes, but is not limited to, DC-DC converter chips and protocol chips.

[0051] Both switches K1 and K2 can be controlled to close and close by a processor, which can be a microcontroller unit (MCU) or similar. The type of processor is not limited here.

[0052] The ADC sampling module can be, for example, a 16-bit ADC data acquisition chip such as AD7606, but this is not a unique limitation.

[0053] The resistance of load resistor RL1 can be 100 ohms, and the resistance of load resistor RL2 can be, for example, 1000 ohms, etc. There is no unique limitation here.

[0054] The connection between the IC chip and the calibration circuit can be achieved through traces on the PCB and external ports, or it can be a direct connection; no single limitation is made here. For example, the IC chip can connect to the system communication module of the calibration circuit through commonly used pins of the USB port on the PCB (e.g., CC, D+, D-, etc.), enabling communication with the internal IC chip and allowing control over reading and writing of the IC's internal registers, as well as switching the current output voltage or current of the IC chip.

[0055] The calibration circuit further includes a memory connected to the processor, which stores a program for executing the steps in the current and voltage calibration method of the embodiments of this application.

[0056] The calibration circuit is used to control the switches K1 and K2 to disconnect, so that the output is unloaded;

[0057] And for setting the value of the internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtaining the current actual output voltage VO1 through the ADC sampling module;

[0058] And the system communication module is used to set the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module obtains the current actual output voltage as VO2.

[0059] And the calibration values ​​for the voltage parameters Voffset and Vstep to be calibrated, which are calculated using the following formulas:

[0060] Vstep=(VO2-VO1)÷(VREG2-VREG1),

[0061] Voffset=VO1-[(VO2-VO1)÷(VREG2-VREG1)]×VREG1,

[0062] The actual output voltage Vo of the IC chip and the value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship. The value of the internal output voltage register corresponds to the internal reference voltage of the IC chip. The first linear relationship satisfies the following formula:

[0063] VO = Voffset + Vstep × VREG

[0064] Wherein, Voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register.

[0065] Voffset and Vstep are the voltage calibration parameters of the IC chip.

[0066] Since the actual output voltage Vo of the IC chip and the value IREG of the IC chip's internal output voltage register satisfy the first linear relationship, during testing, the value of the internal output voltage register is set to VREG1, and the calibration system satisfies the equation...

[0067] VO1 = Voffset + Vstep × VREG1

[0068] The value of the internal output voltage register is set to VREG2, and the calibration system satisfies the equation.

[0069] VO2 = Voffset + Vstep × VREG2

[0070] Subtracting the two equations, we get

[0071] VO2-VO1=Vstep×VREG2-Vstep×VREG1,

[0072] That is, Vstep=(VO2-VO1)÷(VREG2-VREG1).

[0073] In one possible example, the calibration circuit is also used to set the value of the internal output voltage register of the IC chip to VREG3 via the system communication module;

[0074] The internal output current register of the IC chip is set to its maximum value. Switch K1 is closed, switch K2 is opened, and the current actual output voltage VO3 is obtained through the ADC sampling module. The current actual output current IO1 is then calculated using the following formula:

[0075] IO1 = VO3 ÷ RL1,

[0076] The internal output current register of the IC chip is set, and the output voltage is gradually decreased and sampled until the current output voltage decreases or is completely turned off, which triggers the overcurrent protection action and obtains the value of the internal output current register IREG1. The value of the internal output current register IREG1 corresponds to the overcurrent protection OCP point of the current output current.

[0077] Set the value of the internal output current register of the IC chip to its maximum value, open switch K1, close switch K2, and then obtain the current actual output voltage VO4 through the ADC sampling module. Calculate the current actual output current IO2 using the following formula:

[0078] IO2 = VO4 ÷ RL2,

[0079] The internal output current register of the IC chip is set, and the output voltage is decreased step by step and the output voltage is collected until the current output voltage decreases or is completely turned off, which triggers the overcurrent protection action and obtains the value of the internal output current register IREG2. The value of the internal output current register IREG2 corresponds to the overcurrent protection OCP point of the current output current.

[0080] The calibration values ​​of the current parameters IOffset and Istep to be calibrated are calculated using the following formulas:

[0081] Istep=(IO2-IO1)÷(IREG2-IREG1),

[0082] IOffset=IO1-[(IO2-IO1)÷(IREG2-IREG1)]×IREG1,

[0083] The actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship. The value of the internal output current register corresponds to the output current when the IC chip reaches the overcurrent protection state. The second linear relationship satisfies the following formula:

[0084] IO = IOffset + Istep × IREG

[0085] Where IOffset is the drift of the internal output current register, and Istep is the current step size of the internal output current register.

[0086] Among them, IOffset and Istep are the current calibration parameters of the IC chip.

[0087] Because the actual output current IO of the IC chip and the value IRG of the internal output current register of the IC chip satisfy the second linear relationship, the initial value of the internal output current register is set to the maximum value during testing. In this case, the actual current VO / RL is less than the maximum set current (i.e., the overcurrent protection point). Therefore, the level of the internal output current register needs to be gradually reduced, continuously monitored until it decreases to the reference value, at which point it takes effect (i.e., the overcurrent protection activates, specifically manifested as the current output voltage starting to decrease or completely shutting off). Different load resistors RL correspond to different overcurrent protection point currents IO, and thus the corresponding values ​​of the internal output current register are also different.

[0088] Specifically, when the load resistor RL1 is applied, the calibration system satisfies the equation

[0089] IO1 = IOffset + Istep × IREG1

[0090] When the load resistor RL2 is applied, the calibration system satisfies the equation

[0091] IO2 = IOffset + Istep × IREG2

[0092] Subtracting the two equations, we get

[0093] IO2-IO1=Istep×IREG2-Istep×IREG1=Istep×(IREG2-IREG1),

[0094] That is, Istep = (IO2 - IO1) ÷ (IREG2 - IREG1).

[0095] As can be seen, in this example, directly calibrating the IC on the finished PCB eliminates calibration deviations caused by test fixtures and PCB traces in traditional calibration methods, effectively improving calibration accuracy. It also avoids the risk of damage to the IC during disassembly and assembly, ensuring higher quality ICs at the factory. Furthermore, calibrating mass-produced ICs using the onboard ports eliminates the need for disassembly, simplifying operation, significantly reducing costs, and shortening the development cycle. The calibration circuit is suitable for both voltage and current calibration, offering flexibility and comprehensiveness.

[0096] In one possible example, before the calibration circuit gradually decreases in step size, it is further configured to: acquire historical test data of multiple IC chips on the same calibrated production line; determine the deviation of the target parameter of each of the multiple IC chips based on the historical test data, the target parameter including output voltage and / or output current; identify at least one IC chip among the multiple IC chips whose deviation is greater than a preset deviation; determine the accuracy of the chip calibration system based on the at least one IC chip and the multiple IC chips; determine the user-set single-chip calibration reference speed-up time; and obtain the target step size for calibration of this batch of products based on the accuracy, the single-chip calibration reference speed-up time, the preset reference step size, the reference accuracy, and the single-chip calibration reference time.

[0097] The preset deviation can be, for example, 2%, 1%, 0.1%, etc., and is not limited to a single value. The higher the accuracy of the chip calibration system, the more chips will have deviations within the preset range during actual use after calibration.

[0098] The travel of the internal current register can be, for example, 0-2. 8 That is, 0-256, the reference accuracy can be, for example, 98%, the reference range step size can be set according to the reference accuracy, for example, by experimental testing or by experience to one percent of the stroke (rounded down), i.e., 2 or 3, the single-chip calibration reference time corresponds to the overall time for a single chip to complete the calibration process, which is mainly affected by the number of downgrades (other parameters such as load resistance can be kept consistent to reduce the influence of differential factors). In other words, the range step size is positively correlated with the accuracy and negatively correlated with the single-chip calibration time. By comprehensively considering the influence of accuracy and single-chip calibration time, calibration efficiency and accuracy can be balanced.

[0099] In one possible example, regarding obtaining the target gear step size for calibration of this batch of products based on the accuracy, the single-chip calibration reference speed-up time, the preset reference gear step size, the reference accuracy, and the single-chip calibration reference time, the calibration circuit is specifically used for:

[0100] The range step size SG of the internal output current register is updated using the following formula:

[0101] SG=SG0,τ≧τ0,

[0102]

[0103] Wherein, SG represents the target gear step size, SG0 represents the reference gear step size, SG0 is 1 / 10 of the internal output current register travel, τ represents accuracy, τ0 represents reference accuracy, τ0 is a value specified by industry standards, ΔT represents the single-chip calibration reference speed-up time, and T0 represents the single-chip calibration reference time.

[0104] The accuracy value ranges from [0,1], and the single-chip calibration reference time is obtained based on the actual circuit process detection, which is generally between 100ms and 5 seconds.

[0105] As can be seen in this example, by statistically analyzing the historically calibrated chips, the actual accuracy of the chip calibration system is obtained. For cases where the accuracy is greater than or equal to the reference accuracy, it indicates that the current step size meets the requirements and no further enhancement is needed. For cases where the accuracy is less than the reference accuracy, it indicates that the chip calibration system needs to increase its speed to improve its calibration performance. By comprehensively considering accuracy and single-chip testing time, both calibration efficiency and precision can be balanced.

[0106] In one possible example, the calibration circuit is also used to: write the calibrated voltage calibration value and / or current calibration value into the internal memory of the IC chip.

[0107] Once the IC chip is calibrated, it can calculate the precise output voltage and current according to the formula.

[0108] In one possible example, the internal memory includes any of the following: random access memory (RAM), double data rate synchronous dynamic random access memory (DDR), and non-volatile memory (NVM).

[0109] The storage methods of the internal memory of IC chips include, but are not limited to, the following: flash memory mode, MTP mode (Media Transfer Protocol developed by Microsoft), one-time programmable OTP mode, etc.

[0110] In addition, the IC chip also includes a first differential pressure sampling port IS+ and a second differential pressure sampling port IS-, with a sampling resistor RS connected in series between the two ports. The IC chip can calculate the current output current IO of the IC chip by sampling the voltage difference between IS+ and IS-.

[0111] As can be seen, in this embodiment of the application, voltage calibration of IC is performed directly on the finished PCB, which can eliminate the calibration deviation caused by test fixtures and PCB traces in traditional calibration methods, effectively improve calibration accuracy, and avoid the risk of damage to IC during the disassembly and assembly process of traditional calibration methods. The quality of ICs leaving the factory is more guaranteed. At the same time, by using the ports built into the finished product to calibrate the mass-produced finished product, there is no need to disassemble the casing. The operation is simple and easy, greatly reducing costs and shortening the development cycle.

[0112] Please see Figure 2 , Figure 2 This is a flowchart illustrating a calibration method for an IC chip provided in an embodiment of this application, applicable to, for example... Figure 1 The calibration circuit in the chip calibration system shown in the figure is as follows. The calibration method for this IC chip includes the following operations.

[0113] Step 201: Control the switches K1 and K2 to disconnect, so that the output is unloaded;

[0114] Step 202: Set the value of the internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtain the current actual output voltage VO1 through the ADC sampling module;

[0115] Step 203: Set the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtain the current actual output voltage as VO2 through the ADC sampling module;

[0116] Step 204: Calculate the calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated using the following formulas:

[0117] Vstep=(VO2-VO1)÷(VREG2-VREG1),

[0118] Voffset=VO1-[(VO2-VO1)÷(VREG2-VREG1)]×VREG1,

[0119] The actual output voltage Vo of the IC chip and the value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship. The value of the internal output voltage register corresponds to the internal reference voltage of the IC chip. The first linear relationship satisfies the following formula:

[0120] VO = Voffset + Vstep × VREG

[0121] Wherein, Voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register.

[0122] In one possible instance, the method further includes:

[0123] The system communication module sets the value of the internal output voltage register of the IC chip to VREG3;

[0124] The internal output current register of the IC chip is set to its maximum value. Switch K1 is closed, switch K2 is opened, and the current actual output voltage VO3 is obtained through the ADC sampling module. The current actual output current IO1 is then calculated using the following formula:

[0125] IO1 = VO3 ÷ RL1,

[0126] The internal output current register of the IC chip is set, and the output voltage is gradually decreased and sampled until the current output voltage decreases or is completely turned off, which triggers the overcurrent protection action and obtains the value of the internal output current register IREG1. The value of the internal output current register IREG1 corresponds to the overcurrent protection OCP point of the current output current.

[0127] Set the value of the internal output current register of the IC chip to its maximum value, open switch K1, close switch K2, and then obtain the current actual output voltage VO4 through the ADC sampling module. Calculate the current actual output current IO2 using the following formula:

[0128] IO2 = VO4 ÷ RL2,

[0129] The internal output current register of the IC chip is set, and the output voltage is decreased step by step and the output voltage is collected until the current output voltage decreases or is completely turned off, which triggers the overcurrent protection action and obtains the value of the internal output current register IREG2. The value of the internal output current register IREG2 corresponds to the overcurrent protection OCP point of the current output current.

[0130] The calibration values ​​of the current parameters IOffset and Istep to be calibrated are calculated using the following formulas:

[0131] Istep=(IO2-IO1)÷(IREG2-IREG1),

[0132] IOffset=IO1-[(IO2-IO1)÷(IREG2-IREG1)]×IREG1,

[0133] The actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship. The value of the internal output current register corresponds to the output current when the IC chip reaches the overcurrent protection state. The second linear relationship satisfies the following formula:

[0134] IO = IOffset + Istep × IREG

[0135] Where IOffset is the drift of the internal output current register, and Istep is the current step size of the internal output current register.

[0136] In one possible instance, prior to the step-by-step reduction operation, the method further includes:

[0137] Obtain historical test data for multiple IC chips on the same calibrated production line;

[0138] The deviation of the target parameters for each of the plurality of IC chips is determined based on the historical detection data, wherein the target parameters include output voltage and / or output current;

[0139] Identify at least one IC chip among the plurality of IC chips whose deviation is greater than a preset deviation;

[0140] The accuracy of the chip calibration system is determined based on the at least one IC chip and the plurality of IC chips;

[0141] Determine the user-set single-chip calibration reference speed-up time;

[0142] Based on the accuracy, the single-chip calibration reference acceleration time, the preset reference range step size, the reference accuracy, and the single-chip calibration reference time, the target range step size for calibration of this batch of products is obtained.

[0143] In one possible instance, obtaining the target gear step size for calibration of this batch of products based on the accuracy, the single-chip calibration reference acceleration time, the preset reference gear step size, the reference accuracy, and the single-chip calibration reference time includes:

[0144] The range step size SG of the internal output current register is updated using the following formula:

[0145] SG=SG0,τ≧τ0,

[0146]

[0147] Wherein, SG represents the target gear step size, SG0 represents the reference gear step size, SG0 is 1 / 10 of the internal output current register travel, τ represents accuracy, τ0 represents reference accuracy, τ0 is a value specified by industry standards, ΔT represents the single-chip calibration reference speed-up time, and T0 represents the single-chip calibration reference time.

[0148] In one possible instance, the internal memory includes any of the following: random access memory (RAM), double data rate synchronous dynamic random access memory (DDR), and non-volatile memory (NVM).

[0149] As can be seen, in this embodiment, voltage calibration of IC directly on the finished PCB can eliminate calibration deviations caused by test fixtures and PCB traces in traditional calibration methods, effectively improve calibration accuracy, and avoid the risk of damage to IC during disassembly and assembly in traditional calibration methods. This ensures better quality of ICs leaving the factory. At the same time, by using the ports built into the finished product to calibrate the mass-produced product, there is no need to disassemble it. The operation is simple and easy, greatly reducing costs and shortening the development cycle.

[0150] With the above Figure 2 The embodiments shown are consistent; please refer to [link / reference]. Figure 3 , Figure 3 This is a functional unit block diagram of an IC chip calibration device provided in an embodiment of this application. The IC chip calibration device 300 shown is applied to, for example... Figure 1 The chip calibration system shown; the device includes:

[0151] Disconnection unit 301 is used to control the switches K1 and K2 to disconnect, so that the output is unloaded;

[0152] The sampling unit 302 is used to set the value of the internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtain the current actual output voltage VO1 through the ADC sampling module; and to set the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtain the current actual output voltage VO2 through the ADC sampling module.

[0153] Calculation unit 303 is used to calculate the calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated using the following formula:

[0154] Vstep=(VO2-VO1)÷(VREG2-VREG1),

[0155] Voffset=VO1-[(VO2-VO1)÷(VREG2-VREG1)]×VREG1,

[0156] The actual output voltage Vo of the IC chip and the value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship. The value of the internal output voltage register corresponds to the internal reference voltage of the IC chip. The first linear relationship satisfies the following formula:

[0157] VO = Voffset + Vstep × VREG

[0158] Wherein, Voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register.

[0159] In one possible instance, the device further includes:

[0160] The setting unit is used to set the value of the internal output voltage register of the IC chip to VREG3 through the system communication module;

[0161] The sampling unit is also used to set the value of the internal output current register of the IC chip to the maximum value, close the switch K1, open the switch K2, and then obtain the current actual output voltage VO3 through the ADC sampling module, and calculate the current actual output current IO1 using the following formula:

[0162] IO1 = VO3 ÷ RL1,

[0163] The sampling unit is also used to set the internal output current register of the IC chip, gradually decrease and sample the output voltage until the current output voltage decreases or is completely turned off, triggering the overcurrent protection action, and obtaining the value IREG1 of the currently set internal output current register. The value IREG1 of the currently set internal output current register corresponds to the overcurrent protection OCP point of the current output current.

[0164] The sampling unit is also used to set the value of the internal output current register of the IC chip to the maximum value, open the switch K1, close the switch K2, and then obtain the current actual output voltage VO4 through the ADC sampling module, and calculate the current actual output current IO2 using the following formula:

[0165] IO2 = VO4 ÷ RL2,

[0166] The sampling unit is also used to set the internal output current register of the IC chip, decrease the output voltage step by step and collect the output voltage until the current output voltage decreases or is completely turned off, triggering the overcurrent protection action, and obtaining the value of the internal output current register IREG2, which corresponds to the overcurrent protection OCP point of the current output current.

[0167] The calculation unit is used to calculate the calibration values ​​of the current parameters IOffset and Istep to be calibrated using the following formula:

[0168] Istep=(IO2-IO1)÷(IREG2-IREG1),

[0169] IOffset=IO1-[(IO2-IO1)÷(IREG2-IREG1)]×IREG1,

[0170] The actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship. The value of the internal output current register corresponds to the output current when the IC chip reaches the overcurrent protection state. The second linear relationship satisfies the following formula:

[0171] IO = IOffset + Istep × IREG

[0172] Where IOffset is the drift of the internal output current register, and Istep is the current step size of the internal output current register.

[0173] In one possible instance, before the step-by-step reduction operation, the sampling unit is further configured to: acquire historical test data of multiple IC chips on the same calibrated production line; determine the deviation of a target parameter for each of the multiple IC chips based on the historical test data, the target parameter including output voltage and / or output current; identify at least one IC chip among the multiple IC chips whose deviation is greater than a preset deviation; determine the accuracy of the chip calibration system based on the at least one IC chip and the multiple IC chips; determine the user-set single-chip calibration reference acceleration time; and obtain the target step size for calibration of this batch of products based on the accuracy, the single-chip calibration reference acceleration time, the preset reference step size, the reference accuracy, and the single-chip calibration reference time.

[0174] In one possible instance, the sampling unit is specifically used to update the range step size SG of the internal output current register using the following formula:

[0175] SG=SG0,τ≧τ0,

[0176]

[0177] Wherein, SG represents the target gear step size, SG0 represents the reference gear step size, SG0 is 1 / 10 of the internal output current register travel, τ represents accuracy, τ0 represents reference accuracy, τ0 is a value specified by industry standards, ΔT represents the single-chip calibration reference speed-up time, and T0 represents the single-chip calibration reference time.

[0178] In one possible instance, the device further includes:

[0179] The programming unit is used to program the calibrated voltage and / or current calibration values ​​into the internal memory of the IC chip.

[0180] In one possible instance, the internal memory includes any of the following: random access memory (RAM), double data rate synchronous dynamic random access memory (DDR), and non-volatile memory (NVM).

[0181] It is understood that since the method embodiments and the device embodiments are different presentations of the same technical concept, the content of the method embodiment section in this application should be adapted to the device embodiment section in a synchronous manner, and will not be repeated here.

[0182] With the above Figure 2 The embodiments shown are consistent; please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of the structure of a calibration circuit 400 provided in an embodiment of this application. As shown in the figure, the calibration circuit 400 includes a processor 410, a memory 420, an ADC sampling module 430, a system communication module 440, and one or more programs 421. The one or more programs 421 are stored in the memory 420 and configured to be executed by the application processor 410. The one or more programs 421 include instructions for performing any step in the above method embodiment.

[0183] The foregoing mainly describes the embodiments of this application from the perspective of the method execution process. It is understood that, in order to achieve the above functions, the calibration circuit includes the corresponding hardware structure and software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments provided herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0184] This application embodiment can divide the calibration circuit into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0185] This application also provides a chip, wherein the chip includes a processor for calling and running a computer program from a memory, causing a device on which the chip is installed to perform some or all of the steps described in the calibration circuit of the above method embodiments.

[0186] This application also provides a computer storage medium storing a computer program for electronic data interchange, the computer program causing a computer to perform some or all of the steps of any of the methods described in the above method embodiments, the computer including a calibration circuit.

[0187] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package, and the computer includes calibration circuitry.

[0188] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0189] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0190] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0191] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0192] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0193] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0194] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0195] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip calibration system, characterized in that, The chip calibration system includes an IC chip and a calibration circuit mounted on a finished printed circuit board (PCB). The calibration circuit includes an analog-to-digital converter (ADC) sampling module, switches K1 and K2, load resistors RL1 and RL2, a system communication module, and a processor. The voltage output port of the IC chip is connected to the first terminal of the ADC sampling module, the first terminal of switch K1, and the first terminal of switch K2. The second terminal of switch K1 is connected to the first terminal of load resistor RL1, and the second terminal of switch K2 is connected to the first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module. The IC chip includes a DC-DC converter chip and a protocol chip; Switches K1 and K2 are controlled to close and close by the processor.

2. A calibration method for an integrated circuit (IC) chip, characterized in that, A calibration circuit is used in a chip calibration system. The chip calibration system includes an IC chip mounted on a finished printed circuit board (PCB) and the calibration circuit. The calibration circuit includes an analog-to-digital converter (ADC) sampling module, switches K1 and K2, load resistors RL1 and RL2, a system communication module, and a processor. The voltage output port of the IC chip is connected to the first terminal of the ADC sampling module, the first terminal of switch K1, and the first terminal of switch K2. The second terminal of switch K1 is connected to the first terminal of load resistor RL1, and the second terminal of switch K2 is connected to the first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module. in, The IC chip includes a DC-DC converter chip and a protocol chip; Among them, switches K1 and K2 are controlled to close and close by the processor; The method includes: Disconnect switches K1 and K2 to make the output unloaded; The system communication module sets the value of the internal output voltage register of the IC chip to VREG1, and then the ADC sampling module obtains the current actual output voltage VO1. The system communication module sets the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module obtains the current actual output voltage as VO2. The calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated are calculated using a preset formula.

3. The method according to claim 2, characterized in that, The calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated are calculated using preset formulas, including: the calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated are calculated using the following formulas: Vstep=(VO2-VO1)÷(VREG2-VREG1), Voffset=VO1-[(VO2-VO1)÷(VREG2-VREG1)]×VREG1, The actual output voltage Vo of the IC chip and the value VREG of the internal output voltage register of the IC chip satisfy a first linear relationship. The value of the internal output voltage register corresponds to the internal reference voltage of the IC chip. The first linear relationship satisfies the following formula: VO = Voffset + Vstep × VREG Wherein, Voffset is the drift of the internal output voltage register, and Vstep is the voltage step size of the internal output voltage register.

4. The method according to claim 3, characterized in that, The method further includes: The system communication module sets the value of the internal output voltage register of the IC chip to VREG3; The internal output current register of the IC chip is set to its maximum value. Switch K1 is closed, switch K2 is opened, and the current actual output voltage VO3 is obtained through the ADC sampling module. The current actual output current IO1 is then calculated using the following formula: IO1 = VO3 ÷ RL1 The internal output current register of the IC chip is set, and the output voltage is gradually decreased and sampled until the current output voltage decreases or is completely turned off, which triggers the overcurrent protection action and obtains the value of the internal output current register IREG1. The value of the internal output current register IREG1 corresponds to the overcurrent protection OCP point of the current output current. Set the value of the internal output current register of the IC chip to its maximum value, open switch K1, close switch K2, and then obtain the current actual output voltage VO4 through the ADC sampling module. Calculate the current actual output current IO2 using the following formula: IO2 = VO4 ÷ RL2, The internal output current register of the IC chip is set, and the output voltage is decreased step by step and the output voltage is collected until the current output voltage decreases or is completely turned off, which triggers the overcurrent protection action and obtains the value of the internal output current register IREG2. The value of the internal output current register IREG2 corresponds to the overcurrent protection OCP point of the current output current. The calibration values ​​of the current parameters IOffset and Istep to be calibrated are calculated using the following formulas: Istep=(IO2-IO1)÷(IREG2-IREG1), IOffset=IO1-[(IO2-IO1)÷(IREG2-IREG1)]×IREG1, The actual output current IO of the IC chip and the value IREG of the internal output current register of the IC chip satisfy a second linear relationship. The value of the internal output current register corresponds to the output current when the IC chip reaches the overcurrent protection state. The second linear relationship satisfies the following formula: IO = IOffset + Istep × IREG Where IOffset is the drift of the internal output current register, and Istep is the current step size of the internal output current register.

5. The method according to claim 4, characterized in that, Before the step-by-step reduction operation, the method further includes: Obtain historical test data for multiple IC chips on the same calibrated production line; The deviation of the target parameters for each of the plurality of IC chips is determined based on the historical detection data, wherein the target parameters include output voltage and / or output current; Identify at least one IC chip among the plurality of IC chips whose deviation is greater than a preset deviation; The accuracy of the chip calibration system is determined based on the at least one IC chip and the plurality of IC chips; Determine the user-set single-chip calibration reference speed-up time; Based on the accuracy, the single-chip calibration reference acceleration time, the preset reference range step size, the reference accuracy, and the single-chip calibration reference time, the target range step size for calibration of this batch of products is obtained.

6. A calibration circuit, characterized in that, A calibration circuit is used in a chip calibration system, the chip calibration system including an IC chip mounted on a finished printed circuit board (PCB) and the calibration circuit, the calibration circuit including an analog-to-digital converter (ADC) sampling module, switch K1, switch K2, load resistor RL1, load resistor RL2, a system communication module, and a processor; The voltage output port of the IC chip is connected to the first terminal of the ADC sampling module, the first terminal of switch K1, and the first terminal of switch K2. The second terminal of switch K1 is connected to the first terminal of load resistor RL1, and the second terminal of switch K2 is connected to the first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module. in, The IC chip includes a DC-DC converter chip and a protocol chip; Among them, switches K1 and K2 are controlled to close and close by the processor; The calibration circuit is used to control the switches K1 and K2 to disconnect, so that the output is unloaded; And for setting the value of the internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtaining the current actual output voltage VO1 through the ADC sampling module; And the system communication module is used to set the value of the internal output voltage register of the IC chip to VREG2, and then the ADC sampling module obtains the current actual output voltage as VO2. And the calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated are calculated using a preset formula.

7. A calibration device for an IC chip, characterized in that, A calibration circuit is used in a chip calibration system. The chip calibration system includes an IC chip mounted on a finished printed circuit board (PCB) and the calibration circuit. The calibration circuit includes an analog-to-digital converter (ADC) sampling module, switches K1 and K2, load resistors RL1 and RL2, a system communication module, and a processor. The voltage output port of the IC chip is connected to the first terminal of the ADC sampling module, the first terminal of switch K1, and the first terminal of switch K2. The second terminal of switch K1 is connected to the first terminal of load resistor RL1, and the second terminal of switch K2 is connected to the first terminal of load resistor RL2. The second terminal of the ADC sampling module, the second terminal of load resistor RL1, and the second terminal of load resistor RL2 are combined and grounded. The processor is connected to the ADC sampling module and the system communication module, and the IC chip is connected to the system communication module. in, The IC chip includes a DC-DC converter chip and a protocol chip; Among them, switches K1 and K2 are controlled to close and close by the processor; The device includes: The disconnection unit is used to control the switches K1 and K2 to disconnect, so that the output is unloaded. The sampling unit is used to set the value of the internal output voltage register of the IC chip to VREG1 through the system communication module, and then obtain the current actual output voltage VO1 through the ADC sampling module; and to set the value of the internal output voltage register of the IC chip to VREG2 through the system communication module, and then obtain the current actual output voltage VO2 through the ADC sampling module. The calculation unit is used to calculate the calibration values ​​of the voltage parameters Voffset and Vstep to be calibrated using preset formulas.

8. A calibration circuit, characterized in that, It includes a processor, a memory, and one or more programs, said one or more programs being stored in the memory and configured to be executed by the processor, said programs including instructions for performing the steps of the method as described in any one of claims 2-5.

9. A fast charging chip, characterized in that, The fast charging chip is an IC chip, and it is used in the calibration method of the IC chip as described in any one of claims 2-5.

10. A computer-readable storage medium, characterized in that, A computer program for storing electronic data interchange is provided, wherein the computer program causes a computer to perform the method as described in any one of claims 2-5.

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