Chip-scale packaged light emitting diodes

Abstract

A chip-scale packaged light emitting diode is provided. In the light emitting diode according to the present embodiment, the opening for exposing the pad metal layer is separated from the opening of the lower insulating layer for exposing the ohmic reflective layer formed on the mesa, so that the solder, especially Sn, can be prevented from diffusing and contaminating the ohmic reflective layer.

Description

[0001] This application is a divisional application of a patent application with an application date of August 31, 2017, application number 201780051117.4, and titled “Chip-Scale Packaged Light Emitting Diode”. Technical Field

[0002] The invention relates to a light emitting diode, and in particular to a light emitting diode in a chip-level packaging form. Background Art

[0003] Generally, nitrides of group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have good thermal stability and direct transition band structures, and therefore have recently attracted much attention as light source materials in the visible and ultraviolet regions. In particular, blue and green light-emitting diodes using indium gallium nitride (InGaN) are used in a variety of applications such as large-scale natural color flat panel display devices, signal lights, indoor lighting, high-density light sources, high-resolution output systems, and optical communications.

[0004] Recently, research on chip-scale packaging of light-emitting diodes is being conducted. Since the size of such light-emitting diodes is smaller than that of general packages and there is no need to perform a separate packaging process, the process can be further simplified, thereby saving time and cost.

[0005] A light emitting diode in a chip-scale package generally has a flip-chip-shaped electrode structure, and thus has good heat dissipation characteristics. However, such a light emitting diode is usually manufactured to have a flip-chip-shaped electrode structure, and thus has a problem of making the structure of the light emitting diode quite complicated in order to prevent the diffusion of solder used in flip-chip soldering. However, the solder (especially Sn) may diffuse into the interior of the light emitting diode, thereby contaminating the ohmic reflective layer and causing a defective light emitting diode.

[0006] Therefore, there is a need to provide a light emitting diode that can simplify the structure of the light emitting diode and is reliable. Summary of the invention

[0007] Technical issues

[0008] An object of the present invention is to provide a light emitting diode that can effectively prevent diffusion of solder or other soldering materials without complicatedly changing the structure of the light emitting diode, thereby improving reliability.

[0009] Another problem to be solved by the present invention is to provide a light emitting diode that can effectively prevent the diffusion of solder within a limited design range.

[0010] Another problem to be solved by the present invention is to provide a light emitting diode capable of preventing solder from diffusing in a light emitting diode including a plurality of light emitting units.

[0011] Technical Solution

[0012] A light emitting diode according to an embodiment of the present invention comprises: a substrate; a first conductive semiconductor layer arranged on the substrate; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; an ohmic reflective layer arranged on the table and electrically connected to the second conductive semiconductor layer; a lower insulating layer covering the table and the ohmic reflective layer and comprising a first opening portion for exposing the first conductive semiconductor layer and a second opening portion for exposing the ohmic reflective layer; a first pad metal layer arranged on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening portion; a second pad metal layer arranged on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening portion; and an upper insulating layer covering the first pad metal layer and the second pad metal layer and comprising a first opening portion for exposing the first pad metal layer and a second opening portion for exposing the second pad metal layer, wherein the second opening portion of the upper insulating layer is separated from the second opening portion of the lower insulating layer.

[0013] Since the second opening of the upper insulating layer is separated from the second opening of the lower insulating layer, diffusion of solder into the ohmic reflective layer can be blocked.

[0014] Furthermore, the shortest distance from the second opening of the lower insulating layer to the second opening of the upper insulating layer may be greater than the shortest distance from the second opening of the lower insulating layer to the edge of the second pad metal layer. Although the upper insulating layer and the lower insulating layer block the diffusion of solder, the solder may reach the second opening of the lower insulating layer along the boundary between the lower insulating layer and the second pad metal layer. Therefore, by isolating the second opening of the lower insulating layer away from the second opening of the upper insulating layer within a limited design range, the diffusion path of the solder can be increased, thereby preventing the occurrence of defects caused by the diffusion of solder.

[0015] In addition, the first opening of the lower insulating layer can expose the first conductive type semiconductor layer along the periphery of the mesa, and the first pad metal layer has an external contact portion that contacts the first conductive type semiconductor layer along the periphery of the mesa. Since the first pad metal layer contacts the first conductive type semiconductor layer along the periphery of the mesa, the current dispersion performance of the light emitting diode can be improved.

[0016] Furthermore, the mesa may include a recessed portion that exposes the first conductive semiconductor layer, and the first opening of the lower insulating layer further exposes the first conductive semiconductor layer in the recessed portion. Furthermore, the first pad metal layer may also include an internal contact portion that contacts the first conductive semiconductor layer in the recessed portion. Since the first pad metal layer contacts the first conductive semiconductor layer at the edge of the mesa and inside the mesa, the current dispersion performance of the light-emitting diode is further enhanced.

[0017] Furthermore, the internal contact portion may be connected to the external contact portion, but the present invention is not limited thereto, and the internal contact portion and the external contact portion may also be separated from each other.

[0018] In addition, the second opening of the lower insulating layer may have a shape that is convex on the side facing the second opening of the upper insulating layer, and the second opening of the upper insulating layer may have a concave shape corresponding to the convex shape of the second opening of the lower insulating layer. The second opening of the lower insulating layer may have a size that is relatively smaller than the second opening of the upper insulating layer. Therefore, the convex shape of the lower insulating layer is conducive to patterning. In addition, by making the second opening of the upper insulating layer have a concave portion, the separation distance from the lower insulating layer can be increased.

[0019] In some embodiments, the first pad metal layer and the second pad metal layer exposed through the first opening and the second opening of the upper insulating layer may be solder pads directly soldered with solder. Therefore, the solder contacts the upper surfaces of the first pad metal layer and the second pad metal layer exposed through the opening of the upper insulating layer.

[0020] In another embodiment, the light emitting diode may further include: a first bump pad and a second bump pad, respectively covering the first pad metal layer and the second pad metal layer exposed through the first opening and the second opening of the upper insulating layer. The first bump pad and the second bump pad may lengthen the diffusion path of the solder.

[0021] Furthermore, the first bump pad and the second bump pad may respectively cover the first opening and the second opening of the upper insulating layer to be sealed, thereby preventing the solder from directly contacting the first pad metal layer and the second pad metal layer.

[0022] In addition, the second bump pad may further cover the upper insulating layer above the second opening of the lower insulating layer.

[0023] According to another embodiment of the present invention, a light emitting diode comprises: a substrate; a first light emitting unit and a second light emitting unit, which are adjacently arranged on the substrate and each comprises a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; an ohmic reflective layer, which is arranged on the second conductive semiconductor layer of the first light emitting unit and the second light emitting unit, respectively; a lower insulating layer, which covers the first light emitting unit, the second light emitting unit and the ohmic reflective layer, and has a first opening portion for exposing the first conductive semiconductor layer of the first light emitting unit and the second light emitting unit and a lower insulating layer for exposing the first conductive semiconductor layer of the first light emitting unit and the second light emitting unit. The ohmic reflective layer is exposed at a second opening; a first pad metal layer is arranged on the lower insulating layer and electrically connected to the first conductive semiconductor layer of the first light-emitting unit through the first opening on the first light-emitting unit; a second pad metal layer is arranged on the lower insulating layer and electrically connected to the ohmic reflective layer on the second light-emitting unit through the second opening of the second light-emitting unit; and an upper insulating layer having a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, wherein the second opening of the upper insulating layer is separated from the second opening of the lower insulating layer.

[0024] Therefore, it is possible to provide a light emitting diode capable of preventing diffusion of solder in a light emitting diode including a plurality of light emitting cells.

[0025] Furthermore, the shortest distance from the second opening of the lower insulating layer on the second light emitting unit to the second opening of the upper insulating layer on the second light emitting unit may be greater than the shortest distance from the second opening of the lower insulating layer on the second light emitting unit to the edge of the second pad metal layer. Therefore, solder diffusion can be effectively prevented within a limited design range.

[0026] In addition, the light emitting diode may further include: a connecting metal layer, arranged on the lower insulating layer, electrically connected to the ohmic reflective layer on the first light emitting unit through the second opening of the first light emitting unit, and electrically connected to the first conductive semiconductor layer of the second light emitting unit through the first opening of the second light emitting unit. Therefore, the light emitting units may be connected in series.

[0027] Furthermore, the first opening of the lower insulating layer may expose the first conductive type semiconductor layer on at least one side of each light emitting unit along the edge of each of the first light emitting unit and the second light emitting unit, the first pad metal layer contacts the first conductive type semiconductor layer along the edge of the first light emitting unit, and the connection metal layer contacts the first conductive type semiconductor layer along the edge of the second light emitting unit. The areas where the first pad metal layer and the connection metal layer contact the first conductive type semiconductor layer may be continuous or discontinuous.

[0028] Furthermore, the connection metal layer may contact the first conductive semiconductor layer at at least one side along the edge of the second light emitting unit. In particular, the connection metal layer may contact the first conductive semiconductor layer at four sides along the edge of the second light emitting unit.

[0029] The number of the second opening of the lower insulating layer on the second light emitting unit may be one, but is not limited thereto and may be multiple.

[0030] In some embodiments, the first pad metal layer and the second pad metal layer exposed through the first opening and the second opening of the upper insulating layer may be solder pads directly soldered with solder. Therefore, the solder contacts the upper surfaces of the first pad metal layer and the second pad metal layer exposed through the opening of the upper insulating layer.

[0031] In another embodiment, the light emitting diode may further include: a first bump pad and a second bump pad, respectively covering the first pad metal layer and the second pad metal layer exposed through the first opening portion and the second opening portion of the upper insulating layer.

[0032] The first bump pad and the second bump pad may respectively cover the first opening and the second opening of the upper insulating layer to be sealed.

[0033] Furthermore, the second bump pad may also cover the upper insulating layer above the second opening of the lower insulating layer.

[0034] According to another embodiment of the present invention, a light emitting diode comprises: a first conductive semiconductor layer; a table located on the first conductive semiconductor layer and comprising an active layer and a second conductive semiconductor layer; an ohmic reflective layer arranged on the table and electrically connected to the second conductive semiconductor layer; a lower insulating layer covering the table and the ohmic reflective layer and comprising a first opening portion for exposing the first conductive semiconductor layer and a second opening portion for exposing the ohmic reflective layer; a first pad metal layer arranged on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening portion; a second pad metal layer arranged on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening portion; and an upper insulating layer covering the first pad metal layer and the second pad metal layer and comprising a first opening portion for exposing the first pad metal layer and a second opening portion for exposing the second pad metal layer, wherein the second opening portion of the upper insulating layer is separated from the second opening portion of the lower insulating layer and does not overlap.

[0035] By forming a plurality of second openings in the upper insulating layer, the diffusion path of the solder can be reduced, and the plurality of second openings in the upper insulating layer are further separated from the second openings in the lower insulating layer, thereby blocking the solder from diffusing into the ohmic reflective layer.

[0036] In addition, the light emitting diode may further include: a first bump pad connected to the first pad metal layer through the first opening of the upper insulating layer; and a second bump pad connected to the second pad metal layer through the second opening of the upper insulating layer. Furthermore, the first conductive semiconductor layer may be arranged on a substrate.

[0037] In some embodiments, the shortest distance from the second opening of the lower insulating layer to the second opening of the upper insulating layer may be greater than the shortest distance between the second openings of the upper insulating layer.

[0038] In some embodiments, the lower insulating layer may include a plurality of second openings, and the shortest distance from a second opening of the lower insulating layer to a second opening of the upper insulating layer may be greater than the shortest distance between the second openings of the lower insulating layer.

[0039] Although the upper insulating layer and the lower insulating layer block solder diffusion, the solder may reach the second opening of the lower insulating layer along the boundary between the lower insulating layer and the second pad metal layer. Therefore, by isolating the second opening of the lower insulating layer away from the second opening of the upper insulating layer within a limited design range, the diffusion path of the solder can be increased, thereby preventing defects caused by solder diffusion.

[0040] The first opening of the lower insulating layer can expose the first conductive type semiconductor layer along the periphery of the mesa, and the first pad metal layer has an external contact portion that contacts the first conductive type semiconductor layer along the periphery of the mesa. Since the first pad metal layer contacts the first conductive type semiconductor layer along the periphery of the mesa, the current dispersion performance of the light emitting diode can be improved.

[0041] Furthermore, the mesa may include a recessed portion that exposes the first conductive semiconductor layer, and the first opening of the lower insulating layer further exposes the first conductive semiconductor layer in the recessed portion. Furthermore, the first pad metal layer may also include an internal contact portion that contacts the first conductive semiconductor layer in the recessed portion. The first pad metal layer contacts the first conductive semiconductor layer around and inside the mesa, thereby further enhancing the current dispersion performance of the light-emitting diode.

[0042] Furthermore, the internal contact portion may be connected to the external contact portion, but the present invention is not limited thereto, and the internal contact portion and the external contact portion may also be separated from each other.

[0043] In some embodiments, the table may have a through hole that penetrates the second conductive semiconductor layer and the active layer to expose the first conductive semiconductor layer, the first opening portion of the lower insulating layer exposes the first conductive semiconductor layer exposed in the through hole, and the first pad metal layer has: an internal contact portion that contacts the first conductive semiconductor layer exposed in the through hole.

[0044] Furthermore, the first pad metal layer may have an external contact portion contacting the first conductive type semiconductor layer outside the mesa, wherein the external contact portions are spaced apart from each other.

[0045] In addition, the lower insulating layer may include a plurality of second openings, and the second bump pad covers an upper portion of at least one second opening of the lower insulating layer. Furthermore, the second bump pad may also cover an upper portion of the second opening of the lower insulating layer entirely.

[0046] Furthermore, the first bump pad and the second bump pad can respectively cover the first opening and the second opening of the upper insulating layer to seal. The first bump pad and the second bump pad prevent the first pad metal layer and the second pad metal layer from being exposed to the solder. Furthermore, by forming the first opening and the second opening of the upper insulating layer into a plurality of portions, the path for the solder to diffuse to the first pad metal layer and the second pad metal layer through the first bump pad and the second bump pad can be reduced, thereby delaying the diffusion of the solder.

[0047] In addition, the first raised pad may cover the upper portion of at least one second opening of the lower insulating layer. As long as the first raised pad is insulated from the second pad metal layer, its position and shape may be variously deformed, and as long as the second raised pad is insulated from the first pad metal layer, its position and shape may be variously deformed. For example, a protrusion may be included between the second raised pad and the first raised pad. Furthermore, at least one of the second openings of the lower insulating layer may be located below the protrusion.

[0048] In addition, the second pad metal layer may be surrounded by the first pad metal layer. Therefore, a boundary region in which the lower insulating layer is exposed may be formed between the first pad metal layer and the second pad metal layer. The boundary region may be covered by the upper insulating layer.

[0049] In some embodiments, the lower insulating layer may include a plurality of second openings, and at least one of the second openings of the upper insulating layer is arranged between two second openings of the lower insulating layer.

[0050] In addition, a plurality of mesas may be arranged on the first conductive semiconductor layer, the second opening of the lower insulating layer and the second opening of the upper insulating layer may be arranged on each mesas, and the first bump pad and the second bump pad cover and are arranged to cover and spread over the plurality of mesas, respectively. Further, the first pad metal layer may cover the mesas, and the second pad metal layer may be arranged on each mesas.

[0051] In some embodiments, the second raised pad may be located within an upper region of the second pad metal layer, but is not limited thereto, and the second raised pad may also partially overlap with the first pad metal layer.

[0052] Beneficial Effects

[0053] According to the embodiment of the present invention, by isolating the opening of the upper insulating layer from the opening of the lower insulating layer, it is possible to prevent solder (especially Sn) from diffusing to the ohmic reflective layer through the opening of the lower insulating layer, thereby improving the reliability of the light-emitting diode. In addition, the shortest distance from the opening of the upper insulating layer to the opening of the lower insulating layer is formed to be greater than the shortest distance from the opening of the lower insulating layer to the pad metal layer, thereby effectively preventing the diffusion of solder within a limited design range.

[0054] Other advantages and effects of the present invention will be further clarified through detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 FIG. 1 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention.

[0056] Figure 2 is along Figure 1 A cross-sectional view taken along the cutting line AA.

[0057] Figure 3 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0058] Figure 4 is along Figure 3 A cross-sectional view taken along the cutting line AA.

[0059] Figure 5 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0060] Figure 6 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0061] Figure 7 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0062] Figure 8 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0063] Fig. 9 is along Figure 8 A cross-sectional view taken along the cutting line BB.

[0064] Fig.10 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0065] Fig.11 FIG. 1 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention.

[0066] Fig.12 is along Fig.11 Cross-sectional view taken along the interception line CC.

[0067] Fig.13a and Fig.13b It is used to illustrate and Fig.11 A schematic plan view of openings in a lower insulating layer and an upper insulating layer related to an embodiment of the present invention.

[0068] Fig.14 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0069] Fig.15 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0070] Fig.16 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0071] Fig.17 is along Fig.16 A cross-sectional view taken along the cutting line DD.

[0072] Fig.18 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0073] Fig.19 is along Fig.18 Cross-sectional view taken along the interception line EE.

[0074] Fig.20a and Fig.20b It is used to illustrate and Fig.18 A schematic plan view of openings in a lower insulating layer and an upper insulating layer related to an embodiment of the present invention.

[0075] Fig.21 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0076] Fig. 22 It is an exploded perspective view for explaining a lighting device using a light emitting diode according to an embodiment of the present invention.

[0077] Fig.23 FIG. 4 is a cross-sectional view for illustrating a display device using a light emitting diode according to another embodiment of the present invention.

[0078] Fig.24 FIG. 4 is a cross-sectional view for illustrating a display device using a light emitting diode according to another embodiment of the present invention.

[0079] Fig.25 FIG. 4 is a cross-sectional view for explaining an example in which a light emitting diode is applied to a headlamp according to still another embodiment of the present invention. DETAILED DESCRIPTION

[0080] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In order to fully convey the idea of ​​the present invention to those skilled in the art, the embodiments described below are provided as examples. Therefore, the present invention is not limited to the embodiments described below, and it may be embodied in other forms. Moreover, in the accompanying drawings, the width, length, thickness, etc. of the constituent elements may be exaggerated for convenience. Moreover, when it is recorded that a certain constituent element is arranged "on the top" or "on" of other constituent elements, it includes not only the situation that each part is "directly" arranged "on the top" or "on" of other parts, but also the situation that another constituent element is inserted between each constituent element and other constituent elements. Throughout the specification, the same figure symbols represent the same constituent elements.

[0081] Figure 1 is a schematic plan view for illustrating a light emitting diode according to an embodiment of the present invention, Figure 2 is along Figure 1 A cross-sectional view taken along the cutting line AA.

[0082] Reference Figure 1 and Figure 2 The light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, an ohmic reflective layer 31, a lower insulating layer 33, a first pad metal layer 35a, a second pad metal layer 35b and an upper insulating layer 37. Furthermore, the light emitting diode may further include a preliminary insulating layer 29.

[0083] The substrate 21 is not particularly limited as long as it can grow a gallium nitride semiconductor layer. The substrate 21 can be, for example, a sapphire substrate, a gallium nitride substrate, a SiC substrate, or a variety of other substrates, and can be a patterned sapphire substrate. Figure 1 As shown, the substrate 21 may have a rectangular or square shape, but is not necessarily limited thereto. The size of the substrate 21 is not particularly limited and may be selected in a variety of ways.

[0084] The first conductive semiconductor layer 23 is disposed on the substrate 21. The first conductive semiconductor layer 23 is a layer grown on the substrate 21 and is a gallium nitride semiconductor layer. The first conductive semiconductor layer 23 may be a gallium nitride semiconductor layer doped with impurities, such as Si.

[0085] The first conductive semiconductor layer is provided with a mesa M. The mesa M may be defined inside a region surrounded by the first conductive semiconductor layer 23, so that a region near an edge of the first conductive semiconductor layer is not covered by the mesa M but is exposed to the outside.

[0086] The mesa M includes a second conductive semiconductor layer 27 and an active layer 25. The active layer 25 is inserted between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multi-quantum well structure. The composition and thickness of the well layer in the active layer 25 determine the wavelength of the generated light. In particular, by adjusting the composition of the well layer, an active layer that generates ultraviolet light, blue light, or green light can be provided.

[0087] In addition, the second conductive semiconductor layer 27 may be a gallium nitride semiconductor layer doped with p-type impurities, such as Mg. The first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may be single layers, but are not limited thereto, and may be multiple layers, and may also include a superlattice layer. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 may be grown on the substrate 21 in a chamber using a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0088] In addition, if Figure 1 As shown, a recessed portion penetrating into the interior may be formed on the mesa M, and the upper surface of the first conductive type semiconductor layer 23 may be exposed through the recessed portion. The recessed portion may be formed long from one side edge portion of the mesa M toward the other side edge portion opposite thereto, toward the inside of the mesa M, and may pass through the center of the mesa M. In this embodiment, the case where the mesa M has a recessed portion is described, but the mesa M may also have a quadrilateral shape similar to the substrate 21, and a through hole (or multiple holes) for exposing the first conductive type semiconductor layer 23 may be formed inside the mesa M.

[0089] In addition, the ohmic reflective layer 31 is arranged on the upper portion of the mesa M and contacts the second conductive type semiconductor layer 27. The ohmic reflective layer 31 may be arranged over almost the entire area of ​​the mesa M. For example, the ohmic reflective layer 31 may cover more than 80% of the upper area of ​​the mesa M, and may further cover more than 90%.

[0090] The ohmic reflective layer 31 may include a reflective metal layer, so that light generated in the active layer 25 and propagating toward the ohmic reflective layer 31 may be reflected toward the substrate 21. For example, the ohmic reflective layer 31 may be formed as a single reflective metal layer, but is not limited thereto, and may include an ohmic layer and a reflective layer. A metal layer such as Ni or a transparent oxide layer such as ITO may be used as the ohmic layer, and a metal layer with high reflectivity such as Ag or Al may be used as the reflective layer.

[0091] In addition, the preliminary insulating layer 29 may cover the mesa M around the ohmic reflective layer 31. The preliminary insulating layer 29 may be formed, for example, of SiO2, and may cover the side of the mesa M, and further cover a portion of the first conductive semiconductor layer 23. In another embodiment, the preliminary insulating layer 29 may also be arranged only on the mesa M around the ohmic reflective layer 31.

[0092] The lower insulating layer 33 covers the mesa M and the ohmic reflective layer 31. The lower insulating layer 33 may also cover the first conductive semiconductor layer 23 around the mesa M, and may cover the first conductive semiconductor layer 23 in the recessed portion inside the mesa M. The lower insulating layer 33 particularly covers the side surfaces of the mesa M.

[0093] In addition, the lower insulating layer 33 has first openings 33a1 and 33a2 for exposing the first conductive semiconductor layer, and a second opening 33b for exposing the ohmic reflective layer 31. The first opening 33a1 exposes the first conductive semiconductor layer 23 along the periphery of the mesa M, and the first opening 33a2 exposes the first conductive semiconductor layer 23 in the recessed portion. Figure 1 As shown, the first opening 33a1 and the first opening 33a2 may be connected to each other. However, the present invention is not limited thereto, and the first openings 33a1 and 33a2 may be separated from each other.

[0094] The second opening 33b exposes the ohmic reflective layer 31. A plurality of second openings 33b may be formed, and the second openings 33b may be arranged on both sides of the recessed portion. The positions of the second openings 33b will be described again later.

[0095] In addition, the lower insulating layer 33 covers the preliminary insulating layer 29 and is merged with the preliminary insulating layer 29. Unless otherwise specified, it can be understood that the preliminary insulating layer 29 is included in the lower insulating layer 33. The lower insulating layer 33 can be formed using a single layer of SiO2 or Si3N4, but is not limited thereto. For example, the lower insulating layer 33 can have a multilayer structure including a silicon nitride film and a silicon oxide film, and can also include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

[0096] In addition, the first pad metal layer 35a is arranged on the lower insulating layer 33, and is insulated from the mesa M and the ohmic reflective layer 31 by the lower insulating layer 33. The first pad metal layer 35a contacts the first conductive type semiconductor layer 23 through the first openings 33a1 and 33a2 of the lower insulating layer 33. The first pad metal layer 35a may include: an external contact portion 35a1, which contacts the first conductive type semiconductor layer 23 along the periphery of the mesa M; and an internal contact portion 35a2, which contacts the first conductive type semiconductor layer 23 in the recessed portion. The external contact portion 35a1 contacts the first conductive type semiconductor layer 23 near the edge of the substrate 21 along the periphery of the mesa M, and the internal contact portion 35a2 contacts the first conductive type semiconductor layer 23 inside the region surrounded by the external contact portion 35a1. The external contact portion 35a1 and the internal contact portion 35a2 may be connected to each other, but are not limited thereto, and may be separated from each other.

[0097] In addition, the second pad metal layer 35b is arranged on the lower insulating layer 33 in the upper region of the mesa M, and is electrically connected to the ohmic reflective layer 31 through the second opening 33b of the lower insulating layer 33. The second pad metal layer 35b may be surrounded by the first pad metal layer 35a, and a boundary region 35ab may be formed therebetween. The lower insulating layer 33 is exposed from the boundary region 35ab, and the boundary region 35ab is covered by the upper insulating layer 37 described later.

[0098] The first pad metal layer 35a and the second pad metal layer 35b can be formed together using the same material in the same process. The first pad metal layer 35a and the second pad metal layer 35b may include a high-ohmic reflective layer such as an Al layer, and the high-ohmic reflective layer may be formed on a bonding layer of Ti, Cr or Ni. In addition, a protective layer of a single layer or a composite layer structure of Ni, Cr, Au, etc. may be formed on the high-ohmic reflective layer. The first pad metal layer 35a and the second pad metal layer 35b may have, for example, a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti.

[0099] The upper insulating layer 37 covers the first pad metal layer 35a and the second pad metal layer 35b. Also, the upper insulating layer 37 may cover the first conductive semiconductor layer 23 around the mesa M. However, the upper insulating layer 37 may expose the first conductive semiconductor layer 23 along the edge of the substrate 21.

[0100] In addition, the upper insulating layer 37 has a first opening 37a for exposing the first pad metal layer 35a, and a second opening 37b for exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b can be arranged in the upper region of the mesa M, and can be arranged facing each other. In particular, the first opening 37a and the second opening 37b can be arranged near the edge portions of both sides of the mesa M.

[0101] The second opening 33b of the lower insulating layer 33 may be located between the first opening 37a and the second opening 37b of the upper insulating layer 37. The second opening 33b of the lower insulating layer 33 is separated from not only the first opening 37a of the upper insulating layer 37 but also the second opening 37b.

[0102] like Figure 1 and Figure 2 As shown, the shortest distance L1 from the second opening 37b of the upper insulating layer 37 to the second opening 33b of the lower insulating layer 33 is greater than the shortest distance L2 from the second opening 33b of the lower insulating layer 33 to the edge of the second pad metal layer 35b. Therefore, the second opening 33b of the lower insulating layer 33 can be arranged relatively far away from the second opening 37b of the upper insulating layer 37, so that the solder can be further and better prevented from contaminating the ohmic reflective layer 31.

[0103] The upper insulating layer 37 may be formed of a single layer of SiO2 or Si3N4, but is not limited thereto. For example, the upper insulating layer 37 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may also include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

[0104] The first pad metal layer 35a and the second pad metal layer 35b exposed through the first opening 37a and the second opening 37b of the upper insulating layer 37 can be used as pads to be directly soldered with solder. Therefore, when the light emitting diode according to this embodiment is soldered to a printed circuit board or a base using solder, the solder can directly contact the first pad metal layer 35a and the second pad metal layer 35b. In another embodiment, a first bump pad and a second bump pad can be added to the first pad metal layer 35a and the second pad metal layer 35b, as shown in FIG. Figure 3 and Figure 4 This is explained.

[0105] Figure 3 is a schematic plan view for illustrating a light emitting diode according to another embodiment of the present invention, Figure 4 is along Figure 3 A cross-sectional view taken along the cutting line AA.

[0106] Reference Figure 3 and Figure 4 The light emitting diode according to this embodiment is different from the reference Figure 1 and Figure 2 The light emitting diodes described are generally similar, except that they further include a first bump pad 39a and a second bump pad 39b.

[0107] The first bump pad 39a covers the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b covers the second pad metal layer 35b exposed through the second opening 37b of the upper insulating layer 37. The first bump pad 39a and the second bump pad 39b may cover and seal the first opening 37a and the second opening 37b of the upper insulating layer, respectively. Therefore, the first bump pad 39a and the second bump pad 39b may be larger than the first opening 37a and the second opening 37b.

[0108] Furthermore, the second protruding pad 39b may cover the upper insulating layer 37 above the second opening 33b of the lower insulating layer 33. Figure 3 As shown, the second bump pad 39b may have an almost similar shape to the second pad metal layer 35b, and may also be similar in size.

[0109] By forming the first bump pad 39a and the second bump pad 39b, the path for solder diffusion can be increased, thereby further improving the reliability of the light-emitting diode. In particular, when defects such as pinholes occur in the upper insulating layer 37, the first bump pad 39a and the second bump pad 39b prevent the solder from diffusing through the pinholes, thereby improving the reliability of the light-emitting diode.

[0110] Figure 5 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0111] Reference Figure 5 The light emitting diode according to this embodiment is different from the reference Figure 1 and Figure 2 The light emitting diodes described are generally similar, but differ in that a recessed portion is additionally formed inside the mesa M and its shape is different. In addition, the shape of the second opening 33b of the lower insulating layer 33 is different.

[0112] In this embodiment, two recessed portions are shown, but the number of recessed portions can be greater. The lower insulating layer 33 has a first opening portion 33a2 inside the recessed portion, and the first pad metal layer 35a is connected to the first conductive semiconductor layer 23 through the first opening portion 33a2. Therefore, as the number of recessed portions increases, the number of internal contact portions 35a2 of the first pad metal layer 35a also increases, thereby improving the current dispersion performance.

[0113] In addition, the shape of the end of the recessed portion is Figure 1 The shape of the concave portion is different, and the width becomes wider at the end portion and has a round shape. By forming the shape of the end portion of the concave portion as described above, the lower insulating layer 33 can be formed into a similar shape. In particular, in the case where the lower insulating layer 33 includes a distributed Bragg reflector, if Figure 1 As shown in FIG. 1 , if the width at the end portion is not widened, a serious double step is formed on the side wall of the distributed Bragg reflector, and the inclination angle of the side wall becomes larger, so the first pad metal layer 35a is prone to cracking. Therefore, the shape of the end portion of the recessed portion and the shape of the end portion of the first opening 33a2 of the lower insulating layer 33 are formed as in the present embodiment, so that the lower insulating layer 33 can be formed to have a gentle inclination angle, thereby improving the yield rate of the light-emitting diode.

[0114] In addition, in the above embodiment, the second opening portion 33b of the lower insulating layer 33 has a long shape in a direction perpendicular to the recessed portion, but in this embodiment, the second opening portion 33b has a circular shape, that is, a shape that bulges outward. Although a pattern having a long shape in a one-side direction is not easy to perform an etching process at its end portion, it is easy to form a second opening portion 33b having a circular shape as in this embodiment.

[0115] In this embodiment, the shortest distance between the second opening 33 b and the first opening 37 a of the upper insulating layer 37 may be greater than the shortest distance from the second opening 33 b to the edge of the second pad metal layer 35 b .

[0116] Figure 6 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0117] Reference Figure 6 The light emitting diode according to this embodiment is different from the reference Figure 5 The light emitting diodes described are generally similar, except for the shape of the second opening 37b of the upper insulating layer 37. That is, in this embodiment, the second opening 37b of the upper insulating layer 37 has a concave shape 37br corresponding to the shape of the second opening 33b of the lower insulating layer 33.

[0118] As described above, the second opening 33b of the lower insulating layer 33 may have a circular shape and thus have a shape convex toward the second opening 37b of the upper insulating layer. The second opening 37b of the upper insulating layer 37 has a concave shape 37br corresponding to the convex shape of the second opening 33b of the lower insulating layer 33.

[0119] Therefore, the shortest distance between the second opening portion 33 b of the lower insulating layer 33 and the second opening portion 37 b of the upper insulating layer 37 can be relatively increased, so that the solder diffusion path can be further increased.

[0120] Figure 7 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0121] Reference Figure 7 The light emitting diode according to this embodiment is different from the reference Figure 6 The light emitting diodes described are generally similar, and the difference lies in the shape of the second opening 33b of the lower insulating layer 33. The second opening 33b may have various shapes, and in particular, may have various shapes protruding toward the second opening 37b of the upper insulating layer 37.

[0122] In addition, in reference Figures 5 to 7 In the above-described embodiments, although the first bump pad 39a and the second bump pad 39b are not described separately, in these embodiments, as shown in FIG. Figure 3 and Figure 4 As described above, the first bump pad 39 a and the second bump pad 39 b may be added. The second bump pad 39 b may also cover the second opening 33 b of the lower insulating layer 33 .

[0123] Figure 8 is a schematic plan view for illustrating a light emitting diode according to another embodiment of the present invention, Fig. 9 is along Figure 8 A cross-sectional view taken along the cutting line BB.

[0124] Reference Figure 8 and Fig. 9 The light emitting diode includes a substrate 21, a first light emitting unit C1, a second light emitting unit C2, an ohmic reflective layer 31, a lower insulating layer 133, a first pad metal layer 135a, a second pad metal layer 135b, a connection metal layer 135c and an upper insulating layer 137. In addition, the light emitting diode may include a preliminary insulating layer 29, which is merged into the lower insulating layer 133. In addition, the first light emitting unit C1 and the second light emitting unit C2 respectively include a first conductive semiconductor layer 23 and a mesa M located on the first conductive semiconductor layer, and each mesa M includes an active layer 25 and a second conductive semiconductor layer 27.

[0125] The substrate 21 is a growth substrate for growing a gallium nitride semiconductor layer, and may be, for example, a sapphire substrate, a gallium nitride substrate, a SiC substrate, etc., and may be, in particular, a patterned sapphire substrate. The substrate 21 is preferably an insulating substrate, but is not limited to an insulating substrate. However, when the light-emitting units C1 and C2 arranged on the substrate 21 are connected in series with each other, the substrate 21 must be insulated from the light-emitting units. Therefore, when the substrate 21 is insulating or the substrate 21 is conductive, an insulating material layer is arranged between the light-emitting units C1 and C2 and the substrate 21, so that the substrate 21 is insulated from the light-emitting units C1 and C2. Figure 8 As shown, the substrate 21 may have a rectangular shape.

[0126] The first light emitting cell C1 and the second light emitting cell C2 are arranged on the substrate 21. The first light emitting cell C1 and the second light emitting cell C2 are separated from each other by the separation region I that exposes the substrate 21. Therefore, the semiconductor layers of the first light emitting cell C1 and the second light emitting cell C2 are separated from each other. The first light emitting cell C1 and the second light emitting cell C2 may be arranged facing each other and may have a square or rectangular shape, respectively. In particular, the first light emitting cell C1 and the second light emitting cell C2 may have a rectangular shape that is longer in the direction facing each other.

[0127] The first light-emitting unit C1 and the second light-emitting unit C2 each include a first conductive semiconductor layer 23, an active layer 25, and a second conductive semiconductor layer 27. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 can be formed using III-V nitride semiconductors, for example, nitride semiconductors such as (Al, Ga, In)N. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 can be formed by growing on the substrate 21 in a chamber using a known method such as metal organic chemical vapor deposition (MOCVD). In addition, the first conductive semiconductor layer 23 includes n-type impurities (for example, Si, Ge, Sn), and the second conductive semiconductor layer 27 includes p-type impurities (for example, Mg, Sr, Ba), or vice versa. In one embodiment, the first conductive semiconductor layer 23 may include GaN or AlGaN containing Si as a dopant, and the second conductive semiconductor layer 27 may include GaN or AlGaN containing Mg as a dopant. In the drawings, although the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 are both single layers, these layers may also be multiple layers, and may also include a superlattice layer. The active layer 25 may include a single quantum well structure or a multi-quantum well structure, and the composition ratio of the nitride-based semiconductor is adjusted so that it emits a desired wavelength. For example, the active layer 25 may emit blue light or ultraviolet light.

[0128] The separation region I separates the light emitting units C1 and C2 from each other. Therefore, in the separation region I, the substrate 21 is exposed through the semiconductor layer. The separation region I can be formed by using a photolithography and etching process, and a photoresist pattern with a gently inclined surface is formed, and the semiconductor layer is etched using the pattern as a mask, so that a relatively gently inclined side surface can be formed in the separation region I.

[0129] The light-emitting units C1 and C2 place the separation region I in the middle and face each other. The side surfaces of the light-emitting units C1 and C2 facing each other are defined as inner side surfaces, and the other side surfaces are defined as outer side surfaces. Therefore, the first conductive semiconductor layer 23 in the first light-emitting unit C1 and the second light-emitting unit C2 also includes inner side surfaces and outer side surfaces, respectively. For example, the first conductive semiconductor layer 23 may include one inner side surface and three outer side surfaces.

[0130] A mesa M is arranged on each first conductive semiconductor layer 23. The mesa M may be limited to be located inside the region surrounded by the first conductive semiconductor layer 23, so that the region near the edge portion adjacent to the outer side surface of the first conductive semiconductor layer 23 is not covered by the mesa M but is exposed to the outside. However, the side surface of the mesa M and the side surface of the first conductive semiconductor layer 23 may be continuous with each other at the side wall of the separation region I.

[0131] The mesa M includes a second conductive type semiconductor layer 27 and an active layer 25. The active layer 25 is interposed between the first conductive type semiconductor layer 23 and the second conductive type semiconductor layer 27.

[0132] An ohmic reflective layer 31 is disposed on the second conductive semiconductor layer 27 of the first light emitting unit C1 and the second light emitting unit C2. The ohmic reflective layer 31 contacts the second conductive semiconductor layer 27. The ohmic reflective layer 31 may be disposed over almost the entire area of ​​the mesa M in the upper area of ​​the mesa M. For example, the ohmic reflective layer 31 may cover more than 80% of the upper area of ​​the mesa M, and further more than 90%.

[0133] The ohmic reflective layer 31 may include a reflective metal layer, so that light generated in the active layer 25 and propagating toward the ohmic reflective layer 31 can be reflected toward the substrate 21. For example, the ohmic reflective layer may include Ag or Al. In addition, in order to facilitate the ohmic contact of the ohmic reflective layer 31 with the second conductive semiconductor layer 27, a Ni layer may be included.

[0134] In addition, the preliminary insulating layer 29 may cover the mesa M around the ohmic reflective layer 31. The preliminary insulating layer 29 may be formed using SiO2 by chemical vapor deposition technology, for example, and may cover the side of the mesa M, and further cover a portion of the first conductive semiconductor layer 23. Figure 8As shown, at the side of the separation region I, the preliminary insulating layer 29 may be removed.

[0135] The lower insulating layer 133 covers the mesa M and covers the ohmic reflective layer 31 and the preliminary insulating layer 29. In addition, the lower insulating layer 133 covers the separation region I and the sidewall of the mesa M, and covers a portion of the first conductive type semiconductor layer 23 around the mesa M. Figure 8 As shown in the enlarged cross-sectional view of , when the substrate 21 is a patterned sapphire substrate, the lower insulating layer 133 can be formed in the separation region I along the shape of the protrusion on the substrate 21.

[0136] The lower insulating layer 133 may be arranged between the first pad metal layer 35a and the second pad metal layer 35b and the first light emitting unit C1 and the second light emitting unit C2, and have openings 133a, 133b, 133c, 133d that provide a passage that enables the first pad metal layer 35a and the second pad metal layer 35b to be connected to the first conductive semiconductor layer 23 or the ohmic reflective layer 31. For example, the lower insulating layer 133 may have: first openings 133a and 133b that expose the first conductive semiconductor layer of the first light emitting unit C1 and the second light emitting unit C2; and second openings 133c and 133d that expose the ohmic reflective layer 31 of the first light emitting unit C1 and the second light emitting unit C2. The first opening 133a exposes the first conductive semiconductor layer 23 along the outer side surface of the mesa M, and the first opening 133b exposes the first conductive semiconductor layer 23 along the inner side surface of the mesa M of the second light emitting unit C2. Figure 8 As shown, the first opening 133a and the first opening 133b may be connected to each other, however, the present invention is not limited thereto and they may be separated from each other.

[0137] In addition, the second opening 133c exposes the ohmic reflective layer 31 on the first light emitting unit C1, and the second opening 133d exposes the ohmic reflective layer 31 on the second light emitting unit C2. The second opening 133d may be formed to be smaller than the second opening 133c. The second openings 133c and 133d may have a shape that is generally long along the separation region I, however, they are not necessarily limited thereto and may have various shapes.

[0138] The lower insulating layer 133 may be formed using insulating materials such as SiO2 or Si3N4, and may be formed as a single layer or multiple layers. Furthermore, the lower insulating layer 133 may also include material layers having different refractive indices, for example, a distributed Bragg reflector formed by repeatedly stacking SiO2 / TiO2. When the lower insulating layer 133 includes a distributed Bragg reflector, light incident on a region other than the ohmic reflective layer 31 can be reflected, thereby improving light extraction efficiency.

[0139] In addition, a first pad metal layer 135 a , a second pad metal layer 135 b , and a connection metal layer 135 c are disposed on the lower insulating layer 133 .

[0140] The first pad metal layer 135a is disposed on the first light emitting unit C1 and is in ohmic contact with the first conductive semiconductor layer 23. Figure 8 As clearly shown in the figure, the first pad metal layer 135a can be ohmically contacted with the first conductive semiconductor layer 23 through the first opening 133a of the lower insulating layer 133 along the periphery of the mesa M and between the outer side surface of the first conductive semiconductor layer 23 and the mesa M. Although the drawings illustrate the situation that the first pad metal layer 135a is continuously in contact with the first conductive semiconductor layer 23 along the periphery of the mesa M, the present invention is not limited thereto, and the first pad metal layer 135a can also be in contact intermittently. That is, the first pad metal layer 135a can be in contact with the first conductive semiconductor layer 23 in a plurality of regions separated from each other around the mesa M. Furthermore, the first pad metal layer 135a can cover the upper region and the outer side surface of the mesa M.

[0141] The second pad metal layer 135b is arranged on the second light emitting unit C2 and connected to the ohmic reflective layer 31 on the second light emitting unit C2 through the second opening 133d of the lower insulating layer 133. The second pad metal layer 135b is located on the mesa M and is insulated from the first conductive semiconductor layer 23. For example, the second pad metal layer 135b can be separated from the side of the mesa M on the second light emitting unit C2. The second pad metal layer 135b can cover most of the mesa M on the second light emitting unit C2, for example, it can cover more than 50% of the upper area of ​​the mesa M.

[0142] In addition, the connection metal layer 135c can be electrically connected to the ohmic reflective layer 31 on the first light emitting cell C1 through the second opening 133c of the first light emitting cell C1, and can be electrically connected to the first conductive semiconductor layer 23 on the second light emitting cell C2 through the first openings 133a and 133b of the second light emitting cell C2. Therefore, the first light emitting cell C1 and the second light emitting cell C2 are connected in series via the connection metal layer 135c.

[0143] The connection metal layer 135c may contact the first conductive semiconductor layer 23 at least on one side along the edge of the second light emitting unit C2. In particular, the connection metal layer 135c may contact the first conductive semiconductor layer 23 continuously or discontinuously along the periphery of the mesa M. Furthermore, the connection metal layer 135c may surround the second pad metal layer 135b, and a boundary region 135bc may be formed between the connection metal layer 135c and the second pad metal layer 135b. In addition, a boundary region 135ac may be formed between the connection metal layer 135c and the first pad metal layer 135a. These boundary regions 135ac and 135bc are covered by an upper insulating layer 137 described later.

[0144] The first pad metal layer 135a, the second pad metal layer 135b and the connecting metal layer 135c can be formed together using the same material in the same process. For example, the first pad metal layer 135a, the second pad metal layer 135b and the connecting metal layer 135c may include a high-ohmic reflective layer such as an Al layer, and the high-ohmic reflective layer may be formed on a bonding layer of Ti, Cr or Ni. In addition, a protective layer of a single layer or a composite layer structure of Ni, Cr, Au, etc. may be formed on the high-ohmic reflective layer. The first pad metal layer 135a, the second pad metal layer 135b and the connecting metal layer 135c may have, for example, a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti.

[0145] The upper insulating layer 137 is arranged on the first pad metal layer 135a, the second pad metal layer 135b and the connection metal layer 135c, and has a first opening 137a for exposing the first pad metal layer 135a and a second opening 137b for exposing the second pad metal layer 135b. In addition, the upper insulating layer 137 covers the first pad metal layer 135a and the connection metal layer 135c connected to the first conductive semiconductor layer 23 at the edge of the mesa M. Figure 8 As shown, the region between the first pad metal layer 135a and the connection metal layer 135c and the edge portion of the first conductive type semiconductor layer 23 is covered by the upper insulating layer 137. In addition, the upper insulating layer 137 may cover the connection metal layer 135c on the separation region I, and may be formed to have a concave-convex shape according to the shape of the connection metal layer 135c. The upper insulating layer 137 protects the first pad metal layer 135a, the second pad metal layer 135b and the connection metal layer 135c from the influence of the external environment such as moisture.

[0146] In addition, the first opening 137a is defined to be formed in the upper region of the first pad metal layer 135a, so as to be separated from the connection metal layer 135c and the second opening 133c of the lower insulating layer 133. Moreover, the second opening 137b is defined to be located on the second pad metal layer 135b, and is separated from the connection metal layer 135c. Furthermore, the second opening 137b is separated from the second opening 133d of the lower insulating layer 133. In particular, the shortest distance L1 from the second opening 133d of the lower insulating layer 133 to the second opening 137b of the upper insulating layer 137 may be greater than the shortest distance L2 from the second opening 133d of the lower insulating layer 133 to the edge of the second pad metal layer 135b. By making the second opening 133d of the upper insulating layer 137 farther away from the second opening 137b than the edge of the second pad metal layer 135b, the diffusion of solder can be effectively prevented within a limited design range.

[0147] The upper insulating layer 137 may be formed of a single layer of SiO2 or Si3N4, but is not limited thereto. For example, the upper insulating layer 137 may have a multilayer structure including a silicon nitride film and a silicon oxide film, or may include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

[0148] In this embodiment, the first pad metal layer 135a and the second pad metal layer 135b exposed through the first opening 137a and the second opening 137b of the upper insulating layer 137 can be used as pads for direct soldering. Figure 3 and Figure 4 The first bump pad and the second bump pad may respectively cover the first pad metal layer 135a and the second pad metal layer 135b exposed through the first opening 137a and the second opening 137b of the upper insulating layer 137. Furthermore, the first bump pad and the second bump pad may respectively cover and seal the first opening 137a and the second opening 137b of the upper insulating layer 137, and the second bump pad may cover the upper region of the second opening 133d of the lower insulating layer 133 on the second light emitting cell C2.

[0149] Fig.10 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0150] Reference Fig.10 The light emitting diode according to this embodiment is different from the reference Figure 8 and Fig. 9 The light emitting diodes described are generally similar, with the difference being the overall shape of the light emitting diode and the openings 133a, 133b, 133d of the lower insulating layer being different.

[0151] First, the first light emitting unit C1 and the second light emitting unit C2 have a rectangular shape that is long in a direction perpendicular to the direction facing each other. Therefore, according to the shape of the light emitting unit, the first pad metal layer 135a and the second pad metal layer 135b also have a vertically long shape.

[0152] In addition, in the above-mentioned embodiment, the lower insulating layer 133 has the first opening 133a that exposes the first conductive semiconductor layer 23 along the outer side surface of the mesa M on the first light-emitting unit C1, but in the present embodiment, the first opening 133a extends along the inner side surface of the mesa M on the first light-emitting unit C1 to further expose the first conductive semiconductor layer 23. The end portion of the first opening 133a formed along the inner side surface of the first light-emitting unit C1 may be widened to have a circular shape. By forming the first opening 133a to expose the first conductive semiconductor layer 23 along the inner side surface of the mesa M, the contact area of ​​the first pad metal layer 135a can be increased, thereby improving the current dispersion performance.

[0153] In addition, in the above-mentioned embodiment, the first opening 133b that exposes the first conductive semiconductor layer 23 along the inner side surface of the mesa M of the second light emitting unit C2 is formed along the separation region I and communicates with the first opening 133a, but in the present embodiment, the first opening 133b is separated from the first opening 133a. Furthermore, the end portions of both sides of the first opening 133b may be widened and have a circular shape.

[0154] Also, in the present embodiment, a plurality of second openings 133 d of the lower insulating layer 133 may be formed.

[0155] Fig.11 is a schematic plan view for illustrating a light emitting diode according to an embodiment of the present invention, Fig.12 is along Fig.11 Cross-sectional view taken along the interception line CC.

[0156] Reference Fig.11 and Fig.12 The light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, an ohmic reflective layer 31, a lower insulating layer 33, a first pad metal layer 35a, a second pad metal layer 35b and an upper insulating layer 37. Furthermore, the light emitting diode may further include a preliminary insulating layer 29, and may further include a first bump pad 39a and a second bump pad 39b.

[0157] The substrate 21 is not particularly limited as long as it is a growth substrate capable of growing a gallium nitride-based semiconductor layer. The substrate 21 may be, for example, a sapphire substrate, a gallium nitride substrate, a SiC substrate, etc., and may be a patterned sapphire substrate. Fig.11 As shown, the substrate 21 may have a rectangular or square shape, but is not necessarily limited thereto. The size of the substrate 21 is not particularly limited and may be selected in a variety of ways.

[0158] The first conductive semiconductor layer 23 is disposed on the substrate 21. The first conductive semiconductor layer 23 is a layer grown on the substrate 21 and may be a gallium nitride semiconductor layer. The first conductive semiconductor layer 23 may be a gallium nitride semiconductor layer doped with impurities (eg, Si).

[0159] A mesa M is disposed on the first conductive semiconductor layer 23. The mesa M may be defined inside a region surrounded by the first conductive semiconductor layer 23, so that a region near an edge of the first conductive semiconductor layer is not covered by the mesa M and is exposed to the outside.

[0160] The mesa M includes a second conductive semiconductor layer 27 and an active layer 25. The active layer 25 is inserted between the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multi-quantum well structure. The composition and thickness of the well layer in the active layer 25 determine the wavelength of the generated light. In particular, by adjusting the composition of the well layer, an active layer that generates ultraviolet light, blue light, or green light can be provided.

[0161] In addition, the second conductive semiconductor layer 27 may be a gallium nitride semiconductor layer doped with p-type impurities, such as Mg. The first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may both be a single layer, but are not limited thereto, and may also be a multilayer, and may also include a superlattice layer. The first conductive semiconductor layer 23, the active layer 25, and the second conductive semiconductor layer 27 may be grown on the substrate 21 in a chamber using a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0162] In addition, if Fig.11 As shown, a recessed portion 30 penetrating into the interior may be formed on the mesa M, and the upper surface of the first conductive type semiconductor layer 23 may be exposed through the recessed portion 30. The recessed portion 30 may be formed longer from one edge of the mesa M toward the other edge facing the mesa M. The length of the recessed portion 30 is not particularly limited, and may be 1 / 2 of the length of the mesa M, or greater. Fig.11Two recessed portions 30 are shown in the figure, but the number of recessed portions 30 may be one or more than three. As the number of recessed portions 30 increases, the number of internal contact portions 35a2 of the first pad metal layer 35a also increases, thereby improving the current spreading performance.

[0163] In addition, the recessed portion 30 has a rounded shape with a larger width at the end portion. By forming the shape of the end portion of the recessed portion 30 as described above, the lower insulating layer 33 can be formed into a shape similar to this. In particular, when the lower insulating layer 33 includes a distributed Bragg reflector, if Fig.11 As shown in FIG. 1 , if the width at the end portion is not widened, a serious double step is formed on the side wall of the distributed Bragg reflector, and the inclination angle of the side wall becomes larger, so that the first pad metal layer 35a is prone to cracking. Therefore, the shape of the end portion of the recessed portion 30 and the shape of the end portion of the first opening 33a2 of the lower insulating layer 33 are formed as in the present embodiment, so that the lower insulating layer 33 can be formed to have a gentle inclination angle, thereby improving the yield rate of the light-emitting diode.

[0164] In addition, the ohmic reflective layer 31 is arranged on the upper portion of the mesa M and contacts the second conductive type semiconductor layer 27. The ohmic reflective layer 31 may be arranged over almost the entire area of ​​the mesa M. For example, the ohmic reflective layer 31 may cover more than 80% of the upper area of ​​the mesa M, and may further cover more than 90%.

[0165] The ohmic reflective layer 31 may include a reflective metal layer, so that light generated in the active layer 25 and propagating toward the ohmic reflective layer 31 may be reflected toward the substrate 21. For example, the ohmic reflective layer 31 may be formed as a single reflective metal layer, but is not limited thereto, and may include an ohmic layer and a reflective layer. A metal layer such as Ni or a transparent oxide layer such as ITO may be used as the ohmic layer, and a metal layer with high reflectivity such as Ag or Al may be used as the reflective layer.

[0166] In addition, the preliminary insulating layer 29 may cover the mesa M around the ohmic reflective layer 31. The preliminary insulating layer 29 may be formed, for example, of SiO2, and may cover the side of the mesa M, and further cover a portion of the first conductive semiconductor layer 23. In another embodiment, the preliminary insulating layer 29 may also be arranged only on the mesa M around the ohmic reflective layer 31.

[0167] The lower insulating layer 33 covers the mesa M and the ohmic reflective layer 31. The lower insulating layer 33 may cover the first conductive semiconductor layer 23 along the periphery of the mesa M, and may cover the first conductive semiconductor layer 23 in the recessed portion 30 inside the mesa M. The lower insulating layer 33 particularly covers the side surfaces of the mesa M.

[0168] In addition, the lower insulating layer 33 has first openings 33a1 and 33a2 for exposing the first conductive semiconductor layer and a second opening 33b for exposing the ohmic reflective layer 31. The first opening 33a1 exposes the first conductive semiconductor layer 23 along the periphery of the mesa M, and the first opening 33a2 exposes the first conductive semiconductor layer 23 in the recess 30. Fig.11 As shown, the first opening 33a1 and the first opening 33a2 may be connected to each other. However, the present invention is not limited thereto, and the first openings 33a1 and 33a2 may also be separated from each other.

[0169] The second opening 33b exposes the ohmic reflective layer 31. A plurality of second openings 33b may be formed, and these second openings 33b may be arranged near one edge of the substrate 21 facing the recess 30. The position of the second opening 33b will be described again later.

[0170] In addition, the lower insulating layer 33 covers the preliminary insulating layer 29 and is merged with the preliminary insulating layer 29. Unless otherwise specified, it can be understood that the preliminary insulating layer 29 is included in the lower insulating layer 33. The lower insulating layer 33 can be formed using a single layer of SiO2 or Si3N4, but is not limited thereto. For example, the lower insulating layer 33 can have a multilayer structure including a silicon nitride film and a silicon oxide film, and can also include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

[0171] In addition, the first pad metal layer 35a is arranged on the lower insulating layer 33, and is insulated from the mesa M and the ohmic reflective layer 31 by the lower insulating layer 33. The first pad metal layer 35a contacts the first conductive semiconductor layer 23 through the first openings 33a1 and 33a2 of the lower insulating layer 33. The first pad metal layer 35a may include: an external contact portion 35a1, which contacts the first conductive semiconductor layer 23 along the periphery of the mesa M; and an internal contact portion 35a2, which contacts the first conductive semiconductor layer 23 in the recessed portion. The external contact portion 35a1 contacts the first conductive semiconductor layer 23 near the edge of the substrate 21 along the periphery of the mesa M, and the internal contact portion 35a2 contacts the first conductive semiconductor layer 23 inside the region surrounded by the external contact portion 35a1. The external contact portion 35a1 and the internal contact portion 35a2 may be connected to each other, but are not limited thereto and may be separated from each other.

[0172] In addition, the second pad metal layer 35b is arranged on the lower insulating layer 33 in the upper region of the mesa M, and is electrically connected to the ohmic reflective layer 31 through the second opening 33b of the lower insulating layer 33. The second pad metal layer 35b may be surrounded by the first pad metal layer 35a, and a boundary region 35ab may be formed therebetween. The lower insulating layer 33 is exposed in the boundary region 35ab, and the boundary region 35ab is covered by the upper insulating layer 37 described later.

[0173] The first pad metal layer 35a and the second pad metal layer 35b can be formed together using the same material in the same process. The first pad metal layer 35a and the second pad metal layer 35b may include an ohmic reflective layer such as an Al layer, and the ohmic reflective layer may be formed on a bonding layer of Ti, Cr or Ni. In addition, a protective layer of a single layer or a composite layer structure of Ni, Cr, Au, etc. may be formed on the ohmic reflective layer. The first pad metal layer 35a and the second pad metal layer 35b may have, for example, a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti.

[0174] The upper insulating layer 37 covers the first pad metal layer 35a and the second pad metal layer 35b. Also, the upper insulating layer 37 may cover the first conductive semiconductor layer 23 around the mesa M. However, the upper insulating layer 37 may expose the first conductive semiconductor layer 23 along the edge of the substrate 21.

[0175] In addition, the upper insulating layer 37 has a first opening 37a for exposing the first pad metal layer 35a, and a second opening 37b for exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b can be arranged in the upper region of the mesa M, and can be arranged facing each other. In particular, the first opening 37a and the second opening 37b can be arranged near the edge portions of both sides of the mesa M.

[0176] The second opening 33b of the lower insulating layer 33 may be arranged near the second opening 37b of the upper insulating layer 37. However, the second opening 33b of the lower insulating layer 33 is not only separated from the first opening 37a of the upper insulating layer 37 but also separated from the second opening 37b. Therefore, even if the solder penetrates through the second opening 37b of the upper insulating layer 37, the solder can be prevented from diffusing into the second opening 33b of the lower insulating layer 33, thereby preventing the solder from contaminating the ohmic reflective layer 31.

[0177] The upper insulating layer 37 may be formed as a single layer of SiO2 or Si3N4, but is not limited thereto. For example, the upper insulating layer 37 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may also include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

[0178] In addition, the first bump pad 39a is electrically in contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is electrically in contact with the second pad metal layer 35b exposed through the second opening 37b of the upper insulating layer 37. Fig.11 As shown, the first bump pad 39a completely covers and seals the first opening 37a of the upper insulating layer 37, and the second bump pad 39b completely covers and seals the second opening 37b of the upper insulating layer 37. In addition, the second bump pad 39b covers the upper region of the second opening 33b of the lower insulating layer 33. That is, the second bump pad 39b covers the upper insulating layer 37 above the second opening 33b. The second bump pad 39b may completely cover the second opening 33b of the lower insulating layer 33, but the present invention is not limited thereto, and a portion of the opening 33b may also be located outside the second bump pad 39b.

[0179] In addition, if Fig.11 As shown, the second raised pad 39b may also be limited to be located in the upper region of the second pad metal layer 35b. However, the present invention is not limited thereto, and a portion of the second raised pad 39b may also overlap with the first pad metal layer 35a. However, the upper insulating layer 37 may be located between the first pad metal layer 35a and the second raised pad 39b to insulate them.

[0180] Fig.13a and Fig.13b It is used to illustrate and Fig.11 Schematic plan view of second openings 33b and 37b of the lower insulating layer and the upper insulating layer related to an embodiment of the present invention.

[0181] Fig.13a Shown with Fig.11 The second opening 33b of the lower insulating layer 33 and the second opening 37b of the upper insulating layer 37 are arranged in the same manner as in the embodiment. Fig.13b Another modification is shown.

[0182] Reference Fig.13a and Fig.13b , L1 represents the shortest distance between the second opening 33b and the second opening 37b, L2 represents the shortest distance between the second openings 33b, and L2 represents the shortest distance between the second openings 37b.

[0183] exist Fig.13aIn the embodiment, the second openings 33b and the second openings 37b are arranged vertically, and the second openings 33b and the second openings 37b are arranged alternately in the lateral direction. In such an arrangement, L1 is relatively short compared to L2 and L3. At least one of the second openings 37b is arranged between the second openings 33b.

[0184] exist Fig.13b In the embodiment, the second openings 33b and 37b are arranged vertically, and the second openings 33b and the second openings 37b are arranged alternately in the horizontal direction. In such an arrangement, L1 is relatively longer than L2 and L3. In addition, at least one of the second openings 37b is arranged between the second openings 33b.

[0185] Considering the diffusion of solder, it is advantageous to keep the second opening 33b and the second opening 37b away from each other. Fig.13a The layout, Fig.13b The arrangement may be more advantageous.

[0186] exist Fig.13a and Fig.13b In the figure, the distance between the openings arranged vertically is smaller than the distance between the openings arranged horizontally, but the distance between the openings arranged horizontally can be shorter. In this case, in order to arrange the second opening 33b and the second opening 37b relatively farther apart, the second opening 33b and the second opening 37b are arranged vertically, the second opening 33b is arranged continuously horizontally, and the second opening 37b is also arranged continuously horizontally, which can further help prevent the solder from spreading.

[0187] However, the number or arrangement of the second openings 33b and 37b can be selected in consideration of not only solder contamination of the ohmic reflective layer 31 but also current dispersion efficiency and symmetry of the light emitting pattern, and thus various changes are possible.

[0188] Fig.14 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0189] Reference Fig.14 The light emitting diode according to this embodiment is different from the reference Fig.11 and Fig.12 The light emitting diodes described are generally similar, but differ in the shapes of the first and second pad metal layers 35a and 35b, the arrangement of the second openings 33b of the lower insulating layer 33, and the shape of the second bump pads 39b.

[0190] That is, with Fig.11Compared with the embodiment of the present invention, the second opening 33b of the lower insulating layer 33 is added near the recessed portion 30. The added second opening 33b is arranged closer to the center of the mesa M than to the edge of the mesa M where the second opening 37b of the upper insulating layer 37 is arranged. In the present embodiment, although the additional second opening 33b is arranged in the center of the mesa M close to the edge of the mesa M where the second opening 37b of the upper insulating layer 37 is arranged, the present invention is not limited thereto and may be arranged in the center of the mesa M or close to the edge of the mesa M where the second bump pad 39b is arranged.

[0191] The second pad metal layer 35b is arranged to cover the second opening portion 33b. Fig.14 As shown, the second pad metal layer 35b has a concavo-convex shape having a concave portion near the recessed portion 30. The first pad metal layer 35a may have a concavo-convex shape such that a boundary region 35ab with the second pad metal layer 35b has a predetermined width.

[0192] In addition, the second bump pad 39 b may have a shape similar to that of the second pad metal layer 35 b and may cover an upper region of the additional second opening portion 33 b .

[0193] According to the present embodiment, the second openings 33 b of the lower insulating layer 33 can be distributed relatively more widely, thereby facilitating current dispersion in the ohmic reflective layer 31 .

[0194] Fig.15 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0195] Reference Fig.15 The light emitting diode according to this embodiment is different from the reference Fig.14 The light emitting diodes described are generally similar, but differ in the arrangement of the second openings 33b and 37b, and the shapes of the first bump pads 39a and the second bump pads 39b.

[0196] That is, the first bump pad 39a expands toward the upper region of the second pad metal layer 35b and covers at least a portion of the upper region of the second opening 33b. However, the second opening 37b is separated from the first bump pad 39a and is located outside the first bump pad 39a. The first bump pad 39a may cover the second opening 37b and may cover a portion of the second opening 33b.

[0197] In this embodiment, the first bump pad 39a may partially overlap the second pad metal layer 35b. Different from this, the second bump pad 39b may also partially overlap the first pad metal layer 35a.

[0198] Fig.16 is a schematic plan view for illustrating a light emitting diode according to another embodiment of the present invention, Fig.17 is along Fig.16 A cross-sectional view taken along the cutting line DD.

[0199] Reference Fig.16 and Fig.17 The light emitting diode according to this embodiment is different from the reference Fig.11 and Fig.12 The illustrated light emitting diode is generally similar, however the difference is that a through hole is formed instead of the recess 30 .

[0200] That is, the mesa M has a through hole 230 that penetrates the second conductive semiconductor layer 27 and the active layer 25 to expose the first conductive semiconductor layer 23. The through hole 230 is surrounded by the second conductive semiconductor layer 27 and the active layer 25. The mesa M may have a plurality of through holes 230, and the through holes 230 may be regularly arranged inside the mesa M. Fig.16 9 through holes 230 are shown in the figure, but are not particularly limited. Fig.16 As shown, a concave portion may be formed along the edge of the table M.

[0201] The lower insulating layer 233 covers the mesa M and the ohmic reflective layer 31, and may have a first opening 233a1 exposing the first conductive semiconductor layer 23 outside the mesa M and a first opening 233a2 exposing the first conductive semiconductor layer 23 in the through hole 230. In addition, the lower insulating layer 233 has a second opening 233b exposing the ohmic reflective layer 31 on the mesa M.

[0202] The first pad metal layer 235a includes: an external contact portion 235a1, which contacts the first conductive semiconductor layer 23 through the first opening portion 233a1 of the lower insulating layer 233; and an internal contact portion 235a2, which contacts the first conductive semiconductor layer 23 through the first opening portion 233a2. For current dispersion, the internal contact portion 235a2 may be uniformly distributed inside the mesa M. In addition, as shown in FIG. Fig.16 As shown, the external contact portions 235a1 may be distributed on three side surfaces except one side surface of the mesa M, but the present invention is not limited thereto and may also be distributed on four side surfaces. Furthermore, as in the above embodiment, the external contact portions 235a1 may also be formed continuously around the mesa M.

[0203] In addition, the second pad metal layer 235b is electrically connected to the ohmic reflective layer 31 through the second opening 233b of the lower insulating layer 233. The second pad metal layer 235b is separated from the through hole 230. Fig.16As shown, the second openings 233b of the lower insulating layer 233 are arranged in the area surrounded by the through hole 230, and the second pad metal layer 235b may cover the second openings 233b. Therefore, the first pad metal layer 235a and the second pad metal layer 235b may be formed to have a concave-convex shape.

[0204] In addition, the upper insulating portion 37 has a first opening 37a that exposes the first pad metal layer 235a and a second opening 37b that exposes the second pad metal layer 235b. The first opening 37a and the second opening 37b can be arranged near the edge portions facing each other. In particular, the second opening 37b of the upper insulating portion 37 is separated from the second opening 233b of the lower insulating layer 233 without overlapping.

[0205] In addition, the first bump pad 239 a and the second bump pad 239 b are electrically connected to the first pad metal layer 235 a and the second pad metal layer 235 b through the first opening 37 a and the second opening 37 b of the upper insulating layer 37 , respectively.

[0206] like Fig.16 As shown, the second protruding pad 239b may have a concavo-convex shape to surround the through hole 230. Also, the second protruding pad 239b may cover at least a portion of the second opening 233b of the lower insulating layer 233. For example, Fig.17 As shown, the second protruding pad 239b may surround the upper region of the second opening 233b of the lower insulating layer 233 except the second opening 233b arranged near the central portion of the mesa M. However, the present invention is not limited thereto, and the second protruding pad 239b may also completely cover the upper region of the second opening 233b.

[0207] Fig.18 is a schematic plan view for illustrating a light emitting diode according to another embodiment of the present invention, Fig.19 is along Fig.18 Cross-sectional view taken along the interception line EE.

[0208] Reference Fig.18 and Fig.19 The light emitting diode according to this embodiment is different from the reference Fig.11 and Fig.12 The light emitting diodes described are generally similar, but differ in that they include a plurality of mesas M1 , M2 , M3 .

[0209] That is, in Fig.11 and Fig.12In the embodiment of FIG. 1 , a single mesa M has a structure with a recessed portion 30. On the contrary, the light emitting diode according to this embodiment has a structure in which mesas M1, M2, and M3 are arranged in a spaced relationship from each other. The mesas M1, M2, and M3 can be arranged parallel to each other along the length direction. Such a structure is equivalent to Fig.11 In the embodiment of the present invention, the recessed portion 30 extends from one edge portion to the other edge portion. Therefore, the shapes of the ohmic reflective layer 331, the first pad metal layer 335a and the second pad metal layer 335b are deformed.

[0210] The ohmic reflective layer 331 is located on each of the mesas M1, M2, and M3 and is in ohmic contact with each of the second conductive type semiconductor layers 27. The ohmic reflective layer 331 is limited to the upper region of each of the mesas M1, M2, and M3 and is separated from each other.

[0211] In addition, the preliminary insulating layer 329 may cover the mesas M1, M2, and M3 around the ohmic reflective layer 331. The preliminary insulating layer 329 may be formed, for example, of SiO2, and may cover the side surfaces of the mesas M1, M2, and M3, and further cover a portion of the first conductive semiconductor layer 23. In another embodiment, the preliminary insulating layer 329 may also be arranged only around the ohmic reflective layer 331 on the upper portions of the mesas M1, M2, and M3.

[0212] In addition, the lower insulating layer 333 covers the mesas M1, M2, M3 and the ohmic reflective layer 331. The lower insulating layer 333 may have a first opening 333a1 exposing the first conductive semiconductor layer 23 along the edge of the substrate 21 and a first opening 333a2 exposing the first conductive semiconductor layer 23 between the mesas M1, M2, M3.

[0213] Furthermore, the lower insulating layer 333 has a second opening 333b for exposing the ohmic reflective layer 331 on each of the mesas M1, M2, and M3. The shape of the second opening 333b may be similar to that of the second opening 333b. Fig.11 The embodiment of the present invention is also circular, but it is not limited to this, and can also be as Fig.18 Shown is a long rounded quadrilateral shape.

[0214] The first pad metal layer 335a covers the mesas M1, M2, and M3 and is electrically connected to the first conductive type semiconductor layer 23 through the first openings 333a1 and 333a2. The first pad metal layer 335a may include an external contact portion 335a1 contacting the first conductive type semiconductor layer 23 through the first opening 333a1 and an internal contact portion 335a2 exposed between the mesas M1, M2, and M3 and contacting the first conductive type semiconductor layer 23 through the first opening 333a2.

[0215] In addition, the second pad metal layer 335b is arranged on the mesas M1, M2, and M3, respectively. Each second pad metal layer 335b can be surrounded by the first pad metal layer 335a, so that a ring-shaped boundary area 335ab can be formed on each mesas M1, M2, and M3. The second pad metal layer 335b is electrically connected to the ohmic reflective layer 331 on each mesas M1, M2, and M3 through the second opening 333b of the lower insulating layer 333.

[0216] The upper insulating portion 337 covers the first pad metal layer 335a and the second pad metal layer 335b, and has a first opening portion 337a that exposes the first pad metal layer 335a and a second opening portion 337b that exposes the second pad metal layer 335b. The second pad metal layer 335b on each of the mesas M1, M2, and M3 is exposed through the second opening portion 337b. In addition, the first opening portion 337a can be arranged on each of the mesas M1, M2, and M3.

[0217] In addition, the first bump pad 339a and the second bump pad 339b may be formed to cover the mesas M1, M2, and M3, respectively. The first bump pad 339a contacts the first pad metal layer 335a through the first opening 337a of the upper insulating layer 337, and the second bump pad 339b contacts the second pad metal layer 335b through the second opening 337b of the upper insulating layer 337. Furthermore, the second bump pad 339b may cover the upper region of the second opening 333b of the lower insulating layer 333.

[0218] In this embodiment, the second openings 333b of the lower insulating layer 333 and the second openings 337b of the upper insulating layer 337 can be arranged in various ways. In this embodiment, the second openings 333b and 337b are arranged in the same number on the mesas M1, M2, and M3, and the second openings 333b and the second openings 337b are arranged vertically and have a mirror-symmetrical structure as a whole.

[0219] in addition, Fig.20a and Fig.20b 1 and 12 are schematic plan views for explaining various arrangements of the second openings 333 b of the lower insulating layer 333 and the second openings 337 b of the upper insulating layer 337 .

[0220] Reference Fig.20a The second opening 333b of the lower insulating layer 333 and the second opening 337b of the upper insulating layer 337 are compared with Fig.18 Furthermore, the openings 333b and 337b are arranged to have a mirror-symmetrical structure as a whole.

[0221] Reference Fig.20bOn the first mesa M1 and the third mesa M3, the second openings 333b of the lower insulating layer 333 are arranged vertically, and the second openings 337b of the upper insulating layer 337 are also arranged vertically. In addition, on the second mesa M2, the second openings 333b and the second openings 337b are arranged vertically. Fig.20b In the embodiment, these opening portions 333b, 337b are also arranged to have a mirror-symmetrical structure as a whole.

[0222] By arranging the second openings 333b and 337b to have a mirror-symmetrical structure, a symmetrical light-emitting pattern can be achieved. However, the present invention is not limited thereto, and the arrangement of the openings 333b and 337b may be modified in many ways, and may not have a mirror-symmetrical structure.

[0223] Fig.21 FIG. 1 is a schematic plan view for explaining a light emitting diode according to still another embodiment of the present invention.

[0224] Reference Fig.21 The light emitting diode according to this embodiment is different from the reference Fig.18 and Fig.19 The light emitting diodes described are generally similar, but differ in the number of mesas and the shape of the first opening 437a of the upper insulating layer. Fig.18 and Fig.19 The details of the repeated contents of the items mentioned above are explained mainly with the differences being given.

[0225] In this embodiment, four mesas M1 to M4 are arranged on the first conductive type semiconductor layer 23. However, the number of mesas is not particularly limited, and may be more or less.

[0226] In addition, the first opening portion 437a of the upper insulating layer may be Fig.18 The circular shape is shown, but it can also be Fig.21 The second opening 337b of the upper insulating layer may also be of the same shape, but the sizes of the first opening 437a and the second opening 337a may be different or the same.

[0227] By forming the first opening 437a into a long rounded quadrilateral, the size of the opening can be increased and the distance between the first openings 437a arranged adjacent to each other can be sufficiently ensured. Furthermore, the shape of the first opening 437a is not particularly limited and can be variously modified.

[0228] In addition, in this embodiment, the second opening 337b of the upper insulating layer and the second opening 333b of the lower insulating layer are arranged vertically and horizontally. Fig.18Unlike the embodiment of the present invention, in the present embodiment, the second openings 337b of the upper insulating layer and the second openings 333b of the lower insulating layer on each of the mesas M1 to M4 can be arranged in the same pattern. Therefore, the arrangement of these openings 333b and 337b does not constitute mirror symmetry. The arrangement of these openings 333b and 337b can be modified in various ways as described with reference to FIG. 20, and can be arranged so that the shortest distance between the second openings 333b of the lower insulating layer and the second openings 337b of the upper insulating layer is greater than the shortest distance between the second openings 333b of the lower insulating layer or the shortest distance between the second openings 337b of the upper insulating layer.

[0229] In addition, the first bump pad 439a is formed to cover the first opening 437a of the upper insulating layer over the mesas M1 to M4. Fig.18 In the embodiment described above, the first pad metal layer 335a is connected. In addition, a cathode mark Mc for indicating a cathode may be formed on the first convex pad 439a. Fig.21 As shown, the first bump pad 439a in a quadrangular shape may be formed with a cathode mark Mc by omitting the corner portion.

[0230] The second bump pad 439b is formed to cover the second opening 337b of the upper insulating layer over the mesas M1 to M4. Fig.18 In the embodiment described above, the second bump pad 439b is connected to the second pad metal layer 335b. In addition, the second bump pad 439b may cover the upper region of the second opening portion 333b of the lower insulating layer.

[0231] Fig. 22 It is an exploded perspective view for explaining a lighting device using a light emitting diode according to an embodiment of the present invention.

[0232] Reference Fig. 22 According to the present embodiment, the lighting device includes a diffusion cover 1010, a light emitting element module 1020 and a main body 1030. The main body 1030 can accommodate the light emitting element module 1020, and the diffusion cover 1010 can be arranged on the main body 1030 to cover the upper part of the light emitting element module 1020.

[0233] The main body 1030 is not limited in form as long as it can accommodate and support the light emitting element module 1020 and supply power to the light emitting element module 1020. For example, as shown in the figure, the main body 1030 may include a main body housing 1031, a power supply device 1033, a power housing 1035, and a power connection portion 1037.

[0234] The power supply device 1033 can be accommodated in the power supply housing 1035 and electrically connected to the light emitting element module 1020, and includes at least one IC chip. The IC chip can adjust, convert or control the characteristics of the power supplied to the light emitting element module 1020. The power supply housing 1035 can accommodate and support the power supply device 1033, and the power supply housing 1035 in which the power supply device 1033 is fixed can be located inside the main housing 1031. The power supply connection part 1037 can be arranged at the lower end of the power supply housing 1035, so as to be combined with the power supply housing 1035. Therefore, the power supply connection part 1037 can be electrically connected to the power supply device 1033 inside the power supply housing 1035, so as to play the role of a passage for supplying external power to the power supply device 1033.

[0235] The light emitting element module 1020 includes a substrate 1023 and a light emitting element 1021 disposed on the substrate 1023. The light emitting element module 1020 may be disposed on an upper portion of a main housing 1031 and electrically connected to a power supply device 1033.

[0236] The substrate 1023 is not limited as long as it is a substrate that can support the light emitting element 1021, and for example, it can be a printed circuit board including wiring. The substrate 1023 can have a shape corresponding to the fixing portion of the upper part of the main housing 1031, so that it can be stably fixed to the main housing 1031. The light emitting element 1021 can include at least one of the light emitting diodes according to the embodiments of the present invention described above.

[0237] The diffusion cover 1010 may be arranged on the light emitting element 1021 and fixed to the main housing 1031 to cover the light emitting element 1021. The diffusion cover 1010 may have a light-transmitting material, and the directional characteristics of the lighting device may be adjusted by adjusting the shape and light transmittance of the diffusion cover 1010. Therefore, the diffusion cover 1010 may be deformed into various shapes according to the purpose of use and application of the lighting device.

[0238] Fig.23 FIG. 4 is a cross-sectional view for illustrating a display device using a light emitting diode according to another embodiment of the present invention.

[0239] The display device of this embodiment includes: a display panel 2110 ; a backlight unit for providing light to the display panel 2110 ; and a panel guide for supporting the lower edge of the display panel 2110 .

[0240] The display panel 2110 is not particularly limited, and may be, for example, a liquid crystal display panel including a liquid crystal layer. A gate driver printed circuit board (PCB) for providing a drive signal to a gate line may also be arranged at the edge of the display panel 2110. Here, the gate driver PCB may also be formed on a thin film transistor substrate instead of being formed on an independent PCB.

[0241] The backlight unit includes a light source module including at least one substrate and a plurality of light emitting elements 2160. Furthermore, the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131 and an optical sheet 2130.

[0242] The bottom cover 2180 has an opening formed on the top, which can accommodate the substrate, the light emitting element 2160, the reflective sheet 2170, the diffuser 2131 and the optical sheet 2130. In addition, the bottom cover 2180 can be combined with the panel guide. The substrate can be located at the bottom of the reflective sheet 2170 and arranged in a form surrounded by the reflective sheet 2170. However, it is not limited to this. In the case where the surface is coated with a reflective material, the substrate can also be located on the reflective sheet 2170. In addition, the substrate can be formed in multiples and arranged in a form in which multiple substrates are arranged in parallel, but it is not limited to this and can also be formed as a single substrate.

[0243] The light emitting element 2160 may include the light emitting diode according to the embodiment of the present invention described above. The light emitting element 2160 may be regularly arranged in a predetermined pattern on the substrate. In addition, a lens 2210 is arranged on each light emitting element 2160, so that the uniformity of the light emitted from the plurality of light emitting elements 2160 can be improved.

[0244] The diffusion plate 2131 and the optical sheet 2130 are located on the light emitting element 2160. Light emitted from the light emitting element 2160 may be provided to the display panel 2110 in the form of a surface light source through the diffusion plate 2131 and the optical sheet 2130.

[0245] In this way, the light emitting element according to the embodiment of the invention can be applied to the direct type display device similar to this embodiment.

[0246] Fig.24 FIG. 4 is a cross-sectional view for illustrating a display device using a light emitting diode according to another embodiment of the present invention.

[0247] The display device equipped with a backlight unit according to this embodiment includes: a display panel 3210 for displaying an image; and a backlight unit arranged at the back of the display panel 3210 to emit light. Further, the display device includes: a frame 3240 for supporting the display panel 3210 and accommodating the backlight unit; and covers 3270 and 3280 surrounding the display panel 3210.

[0248] The display panel 3210 is not particularly limited, for example, it can be a liquid crystal display panel including a liquid crystal layer. A gate drive printed circuit board (PCB) for providing a drive signal to the gate line can also be arranged at the edge of the display panel 3210. Here, the gate drive PCB can also be formed on a thin film transistor substrate instead of being constituted as an independent PCB. The display panel 3210 is fixed by covers 3270 and 3280 located at the upper and lower parts thereof, and the cover 3280 located at the lower part thereof can be combined with the backlight unit.

[0249] The backlight unit for providing light to the display panel 3210 includes: a lower cover 3270, a portion of the upper surface of which forms an opening; a light source module, which is arranged on one side of the inner portion of the lower cover 3270; and a light guide plate 3250, which is arranged side by side with the light source module and converts point light into surface light. In addition, the backlight unit according to this embodiment may further include: an optical sheet 3230, which is located on the light guide plate 3250 and diffuses light and condenses light; and a reflective sheet 3260, which is arranged at the lower portion of the light guide plate 3250 and reflects light propagating toward the lower portion of the light guide plate 3250 toward the display panel 3210.

[0250] The light source module includes a substrate 3220 and a plurality of light emitting elements 3110, and the light emitting elements 3110 are arranged at a predetermined interval on one side of the substrate 3220. The substrate 3220 is not limited as long as it can support the light emitting elements 3110 and is electrically connected to the light emitting elements 3110, for example, it can be a printed circuit board. The light emitting element 3110 may include at least one light emitting diode according to the embodiment of the present invention described above. The light emitted from the light source module is incident on the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheet 3230. Through the light guide plate 3250 and the optical sheet 3230, the point light source emitted from the light emitting element 3110 can be converted into a surface light source.

[0251] As described above, the light emitting element according to an embodiment of the present invention can be applied to an edge type display device like this embodiment.

[0252] Fig.25 FIG. 4 is a cross-sectional view for explaining an example in which a light emitting diode is applied to a headlamp according to still another embodiment of the present invention.

[0253] Reference Fig.25 The headlamp includes a lamp body 4070 , a substrate 4020 , a light emitting element 4010 , and a cover lens 4050 . Furthermore, the headlamp may further include a heat dissipation portion 4030 , a support frame (rack) 4060 , and a connecting member 4040 .

[0254] The substrate 4020 is fixed by the support frame 4060, so as to be arranged on the lamp body 4070 in a manner separated from the lamp body 4070. The substrate 4020 is not limited as long as it is a substrate capable of supporting the light emitting element 4010, for example, it can be a substrate having a conductive pattern such as a printed circuit board. The light emitting element 4010 can be located on the substrate 4020 and supported and fixed by the substrate 4020. Furthermore, the light emitting element 4010 can be electrically connected to an external power source through the conductive pattern of the substrate 4020. Furthermore, the light emitting element 4010 can include at least one of the light emitting diodes according to the embodiments of the present invention described above.

[0255] The cover lens 4050 is located on the path of the light emitted from the light emitting element 4010. For example, as shown in the figure, the cover lens 4050 can be arranged to be separated from the light emitting element 4010 by the connecting component 4040, and can be arranged in the direction of the light emitted by the light emitting element 4010. The direction angle and / or color of the light emitted from the headlight to the outside can be adjusted by the cover lens 4050. In addition, the connecting component 4040 can also fix the cover lens 4050 to the substrate 4020, and be arranged to surround the light emitting element 4010 to provide a light guiding function of the light emitting path 4045. At this time, the connecting component 4040 can be formed using a light reflective material, or coated with a light reflective material. In addition, the heat dissipation portion 4030 may include a heat dissipation fin 4031 and / or a heat dissipation fan 4033, and discharge the heat generated when the light emitting element 4010 is driven to the outside.

[0256] As described above, the light emitting element according to the embodiment of the present invention can be applied to headlamps such as the present embodiment, and in particular, to vehicle headlamps.

[0257] Although various embodiments of the present invention have been described above, the present invention is not limited to these embodiments. Furthermore, matters or components described in one embodiment may be applied to other embodiments without departing from the technical concept of the present invention.

Claims

1. A light emitting element, comprising: substrate; A first conductive semiconductor layer is arranged on the substrate; A mesa, located on the first conductive type semiconductor layer, and comprising an active layer and a second conductive type semiconductor layer; An ohmic reflective layer, arranged on the mesa and electrically connected to the second conductive type semiconductor layer; a lower insulating layer covering the mesa and the ohmic reflective layer and comprising a first opening formed on the first conductive type semiconductor layer and a second opening exposing the ohmic reflective layer; A first pad metal layer is arranged on the lower insulating layer and electrically connected to the first conductive type semiconductor layer through the first opening; A second pad metal layer is arranged on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening; as well as The first bump pad and the second bump pad are electrically connected to the first pad metal layer and the second pad metal layer respectively. The second pad metal layer is surrounded by the first pad metal layer, and a boundary region between the second pad metal layer and the first pad metal layer has a ring shape.

2. The light-emitting element according to claim 1, wherein The second bump pad is defined and arranged in an upper region of the second pad metal layer.

3. The light-emitting element according to claim 1, wherein The first opening of the lower insulating layer exposes the first conductive type semiconductor layer along the periphery of the mesa. The first pad metal layer has an external contact portion contacting the first conductive type semiconductor layer along a periphery of the mesa.

4. The light emitting element according to claim 1, further comprising: an upper insulating layer formed on the first pad metal layer and the second pad metal layer, The upper insulating layer has a third opening and a fourth opening. The first bump pad and the second bump pad are respectively connected to the first pad metal layer and the second pad metal layer exposed through the third opening and the fourth opening of the upper insulating layer.

5. The light emitting element according to claim 4, wherein The shortest distance from the second opening of the lower insulating layer to the fourth opening of the upper insulating layer is greater than the shortest distance from the second opening of the lower insulating layer to an edge of the second pad metal layer.

6. The light emitting element according to claim 4, wherein The first bump pad and the second bump pad respectively cover the third opening and the fourth opening of the upper insulating layer to seal the upper insulating layer.

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