Noise Cancellation in Impedance Measurement Circuits

Abstract

The present disclosure relates to noise cancellation in an impedance measurement circuit. An impedance measurement device includes: a first hardware circuit element and a second hardware circuit element; a first DAC arranged to convert a first digital input into a first output signal using the first or second hardware circuit element; and a second DAC arranged to convert a second digital input into a second output signal using the first or second hardware circuit element, wherein the device is configured to operate in the following situations: a first mode, in which the first DAC converts the first digital input using the first hardware circuit element and the second DAC converts the second digital input using the second hardware circuit element, and a second mode, in which the first DAC converts the first digital input using the second hardware circuit element and the second DAC converts the second digital input using the first hardware circuit element.

Description

Technical Field

[0001] The present invention relates to an impedance measurement circuit. In particular, the present disclosure relates to a method and apparatus for reducing noise in an impedance measurement circuit. Background Art

[0002] Impedance measurement circuits are used in a variety of applications to detect impedance changes of interest. Impedance measurement circuits are often used in clinical settings to determine physiological parameters of a subject based on detected changes in bioimpedance. For example, an impedance measurement circuit can be used to detect changes in the impedance of a person's chest. The chest impedance can change as the subject breathes, so by detecting changes in the chest impedance it can be inferred that the subject is breathing. The chest impedance can be used to detect conditions such as sleep apnea. For example, if no changes in the chest impedance are detected over a period of time, it can be inferred that the subject did not breathe during that period and therefore may have sleep apnea.

[0003] Impedance measurement circuits include various components, including digital-to-analog converters (DACs) and analog-to-digital converters (ADCs). The noisy characteristics of the DACs and / or ADCs in the circuit can cause the impedance measurement circuit to erroneously detect changes in impedance. This can therefore affect the circuit's ability to accurately infer information from the impedance being measured. Thus, in the example given above, the noisy characteristics of the circuit can cause an erroneous inference from the chest impedance that the subject is breathing, thus ignoring conditions such as sleep apnea. Summary of the invention

[0004] The present disclosure provides an impedance measurement circuit for measuring and detecting changes in measured impedance and a method for operating the impedance measurement circuit. The impedance measurement circuit includes a plurality of converters, including at least two digital-to-analog converters (DACs). The DACs alternate between a first operating mode and a second operating mode together. In the first mode, the first of the DACs is operable to convert a first digital input signal into a first analog output using a first hardware component, and the second of the DACs is operable to convert a second digital input signal into a second analog output using a second hardware component. In the second mode, the first of the DACs is operable to convert a first digital input signal into a first analog output using a second hardware component, and the second of the DACs is operable to convert a second digital input signal into a second analog output using a first hardware component. By alternating between the first and second modes, the first and second hardware components are alternately used in the first DAC and the second DAC to perform the conversion operation of the corresponding DAC. Each hardware component may be associated with an inherent noise power that causes an amplitude error in the corresponding DAC output. In addition, the DACs may be arranged so that an amplitude error in the first DAC and an amplitude error in the second DAC cause opposite errors in the impedance measurement performed by the impedance measurement circuit. Thus, by alternating between the first mode and the second mode, errors in the impedance measurements performed by the impedance measurement circuit are stabilized or proportionally eliminated over time.

[0005] In a first aspect of the present disclosure, an impedance measurement device is provided, comprising a first hardware circuit element and a second hardware circuit element. The device comprises a first DAC arranged to convert a first digital input into a first output signal using the first or second hardware circuit element. The device also comprises a second DAC arranged to convert a second digital input into a second output signal using the first or second hardware circuit element. The device is configured to operate in the following conditions: a first mode, wherein the first DAC converts the first digital input using the first hardware circuit element and the second DAC converts the second digital input using the second hardware circuit element; and a second mode, wherein the first DAC converts the first digital input using the second hardware circuit element and the second DAC converts the second digital input using the first hardware circuit element.

[0006] In a second aspect of the present disclosure, a method for proportionally eliminating gain errors in an impedance measurement device having a first DAC and a second DAC is provided. The method includes operating the first DAC and the second DAC in a first mode, wherein the first DAC uses a first hardware circuit element to convert a first digital input into a corresponding first output signal, and the second DAC uses a second hardware circuit element to convert a second digital input into a second output signal. The method also includes operating the first DAC and the second DAC in a second mode, wherein the first DAC uses a second hardware circuit element to convert the first digital input into a corresponding first output signal, and the second DAC uses the first hardware circuit element to convert the second digital input into a second output signal.

[0007] In a third aspect of the present disclosure, an impedance measurement device is provided, comprising a first DAC, comprising a first output, wherein the first DAC is configured to convert the first digital input into a first output signal by directing a current from a first current source to the first output based on a first digital input. The device also includes a second DAC, comprising a second output, the second DAC being configured to convert a second digital input into a second output signal by directing a current from a second current source to the second output based on a second digital input. In addition, the device includes a bias circuit configured to bias both the first and second current sources.

[0008] A numbered list of illustrative, non-limiting examples is presented by way of summary below.

[0009] Example 1 includes an impedance measurement device, comprising: a first hardware circuit element and a second hardware circuit element; a first DAC is arranged to convert a first digital input into a first output signal using the first or second hardware circuit element; and a second DAC is arranged to convert a second digital input into a second output signal using the first or second hardware circuit element, wherein the device is configured to operate in the following situations: a first mode, in which the first DAC converts the first digital input using the first hardware circuit element and the second DAC converts the second digital input using the second hardware circuit element; and a second mode, in which the first DAC converts the first digital input using the second hardware circuit element and the second DAC converts the second digital input using the first hardware circuit element.

[0010] Example 2 may include the apparatus of Example 1, wherein the apparatus is configured to alternate between the first mode and the second mode.

[0011] Example 3 may include the apparatus of Example 2, wherein the apparatus is configured to alternate between the first mode and the second mode independently of the first and second digital inputs.

[0012] Example 4 may include the apparatus of Example 3, wherein the apparatus is configured to alternate between the first and second modes randomly or in a predetermined pattern.

[0013] Example 5 may include the apparatus of any preceding example, wherein the first hardware circuit element and the second hardware circuit element are of the same type.

[0014] Example 6 may include the apparatus of any preceding example, wherein the first hardware circuit element is a first current source and the second hardware circuit element is a second current source.

[0015] Example 7 may include the apparatus of Example 6, wherein the first DAC is configured to steer current from the first or second current source to a first DAC output depending on the first digital input, and wherein the second DAC is configured to steer current from the first or second current source to a second DAC output depending on the second digital input.

[0016] Example 8 may include the apparatus of Example 6 or 7, further comprising a plurality of switchable paths arranged such that: in the first mode, current is supplied from the first current source to the first DAC and from the second current source to the second DAC; and in the second mode, current is supplied from the second current source to the first DAC and from the first current source to the second DAC.

[0017] Example 9 may include the apparatus of Example 6, 7, or 8, further comprising a bias circuit configured to bias the first and second current sources.

[0018] Example 10 may include the apparatus described in Examples 1 to 4, wherein the first hardware circuit element is a first bias circuit arranged to bias a first current source of the first DAC or a second current source of the second DAC; and the second hardware circuit element is a second bias circuit arranged to bias the first current source or the second current source.

[0019] Example 11 may include the apparatus of Example 10, wherein the apparatus is configured such that: in the first mode, the first bias circuit biases the first current source and the second bias circuit biases the second current source; and in the second mode, the first bias circuit biases the second current source and the second bias circuit biases the first current source.

[0020] Example 12 may include the apparatus of any preceding example, further comprising: an excitation circuit for outputting an excitation signal to the impedance being measured, the excitation circuit comprising a first DAC; and a sensing circuit arranged to sense a signal across the impedance, the sensing circuit comprising a second DAC.

[0021] Example 13 may include a method for proportionally eliminating gain error in an impedance measurement device having a first DAC and a second DAC, comprising: operating the first DAC and the second DAC in a first mode, wherein the first DAC converts a first digital input into a corresponding first output signal using a first hardware circuit element, and the second DAC converts a second digital input into a second output signal using a second hardware circuit element; operating the first DAC and the second DAC in a second mode, wherein the first DAC converts the first digital input into a corresponding first output signal using the second hardware circuit element, and the second DAC converts the second digital input into a second output signal using the first hardware circuit element.

[0022] Example 14 may include the method of Example 13, further comprising alternating between the first and second operating modes.

[0023] Example 15 may include the method of Example 14, wherein the first and second modes are alternated independently of the digital input.

[0024] Example 16 may include the method of any of Examples 13 to 16, including alternating between the first and second modes randomly or in a predetermined pattern.

[0025] Example 17 may include the method of any one of Examples 13 to 16, wherein the first hardware circuit element is a first current source and the second hardware circuit element is a second current source, and wherein: in the first mode, the first DAC converts the first digital input by directing current from the first current source to a first DAC output depending on the first digital input, and the second DAC converts the second digital input by directing current from the second current source to a second DAC output depending on the second digital input; and in the second mode, the first DAC converts the first digital input by directing current from the second current source to the first DAC output depending on the first digital input, and the second DAC converts the second digital input by directing current from the first current source to the second DAC output depending on the second digital input.

[0026] Example 18 may include the method of any one of Examples 13 to 16, wherein the first hardware circuit element is a first bias circuit and the second hardware circuit element is a second bias circuit, wherein: in the first mode, the first DAC uses a current source biased by the first bias circuit to convert the first digital input, and the second DAC uses a current source biased by the second bias circuit to convert the second digital input; and in the second mode, the first DAC uses a current source biased by the second bias circuit to convert the first digital input, and the second DAC uses a current source biased by the first bias circuit to convert the second digital input.

[0027] Example 19 may include the method of any of Examples 13 to 18, wherein the first DAC is included in an excitation circuit for outputting an excitation signal to a bioimpedance, and the second DAC is included in a sensing circuit arranged to sense a signal across the bioimpedance.

[0028] Example 20 may include an impedance measurement device comprising: a first DAC comprising a first output, wherein the first DAC is configured to convert the first digital input into a first output signal by directing current from a first current source to the first output based on a first digital input; a second DAC comprising a second output, wherein the second DAC is configured to convert the second digital input into a second output signal by directing current from a second current source to the second output based on a second digital input; and a bias circuit configured to bias the first and second current sources. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Examples of the present disclosure are now described with reference to the accompanying drawings, in which:

[0030] Figure 1 An impedance measurement circuit according to an example of the present disclosure is shown;

[0031] Figure 2A The example according to the present disclosure is shown Figure 1 The excitation circuit of the impedance measurement circuit.

[0032] Figure 2B An example according to the present disclosure is shown. Figure 2A The excitation DAC of the excitation circuit;

[0033] Figure 3A An example according to the present disclosure is shown. Figure 1 The sensing circuit of the impedance measurement circuit.

[0034] Figure 3B An example according to the present disclosure is shown. Figure 3A ADC of the sensing circuit;

[0035] Figure 3C The example according to the present disclosure is shown Figure 3B The feedback DAC of the ADC;

[0036] Figure 4 Shows Figure 2B The excitation DAC and / or Figure 3C Example implementations of a DAC cell and bias circuit for a feedback DAC;

[0037] Figure 5A A first mode of a noise error reduction arrangement of an excitation DAC and a feedback DAC according to an example of the present disclosure is shown;

[0038] Figure 5B Shows Figure 5A a second mode of noise error reduction arrangement of the excitation DAC and the feedback DAC;

[0039] Figure 6 Another example of a noise error reduction arrangement for an excitation DAC and a feedback DAC is shown, which involves swapping the current source of the excitation DAC with the current source of the feedback DAC;

[0040] Figure 7 Shows Figure 6 Example implementation of a noise error reduction device;

[0041] Figure 8 Shows Figure 6 An alternative embodiment of a noise error reduction device;

[0042] Fig. 9 Shows Figure 5A and 5B An example implementation of a noise error reduction apparatus of the invention involves swapping a bias circuit of an excitation DAC with a bias circuit of a feedback DAC;

[0043] Fig.10 A noise error reduction arrangement of an excitation DAC and a feedback DAC according to yet another example of the present disclosure is shown, which involves sharing a bias circuit between the excitation DAC and the feedback DAC;

[0044] Fig.11 An alternative example of a sensing circuit according to an example of the present disclosure is shown;

[0045] Fig.12 A flow chart illustrating a method of operating an impedance measurement circuit according to examples of the present disclosure is shown. DETAILED DESCRIPTION

[0046] The present disclosure relates to an impedance measurement circuit. In particular, the present disclosure relates to a method and a circuit arrangement for reducing the influence of hardware inherent noise in an impedance measurement circuit.

[0047] The impedance measurement circuit may include an excitation DAC that excites the impedance with a carrier signal, such as a 50kHz sine wave. The carrier signal is typically a current signal. The sensing ADC then senses a voltage signal across the impedance. The ADC converts the detected voltage signal into a detected digital signal. The impedance measurement circuit analyzes the sensed digital signal to detect changes in impedance. Depending on the frequency of the carrier signal, the sensed digital signal may include a frequency component at 50kHz. The sensed digital signal may also include additional frequency components corresponding to the frequency of impedance change. In one application, the impedance may be the thoracic impedance of a human subject, which changes as the subject breathes. Therefore, the additional frequency components caused by the slow change in impedance may be much lower, approximately 0.3Hz. The sensed digital signal may be analyzed to detect the 0.3Hz component to determine whether the subject is breathing.

[0048] One problem with this type of circuit is that noise from the circuit components of the excitation DAC affects how the excitation DAC generates the carrier signal. This can cause errors in the amplitude of the carrier signal. In addition, noise from the feedback DAC circuit components affects how the ADC converts the sense voltage signal into the sense digital signal, which can cause sense digital signal amplitude errors. Overall, these two types of errors may mix together and cause time-varying amplitude errors in the sensed digital signal. The time-varying error will vary at a low frequency, such as close to 0.3Hz. Therefore, even when the impedance is not changing, the impedance measurement circuit may detect an error frequency component that looks like a frequency component of the impedance and erroneously determine that the impedance is changing. If the impedance is thoracic impedance as described above, this can cause the impedance measurement circuit to erroneously detect breathing and may ignore conditions such as sleep apnea.

[0049] The present disclosure proposes averaging or "proportionally canceling" time-varying errors over time by exchanging and / or sharing components between the excitation DAC and the feedback DAC. In particular, the inventors have determined that a noise component used in the excitation DAC to generate a carrier signal will have an opposite error effect on the sensed digital signal than when the same noise component is used in the feedback DAC of the ADC. Similarly, a noise component originally used in the feedback DAC will have an opposite error effect on the sensed digital signal than when the same noise component is used in the excitation DAC. Therefore, by exchanging noise components back and forth between the excitation DAC and the feedback DAC over time, the amplitude error in the sensed digital signal can be stabilized, and the error frequency components of the sensed digital signal can be suppressed. In addition, sharing some noise components can reduce the total amount of noise in the impedance measurement circuit and further reduce the amplitude error.

[0050] Typically, the excitation DAC and the feedback DAC include corresponding current source groups for generating their corresponding outputs. In addition, each DAC typically includes at least one corresponding bias circuit for setting the current level of the DAC current source. However, as described above, the current source and the bias circuit may be noisy components. Therefore, in one example, the impedance measurement circuit may include a circuit arrangement to exchange the current source of the excitation DAC with the corresponding current source of the feedback DAC back and forth over time. Therefore, it can be seen that the current source of the excitation DAC and the corresponding current source of the feedback DAC operate in the following modes: in the first mode, the current source of the excitation DAC is used to excite the DAC to generate a carrier signal, and the current source of the feedback DAC is used to feedback the DAC as part of the ADC function; in the second mode, the current source originally from the excitation DAC is now used for the feedback DAC as part of the ADC function, and the current source originally from the feedback DAC is now used to excite the DAC to generate a carrier signal.

[0051] In another example, the impedance measurement circuit may include a circuit arrangement to swap the bias circuit of the excitation DAC with the bias circuit of the feedback DAC back and forth over time. Thus, the bias circuit may be viewed as operating in the following modes: in a first mode, the bias circuit of the excitation DAC is used in the excitation DAC to set the current of the excitation DAC current source, and the feedback DAC bias circuit is used in the feedback DAC to set the current of the feedback DAC current source; in a second mode, the bias circuit from the excitation DAC is used in the feedback DAC to set the current of the feedback DAC current source, and the bias circuit from the feedback DAC is used in the excitation DAC to set the current of the excitation DAC current source.

[0052] In an alternative example, the excitation DAC and the feedback DAC may instead share the same bias circuit, such that the same bias circuit sets the current of the current sources of both the excitation DAC and the feedback DAC.

[0053] Impedance measurement circuit

[0054] Figure 1 The diagram shows the impedance Z BIO and in particular for detecting the impedance Z BIO The impedance measurement circuit 100 of the change of Z. In the example scenario, the impedance Z BIO is a bioimpedance that may correspond to the thoracic impedance of a human subject. As the subject breathes, the thoracic impedance may change or vary over time. A typical thoracic impedance may be about 1 kOhm. As the subject breathes, the thoracic impedance may be expected to change at about F BIO =0.3Hz frequency changes periodically, and the change amplitude is about 1 ohm. In this case, it is necessary to detect the bioimpedance Z BIO to determine whether the patient is breathing.

[0055] The impedance measurement circuit 100 includes an excitation circuit 110 and a sensing circuit 120. The excitation circuit 110 is configured to generate an excitation current signal I X (t) and output it to the bioimpedance Z BIO Specifically, the excitation circuit 110 provides a current to the bioimpedance Z via the first current path 112. BIO Provide current signal I X (t), and returns the current signal I through the second current path 114 X (t). Preferably, the current signal I X (t) is an AC sine wave that varies with time. In the example scenario, the current signal I X (t) may have F C =50kHz. However, it should be understood that depending on the impedance Z being measured BIO Types of F can be used with different shapes and / or frequencies C Different types of excitation signals.

[0056] By using the excitation current signal I X (t) Excitation bioimpedance Z BIO , in the bioimpedance Z BIO The voltage signal V is induced on S (t). Voltage signal V S (t) will also be the frequency F C =50KHz time-varying AC signal, corresponding to the excitation signal I X (t). However, if the bioimpedance Z BIO At frequency F BIO changes, which will further increase with frequency F BIO Modulation voltage signal V S (t). Since F BIO Significantly smaller than F C , so the frequency component F C In fact, the frequency component F BIO The carrier frequency is . Therefore, the voltage signal V S (t) will contain F C and F C ±F BIO Therefore, in the above example, the voltage signal V S (t) will contain frequency components at approximately 50kHz, 50000.3Hz and 49999.7Hz.

[0057] The sensing circuit 120 is configured to sense the bioimpedance Z BIO The voltage signal V S (t). In addition, the sensing circuit 120 is configured to detect the voltage signal V S(t) The frequency component F BIO In some examples, the sensing circuit 120 can detect the bioimpedance frequency component F BIO First demodulate V S (t) to remove the carrier frequency component F C In any case, by detecting the specific frequency component of interest F BIO The presence of Z BIO , and thus detect whether the subject is breathing.

[0058] As will be described in more detail below, noise sources in both the excitation circuit 110 and the sensing circuit 120 may cause the sensing circuit 120 to erroneously detect the frequency component F BIO , and thus lead to false detection of the subject's breathing.

[0059] Figure 2A Pictured Figure 1 The excitation circuit 110 includes an excitation DAC 203 and a digital signal generator 209. The digital signal generator 209 is coupled to the excitation DAC 203 via a digital signal line 201. The signal generator 209 is configured to generate an N-bit digital signal D X [p], where p = t / T X And T X is the clock period of the signal generator 209 and the excitation DAC 203. The digital signal D X [p] is the excitation signal I X (t) is a digital representation of the signal. In particular, the digital signal D X [p] may be a C = A digital representation of a sine signal of 50 kHz, corresponding to the analog excitation signal I in the above example case X Characteristics of (t).

[0060] The excitation DAC 203 is used to receive the digital signal D through the digital signal line 201. X [p], and the digital signal D X [p] converted to analog excitation signal I X (t). Specifically, the DAC 203 is driven at a clock frequency of 1 / T X The digital signal D X The instance or value of [p] is converted into an analog stimulus signal I X (t). Preferably, the excitation DAC 203 is a current-controlled DAC so that it can output an excitation current signal I X (t). More preferably, the excitation DAC 203 is a differential current control DAC. Therefore, Figure 2AAs shown, the excitation DAC 203 converts the excitation current signal I X (t) is output to the differential output 240. The excitation current signal I X (t) The positive portion I of the positive branch 205p provided to the differential output 240 XP and the negative portion I provided to the negative branch 205n of the differential output 240 XN Formation, where I X (t) = I XP -I XN .like Figure 2A As shown, each branch 205p and 205n of the differential output 240 can be coupled to the bioimpedance Z BIO to the corresponding side of the bioimpedance Z BIO Provide excitation signal I X (t). Optionally, although not in Figure 2A However, the excitation circuit 110 may further include a buffer circuit, which is arranged to X (t) Provides bioimpedance Z BIO The output of the excitation DAC 203 is previously buffered.

[0061] Figure 2B Pictured Figure 2A 2. The excitation DAC 203 includes a plurality of DAC units 220.1, 220.2, ..., 220.N. Each DAC unit 220.1, 220.2, ..., 220.N is coupled between a power supply rail 231 and an output 240 of the DAC. In addition, each n-th DAC unit 220.n is configured to convert a digital signal D X The corresponding nth bit D of [p] X [p] n To provide an excitation signal I X (t), where n = 1…N.

[0062] Each nth DAC unit 220.n includes a current source 222.n and a current steering circuit 224.n. The current source 222.n is coupled between a power rail 231 and a current control circuit 224.n. The current source 222.n is arranged to provide a current I to the current steering circuit 224.n. n .

[0063] The current steering circuit 224.n is arranged to receive a current I from the current steering circuit 224.n. n The current steering circuit 224.n is configured to convert the current I provided by the current source 222.n to n The positive branch 205p or the negative branch 205n directed to the DAC output 240 depends on the digital signal D X The corresponding nth bit D of [p]X [p] n In particular, the current diverting circuit 224.n includes a pair of current diverting switches, including a first current diverting switch 226.n and a second current diverting switch 228.n. The first current control switch 226.n is arranged to switchably couple the output of the current source 222.n to the positive branch 205p of the DAC output. The second current control switch 228.n is arranged to switchably couple the output of the current source 222.n to the negative branch 205n of the DAC output.

[0064] In operation, if for a particular instance p, D X [p] n ='1' or 'high', the current steering circuit 224.n can switch the current I by closing the first current steering switch 226.n and opening the second current steering switch 228.n. n The positive branch 205p leads to the DAC output 240. If for a particular instance p, D X [p] n ='0' or 'low', the current steering circuit 224.n can turn on the first current steering switch 226.n and close the second current steering switch 228.n to switch the current I n The negative branch 205n is directed to the DAC output 240. Therefore, the feedback DAC 303 is able to convert the digital signal D into a positive signal by appropriately directing the output of each current source 222.1 to 222.N to the DAC output 240. X [p] Convert to analog output I X (t).

[0065] Although not in Figure 2B , but each current steering circuit 224.n may be configured to receive a digital signal D X The corresponding nth bit D of [p] X [p] n And according to the nth D X [p] n The value of D controls its operation. For example, the current diverter switch 226.n can be arranged to receive the nth bit D X [p] n As a control signal, when D X [p] n When it is 1 or high, the current diverter switch 226.n is closed, or when D X [p] n When it is 0 or low, it is in an open circuit state. In addition, the current diverter switch 228.n can receive the nth bit D X [p] nof the complement of the digital signal so that it is in the opposite state as the other current steering switch 226.n for each instance of the digital signal.

[0066] The excitation DAC 203 also includes a bias circuit 233. The bias circuit 233 is coupled to the power rail 231 and each of the current sources 222.1, 222.2 ... 222.N. The bias circuit 233 is configured to bias each of the current sources 222.1, 222.2 ... 222.N. Preferably, the bias circuit 233 biases each current source so that each current source outputs substantially the same current, so that I1 = I2 = ... = I N However, in other examples, the current sources may be binary weighted such that I1=2 0 *I1, I2 = 2 1 *I1,…I N =2 N-1 *I1.

[0067] Figure 3A Pictured Figure 1 The sensing circuit 120 includes an input buffer 301, an analog-to-digital converter (ADC) 315, and a digital signal processor (DSP) 313. The input buffer 301 is arranged to receive a voltage signal V S (t) and the voltage signal V S (t) is provided to ADC 315. ADC 315 is configured to convert the voltage signal V S (t) is converted into an M-bit digital representation of a voltage signal, expressed as D S [q], where q is an integer, q = t / T S And T S is the sampling frequency of ADC 315. ADC 315 is arranged to convert the digital signal D S [q] is output to DSP 313. DSP 313 is configured to analyze the digital signal D S [q] to detect bioimpedance Z BIO For example, DSP 313 can be configured to detect the frequency of interest F BIO and other frequencies of interest, as described above. In some examples, DSP 313 is also configured to detect bioimpedance Z BIO Before the change of the digital signal D S [q] from the carrier frequency F C Digitally demodulated to DC level.

[0068] Figure 3B Pictured Figure 3A304. In this example, the ADC 315 is a continuous time Sigma Delta ADC. The ADC 315 includes a subtractor 305, a loop filter 307, a quantizer 309, and a feedback DAC 303.

[0069] Preferably, the feedback DAC 303 is a current controlled DAC similar to the excitation DAC 203. The feedback DAC 303 is arranged to receive the digital signal D from the output of the ADC 315 in a feedback path on the digital signal line 311. S [q]. The feedback DAC 303 is used to convert the digital signal D S [q] is converted into an analog feedback current signal I F In particular, the feedback DAC 303 is clocked at 1 / T S The digital signal D S The instance or value of [q] is converted into an analog feedback signal I F (t). The feedback DAC 303 is configured to convert the feedback current signal I F (t) is output to the output 340 of the DAC 303 .

[0070] Subtractor 305 is used to obtain the voltage signal V S (t) minus the feedback current signal I F (t). The subtractor 305 may be configured to first convert the feedback current signal I F (t) is converted into the corresponding voltage signal V F Alternatively, the input buffer 301 or the subtractor 305 may be configured to convert the voltage signal V S (t) is converted into the corresponding current signal I S (t).

[0071] The loop filter is configured to filter the output of the subtractor 305. The quantizer 309 is configured to quantize the output of the loop filter to generate a digital signal D S It should be understood that the continuous-time Σ-Δ ADC 315 may operate as known in the art, and thus the operating principle of the ADC 315 is not described in detail.

[0072] Figure 3C Pictured Figure 3B320. The feedback DAC 303 includes a plurality of DAC units 320.1, 320.2, ..., 320.M. Each DAC unit 320.1, 320.2, ..., 320.M is coupled between a power supply rail 331, a DAC output 340, and a ground 335. In addition, each m-th DAC unit 320.m is configured to convert a digital signal D S The corresponding mth bit D of [q] S [q] m , where m=1…M.

[0073] Each m-th DAC unit 320.m includes a current source 322.m and a current steering circuit 324.m. The current source 322.m is coupled between the power rail 331 and the current control circuit 324.m. The current source 322.m is arranged to provide a current I m .

[0074] The current steering circuit 324.m is arranged to receive the current I from the current source 322.m. m The current control circuit 324.m is configured to convert the current I provided by the current source 322.m to m Controlled to DAC output 340 or ground 335, depending on the digital signal D S The corresponding mth bit D of [q] S [q] m In particular, the current diverting circuit 324.m includes a pair of current diverting switches, including a first current diverting switch 326.m and a second current diverting switch 328.m. The first current diverting switch 326.m is arranged to switchably couple the output of the current source 322.m to the DAC output 340. The second current diverting switch 328.m is arranged to switchably couple the output of the current source 322.m to the ground 335.

[0075] In operation, if D S [q] m ='1' or 'high', the current diversion circuit 324.m can divert the current I m The DAC output is 340. If D S [q] m ='0' or 'low', the current steering circuit 324.m can steer the current I by opening the first current steering switch 326.m and closing the second current steering switch 328.m. m Therefore, the feedback DAC 303 is able to convert the digital signal D to ground by appropriately directing the output of each of the current sources 322.1 to 322.M to the output 340. S[q] Convert to analog output I F (t).

[0076] Although not in Figure 3C As shown in FIG. 1 , each current steering circuit 324.m may be configured to receive a digital signal D S The corresponding mth bit D of [q] S [q] m And according to the mth D S [q] m For example, the current diverter switch 326.m may be arranged to receive the mth bit D S [q] m As a control signal, when D S [q] m When it is 1 or high, the current diverter switch 326.m is in the closed state. S [q] m When it is 0 or low, it is in the open state. In addition, the current diverter switch 328.m can receive the nth bit D S [q] m 's complement so that it is in the opposite state as the other current steering switch 326.n for each instance of the digital signal.

[0077] Feedback DAC 303 also includes bias circuit 333. Bias circuit 333 is coupled to power rail 331 and each of current sources 322.1, 322.2 ... 322.M. Bias circuit 333 is configured to bias each of current sources 322.1, 322.2 ... 322.M. In particular, bias circuit 333 preferably biases each current source so that each current source outputs substantially the same current, such that I1 = I2 = ... = I M However, in other examples, the current sources may be binary weighted such that I1=2 0 I1, I2 = 2 1 I1,…I M =2 M-1 I1.

[0078] In a preferred example of the impedance measurement circuit 100, the digital signal D S [q] and D X [p] has the same resolution, so the excitation DAC 203 and the feedback DAC 303 also have the same resolution, so that N = M. In other words, the digital signal D S [q] and D X[p] has the same number of bits, so the excitation DAC 203 and the feedback DAC 303 are configured to convert the same number of bits, so that N = M. In another preferred example of the impedance measurement circuit, each nth current source of the excitation DAC 203 is configured and biased to output the same current as each mth current source corresponding to the same bit. In other words, the current source is biased so that for each n = 1 to N and m = 1 to M and n = m, I n =I m .

[0079] Although the feedback DAC 303 is described as providing a single-ended output 340, it should be understood that the feedback DAC 303 may also be implemented with a differential output, similar to the output of the excitation DAC 203 described above.

[0080] System gain error

[0081] The digital output D of ADC 315 S [q] can be expressed as:

[0082] D S [q] = G*f(I X (t),Z BIO ), (1)

[0083] Where G represents the system gain of the impedance measurement circuit 100, and the function f(I X (t),Z BIO ) represents D S [q] for the excitation signal I X (t) and impedance Z BIO The system gain G can be defined as:

[0084] G=I ADC / I XDAC , (2)

[0085] Thus I ADC represents the full-scale current of the ADC 315 of the sensing circuit 120, and I XDAC represents the full-scale current of the excitation DAC 203 of the excitation circuit 110. In other words, I ADC The feedback signal I at the output 340 of the feedback DAC 303 may be considered as F (t) is the maximum achievable current. Similarly, I XDAC can be considered as the excitation signal I at the output 240 of the excitation DAC 203 X (t) The maximum current that can be achieved. In operation, the output I of the feedback DAC 303 F (t) is actually the full-scale current I ADCpart of the feedback DAC 303 digital input D S Similarly, the output I of the stimulus DAC 203 is controlled by X (t) is actually the full-scale current I XDAC part of the digital input D X The value of [p] is controlled.

[0086] Ideally, the full-scale current I ADC and I XDAC Keep constant, the system gain G remains stable. Therefore, according to equation (1), the digital signal D S [q] should only contain the excitation signal I X (t) and from the bioimpedance Z BIO The frequency components of the variations, as described above.

[0087] However, the hardware components / elements of the excitation DAC 203 may exhibit inherent noise characteristics. This may cause the full-scale current I of the excitation DAC 203 to be XDAC Similarly, the hardware components / elements of the feedback DAC 303 may also exhibit inherent noise characteristics. This may also cause the ADC 315 full-scale current I ADC Changes over time.

[0088] I XDAC and I ADC The change in system gain G may cause the system gain G to change with frequency F G Therefore, according to equation (1), the digital output D of ADC 315 is S [q] will contain the corresponding time-varying amplitude error caused by noise from both the excitation circuit 110 and the sensing circuit 120. The amplitude error will also vary with frequency F G The problem is that the amplitude error frequency F G may be at or near the frequency of interest F BIO , so that F G ≈F BIO Therefore, even when the bioimpedance Z BIO When there is no change, DSP 317 can also detect the digital signal D S [q] is the frequency of interest F BIO The corresponding frequency component F G In the example scenario above, this could cause the impedance measurement circuit to erroneously detect the thoracic impedance Z BIO , thereby falsely determining that the subject is breathing.

[0089] The hardware components of the excitation DAC 203 and the feedback DAC 303 that exhibit intrinsic noise may include: current sources 222.1 ... 222.N and bias circuit 233 of the excitation DAC 203, and current sources 322.1 ... 322.M and bias circuit 333 of the feedback DAC 303. Figure 2B , each current source 222.1 to 222.N may exhibit hardware intrinsic noise, causing the DAC full-scale current I XDAC For example, each current source may have an inherent noise power P XNC In addition, the bias circuit 233 may also have a function that causes the DAC 203 full-scale current I XDAC For example, bias transistor 4330 may have a noise power P XB Since the excitation DAC 203 has N DAC units, the excitation DAC 203 may have N*P XB +√N*P XNC The current sources 322.1 to 322.M of the feedback DAC 303 and the bias circuit 333 may have similar noise characteristics P SNC and P SB Therefore, since the feedback DAC 303 has M DAC units, the excitation DAC 203 may have M*P SB +√M*P SNC The total noise power.

[0090] Figure 4 An example implementation of a bias circuit 433 and a DAC unit 420 is illustrated. The DAC unit 420 includes a current source 422 and a current diverting circuit 424. The current diverting circuit 424 includes a first current diverting switch 426 and a second current diverting switch 428.

[0091] DAC unit 420 may be considered as an example implementation of each DAC unit 220.1 to 220.N from excitation DAC 203 and each DAC unit 320.1 to 320.M from feedback DAC 303. In addition, bias circuit 433 may also be considered as an example implementation of bias circuit 233 from excitation DAC 203 and bias circuit 333 from feedback DAC 303. Therefore, DAC unit 420 and bias circuit 433 may operate as described above with respect to excitation DAC 203 and feedback DAC 303, and thus the working principles of DAC unit 420 and bias circuit 433 are not described in detail.

[0092] like Figure 4As shown, each of the first current control switch 426, the second current control switch 428, the current source 422 and the bias circuit 433 is implemented by a corresponding MOS transistor 4260, 4280, 4220 and 4330. Figure 4 In FIG. 4 , transistors 4260 , 4280 , 4220 , and 4330 are PMOS transistors. However, it should be understood that implementations using NMOS transistors are also possible.

[0093] The MOS transistors 4220 of the current source 422 may exhibit hardware intrinsic noise, causing the full-scale current of the DAC to fluctuate. For example, each current source transistor 4220 may have an intrinsic noise power P NC In addition, the MOS transistor 4330 of the bias circuit 433 may also have an associated noise power P B Therefore, for a DAC with N DAC cells, the DAC may have N*P B +√N*P NC The total noise power.

[0094] Gain error ratio cancellation

[0095] From equations (1) and (2) above, it can be seen that the full-scale current I XDAC With digital signal D S [q] is inversely proportional. Therefore: the full-scale current I XDAC A positive amplitude error will result in a negative error in the system gain G and the digital signal D S Negative error of [q]; I XDAC A negative amplitude error in will result in a positive error in the system gain G and the digital signal D S On the other hand, the full-scale current I ADC With digital signal D S [q] is proportional, so: full-scale current I ADC A positive amplitude error will result in a positive error in the system gain G and the digital signal D S Positive error of [q]; I ADC A negative amplitude error will result in a negative error in the system gain G and the digital signal D S Negative error of [q].

[0096] The inventors of the present invention have determined that by alternately exchanging the noise components of the excitation DAC 203 with the corresponding noise components of the feedback DAC 303 at an appropriate rate, the amplitude error in the system gain G can be proportionally eliminated. Therefore, the system gain G can be adjusted for I XDAC and I ADC By stabilizing the system gain G, the digital signal D S[q] may no longer contain frequency components F associated with changes in system gain G G , thus significantly reducing the false detection Z BIO Opportunity for change.

[0097] Figure 5A 2 shows an example view of an excitation DAC 203 and a feedback DAC 303 according to an example of an impedance measurement circuit 100 configured to proportionally eliminate system gain errors. Figure 5A As shown, the excitation DAC 203 includes a first hardware component 520, while the feedback DAC 303 includes a second hardware component 530. The hardware component 520 may be any component of the excitation DAC 203 that exhibits an inherent noise power that contributes to the error in the system gain G, as described above. For example, the hardware component 520 may be the nth current source 222.n or the bias circuit 233 of the excitation DAC 203. Preferably, the hardware component 530 is a corresponding component of the feedback DAC 303 that performs the same or corresponding function as the hardware component 520 in the feedback DAC 303. For example, if the hardware component 520 is the nth current source 222.n of the excitation DAC 203, then the hardware component 530 may be the mth current source 322.m of the feedback DAC 303, such that n=m. Alternatively, if the hardware component 520 is the bias circuit 233 of the excitation DAC 203, then the hardware component 530 may be the bias circuit 333 of the feedback DAC 303. Therefore, hardware components 520 and 530 may be considered as a pair of corresponding hardware components 540 .

[0098] Figure 5A 5. A first operating mode of the hardware component pair 540 is illustrated. In the first mode, the hardware component 520 is used in the stimulus DAC 203. Specifically, the hardware component 520 is used to perform operations in the stimulus DAC 203 to convert the digital input signal D X [p] instance is converted to analog output I X (t), as described above. For example, if hardware component 520 is the nth current source 222.n, hardware component 520 provides current to current steering circuit 224.n and current steering circuit 224.n operates as described above. If hardware component 520 is bias circuit 233, hardware component 520 biases each current source 222.1 to 222.N that excites the DAC.

[0099] In addition, hardware component 530 is initially used in feedback DAC 303 to perform the conversion of digital input D S [q] is converted to analog output I F(t) is operated as described above. For example, if the hardware component 530 is the mth current source 322.m, the hardware component 530 provides current to the current steering circuit 324.m that operates as described above. If the hardware component 530 is the bias circuit 333, the hardware component 530 biases each current source 322.1 to 322.M of the feedback DAC.

[0100] Therefore, in Figure 5A In the first mode shown, hardware component 520 may cause I XDAC Hardware component 530 may cause I ADC Error in .

[0101] Figure 5B A second operating mode of hardware component pair 540 is shown. Figure 5B As shown, hardware component 520 has been exchanged with hardware component 530. Specifically, hardware component 530 is now being used to perform the conversion of digital input signal D X [p] instance is converted to analog output I X For example, if hardware component 530 is the mth current source 322.m of feedback DAC 303, hardware component 530 now provides current to current steering circuit 224.n in excitation DAC 203. If hardware component 530 is bias circuit 333, hardware component 530 now biases each current source 222.1 to 222.N of the excitation DAC.

[0102] In addition, Figure 5B , hardware component 520 is now used in feedback DAC 303 to perform the conversion of the digital input D S [q] is converted to analog output I F For example, if hardware component 520 is the nth current source 222.n of excitation DAC 203, hardware component 520 now provides current to current steering circuit 324.m of feedback DAC 303. If hardware component 520 is bias circuit 233, hardware component 520 now biases each current source 322.1 to 322.M of the excitation DAC.

[0103] Thus, in the second mode, hardware component 520 may now cause I ADC and hardware component 530 may now cause I XDAC Error in .

[0104] By continuously alternating between the first and second modes at an appropriate speed, I XDAC Will experience I for a period of time ADCIn particular, the error caused by the first hardware component 520 will be evenly distributed over time between the denominator and numerator of the system gain G. Similarly, the error caused by the second hardware component 530 will be evenly distributed over time between the denominator and numerator of the system gain G. Thus, the system gain G will be effectively stabilized against the amplitude errors caused by both hardware components 520 and 530 in the hardware component pair 540.

[0105] The impedance measurement circuit 100 may be configured to switch the hardware component pair 540 between the first and second operating modes using any suitable means. Figure 5A and 5B As shown, the impedance measurement circuit 100 may include a controller 590 that is arranged to control the exchange of the hardware component pair 540 between the excitation DAC 203 and the feedback DAC 303 in the first and second operating modes. In some examples, the controller 590 may switch the hardware component pair 540 between the first mode and the second mode at a predetermined frequency. For example, the predetermined frequency may be equal to the clock frequency of the excitation DAC and the feedback DAC, so that the excitation DAC and the feedback DAC have the same clock frequency (1 / T S =1 / T X ). In such an example, each DAC may convert one instance of the corresponding digital input in each operating mode before changing to the next operating mode. Alternatively, the predetermined frequency may be lower than the excitation DAC (1 / T X ) and the feedback DAC (1 / T S ) of the clock frequency. This can allow multiple instances of the digital input to be switched between changes in operating modes. In such an example, the feedback DAC and the excitation DAC may or may not have equal clock frequencies. In either case, the predetermined frequency may also be a frequency F that is greater than the amplitude error of the system gain G. G More specifically, the predetermined frequency may be a frequency F greater than the amplitude error in the system gain G. G Twice the frequency, thereby accounting for fluctuations in error. In other examples, controller 590 may switch hardware component pairs 540 in a predetermined pattern or randomly. The optimal switching frequency and / or switching pattern for proportionally canceling gain errors may be determined through simulation and test data.

[0106] The above technique can be extended to stabilize the system gain G against amplitude errors from multiple pairs of hardware components. For example, Figure 6 2 shows an example view of an excitation DAC 203 and a feedback DAC 303 according to another example of an impedance measurement circuit 100 configured to proportionally eliminate system gain errors. Figure 6As shown, excitation DAC 203 initially includes each current source 222.1 to 222.N, and feedback DAC 303 initially includes each current source 322.1 to 322.M. As shown, the current sources can be considered to be grouped into different pairs, such that a pair 640.k includes current source 222.n and current source 322.m, where k=1...K and k=n=m and K=N=M.

[0107] Each kth pair of current sources 640.k is arranged to operate in respective first and second modes, as described above with respect to Figure 5A and 5B Specifically, in the first mode of pair 640.k, current source 222.n is used in excitation DAC 203 to perform an operation in excitation DAC 203 to convert the digital input signal D X [p] instance is converted to analog output I X (t), as described above. For example, current source 222.n provides current to current steering circuit 224.n and current steering circuit 224.n operates as described above. In addition, current source 322.m is used in feedback DAC 303 to perform the conversion of digital input D S [q] is converted to analog output I F (t) is operated as described above. For example, current source 322.m provides current to current steering circuit 324.m which operates as described above. Thus, in the first mode, current source 222.n may cause I XDAC The current source 322.m may cause the I ADC The error in .

[0108] In the second mode of operation of pair 640.k, current source 222.n will be swapped with current source 322.m. Specifically, current source 322.m will now provide current to current steering circuit 224.n in excitation DAC 203 instead of current steering circuit 324.m. Furthermore, in the second mode, current source 222.n will now be used to provide current to current control circuit 324.m of feedback DAC 303 instead of current control circuit 224.n.

[0109] Each pair of current sources 640.k may be controlled to switch continuously between respective first and second modes of operation, independent of the modes of operation of the other pairs of current sources. Figure 6As shown, the impedance measurement circuit 100 may include a controller 690 configured to independently control the operating mode of each pair of current sources 640.1 to 640.K. In this way, each pair of current sources 660.k can be switched between the first and second operating modes based on their respective requirements to optimally stabilize the system gain G. In some examples, the controller 690 can switch each pair of current sources 660.k between the first and second modes at respective predetermined frequencies, such as any of the predetermined frequencies described above. In other examples, the controller 690 can switch the pairs of current sources 640.1 to 640.k between the first and second modes in a predetermined pattern or randomly. The optimal switching frequency and / or switching pattern for proportionally canceling the gain error can be determined through simulation and test data.

[0110] Figure 7 An example current source switch arrangement is illustrated by which the kth pair of current sources 640.k can operate in the first and second modes as described above. In particular, Figure 7 An example arrangement is shown of how the current source 222 . n of the nth DAC cell 220 . n from the excitation DAC 203 may be swapped with the corresponding current source 322 . m of the mth DAC cell 320 . m from the feedback DAC 303 as described above.

[0111] like Figure 7 As shown, the impedance measurement circuit 100 also includes a switch network 710.k. The switch network 710.k includes a plurality of switches 721.k, 723.k, 725.k, and 727.k. The switch 721.k is arranged to switchably couple the output of the current source 222.n to the current steering circuit 224.n. The switch 723.k is arranged to switchably couple the output of the current source 322.m to the current steering circuit 224.n. The switch 725.k is arranged to switchably couple the output of the current source 222.n to the current steering circuit 324.m. The switch 727.k is arranged to switchably couple the output of the current source 322.m to the current steering circuit 324.m. As such, switch network 710.k provides a switchable current path from current source 222.n to each current steering circuit 224.n and 324.m, and from current source 322.m to each current steering circuit 224.n and 324.m. In addition, switch network 710.k and each current steering circuit 224.n and 324.m together provide multiple switchable current paths from current source 222.n to each DAC output 240 and 340, and from current source 322.m to each DAC output 240 and 340.

[0112] In the first mode of operation, switches 721.k and 727.k are closed, while switches 723.k and 725.k are open. Current source 222.n provides current I to current steering circuit 224.n that excites DAC 203. n , the current source 322.m provides a current I to the current steering circuit 324.m of the feedback DAC 303 m The current steering circuit 224.n can be configured to generate a current according to the digital input signal D X [p] n The value corresponding to the nth bit will be the current I n Either branch 205p / 205n directed to the DAC output 240, as described above with respect to Figure 2B In addition, the current control circuit 324.m can be configured according to the digital input signal D S [q] m The value corresponding to the mth bit will be the current I m Control to DAC output 340, as described above with respect to Figure 3C In a first mode, each DAC 203 and 303 may convert one or more instances of a corresponding digital input signal.

[0113] In the second mode of operation, switches 721.k and 727.k are open, while switches 723.k and 725.k are closed. Current source 322.m provides current I to current steering circuit 224.n of drive DAC 203. m , the current source 222.n provides a current I to the current steering circuit 324.m of the feedback DAC 303 n Therefore, in the second mode, the current steering circuit 224.n is changed to be based on the digital input signal D X [p] n The value corresponding to the nth bit will be the current I m The current steering circuit 324.m is changed to be regulated by the digital input signal D S [q] m The value corresponding to the mth bit will be the current I n Directed to DAC output 340. In a second mode, each DAC 203 and 303 may convert one or more instances of a corresponding digital input signal.

[0114] Although not in Figure 7 , but it should be understood that the states of switches 721.k, 73.k, 725.k and 727.k may be determined by Figure 6 The controller 690 shown in FIG. 1 controls the current source pair 640.k to switch between the first and second operating modes. In addition, it will be understood that the impedance measurement circuit 100 may include a circuit with Figure 7, so as to independently switch each pair of current sources 640.1 to 640.K between the first and second modes, as described with respect to Figure 6 as described.

[0115] Figure 8 Shows Figure 7 Alternative current source switch arrangements. Figure 8 As shown, the switch network 710.k can be replaced by a multiplexer 810.k. The multiplexer includes a first input 820.k coupled to the output of the current source 222.n, a second input 830.k coupled to the output of the current source 322.m, a first output 840.k coupled to the input of the current steering circuit 224.n, and a second output 850.k coupled to the input of the current steering circuit 324.m. The multiplexer 810.k also includes a selection input 860.k configured to receive a control signal "Sk".

[0116] In the first mode (e.g., when Sk=1 or high), the multiplexer 810.k couples the first input 820.k to the first output 840.k and the second input 830.k to the second output 850.k. Thus, in the first mode, the output of the current source 222.n will be routed or coupled to the input of the current control circuit 224.n, and the current source 322.m will be routed or coupled to the input of the current control circuit 324.m. Thus, the current steering circuit 224.n can be configured to control the current of the current control circuit 324.m according to the digital input signal D X [p] n The value corresponding to the nth bit will be the current I n The current steering circuit 324.m can be configured to direct the current to any branch 205p / 205n of the DAC output 240, as described above. In addition, as also described above, the current steering circuit 324.m can be configured to direct the current to any branch 205p / 205n of the DAC output 240 according to the digital input signal D S [q] m The value corresponding to the mth bit will be the current I m Directed DAC output 340.

[0117] In the second mode (e.g., when Sk=0 or low), the multiplexer 810.k couples the first input 820.k to the second output 850.k and the second input 830.k to the first output 840.k. Thus, in the second mode, the output of the current source 222.n will be routed or coupled to the input of the current control circuit 324.m, and the current source 322.m will be routed or coupled to the input of the current control circuit 224.n. Thus, in the second mode, the current steering circuit 224.n is instead controlled according to the digital input signal D X [p] n The corresponding nth bit value will be the current I mThe current steering circuit 324.m is changed to be regulated by the digital input signal D S [q] m The value corresponding to the mth bit will be the current I n Directed to DAC output 340.

[0118] Although not in Figure 8 However, it should be understood that the control signal Sk can be Figure 6 The controller 690 shown in FIG. 1 is provided to switch the current source pair 640.k between the first and second operating modes. In addition, it will be understood that the impedance measurement circuit 100 may include a Figure 8 A total of K multiplexers are similar to the multiplexer 810.k shown in FIG. 8 , so that as described with respect to FIG. Figure 6 Each pair of current sources 640.1 to 640.K is switched between the first and second modes. However, other arrangements are possible. For example, the impedance measurement circuit 100 may alternatively include a multiplexer configured to perform the operations of each of the multiplexers 810.1 and 810.K.

[0119] In most cases, swapping the current sources of the excitation and feedback DACs as described above is sufficient to stabilize the system gain G, taking into account the current source noise and the bias circuit noise. For example, by using the current source 222.n of the excitation DAC in the feedback DAC, the noise of the bias circuit 233 of the bias current source 222.n will have an impact on the feedback DAC and thus affect the full-scale current I of the ADC 315. ADC However, to further control the system gain G, it is still advantageous to swap the bias circuits 233 and 333 of the excitation and feedback DACs independently of their current sources.

[0120] Fig. 9 An example bias switching arrangement for swapping the bias circuit 233 of the excitation DAC 203 and the bias circuit 333 of the feedback DAC 303 is shown, as described above with respect to FIG. Figure 5A and 5B As stated. Fig. 9 As shown, the impedance measurement circuit 100 may include a bias switch network 910 coupled to both the excitation DAC 203 and the feedback DAC 303 .

[0121] Bias switch network 910 includes a plurality of switches 921, 923, 925, and 927. Switch 921 is arranged to switchably couple bias circuit 233 to each of current sources 222.1 to 222.N of excitation DAC 203. Switch 923 is arranged to switchably couple bias circuit 333 to each of current sources 222.1 to 222.N of excitation DAC 203. Switch 925 is arranged to switchably couple bias circuit 333 to each of current sources 322.1 to 322.M of feedback DAC 303. Switch 927 is arranged to switchably couple bias circuit 233 to each of current sources 322.1 to 322.M of feedback DAC 303.

[0122] In a first mode of operation of the bias switch network 910, switches 921 and 925 are closed, while switches 923 and 927 are open. As previously described, bias circuit 233 biases each of current sources 222.1 through 222.N of the excitation DAC 203, and bias circuit 333 biases each of current sources 322.1 through 322.M of the feedback DAC 303. In the first mode, each DAC 203 and 303 can convert one or more instances of a corresponding digital input signal.

[0123] In the second mode of operation, switches 921 and 925 are open, while switches 923 and 927 are closed. Bias circuit 333 now biases each of current sources 222.1 through 222.N of excitation DAC 203, and bias circuit 233 now biases each of current sources 322.1 through 322.M of feedback DAC 303. While in the second mode, each DAC 203 and 303 can convert one or more instances of a corresponding digital input signal.

[0124] Although not in Fig. 9 , but it should be understood that the states of switches 921, 923, 925, and 927 can be controlled by a controller as described above to switch the bias circuit between the first and second operating modes. It should be understood that the impedance measurement circuit 100 may include and incorporate Figures 6 to 8 The current source switching device shown uses Fig. 9 In this case, the controller can be configured to control the operating mode of the bias switch network 910 independently of the operating mode of the current source pairs 610.1 to 610.K. However, in other examples, the impedance measurement circuit 100 can be implemented without the current source switch arrangement. Fig. 9 In other examples, the impedance measurement circuit 100 can implement a current source switch device without a bias switch device.

[0125] In the above examples, the excitation DAC 203 and the feedback DAC 303 are described and illustrated as including their respective bias circuits 233 and 333. However, in some examples, the excitation DAC 203 and the feedback DAC 303 may share the same bias circuit.

[0126] Fig.10 Another example arrangement of the excitation DAC 203 and the feedback DAC 303 of the impedance measurement circuit 100 is illustrated. As shown, the impedance measurement circuit 100 may include a bias circuit 1033 coupled to the power rail 1031. In addition, the bias circuit 1033 is coupled to each current source 222.1 to 222.N of the excitation DAC 203 and each current source 322.1 to 322.M of the feedback DAC 303. Thus, the bias circuit 1033 is configured to bias each of those current sources of the excitation DAC 203 and the feedback DAC 303.

[0127] exist Fig.10 In an example implementation of the arrangement, the bias circuit 1033 may include the above-mentioned Figure 4 The gate terminal of the bias transistor can be coupled to the gate terminal of the MOS transistor in each of the current sources 222.1 to 222.N and 322.1 to 322.M. Therefore, each current source 222.1 to 222.N and 322.1 to 322.M can be biased to output substantially the same current.

[0128] Advantageously, by sharing one bias circuit 1033 between the excitation DAC 203 and the feedback DAC 303, the effect of inherent noise from the bias circuit is significantly reduced compared to each DAC having a bias circuit. This can further improve the stability of the system gain G.

[0129] It should be understood that Fig.10 The bias circuit arrangement can be combined with Figures 6 to 8 Any current source switch arrangement is implemented in the impedance measurement circuit 100. However, for Fig.10 The bias circuit arrangement does not have to be implemented in the impedance measurement circuit 100 Fig. 9 In other examples, Fig.10 The bias circuit arrangement can be implemented in the impedance measurement circuit 100 without the current source switching arrangement, with Figure 2B and 3C This may still result in a more stable system gain G compared to the DAC arrangement.

[0130] In some embodiments of the impedance measurement circuit 100, the sensing circuit 120 may convert the voltage signal V S(t) Demodulate the voltage signal V in the analog domain before converting it into a digital signal for DSP S (t). For example, Fig.11 An alternative sensing circuit 1120 is shown, which includes an input buffer 1101, an analog demodulator 1130, an analog-to-digital converter (ADC) 1115, and a digital signal processor (DSP) 1113. The input buffer 1101 is arranged to receive a voltage signal V S (t) and the voltage signal V S (t) is provided to the demodulator 1130. The demodulator 1130 is configured to demodulate the voltage signal V in the analog domain. S (t) From the voltage signal V S (t) Remove the carrier frequency component F C The demodulator 1130 outputs the corresponding demodulated signal V d (t), which may include -F BIO and +F BIO ADC 1115 is configured to demodulate the voltage signal V d (t) is converted into a digital representation of the demodulated voltage signal, denoted as D d [r] ADC 1115 is arranged to convert the digital signal D d [r] is output to DSP 1113. DSP 1113 is configured to analyze the digital signal D d [q] to detect bioimpedance Z BIO For example, DSP 1113 can be configured to detect the frequency of interest F BIO , as described above.

[0131] exist Fig.11 In an arrangement of , the demodulator 1130 may include a reference DAC for generating a reference voltage. The reference DAC may have a structure similar to the excitation DAC described above. In addition, the excitation DAC 203 and the reference DAC may together exhibit a signal D d The inherent noise characteristics of the amplitude error in [r] and thus the bioimpedance Z BIO Therefore, the techniques described above with respect to the excitation DAC 203 and the feedback DAC 303 can also be applied between the excitation DAC 203 and the reference DAC to proportionally eliminate the digital signal D when using the analog demodulator 1130. d The error in [r].

[0132] Fig.12 A method of operating an impedance measurement circuit including a first DAC and a second DAC according to an example of the present disclosure is shown. In particular, Fig.12 The methods shown in the figure can be understood to be operated using the techniques disclosed herein. Figure 1-11The impedance measurement circuit 100 shown in the method. In some examples, the first DAC can be the excitation DAC 203 and the second DAC can be the feedback DAC 303. In other examples, the second DAC can be Fig.11 The reference DAC shown in .

[0133] At step S1210, the first DAC and the second DAC operate in a first operation mode. In the first mode, the first DAC uses the first hardware circuit element to convert the corresponding digital input signal into an analog output. For example, if the first DAC is the excitation DAC 203, the first DAC uses the first hardware circuit element to convert the digital input signal D X [p] is converted to its analog output I X (t). In addition, in the first mode, the second DAC converts its corresponding digital input signal to its corresponding analog output using the second hardware circuit element. For example, if the second DAC is the feedback DAC 303, the second DAC converts its corresponding digital input signal to its corresponding analog output using the second hardware circuit element. S [q] is converted to its corresponding analog output I F As described above, according to some examples, the first hardware circuit element may be the current source 222.n of the excitation DAC 203, and the second hardware circuit element may be the corresponding current source 322.m of the feedback DAC 303. Alternatively or in addition, the first hardware circuit element may be the bias circuit 233 of the excitation DAC 203, and the second hardware circuit element may be the bias circuit 333 of the feedback DAC 303.

[0134] At step S1220, the first DAC and the second DAC are operated in a second operating mode. In the second mode, the first DAC now uses the second hardware circuit element to convert the corresponding digital input signal to an analog output. For example, if the first DAC is the excitation DAC 203, the first DAC now uses the second hardware circuit element to convert its corresponding digital input signal D X [p] is converted to its analog output I X (t). In addition, in the second mode, the second DAC now uses the first hardware circuit element to convert the corresponding digital input to the corresponding analog output. For example, if the second DAC is the feedback DAC 303, the second DAC now uses the first hardware circuit element to convert its corresponding digital input D S [q] is converted to its corresponding analog output I F (t). In other words, the first hardware circuit element and the second hardware circuit element are effectively swapped between the first DAC and the second DAC.

[0135] It should be understood that according to the present method, any of the above techniques and examples can be used to exchange the first hardware circuit element and the second hardware circuit element. For example, if the first hardware circuit element is a current source first DAC and the second hardware circuit element is a corresponding current source of a feedback DAC, then FIG. 5A to FIG. 8 Alternatively or additionally, if the first hardware circuit element is a bias circuit for a first DAC and the second hardware circuit element is a bias circuit for a second DAC, then a circuit similar to Figure 5A and 5B and Fig. 9 Alternatively, in some examples of the method, the first and second DACs may share a bias circuit, such as with respect to Fig.10 described.

[0136] In some examples, Fig.12 The method shown may also include alternating between the first and second operating modes. In some examples, the method may include alternating between the first mode and the second mode at a predetermined frequency. For example, the predetermined frequency may be equal to the clock frequency of the excitation DAC and the feedback DAC, so that the excitation DAC and the feedback DAC have the same clock frequency (1 / T S =1 / T X ). In such an example, each DAC may convert one instance of the corresponding digital input in each operating mode before changing to the next operating mode. Alternatively, the predetermined frequency may be a frequency lower than the clock frequency of the first DAC and the second DAC to allow multiple instances of the digital input to be converted between changes in operating modes. In such an example, the feedback DAC and the excitation DAC may or may not have equal clock frequencies. In either case, the predetermined frequency may also be a frequency F that is greater than the amplitude error of the system gain G. G More specifically, the predetermined frequency may be a frequency F greater than the amplitude error of the system gain G of the impedance measurement circuit 100. G The first mode and the second mode may be alternated in a predetermined pattern or randomly. The optimal switching frequency and / or switching pattern for proportionally eliminating gain errors may be determined through simulation and test data.

[0137] Further variations and examples

[0138] In the above example, the bioimpedance Z is described BIO can be the thoracic impedance, and the impedance measurement circuit 100 can be used to measure the impedance at low frequency Z BIO=0.3 Hz to measure changes in thoracic impedance. However, it should be understood that the above techniques can be applied to any scenario where an impedance measurement circuit is required to detect and analyze slow changes in impedance. For example, the impedance measurement circuit 100 can be used for lung humidity analysis, impedance tomography for bladder, lung or throat mapping, skin impedance analysis, and / or sweat analysis. In addition, the impedance measurement circuit 100 is used to analyze non-clinical impedance, such as electrical impedance spectroscopy for gas or sample analysis, and for measuring battery health.

[0139] In the above disclosure, preferred examples of ADC 315, feedback DAC 303, excitation DAC 203, and preferred examples of hardware components for exchanging feedback DAC 303 and excitation DAC 203 according to the techniques of the present disclosure are described. However, it should be understood that the techniques of the present disclosure can be used with any type of impedance measurement circuit including an excitation DAC and an ADC including a DAC (e.g., a feedback DAC) having a structure or architecture similar to or corresponding to the excitation DAC.

[0140] For example, it is explained above that ADC 315 is preferably a continuous time sigma delta ADC. In other examples, ADC 315 may be a successive approximation register (SAR) ADC. The SAR ADC may include a DAC, such as a feedback DAC arranged in a feedback loop of the SAR ADC, which is similar in structure or architecture to or corresponds to the excitation DAC 203 described above. As described herein, the hardware circuit elements of the feedback DAC of the SAR ADC may be exchanged with the corresponding hardware circuit elements of the excitation DAC 203.

[0141] In other examples of impedance measurement circuits, the ADC may be a discrete time Sigma-Delta ADC that includes a feedback DAC that is similar or corresponding in structure or architecture to the excitation DAC 203. The hardware circuit elements of the feedback DAC of the discrete time Sigma-Delta ADC may be swapped with corresponding hardware circuit elements of the excitation DAC 203 described herein.

[0142] It is further described above that the feedback DAC 303 and the excitation DAC 203 are preferably current-controlled DACs. In such DACs, the current source and / or bias circuit of the DAC may exhibit inherent noise that causes a systematic gain error, in which case it is preferred to at least swap the current source and / or bias circuit of the feedback DAC 303 with the corresponding current source and / or bias circuit of the excitation DAC 203 to proportionally cancel the systematic gain error.

[0143] In other examples, the feedback DAC 303 and the excitation DAC 203 may include other components that contribute to the system gain error. In some examples, each DAC may include one or more resistors. As a specific example, the DAC may include a resistor network, such as an R-2R ladder network. The resistors in each DAC may also exhibit inherent noise, thereby causing errors in the system gain over time. As such, the techniques disclosed herein may also be used to swap one or more resistors of the feedback DAC 303 with one or more resistors of the excitation DAC 203. For example, referring to Figure 5A and 5B , hardware component 520 may be considered a resistor of the excitation DAC 203. Hardware component 530 may be considered a corresponding resistor of the feedback DAC 303. In a specific example, if a resistor of the excitation DAC 203 is associated with a particular nth bit or cell of the excitation DAC 203, a resistor of the feedback DAC may be associated with a corresponding mth bit or cell of the feedback DAC 303.

[0144] In other examples, each DAC may include one or more capacitors. As a specific example, a DAC may include a capacitor network, such as a switched capacitor network. The capacitors in each DAC may also exhibit inherent noise and thus cause time-varying errors in the system gain, or benefit from swapping. Thus, the techniques disclosed herein may also be used to swap one or more capacitors of the feedback DAC 303 with one or more capacitors of the excitation DAC. For example, referring to Figure 5A and 5B As discussed above, hardware component 520 may be a capacitor of excitation DAC 203. Hardware component 530 may be a corresponding capacitor of feedback DAC 303. In a particular example, if the capacitor of excitation DAC 203 is associated with a particular nth bit or cell of excitation DAC 203, the capacitor of feedback DAC may be associated with a corresponding mth bit or cell of feedback DAC 303.

[0145] As can be seen from the above, hardware component 520 can be any hardware component of the excitation DAC 203 (e.g., a resistor, a capacitor, a current source, or a bias circuit), and hardware component 530 can be any corresponding hardware component of the feedback DAC (e.g., a resistor, a capacitor, a current source, or a bias circuit) that can benefit from exchange using the techniques described herein.

Claims

1. An impedance measuring device, comprising: a first hardware circuit element and a second hardware circuit element; a first DAC arranged to convert a first digital input into a first output signal using said first or second hardware circuit element; and a second DAC arranged to convert a second digital input into a second output signal using said first or second hardware circuit element, The device is configured to operate in the following situations: a first mode in which the first DAC converts the first digital input using the first hardware circuit element and the second DAC converts the second digital input using the second hardware circuit element, and a second mode wherein the first DAC converts the first digital input using the second hardware circuit element and the second DAC converts the second digital input using the first hardware circuit element.

2. The apparatus of claim 1, wherein the apparatus is configured to alternate between the first mode and the second mode.

3. The apparatus of claim 2, wherein the apparatus is configured to alternate between the first mode and the second mode independently of the first and second digital inputs.

4. The apparatus of claim 3, wherein the apparatus is configured to alternate between the first and second modes randomly or in a predetermined pattern.

5. The apparatus of claim 1, wherein the first hardware circuit element and the second hardware circuit element are of the same type.

6. The apparatus of claim 1, wherein the first hardware circuit element is a first current source and the second hardware circuit element is a second current source.

7. The apparatus of claim 6, wherein the first DAC is configured to steer current from the first or second current source to a first DAC output depending on the first digital input, and wherein the second DAC is configured to steer current from the first or second current source to a second DAC output depending on the second digital input.

8. The apparatus of claim 6, further comprising a plurality of switchable paths arranged to: in the first mode, supply current from the first current source to the first DAC and from the second current source to the second DAC; and in the second mode, supply current from the second current source to the first DAC and from the first current source to the second DAC.

9. The apparatus of claim 6, further comprising a bias circuit configured to bias the first and second current sources.

10. The device according to claim 1, The first hardware circuit element is a first bias circuit, arranged to bias a first current source of the first DAC or a second current source of the second DAC; and the second hardware circuit element is a second bias circuit, arranged to bias the first current source or the second current source.

11. The apparatus of claim 10, wherein the apparatus is configured such that: In the first mode, the first bias circuit biases the first current source and the second bias circuit biases the second current source; and In the second mode, the first bias circuit biases the second current source and the second bias circuit biases the first current source.

12. The apparatus of claim 1, further comprising: An excitation circuit, used for outputting an excitation signal to the measured impedance, the excitation circuit comprising a first DAC; and A sensing circuit is arranged to sense a signal across the impedance, the sensing circuit comprising a second DAC.

13. A method for scaling gain error in an impedance measurement device having a first DAC and a second DAC, comprising: operating a first DAC and a second DAC in a first mode, wherein the first DAC converts a first digital input into a corresponding first output signal using a first hardware circuit element, and the second DAC converts a second digital input into a second output signal using a second hardware circuit element; The first DAC and the second DAC are operated in a second mode, wherein the first DAC converts a first digital input to a corresponding first output signal using the second hardware circuit element, and the second DAC converts a second digital input to a second output signal using the first hardware circuit element.

14. The method of claim 13, further comprising alternating between first and second operating modes.

15. The method of claim 14, wherein the first and second modes are alternated independently of a digital input.

16. The method of claim 13, comprising alternating between the first and second modes randomly or in a predetermined pattern.

17. The method of claim 13, wherein the first hardware circuit element is a first current source and the second hardware circuit element is a second current source, and wherein: in the first mode, the first DAC converts the first digital input by directing current from a first current source to a first DAC output dependent on the first digital input, and the second DAC converts the second digital input by directing current from the second current source to a second DAC output dependent on the second digital input; and In the second mode, the first DAC converts the first digital input by directing current from a second current source to a first DAC output depending on the first digital input, and the second DAC converts the second digital input by directing current from the first current source to a second DAC output depending on the second digital input.

18. The method of claim 13, wherein the first hardware circuit element is a first bias circuit and the second hardware circuit element is a second bias circuit, wherein: In the first mode, the first DAC converts the first digital input using a current source biased by the first bias circuit, and the second DAC converts the second digital input using a current source biased by the second bias circuit; and In the second mode, the first DAC converts the first digital input using a current source biased by the second bias circuit, and the second DAC converts the second digital input using a current source biased by the first bias circuit.

19. The method of claim 13, wherein the first DAC is included in an excitation circuit for outputting an excitation signal to a bio-impedance, and the second DAC is included in a sensing circuit arranged to sense a signal across the bio-impedance.

20. An impedance measuring device, comprising: a first DAC comprising a first output, wherein the first DAC is configured to convert a first digital input into a first output signal by directing current from a first current source to the first output based on a first digital input; a second DAC comprising a second output, wherein the second DAC is configured to convert the second digital input into a second output signal by directing current from a second current source to the second output based on the second digital input; and A bias circuit is configured to bias the first and second current sources.

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