Silicon photonic interposer with two metal redistribution layers

Abstract

A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes: a first conductive trace located on a top surface of the silicon integrated circuit; a dielectric layer located on the first conductive trace; and a second conductive trace located on the dielectric layer and connected to the first conductive trace through a first via.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 858,894, filed on June 7, 2019, entitled “SILICON PHOTONIC INTERPOSER WITH TWO METAL REDISTRIBUTION LAYERS,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more aspects of embodiments according to the present disclosure relate to silicon photonic packaging, and more particularly, to a silicon photonic interposer having two redistribution metal layers. Background Art

[0004] In a package that combines a photonic integrated circuit with one or more electronic integrated circuits, it may be advantageous for the photonic integrated circuit to provide some electrical signal routing and for the photonic integrated circuit to provide under-bump metallization capture pads to capture solder bumps for electrical connection to the electronic integrated circuit or package (e.g., a fan-out wafer-level package that may contain one or more electronic integrated circuits).

[0005] Therefore, there is a need for an improved system for forming metallic features on the top surface of a photonic integrated circuit. Summary of the invention

[0006] According to an embodiment of the present invention, a silicon integrated circuit is provided, comprising: a first conductive trace located on a top surface of the silicon integrated circuit; a dielectric layer located on the first conductive trace; and a second conductive trace located on the dielectric layer and connected to the first conductive trace through a first through hole.

[0007] In some embodiments, the silicon integrated circuit further includes an under bump metallization capture pad located on the first conductive trace and connected to the first conductive trace through a second via.

[0008] In some embodiments, the under bump metallization capture pad includes: a nickel layer and a gold layer on the nickel layer.

[0009] In some embodiments, the silicon integrated circuit further includes a wire bond pad located on the first conductive trace and connected to the first conductive trace through the second via.

[0010] In some implementations, the first conductive trace is composed of a material selected from the group consisting of: gold, aluminum, copper, and alloys, and combinations thereof.

[0011] In some implementations, the second conductive trace is composed of a material selected from the group consisting of gold, aluminum, copper, titanium, tungsten, tantalum, and alloys, and combinations thereof.

[0012] In some embodiments, the second conductive trace further includes a titanium tungsten layer.

[0013] In some implementations, the dielectric layer is composed of a material selected from the group consisting of silicon oxide, silicon nitride, benzocyclobutene, polyimide, and combinations thereof.

[0014] In some embodiments, the dielectric layer is composed of silicon nitride.

[0015] According to an embodiment of the present invention, a method for manufacturing a silicon integrated circuit is provided, the method comprising: manufacturing a first intermediate product, comprising: a silicon substrate, a first conductive layer on the silicon substrate, and a dielectric layer on the first conductive layer; etching a first opening and a second opening into the dielectric layer and onto the first conductive layer; forming a second conductive layer on the dielectric layer and on the first conductive layer in the first opening and the second opening; and removing a portion of the second conductive layer in an area including the second opening and an area surrounding the second opening.

[0016] In some embodiments, the method further includes forming a wire bond pad on the first conductive layer in the second opening.

[0017] In some embodiments, the method further includes: forming an under bump metallization capture pad on the first conductive layer in the second opening and an area surrounding the second opening; and removing a remaining portion of the second conductive layer in an area surrounding the under bump metallization capture pad.

[0018] In some embodiments, the under bump metallization capture pad includes: a nickel layer and a gold layer on the nickel layer.

[0019] In some embodiments, the first conductive layer is composed of a material selected from the group consisting of aluminum, copper, gold, and alloys, and combinations thereof.

[0020] In some embodiments, the second conductive layer includes a layer of a material selected from the group consisting of gold, copper, aluminum, and alloys, and combinations thereof.

[0021] In some embodiments, the second conductive layer further includes a layer of a material selected from the group consisting of titanium, tungsten, tantalum, and alloys, and combinations thereof.

[0022] In some implementations, the dielectric layer is composed of a material selected from the group consisting of silicon oxide, silicon nitride, benzocyclobutene, polyimide, and combinations thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] These and other features and advantages of the present disclosure will be understood and appreciated with reference to the specification, claims and drawings, in which:

[0024] Figure 1A is a side view of a portion of a package according to an embodiment of the present disclosure;

[0025] Figure 1B is a side view of a portion of a photonic integrated circuit according to an embodiment of the present disclosure;

[0026] Figure 1C According to the embodiment of the present disclosure Figure 1B A top view of a portion of the package shown in ;

[0027] Figure 2A is a side view of an intermediate product according to an embodiment of the present disclosure;

[0028] Figure 2B According to the embodiment of the present disclosure Figure 2A A top view of the intermediate product;

[0029] Figure 3A is a side view of an intermediate product according to an embodiment of the present disclosure;

[0030] Figure 3B According to the embodiment of the present disclosure Figure 3A A top view of the intermediate product;

[0031] Figure 4A is a side view of an intermediate product according to an embodiment of the present disclosure;

[0032] Figure 4B According to the embodiment of the present disclosure Figure 4A A top view of the intermediate product;

[0033] Figure 5A is a side view of an intermediate product according to an embodiment of the present disclosure;

[0034] Figure 5B According to the embodiment of the present disclosure Figure 5A A top view of the intermediate product;

[0035] Fig. 6A is a side view of an intermediate product according to an embodiment of the present disclosure;

[0036] Figure 6B According to the embodiment of the present disclosure Fig. 6A A top view of the intermediate product;

[0037] Fig. 7A is a side view of an intermediate product according to an embodiment of the present disclosure;

[0038] Figure 7BAccording to the embodiment of the present disclosure Fig. 7A A top view of the intermediate product;

[0039] Fig. 8A is a side view of an intermediate product according to an embodiment of the present disclosure;

[0040] Figure 8B According to the embodiment of the present disclosure Fig. 8A A top view of the intermediate product;

[0041] Fig. 9A is a side view of a portion of a photonic integrated circuit according to an embodiment of the present disclosure;

[0042] Fig. 9B is a side view of a portion of a photonic integrated circuit according to an embodiment of the present disclosure;

[0043] Fig.10 is a top view of a portion of a photonic integrated circuit according to an embodiment of the present disclosure; and

[0044] Fig.11 is a side view of a portion of a photonic integrated circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of an exemplary embodiment of a silicon photonic interposer with two metal redistribution layers provided in accordance with the present disclosure, and is not intended to represent the only form in which the present disclosure may be constructed or utilized. The description sets forth features of the present disclosure in conjunction with the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures may be implemented by different embodiments, which are also intended to be included within the scope of the present disclosure. As indicated elsewhere herein, similar element numbers are intended to indicate similar elements or features.

[0046] Figure 1AApplications of some embodiments are shown: conductors on a photonic integrated circuit (PIC) 104 are used to form a connection between a fan-out wafer-level package 100 and an electro-optical device 101 (or "electro-optical chip") such as a modulator, a laser, or a photodetector. The photonic integrated circuit 104 can be used to support and connect the fan-out wafer-level package and one or more electro-optical chips, for example, by providing an under-bump metallization capture pad to capture the solder bumps 103 on the fan-out wafer-level package 100. The photonic integrated circuit 104 can also provide an interface between one or more optical fibers and one or more electro-optical chips. This interface may include a V-groove for aligning the optical fiber with a waveguide on the photonic integrated circuit, a mode converter for converting the mode shape of the optical fiber to a mode shape suitable for interacting with the electro-optical chip, and a waveguide for guiding light between the optical fiber and the electro-optical chip (which may include a segment operating as a mode converter, such as a tapered segment). The photonic integrated circuit can be manufactured on a silicon substrate (e.g., a silicon-on-insulator (SOI) substrate), that is, it can be a silicon integrated circuit. The surface of a photonic integrated circuit on which fine features, such as waveguides and conductive traces (as described herein), are fabricated may be referred to as the "top surface" of the photonic integrated circuit.

[0047] Figure 1A and Figure 1B1 , a structure according to some embodiments is shown. The first conductive trace 105 (e.g., a conductive trace composed of aluminum, copper, gold, or other suitable metal) can be part of a first metal layer, which can be referred to as a first RDL conductive layer (wherein RDL is an abbreviation for a redistribution layer). The dielectric layer 110 can be formed on the first metal layer, that is, on the first conductive trace 105, and a layer that can be referred to as a UBM1 layer forming the second conductive trace 115 can be formed on the dielectric layer 110. The UBM1 layer can be an integrated layer including (i) a second RDL conductive layer and (ii) an under bump metallization (UBM) layer. For example, the UBM1 layer can be a composite layer composed of sublayers, the sublayers including a first barrier layer 116 (e.g., a first TiW layer) on the dielectric layer 110, a conductive metal layer (e.g., a first gold layer) on the first barrier layer, a second barrier layer (e.g., a second TiW layer) on the conductive metal layer, and a solder adhesion metal layer (e.g., a second gold layer) on the second barrier layer. For ease of illustration, the four layers of the UBM1 layer 115 are shown in FIG. 1 as two layers: a first barrier layer 116, and on the first barrier layer 116, a composite "upper layer" 117, the composite upper layer comprising a conductive metal layer, a second barrier layer, and a solder adhesion metal layer. Within the UBM1 layer, the first barrier layer and the conductive metal layer can together form a second RDL conductive layer, and the second barrier layer and the solder adhesion metal layer can together form a UBM layer. In some embodiments, the structure includes multiple metal layers, such as the first metal layer described above, each metal layer including one or more conductive traces. These layers can be formed, for example, by alternating deposition steps of dielectrics and metals, and the traces therein can be interconnected at vias.

[0048] The UBM1 layer may extend into the cavity 102 (see FIG. 2A to FIG. 8B); in the cavity, the UBM layer within the UBM1 layer (e.g., the upper two sublayers of the UBM1 layer) can act as an under-bump metallization layer for attaching an electro-optical chip (e.g., using gold-tin solder, as discussed in further detail below). As used herein, an "under-bump metallization" layer or "under-bump metallization" layer or "UBM" layer is a layer (a "simple" layer composed of a single material, or a "composite" layer composed of multiple simple layers of different materials) having the following characteristics: (i) having an upper surface suitable for forming a solder joint (a "solder adhesion" surface), and (ii) being or including a barrier layer for preventing solder (or other materials in the UBM layer) from diffusing into the surface forming the UBM layer. The UBM layer of the UBM1 layer (which, as described above, can be a composite layer including a TiW layer and a gold layer) can be used as a barrier and adhesion layer for subsequent back-end processing (e.g., for soldering the electro-optical chip to the UBM1 layer). As described above, the TiW layer of the UBM layer of the UBM1 layer can be used as a diffusion barrier; it can prevent Au from mixing with or diffusing into the Al pad or silicon in the PIC. In some embodiments, materials other than TiW can be used in one or more barrier layers, for example, Pt, Cr, Ni, NiV, Ti, or W can be used instead of TiW. In some embodiments, the UBM layer or UBM1 layer can be composed of any other combination of materials known in the art for under bump metallization (e.g., nickel and gold, or nickel, palladium, and gold).

[0049] The second conductive trace 115 can be connected to the first conductive trace 105 at the first via 120 (formed as an opening in the dielectric layer 110 where the second conductive trace 115 can contact the first conductive trace 105). An under bump metallization capture pad 125 (e.g., a pad including a nickel layer and a gold layer on the nickel layer) can also be formed on the dielectric layer 110 and extend through the dielectric layer 110 at the second via 130 to contact the first conductive trace 105.

[0050] The UBM capture pad 125 may be surrounded by a dielectric layer 110, which may be used to passivate the underlying metal layer and prevent solder from wetting the area around the capture pad. For example, if the UBM capture pad 125 is used to capture solder bumps on a fan-out wafer level package, the dielectric layer 110 may prevent solder from the solder bump from diffusing outside the UBM capture pad 125, just as if the UBM capture pad 125 were surrounded by a material wettable by solder (e.g., gold) instead of being surrounded by the dielectric layer 110 (which is not wettable by solder).

[0051] FIG. 2A to FIG. 8B In some embodiments, a method for manufacturing and Figure 1B and Figure 1CSimilar structure of the process (intermediate products and final products). Figure 2A and Figure 2B A structure that can be produced by a front-end-of-line (FEOL) process using an SOI wafer is shown. The structure includes a cavity 102 for an electro-optical chip extending below a buried oxide (BOX) layer 116, a dielectric cladding layer 110, and a first metal layer in the dielectric cladding layer (forming, for example, conductive traces, including first conductive trace 105). Some or all of the conductive traces of the first metal layer may have a Figure 8B , where two circular portions 135 forming the first and second vias 120 and 130 are connected by a narrower conductive strip 140. The dielectric cladding layer may be composed of any suitable dielectric such as silicon oxide, silicon nitride, benzocyclobutene (BCB), or polyimide.

[0052] Figure 3A and Figure 3B An intermediate structure is shown formed after a pad opening etch to expose the rounded portion 135 (or "pad") of the dogbone. Narrower conductive strips 140 may be beneath the dielectric cladding, isolating the pad. Fabricating the dogbone structure in the FEOL can significantly simplify the back-end of line (BEOL) process flow.

[0053] Figure 4A and Figure 4B The intermediate structure after the deposition of the UBM1 layer is shown. As described above, the UBM1 metal stack can be used as a barrier and adhesion layer for subsequent back-end processing, as well as as a second RDL conductive layer. Figure 4A and Figure 4B In the example, UBM 1115 covers two Al pads 135 .

[0054] Figure 5A and Figure 5B The intermediate structure is shown after portions of the UBM1 layer are removed to define conductive traces for forming connections to the electro-optical chip and for forming mesas 142. Each mesa 142 can be formed by etching away the two top sublayers of the UBM1 layer in the area surrounding the mesa 142, and each mesa 142 can be used to reduce the tendency of solder used to attach the electro-optical chip to flow into the conductive trace area around the mesa. The Au / TiW metal trace 115 makes electrical contact with the Al dog bone at the first via 120. In the area including the opening where the second via 130 will be formed, an etch referred to as the "SB_UBM" etch removes all layers of the UBM1 layer except the first barrier layer 116 to expose the first barrier layer (e.g., the first TiW layer), which still serves as a seed layer for the Ni and Au plating of the pad. For ease of illustration, the mesas 142 are shown in Figure 5A Not shown.

[0055] Fig. 6A and Figure 6B The intermediate structure formed after patterning the photoresist to design the Ni / Au pad, electroplating nickel and electroplating Au on the nickel, and stripping the photoresist is shown. The nickel and gold (Au) layers form a second under bump metallization layer (UBM2), which serves as an under bump metallization capture pad 125 (formed on the second through hole 130), which is suitable for forming a Sn Ag Cu (SAC) solder joint with a SAC solder bump that may be present on the surface of a fan-out wafer-level package.

[0056] Fig. 7A and Figure 7B An intermediate structure is shown after etching away the TiW seed layer between the pads of the dog-bone, thereby isolating the pads of the dog-bone. Fig. 8A and Figure 8B The structure formed is shown after deposition and patterning of AuSn pads 145. Each such AuSn pad 145 can be used to solder a terminal of an electro-optical chip to a corresponding second conductive trace 115.

[0057] Two different methods can be used ( Fig. 7A and Figure 7B )TiW etching. Fig. 9A Results are shown for a method in which photoresist is used to offset the TiW pattern layer so that after etching it extends beyond the pad. Fig. 9B Results are shown for another approach involving the use of a blanket wet etch without a photoresist mask, relying on BEOL structures (eg, structures formed prior to this etch) to mask and define the TiW seed layer during the wet etch. Fig.10 A top view showing the high-speed metal trace and pad design.

[0058] In some embodiments, each connection from the fan-out wafer level package can be made by wire bonding to a wire bonding pad on the second via 130 (rather than by solder joints to the under bump metallization capture pad 125). In such an embodiment, the structure of the pad can be made from, for example Fig. 6A and Figure 6B The structure of the under bump metallization capture pad 125 shown above is modified accordingly. For example, the wire bond pad may be just a gold layer on a suitable barrier layer (eg, TiW), or it may be part of the UBM1 layer.

[0059] Fig.11 Shows something like Figure 1BIn some embodiments, the under bump metallization capture pad 125 includes a copper pillar bump, including, for example, a copper pillar 150, a nickel layer 155 on the copper pillar 150, and a tin-silver solder bump 160 on the nickel layer 155. In some embodiments, the first barrier layer 116 is present (as shown); in some embodiments, the first barrier layer is not present.

[0060] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited to these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the spirit and scope of the present invention, the first element, component, region, layer or section discussed herein may be referred to as a second element, component, region, layer or section.

[0061] For ease of description herein, spatial relative terms (e.g., "below," "below," "lower," "lower," "above," "upper," etc.) may be used to describe the relationship between an element or feature and another element or feature as shown in the figure. It should be understood that such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure flips, the element described as being "below" or "below" or "lower" of other elements or features will be oriented to be "above" other elements or features. Therefore, the exemplary terms "below" and "lower" may include both the orientation of the upper and lower parts. The device may be oriented in addition (e.g., rotated 90 degrees or other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intermediate layers may also be present.

[0062] The terms used herein are only for describing specific embodiments and are not intended to limit the concepts of the present invention. As used herein, the terms "substantially", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to illustrate the inherent deviations in measured or calculated values ​​that will be recognized by those of ordinary skill in the art. As used herein, the term "major component" refers to a component present in a composition, polymer or product in an amount greater than any other single component in the composition or product. In contrast, the term "significant component" refers to a component that constitutes at least 50% by weight or more of a composition, polymer or product. As used herein, the term "significant portion" refers to at least half of an item when applied to multiple items. As used herein, any structure or layer described as "made of a substance" or "consisting of a substance" should be understood to include (i) in some embodiments, the substance as a major component, or (ii) in some embodiments, the substance as a significant component. As used herein, an element "consisting of" a material does not need to have a uniform composition; for example, a conductive trace comprising a gold layer on a titanium tungsten layer can be considered to be "consisting of" a combination of gold, titanium and tungsten.

[0063] As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprises" and / or "comprising" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. For example, the expression "at least one of..." before the element list will modify the entire element list without modifying the individual elements in the list. In addition, the use of "may" when describing the implementation of the inventive concept refers to "one or more embodiments of the present disclosure". In addition, the term "exemplary" is intended to refer to an example or illustration. As used herein, the terms "use", "using" and "used" can be considered to be synonymous with the terms "utilize", "utilizing" and "utilized", respectively.

[0064] It should be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0065] As used herein, the word "or" is inclusive, thus, for example, "A or B" means any of (i) A, (ii) B, and (iii) A and B. As used herein, "a portion of" something means all or less than all of that thing. Thus, for example, "a portion of a layer" means all or less than all of the layer.

[0066] Any numerical range recited herein is intended to include all subranges of the same numerical precision contained within the recited range. For example, a range of "1.0 to 10.0" is intended to include all subranges between the cited minimum value 1.0 and the cited maximum value 10.0 (including 1.0 and 10.0), i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit recited herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit recited in this specification is intended to include all higher numerical limits contained therein.

[0067] Although exemplary embodiments of a silicon photonic interposer with two metal redistribution layers have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that a silicon photonic interposer with two metal redistribution layers constructed according to the principles of the present disclosure may be implemented otherwise than as specifically described herein. The present invention is also defined by the following claims and their equivalents.

Claims

1. A silicon integrated circuit comprising: a first conductive trace located on a top surface of the silicon integrated circuit; a dielectric layer disposed on the first conductive trace; a second conductive trace layer including a conductive metal layer disposed on the dielectric layer and connected to the first conductive trace through a first via; An under bump metallization (UBM) layer includes a barrier layer on the conductive metal layer and a solder adhesion metal layer on the barrier layer.

2. The silicon integrated circuit of claim 1 further comprising an under bump metallization capture pad located on the first conductive trace and connected to the first conductive trace through a second via.

3. The silicon integrated circuit of claim 2, wherein the under bump metallization capture pad comprises: Nickel layer, and A gold layer on the nickel layer.

4. The silicon integrated circuit of claim 1 further comprising a wire bond pad on the first conductive trace and connected to the first conductive trace through a second via.

5. The silicon integrated circuit of any one of the preceding claims, wherein the first conductive trace is composed of a material selected from the group consisting of: Gold, aluminum, copper and alloys and combinations thereof.

6. The silicon integrated circuit of any one of claims 1 to 4, wherein the second conductive trace layer is composed of a material selected from the group consisting of: Gold, aluminum, copper, titanium, tungsten, tantalum and alloys and combinations thereof.

7. The silicon integrated circuit of claim 6 wherein the second conductive trace layer further comprises a titanium tungsten layer.

8. The silicon integrated circuit of any one of claims 1 to 4, wherein the dielectric layer is composed of a material selected from the group consisting of: Silicon oxide, silicon nitride, benzocyclobutene, polyimide, and combinations thereof.

9. A silicon integrated circuit as claimed in any one of claims 1 to 4, wherein the dielectric layer consists of silicon nitride.

10. A method for manufacturing a silicon integrated circuit, the method comprising: Producing a first intermediate product, comprising: Silicon substrate, a first conductive layer located on the silicon substrate, and a dielectric layer disposed on the first conductive trace; etching a first opening and a second opening into the dielectric layer and onto the first conductive layer; forming a second conductive layer on the dielectric layer and on the first conductive layer in the first opening and the second opening; and A portion of the second conductive layer is removed in a region including the second opening and a region surrounding the second opening. 11 . The method of claim 10 , further comprising forming a wire bonding pad on the first conductive layer in the second opening.

12. The method of claim 10, further comprising: An under bump metallization capture pad is formed on: the first conductive layer in the second opening, and an area surrounding the second opening; as well as A remaining portion of the second conductive layer is removed in an area surrounding the under bump metallization capture pad.

13. The method of claim 12, wherein the under bump metallization capture pad comprises: Nickel layer, and A gold layer on the nickel layer.

14. The method of any one of claims 10 to 13, wherein the first conductive layer is composed of a material selected from the group consisting of: Aluminum, copper, gold and alloys and combinations thereof.

15. The method of any one of claims 10 to 13, wherein the second conductive layer comprises a layer of a material selected from the group consisting of: gold, copper, aluminum, and alloys, and combinations thereof.

16. The method of claim 15, wherein the second conductive layer further comprises a layer of a material selected from the group consisting of: titanium, tungsten, tantalum, and alloys, and combinations thereof.

17. The method of any one of claims 10 to 13, wherein the dielectric layer is composed of a material selected from the group consisting of: Silicon oxide, silicon nitride, benzocyclobutene, polyimide, and combinations thereof.

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