Instruction Stream Consistency Test Method

Abstract

The invention discloses an instruction stream consistency test method, S1, initializing various parameters; S2, reading in command line parameters; S3, setting the size of the shared space, applying for a shared executable space; S4, forking the process, and binding the process to different cores; S5, entering the instruction cache test entry module, initializing an array composed of random numbers, and adding prefix instructions; S6, entering the automatic test module; S7, entering the execution instruction module; S8, the execution instruction module runs to the end, and enters the end test module; S9, in the end test module, judging whether it exceeds the set execution number, if it exceeds, performing result verification, if it does not exceed, entering the automatic test module again; S10, after the test is finished, reporting the test result and recycling the process, and then exiting and ending. The invention solves the problem of difficult instruction cache consistency verification.

Description

Technical Field

[0001] The invention relates to an instruction stream consistency testing method, and belongs to the field of functional correctness verification of domestic processors. Background Art

[0002] On the same CPU or different CPUs, when some cores load instructions and other cores execute the loaded instructions, the consistency of the instruction stream will be generated. This often happens in the scenario of JAVA interpretation and execution. In the chip design stage, due to the slow speed of the simulation environment, using JAVA programs to verify the consistency of the instruction stream is not only inefficient, but also difficult to find errors. In cache consistency verification, the consistency verification of data cache is common, and the consistency verification of instruction cache is rare. At present, the number of CPU cores is increasing, and the verification of instruction cache is also indispensable. Summary of the invention

[0003] The purpose of the present invention is to provide an instruction stream consistency testing method to solve the problem of difficulty in instruction cache consistency verification.

[0004] To achieve the above object, the technical solution adopted by the present invention is: to provide an instruction stream consistency testing method, comprising the following steps:

[0005] S1. Initialize various parameters, including the total number of executions, the number of verifications, the number of verification failures, and the initial values ​​of global variables. In the following steps, change the parameters and assign new values;

[0006] S2, read the command line parameters, including the number of CPUs and the bitmap of the cores of each CPU;

[0007] S3. Set the size of the shared space and apply for the shared executable space;

[0008] S4, Fork process and bind the process to different cores;

[0009] S5, enter the instruction cache test entry module, initialize the array composed of random numbers, and add prefix instructions;

[0010] S6, enter the automatic test module, first initialize the register area and the memory area, then fill the random instruction sequence into the executable space according to the instruction template, and after the random instruction sequence is loaded, jump to the execution instruction module;

[0011] S7, entering the execution instruction module, first loading the values ​​of the integer register, the floating point register and the floating point control register, and then executing the loaded random instruction sequence;

[0012] The last few instructions of the random instruction sequence are loaded as return instructions, so that after the random instruction sequence is executed, it returns to the execution instruction module;

[0013] S8, the execution instruction module is finished, and the automatic test module is returned, and then the instruction cache test entry module is returned, and the end test module is entered;

[0014] S9, in the end test module, determine whether the number of automatic test passes exceeds the set execution number, if it exceeds, perform result verification, if not, enter the automatic test module again;

[0015] S10. After the test is finished, report the test results and recycle the process, then exit and end.

[0016] The further improved scheme in the above technical scheme is as follows:

[0017] 1. In the above scheme, S9 verifies the result by comparing the value in the shared space after execution of each core with the register value.

[0018] 2. In the above scheme, in S6, the instruction loading method includes: the even-numbered processes are loaded and all the processes are executed together; the odd-numbered processes are loaded and the even-numbered processes are executed; some processes are loaded and all the processes are executed together; half of the processes are loaded and half of the processes are executed.

[0019] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0020] The present invention designs a framework for instruction stream consistency testing. By constructing a model for instruction stream consistency verification, it supports multiple instruction block loading methods and flexibly controls the scenarios of instruction stream consistency testing. It can enhance the verification of instruction stream consistency before tape-out and ensure the correctness of chip functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Attached Figure 1 A schematic diagram of an instruction stream consistency testing method of the present invention. DETAILED DESCRIPTION

[0022] Embodiment: The present invention provides an instruction stream consistency testing method, which specifically comprises the following steps:

[0023] S1. Initialize various parameters, including the initial values ​​of global variables such as the total number of execution passes, the number of verifications, the number of verification failures, and the number of instructions. In the following steps, change the parameters and assign new values;

[0024] S2, read the command line parameters, including the number of CPUs, the bitmap of each CPU core, etc.;

[0025] S3. Set the size of the shared space and apply for the shared executable space;

[0026] S4, Fork the process and bind the process to different cores, laying the foundation for implementing different loading methods for different cores of one or more CPUs;

[0027] S5, enter the instruction cache test entry module, initialize the array composed of random numbers, and add prefix instructions;

[0028] S6, enter the automatic test module, first initialize the register area and the memory area, then fill the random instruction sequence into the executable space according to the instruction template, and after the random instruction sequence is loaded, jump to the execution instruction module;

[0029] S7, entering the execution instruction module, first loading the values ​​of the integer register, the floating point register and the floating point control register, and then executing the loaded random instruction sequence;

[0030] The last few instructions of the random instruction sequence are loaded as return instructions, so that after the random instruction sequence is executed, it returns to the execution instruction module;

[0031] S8, the execution instruction module is finished, and the automatic test module is returned, and then the instruction cache test entry module is returned, and the end test module is entered;

[0032] S9, in the end test module, determine whether the number of automatic test passes exceeds the set execution number, if it exceeds, perform result verification, if not, enter the automatic test module again;

[0033] S10. After the test is finished, report the test results and recycle the process, then exit and end.

[0034] In S9, the result is verified by comparing the value in the shared space after execution of each core with the register value.

[0035] In S6, the instruction loading method is customized by the programmer, including: loading even-numbered processes, all processes are executed together; loading odd-numbered processes, even-numbered processes are executed; loading some processes, all processes are executed together; loading half of the processes, and half of the processes are executed.

[0036] The further explanation of the above embodiment is as follows:

[0037] The instruction sequence formed by the present invention is random, and the operation of commonly used registers is difficult to predict, so that the test verification can cover more practical application scenarios. The random instruction sequence is used to fill the instruction cache, and through process binding, some cores write instruction streams on the same CPU and different CPUs, and other cores (which can be the same as the written core number or different) execute the written instructions, thereby achieving the purpose of instruction stream consistency testing.

[0038] The present invention is mainly divided into five parts, the details of which are as follows:

[0039] 1. Initialize the shared executable space, set various parameters, and generate instruction templates using the instruction format;

[0040] 2. Through process binding, different core combinations and loading methods can be realized on the same CPU and different CPUs. Different random instruction sequences are formed by automatically generating random numbers and instruction templates, and the instruction sequences are loaded into the executable space;

[0041] 3. Load commonly used registers and back up the register values ​​so that the registers can be restored after the program ends to restore the system status;

[0042] 4. Enter the instruction execution port and set different core combinations to execute the loaded instruction sequence;

[0043] 5. After the instruction sequence is executed, the commonly used register values ​​are loaded into the shared memory space. Different cores can repeatedly load the shared space. The values ​​in the shared memory space after execution of each core are compared with the register values ​​to verify the consistency of the instruction stream.

[0044] When using the above-mentioned instruction stream consistency test method, a framework for instruction stream consistency testing is designed. By constructing a model for instruction stream consistency verification, it supports multiple instruction block loading methods and flexibly controls the instruction stream consistency test scenarios. It can enhance the verification of instruction stream consistency before tape-out and ensure the correctness of chip functions.

[0045] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for testing consistency of instruction stream, characterized in that: The following steps are involved: S1. Initialize various parameters, including the total number of executions, the number of verifications, the number of verification failures, and the initial values ​​of global variables. In the following steps, change the parameters and assign new values; S2, read the command line parameters, including the number of CPUs and the bitmap of the cores of each CPU; S3. Set the size of the shared space and apply for the shared executable space; S4, Fork process and bind the process to different cores; S5, enter the instruction cache test entry module, initialize the array composed of random numbers, and add prefix instructions; S6, enter the automatic test module, first initialize the register area and the memory area, then fill the random instruction sequence into the executable space according to the instruction template, and after the random instruction sequence is loaded, jump to the execution instruction module; S7, entering the execution instruction module, first loading the values ​​of the integer register, the floating point register and the floating point control register, and then executing the loaded random instruction sequence; The last few instructions of the random instruction sequence are loaded as return instructions, so that after the random instruction sequence is executed, it returns to the execution instruction module; S8, the execution instruction module is finished, and the automatic test module is returned, and then the instruction cache test entry module is returned, and the end test module is entered; S9, in the end test module, determine whether the number of automatic test passes exceeds the set number of execution passes, if exceeded, perform result verification, if not exceeded, enter the automatic test module again; S10. After the test is finished, report the test results and recycle the process, then exit and end.

2. The method for testing the consistency of an instruction stream according to claim 1, characterized in that: In S9, the result is verified by comparing the value in the shared space after execution of each core with the register value.

3. The method for testing the consistency of an instruction stream according to claim 1, characterized in that: In S6, the instruction loading methods include: loading of even-numbered processes, and execution of all processes together; loading of odd-numbered processes, and execution of even-numbered processes; loading of some processes, and execution of all processes together; and loading of half of the processes, and execution of half of the processes.

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