Current and Average Power Detection Circuit for Motor Drive Circuit

Abstract

The present invention provides a current and average power detection circuit for a motor drive circuit, the detection circuit comprising: a voltage shift circuit, used for realizing voltage shift of the sampling point through high input impedance; a programmable amplifier, used for detecting the driving current of the external drive circuit according to the differential signal output by the voltage shift circuit; an anti-aliasing filter, used for filtering the differential signal output by the voltage shift circuit to obtain a differential filter signal; a switched capacitor low-pass filter amplifier, used for detecting the average power of the external drive circuit according to the differential filter signal; the problem that the low-pass filter resistance affects the amplifier gain in the current and average power detection circuit of the motor drive circuit in the prior art is solved, the high input impedance makes the gain not affected by external components, and the differential input and output ensure the anti-interference performance of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly to a current and average power detection circuit for a motor drive circuit. Background Art

[0002] In the field of motor control, whether it is a DC, two-phase, three-phase, or five-phase motor, in order to achieve automatic control, the drive of each group of phase lines is driven by a half-bridge circuit composed of an upper MOSFET and a lower MOSFET; in order to achieve precise control, most drive circuits include a current sampling circuit to achieve current closed-loop control.

[0003] Figure 1 The following is a schematic diagram of the current and average power detection circuit of a traditional motor drive circuit: RS is a current sampling resistor, and R1, R2, and C0 form a low-pass filter to filter out high-frequency interference. The resistors R1, R2, R3, R4, R5, and R6, together with the internal DAC and operational amplifier, form a pseudo-differential amplifier, and the output voltage corresponds to the current to be detected; after the output of the amplifier passes through a low-pass filter composed of R7 and C1 with an order of magnitude of 10 Hz, an approximately DC average current is obtained. Under the condition of known power supply voltage, the average current can represent the average power, so the average power detection circuit corresponds to the average current detection circuit. Finally, the amplifier output signal and the low-pass filter output signal are quantized by an ADC respectively.

[0004] However, the traditional motor drive current detection circuit has the problem that the resistance of the low-pass filter affects the gain of the amplifier, thus reducing the gain accuracy; the traditional low-pass filter scheme with an order of magnitude as low as 10 Hz requires large resistors or large capacitors and cannot be integrated, increasing the system volume and cost. Summary of the Invention

[0005] Aiming at the deficiencies in the prior art, the current and average power detection circuit for a motor drive circuit provided by the present invention solves the problem that the resistance of the low-pass filter in the current detection circuit of the existing motor drive circuit affects the gain of the amplifier. The high input impedance makes the gain not affected by external components, and the differential input and output ensure the anti-interference performance of the circuit; it also solves the problem that the traditional 10 Hz order RC low-pass filter cannot be integrated.

[0006] The present invention provides a current and average power detection circuit for a motor drive circuit. The detection circuit includes: a voltage translation circuit, the differential input terminals of the voltage translation circuit are connected to the sampling point of an external drive circuit during use, and are used to achieve voltage translation of the sampling point through a high input impedance; a programmable amplifier, the input terminal of the programmable amplifier is connected to the differential output terminal of the voltage translation circuit, and is used to detect the drive current of the external drive circuit according to the differential signal output by the voltage translation circuit; an anti-aliasing filter, the input terminal of the anti-aliasing filter is connected to the differential output terminal of the voltage translation circuit, and is used to filter the differential signal output by the voltage translation circuit to obtain a differential filtered signal; a switched-capacitor low-pass filter amplifier, the input terminal of the switched-capacitor low-pass filter amplifier is connected to the output terminal of the anti-aliasing filter, and is used to detect the average power of the external drive circuit according to the differential filtered signal.

[0007] Optionally, the voltage translation circuit includes: a first current source, a second current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; the first ends of the first current source and the second current source are connected to the power output terminal during use, the second end of the first current source is connected to the source of the third PMOS transistor, and the second end of the second current source is connected to the source of the fourth PMOS transistor; the gate of the first PMOS transistor is connected to the first input terminal of the differential signal, the drain of the first PMOS transistor is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the third PMOS transistor serves as the first output terminal; the gate of the second PMOS transistor is connected to the second input terminal of the differential signal, the drain of the second PMOS transistor is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor serves as the second output terminal.

[0008] Optionally, the voltage translation circuit further includes: a low-pass filter, the input terminals of the low-pass filter are respectively connected to the first output terminal and the second output terminal, and are used to filter out high-frequency noise in the signal; a super source follower, the input terminal of the super source follower is connected to the output terminal of the low-pass filter, and the output terminal of the super source follower is connected to a subsequent circuit during use.

[0009] Optionally, the low-pass filter includes: a first resistor, a second resistor, and a first filter capacitor; a first end of the first resistor is connected to a source electrode of the third PMOS transistor, and a second end of the first resistor is connected to a first end of the first filter capacitor; a first end of the second resistor is connected to a source electrode of the fourth PMOS transistor, and a second end of the second resistor is connected to a second end of the first filter capacitor.

[0010] Optionally, the super source follower includes: a first NMOS transistor, a second NMOS transistor, a third current source, and a fourth current source; a gate of the first NMOS transistor is connected to a first output end of the low-pass filter, a drain of the first NMOS transistor is connected to a power output end, a source of the first NMOS transistor is connected to a first end of the third current source, and a second end of the third current source is grounded; a gate of the second NMOS transistor is connected to a second output end of the low-pass filter, a drain of the second NMOS transistor is connected to the power output end, a source of the second NMOS transistor is connected to a first end of the fourth current source, and a second end of the fourth current source is grounded.

[0011] Optionally, the super source follower further includes: a fifth current source, a sixth current source, a fifth PMOS transistor, and a sixth PMOS transistor; a first end of the fifth current source and a first end of the sixth current source are connected to the power output end during use, a second end of the fifth current source is connected to a drain of the first NMOS transistor, and a second end of the sixth current source is connected to a drain of the second NMOS transistor; a source of the fifth PMOS transistor is connected to the power output end, a gate of the fifth PMOS transistor is connected to the second end of the fifth current source, and a drain of the fifth PMOS transistor is connected to a source of the first NMOS transistor; a source of the sixth PMOS transistor is connected to the power output end, a gate of the sixth PMOS transistor is connected to the second end of the sixth current source, and a drain of the sixth PMOS transistor is connected to a source of the second NMOS transistor.

[0012] Optionally, the anti-aliasing filter includes: a third resistor, a fourth resistor, a second filter capacitor, a seventh current source, an eighth current source, a seventh PMOS transistor, and an eighth PMOS transistor; a first end of the third resistor is connected to a first differential signal output end of the voltage translation circuit, a second end of the third resistor is connected to a first end of the second filter capacitor and a gate of the seventh PMOS transistor, a first end of the fourth resistor is connected to a second differential signal output end of the voltage translation circuit, a second end of the fourth resistor is connected to a second end of the second filter capacitor and a gate of the eighth PMOS transistor; a first end of the seventh current source and a first end of the eighth current source are connected to a power output end during use, a second end of the seventh current source is connected to a source of the seventh PMOS transistor, and a second end of the eighth current source is connected to a source of the eighth PMOS transistor.

[0013] Optionally, the switched-capacitor low-pass filter amplifier includes: first to fourth capacitors, an amplifier, and first to eighth clock switches; a first output end of the anti-aliasing filter is connected to a first end of the first capacitor through the first clock switch, the first end of the first capacitor is further connected to a common-mode voltage through the second clock switch, a second end of the first capacitor is connected to an inverting input end of the amplifier, the second end of the first capacitor is further connected to a first end of the second capacitor, a second end of the second capacitor is connected to a first output end of the amplifier through the third clock switch, and the second end of the second capacitor is further connected to the common-mode voltage through the fourth clock switch; a second output end of the anti-aliasing filter is connected to a first end of the third capacitor through the fifth clock switch, the first end of the third capacitor is further connected to the common-mode voltage through the sixth clock switch, a second end of the third capacitor is connected to a non-inverting input end of the amplifier, the second end of the third capacitor is further connected to a first end of the fourth capacitor, a second end of the fourth capacitor is connected to a second output end of the amplifier through the seventh clock switch, and the second end of the fourth capacitor is further connected to the common-mode voltage through the eighth clock switch.

[0014] Optionally, the switched-capacitor low-pass filter amplifier further includes: fifth to eighth capacitors, and ninth to twelfth clock switches; a first end of the fifth capacitor is connected to a second end of the first capacitor through the ninth clock switch, the first end of the fifth capacitor is further connected to a common-mode voltage through the tenth clock switch, a second end of the fifth capacitor is connected to a first output end of the amplifier, a first end of the sixth capacitor is connected to an inverting input end of the amplifier, and a second end of the sixth capacitor is connected to the first output end of the amplifier; a first end of the seventh capacitor is connected to a second end of the third capacitor through the eleventh clock switch, the first end of the seventh capacitor is further connected to the common-mode voltage through the twelfth clock switch, a second end of the seventh capacitor is connected to a second output end of the amplifier, a first end of the eighth capacitor is connected to a non-inverting input end of the amplifier, and a second end of the eighth capacitor is connected to the second output end of the amplifier.

[0015] Optionally, the first clock switch, the third clock switch, the fifth clock switch, the seventh clock switch, the ninth clock switch, and the eleventh clock switch are controlled by a first clock signal, and the second clock switch, the fourth clock switch, the sixth clock switch, the eighth clock switch, the tenth clock switch, and the twelfth clock switch are controlled by a second clock signal; wherein, the first clock signal and the second clock signal are complementary clocks.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The voltage translation circuit in the present invention has characteristics such as high input impedance, supporting negative voltage input, high-precision fully differential input and output circuit, strong driving ability, configurable low-pass cut-off frequency, etc. The high input impedance makes the gain not affected by external components, and the differential input and output ensure the anti-interference performance of the circuit; the programmable amplifier adopts a fully differential circuit, which significantly improves the anti-interference performance and can avoid using an additional DAC to control the output common-mode voltage; replacing the traditional RC low-pass filter amplifier with a switched-capacitor low-pass filter amplifier can achieve a low-pass cut-off frequency as low as the order of 10 Hz with a small area, thereby avoiding the use of an off-chip uF-level first filter capacitor. Setting the low-pass cut-off frequency of the switched-capacitor low-pass filter amplifier at about 10 Hz is sufficient to filter out the high-order harmonics in the motor current signal and only retain the low-frequency components, that is, the corresponding average current. Since the supply voltage of the motor drive circuit remains unchanged, the average current corresponds to the average power; therefore, the present invention solves the problem in the prior art that the low-pass filter resistor in the current and average power detection circuit of the motor drive circuit affects the amplifier gain. The high input impedance makes the gain not affected by external components, and the differential input and output ensure the anti-interference performance of the circuit; it also solves the problem that the traditional RC low-pass filter of the order of 10 Hz cannot be integrated. Description of the Drawings

[0018] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 The figure shows a circuit schematic diagram of the current and average power detection circuit of a traditional motor drive circuit;

[0021] Figure 2 The figure shows a structural schematic diagram of the current and average power detection circuit of a motor drive circuit provided by an embodiment of the present invention;

[0022] Figure 3 The figure shows a circuit schematic diagram of a voltage translation circuit provided by an embodiment of the present invention;

[0023] Figure 4 The figure shows a circuit schematic diagram of an anti-aliasing filter provided by an embodiment of the present invention;

[0024] Figure 5 The figure shows a circuit schematic diagram of a switched-capacitor low-pass filter amplifier provided by an embodiment of the present invention;

[0025] Figure 6 The figure shows a circuit schematic diagram of a programmable amplifier provided by an embodiment of the present invention. Detailed Embodiments

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application. In the embodiments of the present invention, functional units with the same reference numerals have the same and similar structures and functions.

[0027] Embodiment 1

[0028] Figure 2 The figure shows a structural schematic diagram of the current and average power detection circuit of a motor drive circuit provided by an embodiment of the present invention, as Figure 2As shown, the current and average power detection circuit of the motor drive circuit specifically includes:

[0029] A voltage translation circuit, whose differential input terminals are connected to the sampling point of the external drive circuit during use, and is used to achieve voltage translation of the sampling point through a high input impedance;

[0030] A programmable amplifier, whose input terminal is connected to the differential output terminal of the voltage translation circuit, and is used to detect the drive current of the external drive circuit according to the differential signal output by the voltage translation circuit;

[0031] An anti-aliasing filter, whose input terminal is connected to the differential output terminal of the voltage translation circuit, and is used to filter the differential signal output by the voltage translation circuit to obtain a differential filtered signal;

[0032] A switched-capacitor low-pass filter amplifier, whose input terminal is connected to the output terminal of the anti-aliasing filter, and is used to detect the average power of the external drive circuit according to the differential filtered signal.

[0033] It should be noted that the current and average power detection circuit of the motor drive circuit in this embodiment includes a voltage translation circuit, a programmable amplifier, an anti-aliasing filter, and a switched-capacitor low-pass filter amplifier; among them, the programmable amplifier is used to detect the rapidly changing motor drive current, and the switched-capacitor low-pass filter amplifier realizes a low-pass cut-off frequency of the order of 10 Hz and is used to obtain the average power. Finally, the drive current output by the programmable amplifier and the average power output by the switched-capacitor low-pass filter amplifier are input to the subsequent ADC module for quantization.

[0034] The voltage translation circuit in this embodiment has characteristics such as high input impedance, support for negative voltage input, high-precision fully differential input-output circuit, strong driving ability, and configurable low-pass cut-off frequency. The high input impedance makes the gain unaffected by external components, and the differential input-output ensures the anti-interference performance of the circuit; the programmable amplifier uses a fully differential circuit, which significantly improves the anti-interference performance and can avoid using an additional DAC to control the output common-mode voltage; the anti-aliasing filter can prevent the aliasing effect of high-frequency signal components from deteriorating the accuracy of the subsequent switched first filter capacitor circuit; the switched-capacitor low-pass filter amplifier can achieve a low-pass cut-off frequency as low as the order of 10 Hz with a small area, thus avoiding the use of off-chip uF-level first filter capacitors. Setting the low-pass cut-off frequency of the switched-capacitor low-pass filter amplifier at about 10 Hz is sufficient to filter out the high-order harmonics in the motor current signal and retain only the low-frequency components, which corresponds to the average current. Since the supply voltage of the motor drive circuit remains unchanged, the average current corresponds to the average power; therefore, the present invention solves the problem in the prior art that the low-pass filter resistance in the current and average power detection circuits of the motor drive circuit affects the amplifier gain. The high input impedance makes the gain unaffected by external components, and the differential input-output ensures the anti-interference performance of the circuit.

[0035] Embodiment 2

[0036] Figure 3 The following is a circuit schematic diagram of a voltage translation circuit provided by an embodiment of the present invention, as Figure 3 shown, the voltage translation circuit includes:

[0037] A first current source l_D1, a second current source l_D2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4;

[0038] The first end of the first current source l_D1 and the first end of the second current source l_D2 are connected to the power supply output terminal during use. The second end of the first current source l_D1 is connected to the source of the third PMOS transistor MP3, and the second end of the second current source l_D2 is connected to the source of the fourth PMOS transistor MP4;

[0039] The gate of the first PMOS transistor MP1 is connected to the first input terminal of the differential signal. The drain of the first PMOS transistor MP1 is connected to the gate of the first PMOS transistor MP1. The source of the first PMOS transistor MP1 is connected to the drain of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is connected to the drain of the third PMOS transistor MP3. The source of the third PMOS transistor MP3 serves as the first output terminal;

[0040] The gate of the second PMOS transistor MP2 is connected to the second input terminal of the differential signal. The drain of the second PMOS transistor MP2 is connected to the gate of the second PMOS transistor MP2. The source of the second PMOS transistor MP2 is connected to the drain of the fourth PMOS transistor MP4. The gate of the fourth PMOS transistor MP4 is connected to the drain of the fourth PMOS transistor MP4. The source of the fourth PMOS transistor MP4 serves as the second output terminal.

[0041] It should be noted that the voltage translation circuit provided in this embodiment is composed of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first current source, and a second current source. Since two PMOS transistors are connected in series at the differential signal input terminal of the current and average power detection circuit of the motor drive circuit, there will be two Vsg voltages, thereby raising the input level by the conduction voltages of the two PMOS transistors, so that even if the input voltage is as low as a negative voltage, the subsequent circuit can still be biased in the normal operating range.

[0042] In addition, compared with the traditional PMOS input type source follower translation circuit, the current and average power detection circuit of the motor drive circuit provided in this embodiment has higher precision. The drain of the traditional PMOS source follower is grounded. Therefore, the differential input signal will cause different source-drain voltages in the two input PMOS transistors, and the channel length modulation effect further causes an error in the gate-source voltage. The reason for this error can be presented by the following expression of the MOS transistor current Ids:

[0043]

[0044] Where is the hole mobility, Cox is the first filtering capacitance of the gate oxide layer per unit area, W is the width of the PMOS transistor, L is the length of the PMOS transistor, Vsg is the source-gate voltage, Vth is the threshold voltage of the PMOS transistor, λ is the channel length modulation coefficient, and Vsd is the source-drain voltage. It can be seen that even if the Ids of a pair of source followers are the same, due to different Vsd, there will be a difference in the source-gate voltage. In the application of motor drive current detection, the input voltage can be as low as a negative voltage, making the PMOS transistor Vsd very small, even approaching the linear region, worsening the above error. In addition, the higher-order effects of short-channel transistors will further increase the above error, making the gain error easily exceed 2%.

[0045] In the current and average power detection circuit of the motor drive circuit provided in this embodiment, connecting the gate and drain of the PMOS transistor together avoids the above problems. The voltage gain Gain1 of this translation circuit can be expressed as:

[0046]

[0047] Where Rext represents the external resistor connected in series between the sampling resistor and the input port, usually at the kohm level. If no external resistor is used, this value is 0. gm_p represents the transconductance of the PMOS transistor, and Ro_src represents the equivalent output impedance of the current sources I_D1 and I_D2, that is, the equivalent input impedance of the translation circuit. Ro_src can be easily designed to be above 10 Mohm, making the influence of peripheral components on the gain accuracy negligible. Therefore, the voltage gain of the current detection circuit of the motor drive circuit provided in this embodiment is approximately equal to 1, and it has higher translation accuracy compared to the traditional PMOS input type source follower.

[0048] In this embodiment, two PMOS transistors are connected in series at the differential signal input end of the voltage translation circuit, and there will be two Vsg voltages, thus raising the input level by the conduction voltages of the two PMOS transistors, so that even if the input voltage is as low as a negative voltage, the output end of the voltage translation circuit can still bias the subsequent circuit in the normal operating range; since the Vsd of the two PMOS transistors does not change with the change of the input signal amplitude, the provided voltage translation circuit has higher translation accuracy compared to the traditional PMOS input type source follower; and the voltage translation circuit provided by the present invention has a high input impedance, so that the signal gain is not affected by the internal resistance of the input signal source; differential input and output ensure the anti-interference ability of the circuit.

[0049] Embodiment Three

[0050] As Figure 2 shown, the voltage translation circuit further includes: a low-pass filter, the input end of the low-pass filter is respectively connected to the first output end and the second output end, and is used to filter out high-frequency noise in the signal; a super source follower, the input end of the super source follower is connected to the output end of the low-pass filter, and the output end of the super source follower is connected to the subsequent circuit during use.

[0051] In this embodiment, the low-pass filter includes: a first resistor, a second resistor, and a first filter capacitor; the first end of the first resistor is connected to the source of the third PMOS transistor, and the second end of the first resistor is connected to the first end of the first filter capacitor; the first end of the second resistor is connected to the source of the fourth PMOS transistor, and the second end of the second resistor is connected to the second end of the first filter capacitor. The first resistor R1, the second resistor R2, and the first filter capacitor CF; the first end of the first resistor R1 is connected to the source of the third PMOS transistor MP3, and the second end of the first resistor R1 is connected to the first end of the first filter capacitor CF; the first end of the second resistor R2 is connected to the source of the fourth PMOS transistor MP4, and the second end of the second resistor R2 is connected to the second end of the first filter capacitor CF.

[0052] In this embodiment, the super source follower includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third current source l_D3, and a fourth current source l_D4; the gate of the first NMOS transistor MN1 is connected to the first output terminal of the low-pass filter, the drain of the first NMOS transistor MN1 is connected to the third terminal of the feedback circuit, the source of the first NMOS transistor MN1 is connected to the first terminal of the third current source l_D3, and the second terminal of the third current source l_D3 is grounded; the gate of the second NMOS transistor MN2 is connected to the second output terminal of the low-pass filter, the drain of the second NMOS transistor MN2 is connected to the third terminal of the feedback circuit, the source of the second NMOS transistor MN2 is connected to the first terminal of the fourth current source l_D4, and the second terminal of the fourth current source l_D4 is grounded.

[0053] Further, the super source follower further includes: a fifth current source l_D5, a sixth current source l_D6, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6; the first terminals of the fifth current source l_D5 and the sixth current source l_D6 are connected to the power supply output terminal during use, the second terminal of the fifth current source l_D5 is connected to the drain of the first NMOS transistor MN1, and the second terminal of the sixth current source l_D6 is connected to the drain of the second NMOS transistor MN2; the source of the fifth PMOS transistor MP5 is connected to the power supply output terminal, the gate of the fifth PMOS transistor MP5 is connected to the second terminal of the fifth current source l_D5, and the drain of the fifth PMOS transistor MP5 is connected to the source of the first NMOS transistor MN1; the source of the sixth PMOS transistor MP6 is connected to the power supply output terminal, the gate of the sixth PMOS transistor MP6 is connected to the second terminal of the sixth current source l_D6, and the drain of the sixth PMOS transistor MP6 is connected to the source of the second NMOS transistor MN2.

[0054] It should be noted that the low-pass filter in this embodiment includes a first resistor, a second resistor, and a first filter capacitor, so that the high-frequency noise of the input signal can be effectively filtered. The cut-off frequency fc1 of this low-pass filter can be expressed as:

[0055]

[0056] In this embodiment, in order to adjust the low-pass filter cut-off frequency by controlling the sizes of the resistors and the first filter capacitor to meet the usage requirements of different application scenarios, the first resistor and the second resistor in this embodiment are variable resistors, and the first filter capacitor is a variable first filter capacitor.

[0057] Further, the first resistor and the second resistor are digital potentiometer chips. When in use, the control ends of the digital potentiometer chips are connected to an external controller, and are configured to output corresponding resistance values according to trigger signals of the external controller.

[0058] It should be noted that the output of the super source follower in this embodiment has a very low output impedance, which can easily drive the subsequent circuit, thus ensuring the gain accuracy.

[0059] In summary, the voltage translation circuit in this embodiment has characteristics such as high input impedance, support for negative voltage input, high-precision fully differential input-output circuit, strong driving ability, and configurable low-pass cut-off frequency; the high input impedance enables the gain to be unaffected by external components, and the differential input-output ensures the anti-interference performance of the circuit.

[0060] Embodiment 4

[0061] Figure 4 The following shows a circuit schematic diagram of an anti-aliasing filter provided by an embodiment of the present invention. As Figure 4 shown, the anti-aliasing filter includes:

[0062] A third resistor R3, a fourth resistor R4, a second filter capacitor CF2, a seventh current source l_D7, an eighth current source l_D8, a seventh PMOS transistor MP7, and an eighth PMOS transistor MP8; a first end of the third resistor R3 is connected to a first differential signal output end of the voltage translation circuit, a second end of the third resistor R3 is connected to a first end of the second filter capacitor CF2 and a gate of the seventh PMOS transistor MP7, a first end of the fourth resistor R4 is connected to a second differential signal output end of the voltage translation circuit, a second end of the fourth resistor R4 is connected to a second end of the second filter capacitor CF2 and a gate of the eighth PMOS transistor MP8; a first end of the seventh current source l_D7 and a first end of the eighth current source l_D8 are connected to a power output end when in use, a second end of the seventh current source l_D7 is connected to a source of the seventh PMOS transistor MP7, and a second end of the eighth current source l_D8 is connected to a source of the eighth PMOS transistor MP8.

[0063] It should be noted that the anti-aliasing filter in this embodiment includes a low-pass filter composed of a third resistor, a fourth resistor, and a second filter capacitor, which is connected to a traditional source follower to drive a subsequent switched first filter capacitor filter.

[0064] Embodiment 5

[0065] Figure 5 The following shows a circuit schematic diagram of a switched-capacitor low-pass filter amplifier provided by an embodiment of the present invention. As Figure 5As shown, the switched-capacitor low-pass filter amplifier includes:

[0066] The first to fourth capacitors, an amplifier, and the first to eighth clock switches; the first output terminal of the anti-aliasing filter is connected to the first terminal of the first capacitor C1 through the first clock switch T1, and the first terminal of the first capacitor C1 is also connected to the common-mode voltage through the second clock switch T2. The second terminal of the first capacitor C1 is connected to the inverting input terminal of the amplifier, and the second terminal of the first capacitor C1 is also connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the first output terminal of the amplifier through the third clock switch T3, and the second terminal of the second capacitor C2 is also connected to the common-mode voltage through the fourth clock switch T4. The second output terminal of the anti-aliasing filter is connected to the first terminal of the third capacitor C3 through the fifth clock switch T5, and the first terminal of the third capacitor C3 is also connected to the common-mode voltage through the sixth clock switch T6. The second terminal of the third capacitor C3 is connected to the non-inverting input terminal of the amplifier, and the second terminal of the third capacitor C3 is also connected to the first terminal of the fourth capacitor C4. The second terminal of the fourth capacitor C4 is connected to the second output terminal of the amplifier through the seventh clock switch T7, and the second terminal of the fourth capacitor C4 is also connected to the common-mode voltage through the eighth clock switch T8.

[0067] In this embodiment, the switched-capacitor low-pass filter amplifier further includes: the fifth to eighth capacitors C8, and the ninth to twelfth clock switches T12; the first terminal of the fifth capacitor C5 is connected to the second terminal of the first capacitor C1 through the ninth clock switch T9, and the first terminal of the fifth capacitor C5 is also connected to the common-mode voltage through the tenth clock switch T10. The second terminal of the fifth capacitor C5 is connected to the first output terminal of the amplifier. The first terminal of the sixth capacitor C6 is connected to the inverting input terminal of the amplifier, and the second terminal of the sixth capacitor C6 is connected to the first output terminal of the amplifier. The first terminal of the seventh capacitor C7 is connected to the second terminal of the third capacitor C3 through the eleventh clock switch T11, and the first terminal of the seventh capacitor C7 is also connected to the common-mode voltage through the twelfth clock switch T12. The second terminal of the seventh capacitor C7 is connected to the second output terminal of the amplifier. The first terminal of the eighth capacitor C8 is connected to the non-inverting input terminal of the amplifier, and the second terminal of the eighth capacitor C8 is connected to the second output terminal of the amplifier.

[0068] In this embodiment, the first clock switch T1, the third clock switch T3, the fifth clock switch T5, the seventh clock switch T7, the ninth clock switch T9, and the eleventh clock switch T11 are controlled by a first clock signal, and the second clock switch T2, the fourth clock switch T4, the sixth clock switch T6, the eighth clock switch T8, the tenth clock switch T10, and the twelfth clock switch T12 are controlled by a second clock signal.

[0069] It should be noted that the first clock signal and the second clock signal are complementary clocks, and the operating frequency is ; Vcm is a stable common-mode voltage; the capacitance values of capacitor C1 and C3 are equal; the capacitance values of capacitors C2, C5, C4, and C7 are equal; the capacitance values of capacitors C6 and C8 are equal. According to the circuit principle, the z-domain transfer function of this filter can be deduced as:

[0070]

[0071] Furthermore, its cut-off frequency can be obtained as:

[0072]

[0073] Its DC gain is:

[0074]

[0075] By reasonably setting the operating frequency and capacitance value of the switched capacitor, the low-pass cut-off frequency and gain can be flexibly and efficiently controlled.

[0076] Embodiment Six

[0077] Figure 6 The following is a schematic circuit diagram of a programmable amplifier provided by an embodiment of the present invention. As Figure 6 shown, the programmable amplifier includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and an AMP amplifier. The non-inverting input terminal of the AMP amplifier is connected to the first output terminal of the differential signal of the voltage translation circuit through the fifth resistor R5. The inverting input terminal of the AMP amplifier is connected to the second output terminal of the differential signal of the voltage translation circuit through the sixth resistor R6. The inverting output terminal of the AMP amplifier is connected to the non-inverting input terminal of the AMP amplifier through the seventh resistor R7. The non-inverting output terminal of the AMP amplifier is connected to the inverting input terminal of the AMP amplifier through the eighth resistor R8.

[0078] In this embodiment, the feedback network composed of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 determines the gain of the amplifier, and the gain of the amplifier can be adjusted by controlling the resistance value.

[0079] Combining the above embodiments 1 to 6, it can be seen that the current and average power detection circuit of the motor drive circuit provided by the present invention has the following beneficial effects: 1) The external components are streamlined, reducing the system volume, cost, and design difficulty; 2) The high input impedance makes the gain accuracy immune to the influence of components such as external low-pass filter resistors; 3) The use of a fully differential circuit structure improves the anti-interference ability; 4) The use of an anti-aliasing filter and a switched-capacitor low-pass filter amplifier circuit realizes the integrated scheme for average power detection.

[0080] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0081] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A current and average power detection circuit for a motor drive circuit, characterized in that, the detection circuit includes: A voltage translation circuit, the differential input terminals of the voltage translation circuit are connected to the sampling point of the external drive circuit during use, and are used to achieve voltage translation of the sampling point through a high input impedance; A programmable amplifier, the input terminal of the programmable amplifier is connected to the differential output terminal of the voltage translation circuit, and is used to detect the drive current of the external drive circuit according to the differential signal output by the voltage translation circuit; An anti-aliasing filter, the input terminal of the anti-aliasing filter is connected to the differential output terminal of the voltage translation circuit, and is used to filter the differential signal output by the voltage translation circuit to obtain a differential filtered signal; A switched-capacitor low-pass filter amplifier, the input terminal of the switched-capacitor low-pass filter amplifier is connected to the output terminal of the anti-aliasing filter, and is used to detect the average power of the external drive circuit according to the differential filtered signal; The voltage translation circuit includes: A first current source, a second current source, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; The first ends of the first current source and the second current source are connected to the power supply output terminal during use, the second end of the first current source is connected to the source of the third PMOS transistor, and the second end of the second current source is connected to the source of the fourth PMOS transistor; The gate of the first PMOS transistor is connected to the first input terminal of the differential signal, the drain of the first PMOS transistor is connected to the gate of the first PMOS transistor, the source of the first PMOS transistor is connected to the drain of the third PMOS transistor, the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the source of the third PMOS transistor is used as the first output terminal; The gate of the second PMOS transistor is connected to the second input terminal of the differential signal, the drain of the second PMOS transistor is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fourth PMOS transistor is used as the second output terminal.

2. The current and average power detection circuit for a motor drive circuit according to claim 1, characterized in that, the voltage translation circuit further includes: A low-pass filter, the input terminals of the low-pass filter are respectively connected to the first output terminal and the second output terminal, and are used to filter out high-frequency noise in the signal; A super source follower, the input terminal of the super source follower is connected to the output terminal of the low-pass filter, and the output terminal of the super source follower is connected to the subsequent circuit during use.

3. The current and average power detection circuit for a motor drive circuit according to claim 2, characterized in that, the low-pass filter includes: A first resistor, a second resistor, and a first filter capacitor; The first end of the first resistor is connected to the source of the third PMOS transistor, and the second end of the first resistor is connected to the first end of the first filter capacitor; the first end of the second resistor is connected to the source of the fourth PMOS transistor, and the second end of the second resistor is connected to the second end of the first filter capacitor.

4. The current and average power detection circuit of the motor drive circuit according to claim 2, wherein, the super source follower includes: a first NMOS transistor, a second NMOS transistor, a third current source, and a fourth current source; the gate of the first NMOS transistor is connected to the first output terminal of the low-pass filter, the drain of the first NMOS transistor is connected to the power supply output terminal, the source of the first NMOS transistor is connected to the first end of the third current source, and the second end of the third current source is grounded; the gate of the second NMOS transistor is connected to the second output terminal of the low-pass filter, the drain of the second NMOS transistor is connected to the power supply output terminal, the source of the second NMOS transistor is connected to the first end of the fourth current source, and the second end of the fourth current source is grounded.

5. The current and average power detection circuit of the motor drive circuit according to claim 4, wherein, the super source follower further includes: a fifth current source, a sixth current source, a fifth PMOS transistor, and a sixth PMOS transistor; the first ends of the fifth current source and the sixth current source are connected to the power supply output terminal during use, the second end of the fifth current source is connected to the drain of the first NMOS transistor, and the second end of the sixth current source is connected to the drain of the second NMOS transistor; the source of the fifth PMOS transistor is connected to the power supply output terminal, the gate of the fifth PMOS transistor is connected to the second end of the fifth current source, and the drain of the fifth PMOS transistor is connected to the source of the first NMOS transistor; the source of the sixth PMOS transistor is connected to the power supply output terminal, the gate of the sixth PMOS transistor is connected to the second end of the sixth current source, and the drain of the sixth PMOS transistor is connected to the source of the second NMOS transistor.

6. The current and average power detection circuit of the motor drive circuit according to claim 1, wherein, the anti-aliasing filter includes: a third resistor, a fourth resistor, a second filter capacitor, a seventh current source, an eighth current source, a seventh PMOS transistor, and an eighth PMOS transistor; the first end of the third resistor is connected to the first differential signal output terminal of the voltage translation circuit, the second end of the third resistor is connected to the first end of the second filter capacitor and the gate of the seventh PMOS transistor, the first end of the fourth resistor is connected to the second differential signal output terminal of the voltage translation circuit, and the second end of the fourth resistor is connected to the second end of the second filter capacitor and the gate of the eighth PMOS transistor; The first end of the seventh current source and the first end of the eighth current source are connected to the power supply output terminal during use. The second end of the seventh current source is connected to the source of the seventh PMOS transistor, the drain of the seventh PMOS transistor is grounded, the second end of the eighth current source is connected to the source of the eighth PMOS transistor, and the drain of the eighth PMOS transistor is grounded.

7. The current and average power detection circuit of the motor drive circuit according to claim 1, characterized in that the switched-capacitor low-pass filter amplifier includes: the first to fourth capacitors, an amplifier, and the first to eighth clock switches; The first output terminal of the anti-aliasing filter is connected to the first end of the first capacitor through the first clock switch. The first end of the first capacitor is also connected to the common-mode voltage through the second clock switch. The second end of the first capacitor is connected to the inverting input terminal of the amplifier. The second end of the first capacitor is also connected to the first end of the second capacitor. The second end of the second capacitor is connected to the first output terminal of the amplifier through the third clock switch. The second end of the second capacitor is also connected to the common-mode voltage through the fourth clock switch; The second output terminal of the anti-aliasing filter is connected to the first end of the third capacitor through the fifth clock switch. The first end of the third capacitor is also connected to the common-mode voltage through the sixth clock switch. The second end of the third capacitor is connected to the non-inverting input terminal of the amplifier. The second end of the third capacitor is also connected to the first end of the fourth capacitor. The second end of the fourth capacitor is connected to the second output terminal of the amplifier through the seventh clock switch. The second end of the fourth capacitor is also connected to the common-mode voltage through the eighth clock switch.

8. The current and average power detection circuit of the motor drive circuit according to claim 7, characterized in that the switched-capacitor low-pass filter amplifier further includes: the fifth to eighth capacitors, and the ninth to twelfth clock switches; The first end of the fifth capacitor is connected to the second end of the first capacitor through the ninth clock switch. The first end of the fifth capacitor is also connected to the common-mode voltage through the tenth clock switch. The second end of the fifth capacitor is connected to the first output terminal of the amplifier. The first end of the sixth capacitor is connected to the inverting input terminal of the amplifier. The second end of the sixth capacitor is connected to the first output terminal of the amplifier; The first end of the seventh capacitor is connected to the second end of the third capacitor through the eleventh clock switch. The first end of the seventh capacitor is also connected to the common-mode voltage through the twelfth clock switch. The second end of the seventh capacitor is connected to the second output terminal of the amplifier. The first end of the eighth capacitor is connected to the non-inverting input terminal of the amplifier. The second end of the eighth capacitor is connected to the second output terminal of the amplifier.

9. The current and average power detection circuit of the motor drive circuit according to claim 8, characterized in that The first clock switch, the third clock switch, the fifth clock switch, the seventh clock switch, the ninth clock switch, and the eleventh clock switch are controlled by a first clock signal, and the second clock switch, the fourth clock switch, the sixth clock switch, the eighth clock switch, the tenth clock switch, and the twelfth clock switch are controlled by a second clock signal; wherein, the first clock signal and the second clock signal are complementary clocks.

Images