A method and system for verifying memory disambiguation in a processor

Abstract

The present application relates to the technical field of processor, and particularly relates to a verification method and system for memory disambiguation in a processor, the present application verifies the memory disambiguation logic caused by single core, multi-core and non-aligned access by monitoring the execution information of load instruction and store instruction in DUT, and judges whether the pipeline needs to be refreshed and from which instruction to start refreshing by comparing the memory disambiguation result of DUT and the memory disambiguation result of checker. The present application verifies the logic of memory disambiguation, and simultaneously supports the memory disambiguation of single core and multi-core. The final result of memory disambiguation is whether the pipeline needs to be refreshed and from which instruction to start refreshing, and the present verification method can accurately verify the two points, if the pipeline refresh information is inconsistent with DUT, error information will be reported immediately, which can help the verification personnel to quickly and effectively debug the code.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and more specifically to a method and system for verifying memory disambiguation in a processor. Background Technology

[0002] In high-performance out-of-order processors, memory access instructions are often executed out of order. Load instructions can employ a speculative execution strategy, while store instructions must guarantee sequential writing to memory. After obtaining a physical address, the load instruction can attempt to fetch data. During this process, the load instruction searches for store instructions with address dependencies. If a younger store instruction with the same address exists, the load instruction can directly fetch data from that instruction. However, there are also older store instructions whose physical addresses have not yet been obtained. The load instruction can ignore these older store instructions and fetch data directly. When a store instruction obtains a physical address, it needs to search for a younger load instruction with the same physical address that has already fetched data. If such an instruction exists, the pipeline needs to be re-flushd, and the speculative load instruction needs to be re-executed because it has obtained stale data. This operation is called memory disambiguation.

[0003] Another situation requiring memory disambiguation occurs in multi-core systems. If two load instructions on core 0 access the same address, but for some reason the younger load instruction executes first and obtains the data, then core 1 performs a write operation on that address and changes the data. Afterwards, the older load instruction on core 0 executes and obtains the new data, while the younger load instruction obtains the stale data. In this case, the pipeline needs to be re-flushd to re-execute the younger load instruction.

[0004] In conventional processor verification, memory access modules are modeled separately and the obtained access data is compared. However, it is difficult to accurately verify microarchitectures such as memory disambiguation, especially in multi-core systems. Memory disambiguation verification requires a thorough understanding of the system and microarchitecture, and relevant technologies are currently hard to find on the market. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention discloses a verification method and system for memory disambiguation in a processor, which solves the aforementioned problems.

[0006] This invention is achieved through the following technical solution:

[0007] In a first aspect, the present invention provides a method for verifying memory disambiguation in a processor. The method verifies the memory disambiguation logic caused by single-core, multi-core, and unaligned access by monitoring the execution information of load and store instructions in the DUT. By comparing the memory disambiguation results of the DUT with the memory disambiguation results of the checker, it determines whether the pipeline needs to be re-flushd and from which instruction to start the re-flush. If the pipeline re-flush information is inconsistent with that of the DUT, an error message is immediately reported.

[0008] Furthermore, in the method, single-core memory disambiguation includes memory disambiguation verification caused by the store instruction and memory disambiguation verification caused by cache kick-out.

[0009] Furthermore, in the method, the memory disambiguation verification process caused by the store instruction in a single core is as follows:

[0010] The DUT monitors the store instruction. After the store instruction obtains the physical address, the single-core memory disambiguation checker starts to search for whether there is a load instruction in the core that meets the conditions.

[0011] If there is a load instruction that meets the above conditions, the single-core memory disambiguation judge performs the following operations: compare the age information of these load instructions and find the oldest one; store the selected load instruction information into the commit information of the store instruction. The load instruction information includes its mark or program counter information in the instruction stream.

[0012] If no load instruction meets the above conditions, the single-core memory disambiguation checker invalidates the re-flush pipeline information in the commit information of the store instruction.

[0013] The comparator monitors the commit information of the store instruction in the DUT. When the store instruction commits, the comparator compares the re-flush pipeline information in the DUT commit information with the verified single-core memory disambiguation result. If they are inconsistent, an error is reported. The error information includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

[0014] Furthermore, in the method, the load instruction is satisfied as follows:

[0015] The access scope of the Load directive overlaps with that of the Store directive;

[0016] The Load command has already obtained the data;

[0017] The Load instruction is younger than the Store instruction in program order.

[0018] Furthermore, in the method, the memory disambiguation verification process caused by cache kick-out in a single core is as follows:

[0019] The system monitors whether any L1 cache lines are evicted from the DUT. If so, the single-core memory disambiguation checker begins to search for two types of load instructions that meet the conditions in the local core.

[0020] If the conditions are met, the first type of load instruction will be marked as needing to refresh the pipeline flag:

[0021] If the second type of load instruction meets the conditions, then the load instruction may need to include pipeline re-flush information during the commit:

[0022] Find all load instructions that meet the above two conditions, and check if there are any load instructions of the second type that are older than load instructions of the first type.

[0023] If the above situation exists, find the oldest load instruction in the first type of load instructions that is younger than the second type of load instructions. This load instruction is the starting position where the pipeline needs to be re-flushd. The position information of this load instruction in the program will be marked on the second type of load instruction.

[0024] If none of the above conditions apply, then memory disambiguation is not required.

[0025] When memory disambiguation is required, wait for the commit information of the second type of load instruction in the DUT. When the load instruction commits, the comparator compares the re-flush pipeline information of the DUT and the checker. If they are inconsistent, an error is reported. The error message includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

[0026] Furthermore, in the method, the first type of load instruction satisfies the following condition:

[0027] The physical address of the Load instruction is the same cache line as the cache line that was evicted.

[0028] The Load command has already obtained the data;

[0029] The data for the Load instruction is not obtained from the local core forward;

[0030] The second type of load instruction meets the following conditions:

[0031] The physical address of the Load instruction is the same cache line as the cache line that was evicted.

[0032] The b.Load instruction has not yet received any data.

[0033] Furthermore, the multi-core memory disambiguation verification process in the method is as follows:

[0034] The system monitors the store instructions of each core in a multi-core system. When the data of a store instruction is visible to other cores, the multi-core memory disambiguation check whether there are two types of load instructions in other cores that meet the conditions.

[0035] If the conditions are met, the first type of load instruction will be marked as needing to refresh the pipeline flag:

[0036] If the second type of load instruction meets the conditions, then the load instruction must include pipeline re-flush information during the commit:

[0037] Find all load instructions in each core that meet the above two conditions, and check if there are any load instructions of the second type that are older than load instructions of the first type in the same core.

[0038] If the above situation exists, find the oldest load instruction in the first type of load instructions that is younger than the second type of load instructions. This load instruction is the starting position where the pipeline needs to be re-flushd. The position information of this load instruction in the program will be marked on the second type of load instruction.

[0039] If none of the above conditions apply, then memory disambiguation is not required.

[0040] When memory disambiguation is required, wait for the commit information of the second type of load instruction in the DUT. When the load instruction commits, compare the re-flush pipeline information of the DUT and the checker. If they are inconsistent, an error is reported. The error message includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

[0041] Furthermore, in the method, the first type of load instruction satisfies the following condition:

[0042] The physical address of the Load instruction and the physical address of the Store instruction are in the same cache line;

[0043] The Load command has already obtained the data;

[0044] The data for the Load instruction is not obtained from the local core forward;

[0045] The second type of load instruction meets the following conditions:

[0046] The physical address of the Load instruction and the physical address of the Store instruction are in the same cache line;

[0047] The Load command has not yet received any data.

[0048] Furthermore, in the method, the memory disambiguation verification caused by unaligned access is as follows:

[0049] If the load instruction is an unaligned access, the processor splits the load access into two aligned accesses. The checker processes these two accesses as two independent accesses and performs memory disambiguation checks for single-core and multi-core processors.

[0050] If the store instruction is an unaligned access, the processor splits the store access into two aligned write operations. The checker processes these two write operations into two independent write operations for single-core and multi-core memory disambiguation checks.

[0051] Secondly, the present invention provides a verification system for memory disambiguation in a processor, the system being used to implement the verification method for memory disambiguation in a processor as described in the first aspect, including...

[0052] The memory access instruction monitor is used to monitor the execution information of load and store instructions in the DUT. The execution information of load instructions is stored in the load instruction queue of each core, and the execution information of store instructions is sent to both the single-core memory disambiguation judge and the multi-core memory disambiguation judge.

[0053] The Level 1 cache monitor is used to monitor whether there are cache lines being evicted from the Level 1 cache and sends this information to the single-core memory disambiguation judge.

[0054] The commit information monitor is used to monitor the commit information of load / store instructions in the DUT, including the re-flush pipeline information in the commit information, which is the result of DUT memory disambiguation, and is compared with the memory disambiguation result of the checker.

[0055] The single-core memory disambiguation checker is used to find the corresponding core's load instruction queue based on the input store instruction execution information and L1 cache kick-out information, determine whether the memory disambiguation conditions are met, and finally output the single-core memory disambiguation result.

[0056] The multi-core memory disambiguation checker is used to search the load instruction queues of other cores based on the input store instruction execution information, determine whether the memory disambiguation conditions are met, and finally output the multi-core memory disambiguation results.

[0057] Each core's load instruction queue is used to store the load instruction execution information input by the memory access instruction monitor into the corresponding core's load instruction queue. This information includes the access address of the load instruction, whether the data has been obtained, the data source, and whether it is an unaligned access.

[0058] The comparator is used to compare the memory disambiguation results of the DUT with the memory disambiguation results of the checker.

[0059] The beneficial effects of this invention are as follows:

[0060] This invention verifies the logic of memory disambiguation, supporting both single-core and multi-core memory disambiguation. The final result of memory disambiguation is whether the pipeline needs to be re-flushd, and from which instruction to start the re-flush. This verification method can accurately verify these two points. If the re-flush pipeline information is inconsistent with the DUT, an error message will be reported immediately, helping verification personnel to quickly and effectively debug the code. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a memory disambiguation verification structure diagram according to an embodiment of the present invention;

[0063] Figure 2 This is a flowchart of the single-core memory disambiguation verification process according to an embodiment of the present invention;

[0064] Figure 3 This is a flowchart of the multi-core memory disambiguation verification process according to an embodiment of the present invention. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Example 1

[0067] This embodiment provides a method for verifying memory disambiguation in a processor. The method verifies the memory disambiguation logic caused by single-core, multi-core, and unaligned access by monitoring the execution information of load and store instructions in the DUT. By comparing the memory disambiguation results of the DUT with the memory disambiguation results of the checker, it determines whether the pipeline needs to be re-flushd and from which instruction to start the re-flush. If the pipeline re-flush information is inconsistent with the DUT, an error message is immediately reported.

[0068] This embodiment of the method supports the verification of memory disambiguation in a single-core scenario, including memory disambiguation caused by store instructions and memory disambiguation caused by the removal of L1 cache lines.

[0069] The method in this embodiment supports memory disambiguation verification in multi-core systems, and the number of cores is configurable.

[0070] For processors that support unaligned access, a load / store instruction may be split into two memory accesses. The memory disambiguation generated by such instructions is more complex. This verification method supports the verification of memory disambiguation generated by unaligned access.

[0071] In this embodiment, the checker and DUT data are compared during the commit of the memory access instruction, and information is printed in real time, allowing verification personnel to quickly find the problem.

[0072] Example 2

[0073] Based on Example 1, this example provides a memory disambiguation verification process caused by the store instruction in a single core, as shown below. Figure 2 As shown, the details are as follows:

[0074] The DUT monitors the store instruction. After the store instruction obtains the physical address, the single-core memory disambiguation checker starts to search for whether there is a load instruction in the local core that meets the following three conditions.

[0075] a) The access scope of the Load directive overlaps with that of the store directive;

[0076] b) The Load instruction has already obtained the data;

[0077] c) The Load instruction is younger than the Store instruction in program order.

[0078] If a load instruction that meets the above conditions exists, the single-core memory disambiguation checker performs the following operation:

[0079] a) Compare the age information of these load instructions and find the oldest one.

[0080] b) Store the selected load instruction information into the commit information of the store instruction. The load instruction information includes its mark or program counter information in the instruction stream, which is the information for subsequent pipeline re-flush.

[0081] If no load instruction meets the above conditions, the single-core memory disambiguation checker invalidates the re-flush pipeline information in the commit information of the store instruction.

[0082] The comparator monitors the commit information of the store instruction in the DUT. When the store instruction commits, the comparator compares the re-flush pipeline information in the DUT commit information with the verified single-core memory disambiguation result. If they are inconsistent, an error is reported. The error information includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

[0083] Example 3

[0084] Based on Example 2, this example provides a memory disambiguation verification process for cache-kicked rows in a single core, as follows:

[0085] The system monitors whether any L1 cache lines are evicted from the DUT. If so, the single-core memory disambiguation checker begins to search for two types of load instructions that meet the conditions in the local core.

[0086] A first-class load instruction is flagged as needing to have its pipeline flags re-flushed if it meets the following three conditions:

[0087] a. The physical address of the Load instruction is the same cache line as the cache line that was evicted;

[0088] b. The Load instruction has already obtained the data;

[0089] c. The data for the Load instruction is not obtained from the local kernel forward;

[0090] If the second type of load instruction meets the following two conditions, then the load instruction may need to include pipeline re-flush information during the commit:

[0091] a. The physical address of the Load instruction is the same cache line as the cache line that was evicted;

[0092] b. The Load instruction has not yet received any data;

[0093] Find all load instructions that meet the above two conditions, and check if there are any load instructions of the second type that are older than load instructions of the first type.

[0094] If the above situation exists, find the oldest load instruction in the first type of load instructions that is younger than the second type of load instructions. This load instruction is the starting position where the pipeline needs to be re-flushd. The position information of this load instruction in the program will be marked on the second type of load instruction.

[0095] If none of the above conditions apply, then memory disambiguation is not required.

[0096] When memory disambiguation is required, wait for the commit information of the second type of load instruction in the DUT. When the load instruction commits, the comparator compares the re-flush pipeline information of the DUT and the checker. If they are inconsistent, an error is reported. The error message includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

[0097] Example 4

[0098] Based on Example 1, this example provides a multi-core memory disambiguation verification process, as follows: Figure 3 As shown, the details are as follows:

[0099] The system monitors the store instructions of each core in a multi-core system. When the data of a store instruction is visible to other cores, the multi-core memory disambiguation check whether there are two types of load instructions in other cores that meet the conditions.

[0100] A first-class load instruction is flagged as needing to have its pipeline flags re-flushed if it meets the following conditions:

[0101] The physical address of the d.Load instruction and the physical address of the store instruction are in the same cache line;

[0102] The e.Load instruction has already obtained the data;

[0103] The data for the f.Load instruction is not obtained from the local kernel forward;

[0104] If the second type of load instruction meets the following conditions, then the load instruction may need to include pipeline re-flush information during the commit:

[0105] c. The physical address of the Load instruction and the physical address of the store instruction are in the same cache line;

[0106] The d.Load instruction has not yet received any data;

[0107] Find all load instructions in each core that meet the above two conditions, and check if there are any load instructions of the second type that are older than load instructions of the first type in the same core.

[0108] If the above situation exists, find the oldest load instruction in the first type of load instructions that is younger than the second type of load instructions. This load instruction is the starting position where the pipeline needs to be re-flushd. The position information of this load instruction in the program will be marked on the second type of load instruction.

[0109] If none of the above conditions apply, then memory disambiguation is not required.

[0110] When memory disambiguation is required, wait for the commit information of the second type of load instruction in the DUT. When the load instruction commits, compare the re-flush pipeline information of the DUT and the checker. If they are inconsistent, an error is reported. The error message includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

[0111] Example 5

[0112] Based on Example 1, this example provides a memory disambiguation verification method for unaligned accesses, as follows:

[0113] If the load instruction is an unaligned access, the processor will generally split the load access into two aligned accesses. The checker will process these two accesses as two independent accesses and perform the above single-core and multi-core memory disambiguation checks. The difference is that when marking the pipeline information for re-flushing at the end, the position information of the load instruction is required.

[0114] If the store instruction is an unaligned access, the processor will generally split the store access into two aligned write operations. The checker will also process these two write operations into two independent write operations to perform the above single-core and multi-core memory disambiguation checks. The difference is that when marking the pipeline information for re-flushing, it needs to be marked in the information committed by the store instruction.

[0115] Example 6

[0116] This embodiment provides a verification system for memory disambiguation in a processor, the structure of which is shown in the figure below. Figure 1 As shown, it includes a memory access instruction monitor, a L1 cache monitor, a commit information monitor, a single-core memory disambiguation checker, a multi-core memory disambiguation checker, a load instruction queue for each core, and a comparator. The function of each component is explained below.

[0117] In this embodiment, the memory access instruction monitor is used to monitor the execution information of load and store instructions in the DUT. The execution information of load instructions is stored in the load instruction queue of each core, and the execution information of store instructions is simultaneously sent to the single-core memory disambiguation judge and the multi-core memory disambiguation judge.

[0118] In this embodiment, the Level 1 cache monitor is used to monitor whether there are cache lines being evicted from the Level 1 cache, and this information is sent to the single-core memory disambiguation judge.

[0119] This embodiment's commit information monitor is used to monitor the commit information of load / store instructions in the DUT, including pipeline re-flush information in the commit information. This is the result of DUT memory disambiguation and is used to compare with the memory disambiguation result of the checker.

[0120] This embodiment's single-core memory disambiguation checker is used to search the corresponding core's load instruction queue based on the input store instruction execution information and L1 cache kick-out information, determine whether the memory disambiguation conditions are met, and finally output the single-core memory disambiguation result.

[0121] The multi-core memory disambiguation checker in this embodiment is used to search the load instruction queues of other cores based on the input store instruction execution information, determine whether the memory disambiguation conditions are met, and finally output the multi-core memory disambiguation result.

[0122] In this embodiment, each core's load instruction queue is used to store the load instruction execution information input by the memory access instruction monitor into the corresponding core's load instruction queue. This information includes the access address of the load instruction, whether data has been obtained, the data source, and whether it is an unaligned access, etc.

[0123] The comparator in this embodiment is used to compare the memory disambiguation results of the DUT with the memory disambiguation results of the checker.

[0124] In summary, this invention verifies the logic of memory disambiguation, supporting both single-core and multi-core memory disambiguation. The final result of memory disambiguation is whether the pipeline needs to be re-flushd, and from which instruction to start the re-flush. This verification method can accurately verify these two points. If the re-flush pipeline information is inconsistent with the DUT, an error message will be reported immediately, helping verification personnel to quickly and effectively debug the code.

[0125] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for verifying memory disambiguation in a processor, characterized in that, The method verifies the memory disambiguation logic caused by single-core, multi-core, and unaligned access by monitoring the execution information of load and store instructions in the DUT. By comparing the memory disambiguation results of the DUT with the memory disambiguation results of the checker, it determines whether the pipeline needs to be re-flushed and from which instruction to start the re-flush. If the pipeline re-flush information is inconsistent with the DUT, an error message is immediately reported. In the method, single-core memory disambiguation includes memory disambiguation verification caused by store instructions and memory disambiguation verification caused by cache kick-out. In the method described above, the memory disambiguation verification process caused by the store instruction in a single core is as follows: The DUT monitors the store instruction. After the store instruction obtains the physical address, the single-core memory disambiguation checker starts to search for whether there is a load instruction in the core that meets the conditions. If there is a load instruction that meets the above conditions, the single-core memory disambiguation judge performs the following operations: compare the age information of these load instructions and find the oldest one; store the selected load instruction information into the commit information of the store instruction. The load instruction information includes its mark or program counter information in the instruction stream. If no load instruction meets the above conditions, the single-core memory disambiguation checker invalidates the re-flush pipeline information in the commit information of the store instruction. The comparator monitors the commit information of the store instruction in the DUT. When the store instruction commits, the comparator compares the re-flush pipeline information in the DUT commit information with the verified single-core memory disambiguation result. If they are inconsistent, an error is reported. The error information includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

2. The verification method for memory disambiguation in a processor according to claim 1, characterized in that, In the method described above, the load instruction that is satisfied is as follows: The access scope of the Load directive overlaps with that of the Store directive; The Load command has already obtained the data; The Load instruction is younger than the Store instruction in program order.

3. The verification method for memory disambiguation in a processor according to claim 1, characterized in that, In the method described, the memory disambiguation verification process caused by cache kick-out in a single core is as follows: The system monitors whether any L1 cache lines are evicted from the DUT. If so, the single-core memory disambiguation checker begins to search for two types of load instructions that meet the conditions in the local core. If the conditions are met, the first type of load instruction will be marked as needing to refresh the pipeline flag: If the second type of load instruction meets the conditions, the load instruction may need to include pipeline re-flush information when committing: find all load instructions that meet the above two conditions, and check if there are any second type load instructions that are older than the first type of load instructions. If the above situation exists, find the oldest load instruction in the first type of load instructions that is younger than the second type of load instructions. This load instruction is the starting position where the pipeline needs to be re-flushd. The position information of this load instruction in the program will be marked on the second type of load instruction. If none of the above conditions apply, then memory disambiguation is not required. When memory disambiguation is required, wait for the commit information of the second type of load instruction in the DUT. When the load instruction commits, the comparator compares the re-flush pipeline information of the DUT and the checker. If they are inconsistent, an error is reported. The error message includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

4. The verification method for memory disambiguation in a processor according to claim 3, characterized in that, In the method described above, the first type of load instruction satisfies the following condition: The physical address of the Load instruction is the same cache line as the cache line that was evicted. The Load command has already obtained the data; The data for the Load instruction is not obtained from the local core forward; The second type of load instruction meets the following conditions: The physical address of the Load instruction is the same cache line as the cache line that was evicted. The Load command has not yet received any data.

5. The verification method for memory disambiguation in a processor according to claim 1, characterized in that, The multi-core memory disambiguation verification process in the method is as follows: The system monitors the store instructions of each core in a multi-core system. When the data of a store instruction is visible to other cores, the multi-core memory disambiguation check whether there are two types of load instructions in other cores that meet the conditions. If the conditions are met, the first type of load instruction will be marked as needing to refresh the pipeline flag: If the second type of load instruction meets the conditions, the load instruction needs to include pipeline re-flush information when committing: find all load instructions in each core that meet the above two conditions, and find out if there are any second type load instructions that are older than the first type of load instructions in the same core. If the above situation exists, find the oldest load instruction in the first type of load instructions that is younger than the second type of load instructions. This load instruction is the starting position where the pipeline needs to be re-flushd. The position information of this load instruction in the program will be marked on the second type of load instruction. If none of the above conditions apply, then memory disambiguation is not required. When memory disambiguation is required, wait for the commit information of the second type of load instruction in the DUT. When the load instruction commits, compare the re-flush pipeline information of the DUT and the checker. If they are inconsistent, an error is reported. The error message includes whether the pipeline needs to be re-flushed, and if so, from which load instruction to start the re-flush.

6. The verification method for memory disambiguation in a processor according to claim 5, characterized in that, In the method described above, the first type of load instruction satisfies the following condition: The physical address of the Load instruction and the physical address of the Store instruction are in the same cache line; The Load command has already obtained the data; The data for the Load instruction is not obtained from the local core forward; The second type of load instruction meets the following conditions: The physical address of the Load instruction and the physical address of the Store instruction are in the same cache line; The Load command has not yet received any data.

7. The verification method for memory disambiguation in a processor according to claim 1, characterized in that, In the method described, the memory disambiguation verification caused by unaligned access is as follows: If the load instruction is an unaligned access, the processor splits the load access into two aligned accesses. The checker processes these two accesses as two independent accesses and performs memory disambiguation checks for single-core and multi-core processors. If the store instruction is an unaligned access, the processor splits the store access into two aligned write operations. The checker processes these two write operations into two independent write operations for single-core and multi-core memory disambiguation checks.

8. A verification system for memory disambiguation in a processor, the system being used to implement the verification method for memory disambiguation in a processor as described in any one of claims 1-5, characterized in that, include The memory access instruction monitor is used to monitor the execution information of load and store instructions in the DUT. The execution information of load instructions is stored in the load instruction queue of each core, and the execution information of store instructions is sent to both the single-core memory disambiguation judge and the multi-core memory disambiguation judge. The Level 1 cache monitor is used to monitor whether there are cache lines being evicted from the Level 1 cache and sends this information to the single-core memory disambiguation checker; the commit information monitor is used to monitor the commit information of load / store instructions in the DUT, including the pipeline re-flush information in the commit information, which is the result of DUT memory disambiguation and is compared with the memory disambiguation result of the checker. The single-core memory disambiguation checker is used to find the corresponding core's load instruction queue based on the input store instruction execution information and L1 cache kick-out information, determine whether the memory disambiguation conditions are met, and finally output the single-core memory disambiguation result. The multi-core memory disambiguation checker is used to search the load instruction queues of other cores based on the input store instruction execution information, determine whether the memory disambiguation conditions are met, and finally output the multi-core memory disambiguation results. Each core's load instruction queue is used to store the load instruction execution information input by the memory access instruction monitor into the corresponding core's load instruction queue. This information includes the access address of the load instruction, whether the data has been obtained, the data source, and whether it is an unaligned access. The comparator is used to compare the memory disambiguation results of the DUT with the memory disambiguation results of the checker.

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