A memory controller and chip product

Abstract

The embodiment of the present application provides a memory controller and chip product, the memory controller includes: an asynchronous FIFO module, configured to synchronize data or commands from a first clock domain and from a second clock domain, wherein the first clock domain is a clock domain defined by the clock frequency of the memory controller, and the second clock domain is a clock domain defined by the clock frequency of the memory; a processing unit, configured to obtain a sending interval delay value between any two adjacent commands according to a measured delay value and a protocol delay value between any two adjacent commands specified by the memory protocol, wherein the measured delay value is determined by measuring the interval time variation between two adjacent commands or two adjacent beats of data transmitted from the memory control module to the memory physical interface. Some embodiments of the present application effectively reduce the delay of the memory controller from sending commands to completing data transmission.

Description

Technical Field

[0001] The present application relates to the field of memory controllers, and specifically, embodiments of the present application relate to a memory controller and a chip product. Background Art

[0002] At present, the Soc system (i.e., system-level chip) includes: memory (e.g., Dram), memory controller (e.g., Dramcontroller) and memory physical interface (e.g., Dram Phy). The memory controller Dram controller is responsible for the scheduling of read and write instructions and the timing control of Dram, while Dram phy is responsible for encoding the scheduled instructions according to the requirements of Dram, sending the corresponding write data to the memory Dram, and receiving the memory data read from the memory Dram.

[0003] In the related art, the memory physical interface (e.g., Dram phy) and the memory (e.g., Dram) are designed according to the synchronous clock, that is, the digital logic of the memory physical interface (e.g., Dram phy) has the same clock frequency as the memory (e.g., Dram), or 1 / 2 or 1 / 4 of the clock frequency, that is, these units are in the synchronous clock domain.

[0004] Since the memory (e.g., Dram) needs to meet timing requirements when performing various operations such as read, write, and activate, the memory controller (e.g., Dram controller) needs to meet these requirements of the memory (e.g., Dram) when scheduling read and write commands, so the memory controller (e.g., Dram controller) meets these requirements through some timers. In order to accurately time in the related art, the main logic (including timers) of the memory controller (e.g., Dram controller) and the memory physical interface (e.g., Dram phy) are synchronous clock designs, which leads to a lot of delay in scheduling commands and transmitting data through the memory controller.

[0005] Therefore, how to improve the performance of the memory controller has become a technical problem that needs to be solved urgently. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a memory controller and a chip product, which can effectively reduce the delay of the memory controller in scheduling commands and transmitting data through some embodiments of the present application.

[0007] In a first aspect, some embodiments of the present application provide a memory controller, comprising: an asynchronous FIFO module, configured to synchronize data or commands originating from a first clock domain and from a second clock domain, wherein the first clock domain is a clock domain defined by a clock frequency of the memory controller, and the second clock domain is a clock domain defined by a clock frequency of the memory; a processing unit, configured to obtain a sending interval delay value between any two commands based on a measured delay value and a protocol delay value between any two adjacent commands specified by a memory protocol, wherein the measured delay value is determined by measuring a change in the interval time between two adjacent commands transmitted from the memory control module to the memory physical interface, and the size of the change is related to the asynchronous FIFO module.

[0008] Some embodiments of the present application change the synchronous design between the memory controller (e.g., Dram controller) and the memory physical interface / memory (e.g., Dram phy / Dram) to an asynchronous design, so that no matter what clock frequency the memory (or the memory physical interface) runs at, the memory controller (e.g., Dram controller) runs at a higher clock frequency, thereby reducing the delay in the internal controller scheduling commands and transmitting data.

[0009] In some embodiments of the present application, the any two adjacent commands include a previous command and a subsequent command, and the processing unit is configured to: obtain a protocol delay value for sending the previous command and the subsequent command through the memory protocol; obtain the measured delay value obtained in advance; and obtain the sending interval delay value according to the protocol delay value and the measured delay value.

[0010] Since the memory controller (e.g., Dram controller) and memory / memory physical interface (e.g., Dram / dram_phy) of some embodiments of the present application are asynchronously designed, the interval time t1 between two commands in the command scheduling of the memory controller is not necessarily equal to the interval time t2 between them being transmitted to the memory (e.g., Dram interface) interface. Therefore, it is necessary to correct the count value on the counter on the memory controller so that the commands output by the memory controller meet the protocol requirements.

[0011] In some embodiments of the present application, the processing unit is configured to: obtain, through the memory protocol, a protocol delay value for sending the previous command and the subsequent command that is greater than a first duration t1; obtain the minimum value of the interval time change delta1; and obtain the sending interval delay value by solving the following formula: sending interval delay value >= t1-delat1.

[0012] Some embodiments of the present application can ensure that two adjacent commands sent to the physical interface of the memory meet the requirements of the interface protocol by determining the sending interval delay value through this algorithm, thereby ensuring that these commands are accurately executed by the memory.

[0013] In some embodiments, the processor is configured to: obtain, through the memory protocol, a protocol delay value for sending the previous command and the next command that is less than the first duration t1; obtain the maximum value of the interval time variation as delta0; and obtain the sending interval delay value by solving the following formula: Sending interval delay value <t1-delat0。

[0014] Some embodiments of the present application can ensure that two adjacent commands sent to the physical interface of the memory meet the requirements of the interface protocol by determining the sending interval delay value through this algorithm, thereby ensuring that these commands are accurately executed by the memory.

[0015] In some embodiments, the processing unit is configured to perform a rounding operation on the sending interval delay value to obtain a target count value.

[0016] Some embodiments of the present application can obtain a value that can be counted by a counter through a rounding operation, thereby facilitating a memory controller to perform command or data scheduling.

[0017] In some embodiments, the memory controller further includes: a counter configured to count according to a time when the previous command is sent and the target count value.

[0018] Some embodiments of the present application use a counter to time the calculated sending interval delay value, thereby ensuring that the command scheduling result meets the memory requirement.

[0019] In some implementations, the memory controller further includes: a command scheduler configured to send the next command to the memory physical interface when the counter finishes counting the target count value.

[0020] Some embodiments of the present application implement the scheduling of commands by a memory controller through a command scheduler.

[0021] In a second aspect, some embodiments of the present application provide a chip product, comprising: a processor configured to send a request to a memory; a memory controller as described in any embodiment of the first aspect, configured to receive the request and convert the request into one or more command signals that satisfy a memory interface protocol.

[0022] In some embodiments, the processor and the memory controller operate in the same clock domain.

[0023] In some embodiments, the chip product further includes: a bus module configured to be connected to the processor and the memory controller, wherein the bus module and the memory controller operate in the same clock domain.

[0024] In some embodiments, the chip product further includes: a memory interface module and a memory, wherein the memory interface module and the memory controller operate in different clock domains. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 The block diagram of the chip products provided for related technologies;

[0027] Figure 2 One of the block diagrams of the chip product provided in the embodiment of the present application;

[0028] Figure 3 The second block diagram of the chip product provided in the embodiment of the present application;

[0029] Figure 4 A block diagram of the composition of a memory controller provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0031] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0032] Dram: refers to dynamic random access memory.

[0033] Dram controller: completes Dram memory read and write operations and scheduling, so that the read and write operations meet the relevant protocols and complete data transmission.

[0034] Dram PHY: Converts the scheduling commands of the Dram controller into control signals and data signals that meet the Dram spec standard, and completes data transmission between the Dram Controller and Dram, usually a mixed analog-digital circuit.

[0035] SOC: system on chip.

[0036] Clock synchronization: The frequencies of the clocks are equal or multiple of each other and maintain a fixed phase. Setup and hold timing checks are required between different clock trigger timing logics.

[0037] Clock asynchrony: There is no need to perform setup and hold timing checks between different clock-triggered timing logics.

[0038] Twr: write recovery time.

[0039] Related Art In order to enable the memory (e.g., Dram) to provide the maximum bandwidth, it is hoped that the memory (e.g., Dram) and the memory physical interface (e.g., Dram Phy) run at the maximum frequency. However, the memory controller (e.g., Dramcontroller) is a synthesizable design, and its operating frequency cannot be increased synchronously with the memory (e.g., Dram) and the memory physical interface (e.g., Dram Phy) frequencies. Since they are synchronously designed, when the operating frequency of the memory controller cannot reach the operating frequency of the memory (e.g., Dram) and the memory physical interface (e.g., Dram Phy), the memory controller can only run at 1 / 2 or even 1 / 4 of the frequency of the memory or the memory physical interface. When the operating frequency of the memory controller (e.g., Dram controller) decreases, its delay in scheduling commands and transmitting data will increase accordingly, which will have a greater impact on systems that are sensitive to memory access delays. For example, when DRAM works at 5600Mb / s, its clock runs at 2800Mhz. If the logic part of the DRAM controller cannot run at 2800Mhz, it can only run at 1400Mhz; if it cannot run at 1400Mhz, it can only run at 700Mhz, then the delay of the DRAM controller scheduling commands and transmitting data will almost increase several times accordingly.

[0040] like Figure 1As shown, in the traditional implementation, the main logic (specifically the interface with dram phy) of DRAM (as a specific example of memory), DRAM phy (as a specific example of memory physical interface) and DRAM controller (as a specific example of memory controller) are synchronously designed. Figure 1 The bus module or the processor may be synchronously designed or asynchronously designed, which is related to the system clock. Assume that it takes 10 clock cycles for the Dram controller to schedule commands and transmit data. If the maximum transmission rate of Dram supports up to 5600Mb / s, the clock frequency of Dram is 2.8GHz. Due to the requirements of synchronous clock design, the Dram controller is required to run at 2.8GHz, or 1.4GHz, or 700Mhz. If the maximum operating frequency of the Dram controller can only reach 1.35GHz, then it can only run at 700Mhz. At this time, it takes 10 clock cycles for the dram controller to schedule commands and transmit data = 1 / 0.7*10 = 14.3ns.

[0041] Some embodiments of the present application are at least for reducing the delay of scheduling commands and transmitting data of a memory controller. For example, in some embodiments of the present application, in order to reduce the delay of scheduling commands and transmitting data caused by the memory controller (e.g., Dram controller) running at a lower clock frequency, the synchronous design between the memory controller (e.g., dramcontroller) and the memory physical interface / memory (e.g., Dram phy / Dram) is changed to an asynchronous design, so that no matter what frequency the memory or the memory physical interface runs at, the memory controller runs at a higher frequency, thereby reducing the delay of scheduling commands and transmitting data.

[0042] Please see Figure 2 , Figure 2 The chip product 10 provided in some embodiments of the present application includes: a processor 100, a bus module 700, a memory controller 200, a memory physical interface 300 and a memory 400, wherein Figure 2 The memory controller operates in the first clock domain 600, while the memory physical interface 300 and the memory 400 operate in the second clock domain 500. That is, different from the related art, in some embodiments of the present application, the memory controller 200 and the memory (or memory physical interface) are asynchronously designed.

[0043] Figure 2The processor 100 is configured to send a request to the memory (for example, a request to read or write the memory). In some embodiments of the present application, the memory controller 200 is connected to the processor 100 via the bus module 700. In some embodiments of the present application, the memory controller and the bus module 700 or the processor 100 are synchronous designs, and in other embodiments of the present application, the memory controller and the bus module 700 or the processor 100 are asynchronous designs, which is not limited in the embodiments of the present application.

[0044] Figure 2 The memory controller 200 is configured to receive a request from the processor 100 and convert the request into one or more command signals that meet the interface protocol of the memory 400 .

[0045] In some embodiments, Figure 2 The memory physical interface module 300 and the memory controller 200 of the chip product operate in different clock domains.

[0046] For example, Figure 3 As shown, the chip product 10 of some embodiments of the present application includes: Dramcontroller, Dramphy and Dram, wherein the Dram controller module includes an asynchronous FIFO module, and the Dram controller module communicates with the memory physical interface 300 through the asynchronous FIFO module. Figure 1 The effects of the specific examples of chip products designed synchronously are different (for specific examples, please refer to the above Figure 1 Description), using some embodiments of the present application provided Figure 3 After the solution is implemented, the Dram controller can run at the highest frequency of 1.35GHz. At this time, the operating frequencies of Dram and Dram phy are 2.8Ghz, and the operating frequency of the dram controller is 1.35Ghz. Therefore, it takes 10 clock cycles = 1 / 1.35*10 = 7.4ns for the dram controller to schedule commands and transmit data, saving 6.9ns.

[0047] Combine the following Figure 4 The memory controller 200 provided by some embodiments of the present application is exemplified.

[0048] The memory controller 200 provided in some embodiments of the present application includes: an asynchronous FIFO module 240 and a processing unit 210 .

[0049] The asynchronous FIFO module 240 is configured to synchronize data or commands originating from a first clock domain and from a second clock domain, wherein the first clock domain is a clock domain defined by a clock frequency of a memory controller and the second clock domain is a clock domain defined by a clock frequency of a memory.

[0050] It is understandable that in large-scale ASIC or FPGA design, multi-clock systems are often inevitable, which creates the problem of data transmission in different clock domains. One of the better solutions is to use asynchronous FIFO as a buffer for data transmission in different clock domains, which can not only relax the timing requirements of data transmission in different clock domains, but also improve the transmission efficiency between them. Some embodiments of the present application use asynchronous FIFO modules to solve the problem of cross-clock domains. When applying, the depth of the asynchronous FIFO module needs to be considered according to the actual situation.

[0051] The processing unit 210 is configured to obtain a transmission interval delay value between any two adjacent commands according to a measured delay value and a protocol delay value between any two adjacent commands specified by a memory protocol, wherein the measured delay value is determined by measuring a change in the interval time between two adjacent commands or two adjacent beats of data transmitted from a memory control module to a memory physical interface. For example, the measured delay value is determined by measuring a change in the command interval time between two adjacent commands when they are transmitted from a memory control module to a memory physical interface.

[0052] It should be noted that the memory controller can at least be used for command scheduling, and to complete the scheduling of different commands, it is necessary to know in advance the delay between the scheduled commands. The memory controller and memory (or memory physical interface) of some embodiments of the present application are asynchronous designs. Therefore, if the count value of the counter of the memory controller is obtained directly according to the delay value specified by the memory protocol between the scheduled commands specified by the protocol corresponding to the memory connected to the memory controller, it will cause the memory to be unable to obtain the scheduled command. In order to solve this problem, some embodiments of the present application require the processing unit 210 to pre-calculate the sending interval delay value between adjacent commands, and the sending interval delay value is related to the delay value specified by the memory protocol.

[0053] That is to say, some embodiments of the present application change the synchronous design between the memory controller (e.g., Dramcontroller) and the memory physical interface / memory (e.g., Dram phy / Dram) to an asynchronous design, so that no matter what clock frequency the memory (or the memory physical interface) runs at, the memory controller (e.g., Dram controller) runs at a higher clock frequency, thereby reducing the delay in the internal control controller scheduling commands and transmitting data.

[0054] For example, in some embodiments of the present application, any two adjacent commands include a previous command and a subsequent command, and the processing unit 210 is configured to: obtain, through the memory protocol, protocol delay values for sending the previous command and the subsequent command; obtain the measured delay value measured in advance; and obtain the transmission interval delay value based on the protocol delay value and the measured delay value. Since the memory controller (e.g., Dram controller) and the memory / memory physical interface (e.g., Dram / dram_phy) in some embodiments of the present application are asynchronously designed, when the interval time t1 between the command schedules of two commands in the memory controller is not necessarily equal to the interval time t2 when they are transmitted to the memory (e.g., Dram interface) interface. Therefore, it is necessary to correct the count value on the counter of the memory controller so that the commands output by the memory controller meet the protocol requirements.

[0055] The following takes the dram controller as an example to illustrate the significance and method of obtaining the transmission interval delay value of the memory controller.

[0056] Since in some embodiments of the present application, the Dram controller and the Dram / Dram_phy are asynchronously designed, the interval time t1 between the command schedules of two adjacent commands in the memory controller is not necessarily equal to the interval time t2 when these two adjacent commands are transmitted to the Dram interface. Although t1 meets the Dram standard (i.e., t1 is the protocol delay value specified by the memory protocol), t2 does not necessarily meet the standard. Therefore, special processing is required during command scheduling to obtain the transmission interval delay value of any two adjacent commands. For a specific Dram controller, Dram phy, and Dram system, they operate at a specific frequency. When two commands are transmitted from the command scheduler to the Dram physical interface, the maximum change in their command interval is delta0 (which can be positive or negative), and the minimum change is delta1 (which can be positive or negative), and delta0 > delta1. For a specific system and a specific frequency, delta0 and delta1 are determined and can be measured.

[0057] If the Dram standard (i.e., the protocol corresponding to the memory) requires that the command interval between two commands >= t1, then due to the asynchronous design between the memory controller and the memory physical interface in the present application, in some embodiments of the present application, it is required that the interval between two adjacent commands >= t1 - delat1; if the Dram standard requires that the command interval between two adjacent commands < t1, then due to the asynchronous design between the memory controller and the memory physical interface in the present application, in some embodiments of the present application, it is required that the interval between two adjacent commands < t1 - delat0.

[0058] That is to say, in some embodiments of the present application, the delay value specified by the memory protocol for sending the previous command and the subsequent command is obtained through the attribute parameter value of the memory, including: obtaining the protocol delay value for sending the previous command and the subsequent command through the memory protocol is greater than the first time length t1; obtaining the minimum value of the interval time change is delta1; and obtaining the sending interval delay value by solving the following formula: sending interval delay value>=t1-delat1.

[0059] In other embodiments of the present application, the acquiring of the protocol delay value for sending the previous command and the subsequent command through the memory protocol includes: acquiring the delay value specified by the memory protocol for sending the previous command and the subsequent command to be less than the first duration t1; the acquiring of the measured delay value obtained in advance includes: acquiring the maximum value of the interval time change as delta0; the acquiring of the sending interval delay value according to the protocol delay value specified by the memory protocol and the measured delay value includes: obtaining the sending interval delay value by solving the following formula: sending interval delay value <= t1-delat0.

[0060] Some embodiments of the present application can ensure that two adjacent commands sent to the physical interface of the memory meet the requirements of the interface protocol by determining the sending interval delay value through this algorithm, thereby ensuring that these commands are accurately executed by the memory.

[0061] It is understandable that in order to enable the counter to accurately count according to the sending interval delay value, in some embodiments of the present application, the processing unit 210 is configured to perform a rounding operation on the sending interval delay value to obtain a target count value. Some embodiments of the present application can obtain a value that can be counted by the counter through the rounding operation, which facilitates the memory controller to perform command or data scheduling.

[0062] It should be noted that, in order to enable the memory controller to complete command scheduling, in some embodiments of the present application, the memory controller further includes: a counter 220 and a command scheduler 230, wherein the counter 220 is configured to count according to the time when the previous command is sent and the target count value. The command scheduler is configured to send the subsequent command to the memory physical interface when the counter finishes counting the target count value.

[0063] Some embodiments of the present application implement the scheduling of commands by a memory controller through a command scheduler.

[0064] For example, a method for obtaining the count value of a counter is exemplified by taking Dram memory and a specific command as an example. In some embodiments of the present application, the following method can be used to calculate Dram standard related parameters and count values. The following takes the Twr parameter as an example to show how to calculate the corresponding count value under DDR4400. For DDR4400, the clock frequency of its Dram / Dram_phy is 2.2Ghz, but due to the asynchronous design, the Dram controller can run at a maximum frequency of 2GHz, and its period T=500ps. The Dram standard requires Twr>29.965ns=29965ps, but due to the asynchronous design, some embodiments of the present application have delat0=800ps and delta1=-200ps, so the count value corresponding to the parameter is required to be calculated as follows: (29965-(-200)) / 500=60.33, rounded up to 61.

[0065] It is understandable that some embodiments of the present application can allow the DRAM controller to run at the maximum frequency, reduce the delay in scheduling commands and transmitting data, without being limited by the operating frequency of the DRAM, and allow each to maximize its performance without being interfered by the operating frequency of the other.

[0066] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0067] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0068] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0069] The above description is only an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0070] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0071] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A memory controller, characterized in that: The memory controller comprises: an asynchronous FIFO module configured to synchronize data or commands originating from a first clock domain and from a second clock domain, wherein the first clock domain is a clock domain defined by a clock frequency of a memory controller, and the second clock domain is a clock domain defined by a clock frequency of a memory; The processing unit is configured to obtain a sending interval delay value between any two adjacent commands according to a measured delay value and a protocol delay value between any two adjacent commands specified by a memory protocol, wherein the measured delay value is determined by measuring a change in an interval time between two adjacent commands or two adjacent beats of data transmitted from a memory control module to a memory physical interface; The any two adjacent commands include a previous command and a subsequent command, and the processing unit is configured to: Acquiring, through the memory protocol, a protocol delay value for sending the previous command and the next command that is greater than the first duration t1; The minimum value of the interval time change is obtained as delta1; The sending interval delay value is obtained by solving the following formula: The sending interval delay value>=t1-delat1.

2. The memory controller according to claim 1, wherein: The processing unit is configured to: Acquiring a protocol delay value for sending the previous command and the next command through the memory protocol; Obtaining the measured delay value obtained in advance; The sending interval delay value is obtained according to the protocol delay value and the measured delay value.

3. The memory controller according to claim 1, wherein: The processing unit is configured to: Acquiring, through the memory protocol, a protocol delay value for sending the previous command and the next command that is less than the first duration t1; The maximum value of the interval time variation is obtained as delta0; The sending interval delay value is obtained by solving the following formula: The sending interval delay value is <= t1-delat0.

4. The memory controller according to claim 2 or 3, characterized in that: The processing unit is configured to perform a rounding operation on the sending interval delay value to obtain a target count value.

5. The memory controller according to claim 4, wherein: The memory controller further includes: The counter is configured to count according to the time when the previous command is sent and the target count value.

6. The memory controller according to claim 5, wherein: The memory controller further includes: The command scheduler is configured to send the next command to the memory physical interface when the counter finishes counting the target count value.

7. A chip product, characterized in that: The chip products include: The processor is configured to send requests to the memory; The memory controller according to any one of claims 1 to 6, configured to receive the request and convert the request into one or more command signals that satisfy a memory interface protocol.

8. The chip product according to claim 7, characterized in that: The processor and the memory controller operate in the same clock domain.

9. The chip product according to claim 7, characterized in that: The chip product also includes: The bus module is configured to be connected to the processor and the memory controller, wherein the bus module and the memory controller operate in the same clock domain.

10. The chip product according to claim 7, characterized in that: The chip product further includes: a memory interface module and a memory, wherein the memory interface module and the memory controller operate in different clock domains.

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