Semiconductor package

Abstract

A semiconductor package can include a redistribution substrate having a first surface and a second surface opposite each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate can include a bottom bump pattern coupled to the solder pattern, a first redistribution pattern on the bottom bump pattern, the first redistribution pattern including a first through portion and a first wire portion, and a first seed pattern between the bottom bump pattern and the first redistribution pattern and on side surfaces of the first through portion and a bottom surface of the first wire portion. The bottom surface of the first seed pattern can be at a lower level than a top surface of the bottom bump pattern.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0115500, filed on September 9, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a semiconductor package, and more specifically, to a semiconductor package including a redistributed substrate and a method for manufacturing the same. Background Technology

[0004] A semiconductor package is a structure in which a semiconductor chip is configured to be used as part of an electronic product. Typically, a semiconductor package includes a printed circuit board (PCB) and a semiconductor chip mounted on the PCB, and the semiconductor package is electrically connected to the PCB via bonding wires or bonding bumps. In response to the development of the electronics industry, numerous studies have been conducted to improve the reliability of semiconductor packages. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a semiconductor package with improved reliability and durability, and a method for manufacturing the same.

[0006] According to an exemplary embodiment of the present invention, a semiconductor package may include: a redistribution substrate having a first surface and a second surface opposite to each other; a semiconductor chip located on the first surface of the redistribution substrate; and a solder pattern located on the second surface of the redistribution substrate. The redistribution substrate may include: a bottom bump pattern coupled to the solder pattern; a first redistribution pattern located on the bottom bump pattern, the first redistribution pattern including a first through-hole portion and a first conductive portion; and a first seed pattern located between the bottom bump pattern and the first redistribution pattern and located on the side surface of the first through-hole portion and the bottom surface of the first conductive portion. The bottom surface of the first seed pattern may be located at a lower level than the top surface of the bottom bump pattern.

[0007] According to an exemplary embodiment of the present invention, a semiconductor package may include: a redistribution substrate and a semiconductor chip on a first surface of the redistribution substrate. The redistribution substrate may include: a first redistribution pattern including a first through-hole portion and a first conductive portion; a second redistribution pattern located on the first redistribution pattern, the second redistribution pattern including a second through-hole portion and a second conductive portion; and a seed pattern located between the first redistribution pattern and the second redistribution pattern. The bottom surface of the seed pattern may be located within the first redistribution pattern. The seed pattern may include: an upper portion located on the side surface of the second through-hole portion and the bottom surface of the second conductive portion; a first lower portion located between the bottom surfaces of the central region of the first redistribution pattern and the second through-hole portion; and a second lower portion located within the first redistribution pattern and between the first lower portion and the upper portion. The thickness of the second lower portion of the seed pattern may be less than the thickness of the seed pattern on the bottom surface of the second conductive portion.

[0008] According to an exemplary embodiment of the present invention, a semiconductor package may include: a redistribution substrate having a first surface and a second surface opposite to each other; a semiconductor chip located on the first surface of the redistribution substrate; and a solder pattern located on the second surface of the redistribution substrate. The redistribution substrate may include: a bottom bump pattern coupled to the solder pattern; a first redistribution pattern located on the bottom bump pattern, the first redistribution pattern including a first through-hole portion and a first conductive portion; a first seed pattern located between the bottom bump pattern and the first redistribution pattern; a second redistribution pattern located on the first redistribution pattern, the second redistribution pattern including a second through-hole portion and a second conductive portion; a second seed pattern located between the first redistribution pattern and the second redistribution pattern; a third redistribution pattern located on the second redistribution pattern, the third redistribution pattern including a third through-hole portion and a third conductive portion; a third seed pattern located between the second redistribution pattern and the third redistribution pattern; and a bonding pad electrically connected to the third redistribution pattern. The bottom surface of the first seed pattern may be located within the bottom bump pattern. The bottom surface of the second seed pattern may be located within the first redistribution pattern. The bottom surface of the third seed pattern may be located within the second redistribution pattern. The first seed pattern may include: an upper portion located on the side surface of the first through-part and the bottom surface of the first guide portion; a first lower portion located between the bottom protrusion pattern and the bottom surface of the central region of the first through-part; and a second lower portion located within the bottom protrusion pattern and between the first lower portion and the upper portion. The second seed pattern may include: an upper portion located on the side surface of the second through-part and the bottom surface of the second guide portion; a first lower portion located between the bottom surface of the first redistribution pattern and the central region of the second through-part; and a second lower portion located within the first redistribution pattern and between the first lower portion and the upper portion of the second seed pattern. The third seed pattern may include: an upper portion located on the side surface of the third through-part and the bottom surface of the third guide portion; a first lower portion located between the bottom surface of the second redistribution pattern and the central region of the third through-part; and a second lower portion located within the second redistribution pattern and between the first lower portion and the upper portion of the third seed pattern. The first thickness of the first seed pattern on the bottom surface of the first guide portion may be greater than the second thickness of the second lower portion of the first seed pattern. The third thickness of the second seed pattern on the bottom surface of the second conductor portion may be greater than the fourth thickness of the second lower portion of the second seed pattern. The fifth thickness of the third seed pattern on the bottom surface of the third conductor portion may be greater than the sixth thickness of the second lower portion of the third seed pattern. Attached Figure Description

[0009] The exemplary embodiments will become clearer from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0010] Figure 1AThis is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0011] Figure 1B It is shown Figure 1A An enlarged sectional view of part I.

[0012] Figure 1C It is shown Figure 1B Enlarged sectional view of part II.

[0013] Figure 1D This is a cross-sectional view showing a typical example of a redistribution pattern.

[0014] Figure 1E It is shown Figure 1B Enlarged sectional view of part III.

[0015] Figure 1F It is shown Figure 1A Enlarged sectional view of part IV.

[0016] Figure 2A This is a cross-sectional view illustrating a bottom protrusion pattern, a first seed pattern, and a first redistribution pattern according to an exemplary embodiment of the present invention.

[0017] Figure 2B This is a cross-sectional view illustrating a first redistribution pattern, a second seed pattern, and a second redistribution pattern according to an exemplary embodiment of the concept of the present invention.

[0018] Figure 3A This is a cross-sectional view illustrating a bottom protrusion pattern, a first seed pattern, and a first redistribution pattern according to an exemplary embodiment of the present invention.

[0019] Figure 3B This is a cross-sectional view illustrating a first redistribution pattern, a second seed pattern, and a second redistribution pattern according to an exemplary embodiment of the concept of the present invention.

[0020] Figure 4A This is a cross-sectional view illustrating an exemplary embodiment of a redistributed substrate according to a concept of the present invention.

[0021] Figure 4B This is a cross-sectional view illustrating an exemplary embodiment of a redistributed substrate according to a concept of the present invention.

[0022] Figure 5A This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0023] Figure 5B It is shown Figure 5A An enlarged sectional view of part I.

[0024] Figure 6AThis is a cross-sectional view illustrating an exemplary embodiment of a redistributed substrate according to a concept of the present invention.

[0025] Figure 6B This is a cross-sectional view illustrating an exemplary embodiment of a redistributed substrate according to a concept of the present invention.

[0026] Figure 7 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0027] Figures 8A to 8E , Figure 8G and Figures 8I to 8T This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

[0028] Figure 8F It is shown Figure 8E An enlarged sectional view of part V.

[0029] Figure 8H It is shown Figure 8G An enlarged sectional view of part V.

[0030] Figure 9 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0031] Figure 10A This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0032] Figure 10B It is shown Figure 10A An enlarged sectional view of part VI.

[0033] Figure 11 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0034] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials utilized in particular exemplary embodiments and to supplement the description provided below. However, these figures are not necessarily to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments, and should not be construed as limiting or restricting the range or characteristics of the values ​​contained in the exemplary embodiments. For example, for clarity, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0035] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0036] Figure 1AThis is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention. Figure 1B It is shown Figure 1A An enlarged sectional view of part I. Figure 1C It is shown Figure 1B Enlarged sectional view of part II. Figure 1D This is a cross-sectional view showing a typical example of a redistribution pattern. Figure 1E It is shown Figure 1B Enlarged sectional view of part III. Figure 1F It is shown Figure 1A Enlarged sectional view of part IV.

[0037] Reference Figure 1A , Figure 1B , Figure 1C , Figure 1E and Figure 1F The semiconductor package 10 may include a redistribution substrate 100, a semiconductor chip 200, and / or a solder pattern 500. The redistribution substrate 100 may have a first surface and a second surface opposite to each other. The first surface of the redistribution substrate 100 may be a top surface, and the second surface may be a bottom surface.

[0038] Solder pattern 500 may be disposed on a second surface of redistribution substrate 100. Solder pattern 500 may be used as a terminal of semiconductor package 10. Solder pattern 500 may include solder balls, solder bumps, solder pillars and / or combinations thereof. Solder pattern 500 may include solder material. In this specification, solder material may include tin, bismuth, lead, silver or alloys thereof.

[0039] The redistribution substrate 100 may include a bottom bump pattern 160, a first redistribution pattern 110, a second redistribution pattern 120, a third redistribution pattern 130, a fourth redistribution pattern 140, bonding pads 150, a first seed pattern 115, a second seed pattern 125, a third seed pattern 135, a fourth seed pattern 145, a pad seed pattern 155, and / or an insulating layer. The insulating layer may include first to fifth insulating layers 101, 102, 103, 104, and 105 stacked sequentially.

[0040] The bottom bump pattern 160 may be disposed in the first insulating layer 101. The solder pattern 500 may be disposed on the bottom surface 160b of the bottom bump pattern 160. The bottom bump pattern 160 may be used as a pad for the solder pattern 500. The bottom bump pattern 160 may be formed of at least one metallic material (e.g., copper) or may include at least one metallic material (e.g., copper).

[0041] The first insulating layer 101 can be disposed on the top and side surfaces of the bottom protrusion pattern 160. The first insulating layer 101 can be the bottommost insulating layer. The bottom surface 160b of the bottom protrusion pattern 160 may not be covered by the first insulating layer 101. Figure 1C As shown, the bottom surface 160b of the bottom protrusion pattern 160 may be located at a higher level than the bottom surface 101b of the first insulating layer 101. In this specification, "horizontal" may mean vertical, and the difference in level can be measured in a direction perpendicular to the bottom surface 101b of the first insulating layer 101. Additionally, without additional limitations, the expression "vertical" may mean a direction perpendicular to the bottom surface 101b of the first insulating layer 101. The bottom surface 101b of the first insulating layer 101 may correspond to the bottom surface of the redistribution substrate 100. The first insulating layer 101 may be formed of or may include an organic material (e.g., a photopolymer). In this specification, the photopolymer may include at least one of, for example, photosensitive polyimide, polybenzoxazole, phenolic polymer, or benzocyclobutene polymer.

[0042] The first redistribution pattern 110 may be disposed on the bottom protrusion pattern 160 and may be electrically connected to the bottom protrusion pattern 160. The first redistribution pattern 110 may be disposed in the first insulating layer 101 and on the top surface of the first insulating layer 101. The first redistribution pattern 110 may be formed of a metallic material (e.g., copper), or may include a metallic material (e.g., copper).

[0043] The first redistribution pattern 110 may include a first through-hole portion 110V and a first conductive portion 110W. The first through-hole portion 110V may be disposed in the first insulating layer 101. The first through-hole portion 110V may be located between the bottom protrusion pattern 160 and the first conductive portion 110W. In this specification, the through-hole portion of the conductive element may be a portion for vertical connection. The width of the first through-hole portion 110V may be smaller than the width of the bottom surface 160b of the bottom protrusion pattern 160, but the inventive concept is not limited to this example.

[0044] The first through-hole portion 110V may be a protrusion extending into the bottom protrusion pattern 160. For example... Figure 1CAs shown, the bottom surface 110b of the first through-hole portion 110V may be located at a lower level than the top surface 160a of the bottom protrusion pattern 160. The bottom surface 110b of the first through-hole portion 110V may include portions with different slopes. The first through-hole portion 110V may include a first convex portion 111, which may correspond to the lower part of the first through-hole portion 110V. The first convex portion 111 may be disposed in the bottom protrusion pattern 160. For example, the bottom surface 110b of the first through-hole portion 110V may have a downwardly convex shape. When viewed in a plan view, the bottom surface 110b of the first through-hole portion 110V may have a central region and an edge region. The edge region of the first through-hole portion 110V may be located between the central region and the side surface of the first convex portion 111. When viewed in a plan view, the edge region of the first through-hole portion 110V may be configured to surround the central region. The central region of the first convex portion 111 may protrude toward the bottom surface 160b of the bottom protrusion pattern 160. For example, the bottom surface 110b of the central region of the first through-hole portion 110V may be located at a lower level than the bottom surface 110b of the edge region. The first protruding portion 111 of the first through-hole portion 110V may protrude laterally. For example, at the top surface 160a of the bottom protrusion pattern 160, the width of the first protruding portion 111 may be greater than the width of the first through-hole portion 110V. The width of the first protruding portion 111 may be measured at a position between the bottom surface 110b of the first through-hole portion 110V and the top surface 160a of the bottom protrusion pattern 160.

[0045] A first conductor portion 110W may be disposed on and connected to a first through portion 110V, and there is no boundary between them. The width or length of the first conductor portion 110W may be greater than the width or length of the first through portion 110V. The first conductor portion 110W may extend to cover a portion of the top surface of the first insulating layer 101 and may have a longitudinal axis extending in a first direction. The first direction may be parallel to the bottom surface 101b of the first insulating layer 101. For example, the top surface of the first conductor portion 110W may be substantially parallel to the bottom surface 101b of the first insulating layer 101.

[0046] The first seed pattern 115 may be located between the bottom bump pattern 160 and the first redistribution pattern 110, and between the first insulating layer 101 and the first redistribution pattern 110. The first seed pattern 115 may directly contact the bottom bump pattern 160 and the first redistribution pattern 110. The first seed pattern 115 may not extend to the side surface of the first conductor portion 110W. The first seed pattern 115 may be formed of or include at least one conductive material (e.g., copper, titanium, and alloys thereof). The first seed pattern 115 may serve as a barrier layer and may reduce or prevent material diffusion in the first redistribution pattern 110.

[0047] The bottom surface 115b of the first seed pattern 115 may be disposed within the bottom protrusion pattern 160. For example, the bottom surface 115b of the first seed pattern 115 may be located at a lower level than the top surface 160a of the bottom protrusion pattern 160. The bottom surface 115b of the first seed pattern 115 may have a convex shape. However, the shape of the bottom surface 115b of the first seed pattern 115 is not limited to this example.

[0048] The first seed pattern 115 may include a first lower portion 1151, a second lower portion 1152, and an upper portion 1155. The upper portion 1155 of the first seed pattern 115 may be located at a level higher than the top surface 160a of the bottom protrusion pattern 160. The upper portion 1155 of the first seed pattern 115 may be located between the side surface of the first through portion 110V and the first insulating layer 101, and between the bottom surface 110d of the first conductor portion 110W and the first insulating layer 101. The upper portion 1155 of the first seed pattern 115 may have a first thickness T11. The first thickness T11 may be measured between the bottom surface 110d of the first conductor portion 110W and the first insulating layer 101. The first thickness T11 may be measured between the bottom surface 110d of the first conductor portion 110W and the first insulating layer 101. to Within the range. Each of the first lower portion 1151 and the second lower portion 1152 of the first seed pattern 115 may be located between the bottom protrusion pattern 160 and the first redistribution pattern 110. The first lower portion 1151 and the second lower portion 1152 of the first seed pattern 115 may cover the first protrusion 111. The first lower portion 1151 of the first seed pattern 115 may be disposed on the bottom surface of the central region of the first through portion 110V. The second lower portion 1152 of the first seed pattern 115 may be located between the first lower portion 1151 and the upper portion 1155. The second lower portion 1152 of the first seed pattern 115 may be disposed on the bottom surface 110b of the edge region of the first through portion 110V. The bottom surface 115b of the second lower portion 1152 of the first seed pattern 115 may be located at a higher level than the bottom surface 115b of the first lower portion 1151. The second lower portion 1152 of the first seed pattern 115 may have a second thickness T12. The second thickness T12 may be less than the first thickness T11. For example, the second thickness T12 can be 30% to 80% of the first thickness T11. For example, the second thickness T12 can be... to Within the range.

[0049] Figure 1D This is a cross-sectional view showing a conventional example of the first redistribution pattern.

[0050] Reference Figure 1D A first seed pattern 115A may be disposed on a bottom protrusion pattern 160, and a first redistribution pattern 110 may not protrude into the bottom protrusion pattern 160. The bottom surface 115bb of the first seed pattern 115A may be flat. For example, the bottom surface 115bb of the first seed pattern 115A may be parallel to a first direction. If stress is applied between the first seed pattern 115A and the bottom protrusion pattern 160, a crack Cr may appear between them. Stress may occur during repeated operation of the semiconductor package or during the manufacture of the semiconductor package. The bottom surface 115bb of the first seed pattern 115A may have a flat shape and may be parallel to the first direction, and the crack Cr may propagate quickly and easily along the boundary between the bottom surface 115bb of the first seed pattern 115A and the top surface 160a of the bottom protrusion pattern 160. In some example embodiments, the first seed pattern 115A and the first redistribution pattern 110 may be separable from the bottom protrusion pattern 160.

[0051] Return to reference Figure 1CBecause the first seed pattern 115 and the first through-hole portion 110V are disposed in the bottom protrusion pattern 160, the contact area between the first seed pattern 115 and the bottom protrusion pattern 160 can be increased. Therefore, the first seed pattern 115 can more robustly bond to the bottom protrusion pattern 160, and cracking can be reduced or prevented. The bonding strength between the first redistribution pattern 110 and the bottom protrusion pattern 160 can be improved. Cracks are less likely to propagate from a surface in one direction to a surface in the opposite direction. The bottom surface 115b of the first seed pattern 115 may include portions with different slopes. Therefore, even if a crack forms between the first seed pattern 115 and the bottom protrusion pattern 160, crack propagation can be reduced or prevented. The reliability and / or durability of the semiconductor package 10 can be improved. In an example embodiment where the second thickness T12 is 30% to 80% of the first thickness T11, cracking and crack propagation between the first seed pattern 115 and the bottom protrusion pattern 160 can be reduced or prevented more effectively.

[0052] like Figure 1A and Figure 1B As shown, a second insulating layer 102 may be disposed on the first insulating layer 101 to cover the first redistribution pattern 110. For example, the second insulating layer 102 may cover the side and top surfaces of the first conductor portion 110W. The second insulating layer 102 may comprise the same material as the first insulating layer 101. For example, the second insulating layer 102 may comprise a photosensitive polymer. The second insulating layer 102 and the first insulating layer 101 may be configured so that there is no clear boundary between them.

[0053] The second redistribution pattern 120 may be disposed on the first redistribution pattern 110 and electrically connected to the first redistribution pattern 110. The second redistribution pattern 120 may include a second conductor portion 120W and a second through portion 120V. The second through portion 120V may be disposed in the second insulating layer 102 and may be located between the first redistribution pattern 110 and the second conductor portion 120W. The second through portion 120V may be a protrusion extending into the first redistribution pattern 110. For example, as... Figure 1EAs shown, the bottom surface 120b of the second through-hole portion 120V may be located at a lower level than the top surface 110a of the first redistribution pattern 110. The top surface 110a of the first redistribution pattern 110 may correspond to the top surface of the first conductor portion 110W. The bottom surface 120b of the second through-hole portion 120V may include portions with different slopes. For example, the second through-hole portion 120V may include a second convex portion 121, which may be disposed in the first redistribution pattern 110. The second convex portion 121 may correspond to the lower part of the second through-hole portion 120V. The bottom surface 120b of the second through-hole portion 120V may have a downwardly convex shape. When viewed in a plan view, the bottom surface 120b of the second through-hole portion 120V may have a central region and an edge region. The edge region of the second through-hole portion 120V may be located between the central region and the side surface of the second convex portion 121. The bottom surface 120b of the central region of the second through-section 120V can be located at a lower level than the bottom surface 120b of the edge region. The second convex portion 121 of the second through-section 120V can also protrude laterally. For example, at the top surface 110a of the first redistribution pattern 110, the width of the second convex portion 121 can be greater than the width of the second through-section 120V. The width of the second convex portion 121 can be measured at a position between the bottom surface 120b of the second through-section 120V and the top surface 110a of the first redistribution pattern 110.

[0054] The second conductor portion 120W may be disposed on and connected to the second through portion 120V, and there is no boundary between them. The width or length of the second conductor portion 120W may be greater than the width or length of the second through portion 120V. The second conductor portion 120W may extend to the top surface of the second insulating layer 102. For example, the top surface of the second conductor portion 120W may be parallel to the first direction.

[0055] The second seed pattern 125 may be located between the first redistribution pattern 110 and the second redistribution pattern 120, and between the second insulating layer 102 and the second redistribution pattern 120. The second seed pattern 125 may directly contact the first redistribution pattern 110 and the second redistribution pattern 120. The bottom surface 120b of the second seed pattern 125 may be disposed in the first redistribution pattern 110. For example, the bottom surface 120b of the second seed pattern 125 may be located at a lower level than the top surface 110a of the first redistribution pattern 110. Therefore, the contact area between the second seed pattern 125 and the first redistribution pattern 110 may be increased. The second seed pattern 125 and the second through-hole portion 120V may be robustly coupled to the first redistribution pattern 110, and may reduce or prevent cracking. The second seed pattern 125 may be formed of at least one conductive material (e.g., copper, titanium, and alloys thereof), or may include at least one conductive material (e.g., copper, titanium, and alloys thereof). The second seed pattern 125 can be used as a barrier layer and can reduce or prevent material diffusion in the second redistribution pattern 120.

[0056] The second seed pattern 125 may include a first lower portion 1251, a second lower portion 1252, and an upper portion 1255. The upper portion 1255 of the second seed pattern 125 may be located at a higher level than the top surface 110a of the first redistribution pattern 110. The upper portion 1255 of the second seed pattern 125 may be located between the side surface of the second through portion 120V and the second insulating layer 102, and between the bottom surface 120d of the second conductor portion 120W and the second insulating layer 102. On the bottom surface 120d of the second conductor portion 120W, the upper portion 1255 of the second seed pattern 125 may have a third thickness T13. For example, the third thickness T13 may be measured between the bottom surface 120d of the second conductor portion 120W and the second insulating layer 102. The third thickness T13 may be... to Within the range. The first lower portion 1251 and the second lower portion 1252 of the second seed pattern 125 can be located between the first redistribution pattern 110 and the second redistribution pattern 120, and can cover the second convex portion 121. The first lower portion 1251 of the second seed pattern 125 can be disposed on the bottom surface 120b of the central region of the second through portion 120V. The second lower portion 1252 of the second seed pattern 125 can be located between the first lower portion 1251 and the upper portion 1255. The second lower portion 1252 of the second seed pattern 125 can be disposed on the bottom surface 120b of the edge region of the second through portion 120V. The bottom surface 125b of the second lower portion 1252 of the second seed pattern 125 can be located at a higher level than the bottom surface 125b of the first lower portion 1251. The second lower portion 1252 of the second seed pattern 125 can have a fourth thickness T14. The fourth thickness T14 can be less than the third thickness T13. For example, the fourth thickness T14 can be 30% to 80% of the third thickness T13. For example, the fourth thickness T14 can be... to Within the range.

[0057] The bottom surface 125b of the second seed pattern 125 may include portions with different slopes. Therefore, even if a crack forms between the second seed pattern 125 and the first redistribution pattern 110, crack propagation can be reduced or prevented. In an example embodiment where the fourth thickness T14 is 30% to 80% of the third thickness T13, crack propagation between the second seed pattern 125 and the first redistribution pattern 110 can be reduced or prevented more effectively. The reliability and durability of the semiconductor package 10 can be improved.

[0058] like Figure 1A and Figure 1B As shown, a third insulating layer 103 may be disposed on the second insulating layer 102 to cover the second redistribution pattern 120. For example, the third insulating layer 103 may cover the side and top surfaces of the second conductor portion 120W. For example, the third insulating layer 103 may comprise a photosensitive polymer. The third insulating layer 103 may comprise the same material as the second insulating layer 102. The third insulating layer 103 and the second insulating layer 102 may be configured so that there is no clear boundary between them.

[0059] The third redistribution pattern 130 may be disposed on the second redistribution pattern 120 and may be electrically connected to the second redistribution pattern 120. The third redistribution pattern 130 may include a third conductor portion 130W and a third through portion 130V. The third through portion 130V may be disposed in the third insulating layer 103 and may be located between the second redistribution pattern 120 and the third conductor portion 130W. The third through portion 130V may be a protrusion extending into the second redistribution pattern 120. For example, as... Figure 1EAs shown, the bottom surface 130b of the third through-hole portion 130V can be located at a lower level than the top surface of the second redistribution pattern 120. The top surface of the second redistribution pattern 120 can correspond to the top surface of the second conductor portion 120W. The shape of the third through-hole portion 130V can be similar to... Figure 1C The first penetration section is 110V or Figure 1E The second penetration section is the same as or substantially the same as the 120V. For example, such as Figure 1F As shown, the third through-hole portion 130V may include a third protruding portion 131, which may be disposed in the second redistribution pattern 120. The third protruding portion 131 may correspond to the lower part of the third through-hole portion 130V. The bottom surface 130b of the central region of the third through-hole portion 130V may be located at a lower level than the bottom surface 130b of the edge region. The bottom surface 130b of the third through-hole portion 130V may have a downwardly convex shape. The third protruding portion 131 of the third through-hole portion 130V may also protrude laterally.

[0060] The third conductor portion 130W may be disposed on and connected to the third through portion 130V, and there is no boundary between them. The width of the third conductor portion 130W may be greater than the width of the third through portion 130V. The third conductor portion 130W may extend to the top surface of the third insulating layer 103. The top surface of the third conductor portion 130W may be parallel to the first direction.

[0061] The third seed pattern 135 may be located between the second redistribution pattern 120 and the third redistribution pattern 130, and between the third insulating layer 103 and the third redistribution pattern 130. The third seed pattern 135 may not extend to the side surface of the third conductor portion 130W. The bottom surface 135b of the third seed pattern 135 may be disposed within the second redistribution pattern 120. For example, the bottom surface 135b of the third seed pattern 135 may be located at a lower level than the top surface of the second redistribution pattern 120. Therefore, the contact area between the third seed pattern 135 and the second redistribution pattern 120 can be increased. Thus, the third seed pattern 135 can be robustly bonded to the second redistribution pattern 120, and cracks between the third seed pattern 135 and the second redistribution pattern 120 can be reduced or prevented. The third seed pattern 135 may be formed of at least one conductive material (e.g., copper, titanium, and alloys thereof) or may include at least one conductive material (e.g., copper, titanium, and alloys thereof).

[0062] The third seed pattern 135 may include a first lower portion 1351, a second lower portion 1352, and an upper portion 1355. The upper portion 1355 of the third seed pattern 135 may be located at a higher level than the top surface of the second redistribution pattern 120. The upper portion 1355 of the third seed pattern 135 may be located between the side surface of the third through portion 130V and the third insulating layer 103, and between the bottom surface of the third conductor portion 130W and the third insulating layer 103. The upper portion 1355 of the third seed pattern 135 may have a fifth thickness T15 on the bottom surface of the third conductor portion 130W. The fifth thickness T15 may be... to The first lower portion 1351 and the second lower portion 1352 of the third seed pattern 135 may be located between the second redistribution pattern 120 and the third redistribution pattern 130. The first lower portion 1351 of the third seed pattern 135 may be disposed on the bottom surface 130b of the central region of the third through portion 130V. The second lower portion 1352 of the third seed pattern 135 may be disposed on the bottom surface 130b of the edge region of the third through portion 130V. The second lower portion 1352 of the third seed pattern 135 may be located between the first lower portion 1351 and the upper portion 1355. The bottom surface 135b of the third seed pattern 135 may include portions with different slopes. The bottom surface 135b of the second lower portion 1352 of the third seed pattern 135 may be located at a higher level than the bottom surface 135b of the first lower portion 1351. The second lower portion 1352 of the third seed pattern 135 may have a sixth thickness. The sixth thickness may be less than the fifth thickness T15. For example, the sixth thickness may be 30% to 80% of the fifth thickness T15. For example, the sixth thickness T16 can be... to Within the range. Therefore, the propagation of cracks between the third seed pattern 135 and the second redistribution pattern 120 can be reduced or prevented.

[0063] A fourth insulating layer 104 may be disposed on the third insulating layer 103 to cover the third redistribution pattern 130. For example, the fourth insulating layer 104 may cover the side and top surfaces of the third conductor portion 130W. For example, the fourth insulating layer 104 may comprise a photosensitive polymer. The fourth insulating layer 104 may be formed of the same material as the third insulating layer 103 or may comprise the same material as the third insulating layer 103. The fourth insulating layer 104 and the third insulating layer 103 may be configured such that there is no clear boundary between them.

[0064] A fourth redistribution pattern 140 may be disposed on and electrically connected to the third redistribution pattern 130. The fourth redistribution pattern 140 may include a fourth conductor portion 140W and a fourth through portion 140V. The fourth through portion 140V may be disposed in the fourth insulating layer 104 and may be located between the third redistribution pattern 130 and the fourth conductor portion 140W. The shape of the fourth through portion 140V may be similar to that of the first through portion 110V described above (e.g., see...). Figure 1C (Identical or similar.) For example, the fourth through-hole 140V could be a protrusion extending into the third redistribution pattern 130. Figure 1F As shown, the bottom surface 140b of the fourth through-hole portion 140V may be located at a lower level than the top surface of the third redistribution pattern 130. The fourth through-hole portion 140V may include a fourth protrusion 141, which may be disposed in the third redistribution pattern 130. The fourth protrusion 141 may be the lower part of the fourth through-hole portion 140V. The bottom surface 140b of the fourth through-hole portion 140V may have a downwardly convex shape. The bottom surface 140b of the central region of the fourth through-hole portion 140V may be located at a lower level than the bottom surface 140b of the edge region. The fourth protrusion 141 of the fourth through-hole portion 140V may also protrude laterally.

[0065] The fourth conductor portion 140W can be disposed on and connected to the fourth through portion 140V, and there is no boundary between them. The width of the fourth conductor portion 140W can be greater than the width of the fourth through portion 140V. The fourth conductor portion 140W can extend to the top surface of the fourth insulating layer 104.

[0066] The fourth seed pattern 145 may be located between the third redistribution pattern 130 and the fourth redistribution pattern 140, and between the fourth insulating layer 104 and the fourth redistribution pattern 140. The fourth seed pattern 145 may not extend to the side surface of the fourth conductor portion 140W. The bottom surface 145b of the fourth seed pattern 145 may be disposed within the third redistribution pattern 130. For example, the bottom surface 145b of the fourth seed pattern 145 may be located at a lower level than the top surface of the third redistribution pattern 130. Therefore, the contact area between the fourth seed pattern 145 and the third redistribution pattern 130 can be increased. The fourth seed pattern 145 can be robustly bonded to the third redistribution pattern 130, and cracks between the fourth seed pattern 145 and the third redistribution pattern 130 can be reduced or prevented. The fourth seed pattern 145 may be formed of at least one conductive material (e.g., copper, titanium, and alloys thereof), or may include at least one conductive material (e.g., copper, titanium, and alloys thereof).

[0067] The fourth seed pattern 145 may include a first lower portion 1451, a second lower portion 1452, and an upper portion 1455. The upper portion 1455 of the fourth seed pattern 145 may be located at a higher level than the top surface of the third redistribution pattern 130. The upper portion 1455 of the fourth seed pattern 145 may be located between the side surface of the fourth through portion 140V and the fourth insulating layer 104, and between the bottom surface of the fourth conductor portion 140W and the fourth insulating layer 104. The upper portion 1455 of the fourth seed pattern 145 may have a seventh thickness T17 on the bottom surface of the fourth conductor portion 140W. The seventh thickness T17 may be... to Within the range. The first lower portion 1451 and the second lower portion 1452 of the fourth seed pattern 145 can be located between the third redistribution pattern 130 and the fourth redistribution pattern 140. The first lower portion 1451 of the fourth seed pattern 145 can be disposed on the bottom surface 140b of the central region of the fourth through portion 140V. The second lower portion 1452 of the fourth seed pattern 145 can be disposed between the first lower portion 1451 and the upper portion 1455. The second lower portion 1452 of the fourth seed pattern 145 can be disposed on the bottom surface 140b of the edge region of the fourth through portion 140V. The bottom surface 145b of the fourth seed pattern 145 may include portions with different slopes. The bottom surface 145b of the second lower portion 1452 of the fourth seed pattern 145 can be located at a higher level than the bottom surface 145b of the first lower portion 1451. The second lower portion 1452 of the fourth seed pattern 145 may have an eighth thickness. The eighth thickness may be less than the seventh thickness T17. For example, the eighth thickness can be 30% to 80% of the seventh thickness T17. For example, the eighth thickness can be... to Within this range. Therefore, the propagation of cracks between the fourth seed pattern 145 and the third redistribution pattern 130 can be reduced or prevented.

[0068] A fifth insulating layer 105 may be disposed on the fourth insulating layer 104 to cover the fourth redistribution pattern 140. For example, the fifth insulating layer 105 may cover the side and top surfaces of the fourth conductor portion 140W. For example, the fifth insulating layer 105 may be formed of a photopolymer or may include a photopolymer. The fifth insulating layer 105 may be formed of the same material as the fourth insulating layer 104 or may include the same material as the fourth insulating layer 104. The fifth insulating layer 105 and the fourth insulating layer 104 may be configured to have no clear boundary between them.

[0069] Bonding pads 150 may be disposed on and electrically connected to the fourth redistribution pattern 140. Bonding pads 150 may include stacked first conductive layers 1501, second conductive layers 1502, and / or third conductive layers 1503. The first conductive layer 1501 may be disposed in a fifth insulating layer 105 and may protrude into the fourth redistribution pattern 140. The first conductive layer 1501 may include a fifth protrusion 151, which may be disposed in the fourth redistribution pattern 140. The bottom surface 150b of the bonding pad 150 may be located at a lower level than the top surface of the fourth redistribution pattern 140. The bottom surface 150b of the bonding pad 150 may correspond to the bottom surface of the first conductive layer 1501. The bottom surface 150b of the bonding pad 150 may have a downwardly convex shape. For example, when viewed in a plan view, the bottom surface 150b of the bonding pad 150 may have a central region and an edge region. The bottom surface 150b of the central region of the bonding pad 150 may be located at a lower level than the bottom surface 150b of the edge region of the bonding pad 150. The fifth convex portion 151 of the first conductive layer 1501 may also protrude laterally. The first conductive layer 1501 may be formed of at least one metallic material (e.g., copper) or may include at least one metallic material (e.g., copper).

[0070] A second conductive layer 1502 may be disposed on the first conductive layer 1501. The second conductive layer 1502 can serve as a barrier layer and can reduce or prevent the diffusion of metallic material in the first conductive layer 1501. The second conductive layer 1502 may be formed of a metallic material of a different type than that of the first conductive layer 1501, or may include a metallic material of a different type than that of the first conductive layer 1501. For example, the second conductive layer 1502 may be formed of nickel or may include nickel.

[0071] A third conductive layer 1503 may be disposed on the second conductive layer 1502. The third conductive layer 1503 can serve as a protective layer and can reduce or prevent damage to the first conductive layer 1501 (e.g., oxidation). The third conductive layer 1503 may comprise a metallic material different from the first conductive layer 1501 and the second conductive layer 1502. For example, the third conductive layer 1503 may comprise gold (Au). The third conductive layer 1503 may directly contact the bonding protrusion 250. Unlike what is shown in the figures, at least one of the second conductive layer 1502 and the third conductive layer 1503 may be omitted.

[0072] The pad seed pattern 155 may be located between the fourth redistribution pattern 140 and the bonding pad 150, and between the fifth insulating layer 105 and the bonding pad 150. The bottom surface 155b of the pad seed pattern 155 may be disposed within the fourth redistribution pattern 140. For example, the bottom surface 155b of the pad seed pattern 155 may be located at a lower level than the top surface of the fourth redistribution pattern 140. Therefore, the contact area between the pad seed pattern 155 and the fourth redistribution pattern 140 can be increased. The bonding strength between the pad seed pattern 155 and the fourth redistribution pattern 140 can be improved. The pad seed pattern 155 may be formed of at least one conductive material (e.g., copper, titanium, and alloys thereof) or may include at least one conductive material (e.g., copper, titanium, and alloys thereof).

[0073] The pad seed pattern 155 may include a first lower portion 1551, a second lower portion 1552, and an upper portion 1555. The upper portion 1555 of the pad seed pattern 155 may be located at a higher level than the top surface of the fourth redistribution pattern 140. The upper portion 1555 of the pad seed pattern 155 may be located between the bonding pad 150 and the fifth insulating layer 105. The upper portion 1555 of the pad seed pattern 155 may have a ninth thickness T19, which may be a value measured on the top surface of the fifth insulating layer 105. The ninth thickness T19 may be... to Within the range.

[0074] The first lower portion 1551 and the second lower portion 1552 of the pad seed pattern 155 may be located between the fourth redistribution pattern 140 and the bonding pad 150. The first lower portion 1551 of the pad seed pattern 155 may be disposed on the bottom surface 150b of the central region of the bonding pad 150. The second lower portion 1552 of the pad seed pattern 155 may be disposed on the bottom surface 150b of the edge region of the bonding pad 150. The second lower portion 1552 of the pad seed pattern 155 may be located between the first lower portion 1551 and the upper portion 1555. The bottom surface 155b of the pad seed pattern 155 may include portions with different slopes. The bottom surface 155b of the second lower portion 1552 of the pad seed pattern 155 may be located at a higher level than the bottom surface 155b of the first lower portion 1551. The second lower portion 1552 of the pad seed pattern 155 may have an eighth thickness. The eighth thickness may be less than the ninth thickness T19. For example, the eighth thickness can be 30% to 80% of the ninth thickness T19. Therefore, the propagation of cracks between the pad seed pattern 155 and the fourth redistribution pattern 140 can be reduced or prevented.

[0075] Reference Figure 1B The bottom protrusion pattern 160 can be a relatively large thickness T0, such as... Figure 1BAs shown. For example, the thickness T0 of the bottom bump pattern 160 can be greater than the thickness T1 of the first conductive portion 110W, the thickness T2 of the second conductive portion 120W, the thickness T3 of the third conductive portion 130W, and the thickness T4 of the fourth conductive portion 140W. Therefore, the reliability of the redistributed substrate 100 can be improved. Each of the thicknesses T1 of the first conductive portion 110W, T2 of the second conductive portion 120W, T3 of the third conductive portion 130W, and T4 of the fourth conductive portion 140W can be in the range of about 3 μm to about 5 μm.

[0076] In example embodiments where the thickness T0 of the bottom bump pattern 160 is less than 5 μm, the reliability of the semiconductor package 10 may be degraded. In example embodiments where the thickness T0 of the bottom bump pattern 160 is greater than 20 μm, it is difficult to reduce the size of the semiconductor package 10. In example embodiments, the thickness T0 of the bottom bump pattern 160 can be in the range of about 5 μm to about 20 μm. The semiconductor package 10 can have improved reliability and a small thickness.

[0077] like Figure 1B As shown, at least two of the first through-portions 101V, 102V, 103V, and 104V may not vertically overlap each other. For example, the first through-portions 101V, 102V, 103V, and 104V may have an interleaved structure. Therefore, the external stress applied to the first through-portions 101V, 102V, 103V, and 104V can be weakened. During the process of attaching or mounting the solder pattern 500 onto the package substrate, the external stress can be reduced.

[0078] The number of stacked insulating layers 101, 102, 103, 104, and 105 and the number of redistribution patterns 110, 120, 130, and 140 are not limited to the examples shown and may be varied. The redistribution substrate 100 may also include an upper protective layer (not shown) that may cover the fifth insulating layer 105 and the bonding pads 150. The redistribution substrate 100 may also include a lower protective layer (not shown) that may cover the bottom surface 101b of the first insulating layer 101.

[0079] The semiconductor chip 200 can be mounted on the first surface of the redistribution substrate 100. For example... Figure 1BAs shown, semiconductor chip 200 may include chip pads 205 and integrated circuit 217. Chip pads 205 may be exposed on the bottom surface of semiconductor chip 200. Integrated circuit 217 may be disposed within semiconductor chip 200. Integrated circuit 217 may include memory circuitry, logic circuitry, and / or combinations thereof. Integrated circuit 217 may be electrically connected to chip pads 205 via internal interconnects 216. The expression "component coupled to or connected to chip pads 205" indicates that a component is coupled to or connected to semiconductor chip 200. The expression "component coupled to or connected to semiconductor chip 200" indicates that an integrated circuit is coupled to or connected to semiconductor chip 200. In the following text, for the sake of brevity, Figure 1B In all other figures, integrated circuit 217 and internal interconnect 216 will be omitted.

[0080] like Figure 1A As shown, the semiconductor package 10 may further include bonding bumps 250. Bonding bumps 250 may be disposed between chip pads 205 of the semiconductor chip 200 and bonding pads 150 of the redistribution substrate 100, and may be electrically connected to chip pads 205 and bonding pads 150. Bonding bumps 250 may include at least one of solder, pillars, or protrusions. Bonding bumps 250 may be formed of at least one conductive material (e.g., solder material) or may include at least one conductive material (e.g., solder material). The semiconductor chip 200 may be electrically connected to the redistribution substrate 100 via bonding bumps 250. In this specification, the expression "element electrically connected to redistribution substrate 100" means that the element is electrically connected to at least one of the first to fourth redistribution patterns 110, 120, 130, and 140. The spacing of the bonding bumps 250 may be smaller than the spacing of the solder patterns 500.

[0081] The semiconductor package 10 may further include a molding layer 400. The molding layer 400 may be disposed on the redistribution substrate 100 to cover the semiconductor chip 200. The molding layer 400 may cover the uppermost insulating layer in the insulating layers. The uppermost insulating layer may be a fifth insulating layer 105. The molding layer 400 may extend into the gap between the semiconductor chip 200 and the redistribution substrate 100 to seal the bonding protrusion 250. The molding layer 400 may be formed of an insulating polymer (e.g., epoxy molding compound) or may include an insulating polymer (e.g., epoxy molding compound). In the example embodiment, although not shown, an underfill layer may also be disposed in the gap between the redistribution substrate 100 and the semiconductor chip 200.

[0082] Figure 2A This illustrates an example embodiment of the bottom protrusion pattern, the first seed pattern, and the first redistribution pattern according to the concept of the present invention, and is related to... Figure 1B The enlarged sectional view corresponding to part II in the diagram.

[0083] Reference Figure 2A The arrangement and shape of the bottom protrusion pattern 160, the first seed pattern 115, and the first redistribution pattern 110 can be consistent with... Figure 1C The arrangement and shape are the same or substantially the same. For example, the first conductor portion 110W of the first redistribution pattern 110 may include a first convex portion 111. The first seed pattern 115 may include a first lower portion 1151, a second lower portion 1152, and an upper portion 1155.

[0084] However, the second lower portion 1152 of the first seed pattern 115 may also have a through hole. The first protrusion 111 may extend into the hole of the second lower portion 1152 of the first seed pattern 115 and may directly contact the bottom protrusion pattern 160. Therefore, the bonding strength between the first through portion 110V and the bottom protrusion pattern 160 can be further improved.

[0085] The second thickness of the second lower portion 1152 of the first seed pattern 115 may be less than the first thickness T11 of the upper portion 1155. For example, the second thickness may be 30% to 80% of the first thickness T11. The second thickness may be the thickness of a portion of the second lower portion 1152 where no hole is formed.

[0086] Figure 2B This illustrates an example embodiment of the first redistribution pattern, the second seed pattern, and the second redistribution pattern according to the present invention, and is related to... Figure 1B The enlarged sectional view corresponding to part III.

[0087] Reference Figure 2B The second conductor portion 120W of the second redistribution pattern 120 may include a second protrusion 121. The second seed pattern 125 may include a first lower portion 1251, a second lower portion 1252, and an upper portion 1255. The second lower portion 1252 of the second seed pattern 125 may also have a through hole. The second protrusion 121 may extend into the hole of the second lower portion 1252 of the second seed pattern 125 and may directly contact the first redistribution pattern 110. Therefore, the bonding strength between the first redistribution pattern 110 and the second redistribution pattern 120 may be further improved.

[0088] The fourth thickness of the second lower portion 1252 of the second seed pattern 125 may be 30% to 80% of the third thickness T13 of the upper portion 1255. The fourth thickness may be the thickness of the portion of the second lower portion 1252 where no hole is formed.

[0089] Return to reference Figure 1FAlthough not shown, the second lower portion 1352 of the third seed pattern 135 may also have a hole. The third protrusion 131 of the third redistribution pattern 130 may extend into the hole of the second lower portion 1352 of the third seed pattern 135 and may be in direct / physical contact with the second redistribution pattern 120. The second lower portion 1452 of the fourth seed pattern 145 may also have a hole (not shown). The fourth protrusion 141 may extend into the hole of the second lower portion 1452 of the fourth seed pattern 145 and may be in direct physical contact with the third redistribution pattern 130. The second lower portion 1552 of the pad seed pattern 155 may also have a hole (not shown). The fifth protrusion 151 may extend into the hole of the second lower portion 1552 of the pad seed pattern 155 and may be in direct physical contact with the fourth redistribution pattern 140.

[0090] Figure 3A This illustrates an example embodiment of the bottom protrusion pattern, the first seed pattern, and the first redistribution pattern according to the concept of the present invention, and is related to... Figure 1B The enlarged sectional view corresponding to part II.

[0091] Reference Figure 3A The first through-hole portion 110V of the first redistribution pattern 110 may include a first protrusion 111. The first protrusion 111 may have a downwardly convex shape. However, the first protrusion 111 may not protrude laterally. At the top surface 160a of the bottom protrusion pattern 160, the width of the first protrusion 111 may be smaller than the width of the first through-hole portion 110V.

[0092] Figure 3B This illustrates an example embodiment of the first redistribution pattern, the second seed pattern, and the second redistribution pattern according to the present invention, and is related to... Figure 1B The enlarged sectional view corresponding to part III.

[0093] Reference Figure 3B The second through portion 120V of the second redistribution pattern 120 may include a second protruding portion 121. For example, the second protruding portion 121 may have a downwardly convex shape. However, the second protruding portion 121 may not protrude laterally. At the top surface 110a of the first redistribution pattern 110, the width of the second protruding portion 121 may be smaller than the width of the second through portion 120V.

[0094] Although not shown, the third convex portion 131 of the third redistribution pattern 130, the fourth convex portion 141 of the fourth redistribution pattern 140, or the fifth convex portion 151 of the bonding pad 150 may have the same characteristics as... Figure 3A The first convex portion 111 and Figure 3B The second convex portion 121 has the same or substantially the same shape.

[0095] Figure 4AThis illustrates an example embodiment of a redistributed substrate according to the concept of the present invention, and Figure 1A The enlarged sectional view corresponding to part I.

[0096] Reference Figure 4A The redistribution substrate 100 may include a bottom bump pattern 160; a first redistribution pattern to a fourth redistribution pattern 110, 120, 130 and 140; a first seed pattern to a fourth seed pattern 115, 125, 135 and 145; a pad seed pattern 155; and a bonding pad 150.

[0097] At least one of the first through-portions to the fourth through-portions 110V, 120V, 130V, and 140V may not extend into the corresponding one of the bottom protrusion pattern 160 and the first redistribution pattern to the third redistribution pattern 110, 120, and 130. For example, the bottom surface of the third seed pattern 135 may not be provided in the second redistribution pattern 120. The bottom surfaces of the third through-portion 130V and the third seed pattern 135 may have flat shapes. The bottom surface of the fourth seed pattern 145 may not be provided in the third redistribution pattern 130. The bottom surfaces of the fourth through-portion 140V and the fourth seed pattern 145 may have flat shapes. However, the presence or absence of protrusions in the first through-portions to the fourth through-portions 110V, 120V, 130V, and 140V, as well as the positions of the bottom surfaces of the first seed patterns to the fourth seed patterns 115, 125, 135, and 145, can be varied.

[0098] Figure 4B This illustrates an example embodiment of a redistributed substrate according to the concept of the present invention and is related to... Figure 1A The enlarged sectional view corresponding to part I.

[0099] Reference Figure 4B The redistribution substrate 100 may include a bottom bump pattern 160; a first redistribution pattern to a fourth redistribution pattern 110, 120, 130 and 140; a first seed pattern to a fourth seed pattern 115, 125, 135 and 145; a pad seed pattern 155; and a bonding pad 150.

[0100] The bottom surface of the first through-hole portion 110V can be disposed in the bottom protrusion pattern 160 and can be flat. For example, the bottom surface 110b of the first through-hole portion 110V can be substantially parallel to the first direction. The bottom surface of the first seed pattern 115 can have a substantially flat shape. The bottom surfaces of the second through-hole portion 120V and the second seed pattern 125 can be disposed in the first redistribution pattern 110 and can be flat. The bottom surfaces of the third through-hole portion 130V and the third seed pattern 135 can be disposed in the second redistribution pattern 120 and can be flat. The bottom surfaces of the fourth through-hole portion 140V and the fourth seed pattern 145 can be disposed in the third redistribution pattern 130 and can be flat. The bottom surfaces of the bonding pad 150 and the pad seed pattern 155 can be disposed in the fourth redistribution pattern 140 and can be flat.

[0101] Figure 5A This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention. Figure 5B It is shown Figure 5A An enlarged sectional view of part I.

[0102] Reference Figure 5A and Figure 5B The semiconductor package 11 may include a redistribution substrate 100, a semiconductor chip 200, and a solder pattern 500. The redistribution substrate 100 may include a bottom bump pattern 160; first redistribution patterns and fourth redistribution patterns 110, 120, 130, and 140; first to fourth seed patterns 115, 125, 135, and 145; a pad seed pattern 155; and a bonding pad 150.

[0103] The first through-ports 110V, 120V, 130V, and 140V can be stacked on the bottom protrusion pattern 160. For example, the bottom protrusion pattern 160 can vertically overlap each of the first through-ports 110V, 120V, 130V, and 140V that are electrically connected to the bottom protrusion pattern 160. The first through-ports 101V, 102V, 103V, and 104V can have an aligned structure. Therefore, the arrangement of the first through-ports 110V, 120V, 130V, and 140V can be designed with greater freedom.

[0104] Figure 6A This illustrates an example embodiment of a redistributed substrate according to the concept of the present invention and is related to... Figure 5A The enlarged sectional view corresponding to part I.

[0105] Reference Figure 6AThe top surface 160a of the bottom protrusion pattern 160 may have a dome-shaped cross-section. The top surface 160a of the central region of the bottom protrusion pattern 160 may be located at a higher level than the top surface 160a of the edge region. For example, the top surface 160a of the bottom protrusion pattern 160 may have an upward convex shape. At least a portion of the first redistribution pattern 110 may have a dome-shaped cross-section. For example, the top surface 110a of the central region of the first redistribution pattern 110 may be located at a higher level than the top surface 110a of the edge region. The top surface 110a of the first redistribution pattern 110 may have an upward convex shape. For example, at least a portion of the second redistribution pattern 120 may have a dome-shaped cross-section, and the top surface 120a of the second redistribution pattern 120 may have an upward convex shape. At least a portion of the third redistribution pattern 130 may have a dome-shaped cross-section, and the top surface 130a of the third redistribution pattern 130 may have an upward convex shape. At least a portion of the fourth redistribution pattern 140 may have a dome-shaped cross-section, and the top surface 140a of the fourth redistribution pattern 140 may have a convex shape. The top surface of the bonding pad 150 may have a flat shape. As another example, the top surface of the bonding pad 150 may have a convex shape.

[0106] Figure 6B This illustrates an example embodiment of a redistributed substrate according to the concept of the present invention and is related to... Figure 5A The enlarged sectional view corresponding to part I.

[0107] Reference Figure 6B The top surface 160a of the bottom protrusion pattern 160 may have a concave cross-section. The top surface 160a of the central region of the bottom protrusion pattern 160 may be located at a lower level than the top surface 160a of the edge region. For example, the top surface 160a of the bottom protrusion pattern 160 may have a concave shape. At least a portion of the first redistribution pattern 110 may have a concave cross-section. For example, the top surface 110a of the first redistribution pattern 110 may have a concave shape. For example, the top surface 110a of the central region of the first redistribution pattern 110 may be located at a lower level than the top surface 110a of the edge region. At least a portion of the second redistribution pattern 120 may have a concave cross-section, and the top surface 120a of the second redistribution pattern 120 may have a concave shape. At least a portion of the third redistribution pattern 130 may have a concave cross-section, and the top surface 130a of the third redistribution pattern 130 may have a concave shape. At least a portion of the fourth redistribution pattern 140 may have a concave cross-section, and the top surface 140a of the fourth redistribution pattern 140 may have a recessed shape. The top surface of the bonding pad 150 may have a flat shape. As another example, the top surface of the bonding pad 150 may have a recessed shape.

[0108] Figure 7 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0109] Reference Figure 7 The semiconductor package 12 may include a redistributed substrate 100', a semiconductor chip 200, a molding layer 400, and a solder pattern 500. The solder pattern 500, semiconductor chip 200, and molding layer 400 may be the same as or similar to those in the previously illustrated embodiments. However, the semiconductor package 12 may not include the bonding bumps 250.

[0110] The redistribution substrate 100' may include first to fifth insulating layers 101, 102, 103, 104, and 105; first to fourth redistribution patterns 110, 120, 130, and 140; and first to fourth seed patterns 115, 125, 135, and 145. However, the redistribution substrate 100' may not include bonding pads 150 and pad seed patterns 155 (e.g., see...). Figure 1B The semiconductor chip 200 can directly contact the first surface 100a of the redistribution substrate 100'. For example, the fifth insulating layer 105 can directly physically contact the bottom surface of the semiconductor chip 200.

[0111] The fourth redistribution pattern 140 can be electrically connected to the chip pad 205 of the semiconductor chip 200 without bonding bumps. For example, the fourth seed pattern 145 can be located between the fourth redistribution pattern 140 and the chip pad 205, and can directly contact the fourth redistribution pattern 140 and the chip pad 205.

[0112] Unlike the above, the first through-hole portions 110V, 120V, 130V, and 140V can be distributed on one of the corresponding first to fourth conductor portions 110W, 120W, 130W, and 140W. The top surface of the first through-hole portion 110V can be disposed in the second redistribution pattern 120. The shape of the upper part of the first through-hole portion 110V can be... Figure 1CThe first convex portion 111 has a vertically symmetrical inverted shape. For example, the top surface of the first through-hole portion 110V may have an upwardly convex shape. A first seed pattern 115 may be disposed between the first through-hole portion 110V and the second redistribution pattern 120, and may extend on the side surface of the first through-hole portion 110V and the top surface of the first conductor portion 110W. The first seed thickness of the first seed pattern 115 on the top surface of the first conductor portion 110W may be greater than the second seed thickness of the first seed pattern 115. The second seed thickness may be the thickness of the first seed pattern 115 at the top surface of the edge region of the first through-hole portion 110V in the second redistribution pattern 120. For example, the second seed thickness may be 30% to 80% of the first seed thickness. A solder pattern 500 may be attached to the bottom surface of the first conductor portion 110W of the first redistribution pattern 110. The first conductor portion 110W may be used as a solder pad.

[0113] The top surface of the second through-port 120V can be disposed in the third redistribution pattern 130 and can have an upwardly convex shape. The second seed pattern 125 can be disposed between the second through-port 120V and the third redistribution pattern 130, and can extend on the side surface of the second through-port 120V and the top surface of the second conductor portion 120W. The third seed thickness of the second seed pattern 125 on the top surface of the second conductor portion 120W can be greater than the fourth seed thickness of the second seed pattern 125 in the third redistribution pattern 130 and on the top surface of the edge region of the second through-port 120V. The fourth seed thickness can be 30% to 80% of the third seed thickness.

[0114] The top surface of the third through-section 130V can be disposed in the fourth redistribution pattern 140 and can have an upwardly convex shape. The third seed pattern 135 can be disposed between the third through-section 130V and the fourth redistribution pattern 140, and can extend on the side surface of the third through-section 130V and the top surface of the third conductor portion 130W. The fifth seed thickness of the third seed pattern 135 on the top surface of the third conductor portion 130W can be greater than the sixth seed thickness of the third seed pattern 135 in the fourth redistribution pattern 140 and on the top surface of the edge region of the third through-section 130V. The sixth seed thickness can be 30% to 80% of the fifth seed thickness.

[0115] Example embodiments of the redistributed substrate 100 or 100' can be implemented in a hybrid manner. For example, Figures 1A to 1C , Figure 1E and Figure 1F Example embodiments, Figure 2A Example embodiments, Figure 2B Example embodiments, Figure 3A Example embodiments, Figure 3BExample embodiments, Figure 4A Example embodiments, Figure 4B Example embodiments, Figure 5A and Figure 5B Example embodiments, Figure 6A Example embodiments, Figure 6B Example embodiments, and Figure 7 Example implementations can be carried out in a hybrid manner.

[0116] Hereinafter, a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention may be described.

[0117] Figures 8A to 8E , Figure 8G and Figures 8I to 8T This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. Figure 8F It is shown Figure 8E An enlarged sectional view of part V. Figure 8H It is shown Figure 8G An enlarged sectional view of part V. For the sake of brevity, previously described elements may be identified by the same reference numerals without repeated overlapping descriptions.

[0118] Reference Figure 8A A bottom bump seed layer 165Z, a first resist pattern 191, and a bottom bump pattern 160 can be formed on a carrier substrate 900. First, a carrier substrate 900 and a release layer 990 can be prepared. The release layer 990 can be attached to the carrier substrate 900. The bottom bump seed layer 165Z can be formed on the carrier substrate 900 to cover the release layer 990. The bottom bump seed layer 165Z can be formed by a deposition process.

[0119] A first resist pattern 191 may be formed on the top surface of the bottom bump seed layer 165Z. A first guide opening 191X may be formed in the first resist pattern 191 to expose the bottom bump seed layer 165Z. In an example embodiment, no additional curing process may be performed in the process of forming the first resist pattern 191 and the first guide opening 191X. Therefore, the first guide opening 191X may be formed such that its side surfaces are perpendicular to its bottom surface. The first resist pattern 191 may include a photoresist material.

[0120] A bottom bump pattern 160 can be formed in the first guide opening 191X to cover the bottom bump seed layer 165Z. The bottom bump pattern 160 can be formed by an electroplating process using the bottom bump seed layer 165Z as an electrode. The electroplating process can be performed such that the bottom bump pattern 160 does not extend to the top surface of the first resist pattern 191. Therefore, a separate planarization process is not required in the process of forming the bottom bump pattern 160. Since the side surface of the first guide opening 191X is substantially perpendicular to the bottom surface, the side surface of the bottom bump pattern 160 can also be substantially perpendicular to the bottom surface.

[0121] Reference Figure 8B The first resist pattern 191 can be removed to expose the top surface of the first portion of the bottom bump seed layer 165Z and the side surface of the bottom bump pattern 160. The removal of the first resist pattern 191 can be performed by a stripping process.

[0122] Refer in sequence Figure 8B and Figure 8C The bottom bump seed layer 165Z can be patterned to form a bottom bump seed pattern 165. Patterning the bottom bump seed layer 165Z may include etching an exposed first portion of the bottom bump seed layer 165Z. Therefore, the first portion of the bottom bump seed layer 165Z can be removed, exposing the top surface of the release layer 990. In the etching process, the bottom bump pattern 160 may have etch selectivity relative to the bottom bump seed layer 165Z. A second portion of the bottom bump seed layer 165Z may be disposed on the bottom surface of the bottom bump pattern 160. Therefore, the second portion of the bottom bump seed layer 165Z may not be removed by the etching process. After the etching process, the remaining second portion of the bottom bump seed layer 165Z can form the bottom bump seed pattern 165.

[0123] Reference Figure 8D A first insulating layer 101 may be formed on the release layer 990 and the bottom protrusion pattern 160 to cover the top surface 160a and side surfaces of the bottom protrusion pattern 160. The formation of the first insulating layer 101 may be performed by a coating process (e.g., spin coating or slot coating).

[0124] A first opening 101X can be formed in the first insulating layer 101 by patterning. The first insulating layer 101 can be patterned by an exposure process and a development process. The first opening 101X can be formed to expose at least a portion of the top surface 160a of the bottom protrusion pattern 160. A first scum 101S can remain on the exposed top surface 160a of the bottom protrusion pattern 160. The first scum 101S may include residues of the first insulating layer 101 or process residues. As an example, the first scum 101S may include a photopolymer.

[0125] Reference Figure 8E and Figure 8F The recessed portion 160R can be formed by performing an etching process on the exposed top surface 160a of the bottom protrusion pattern 160. For example, the etching process may include a wet etching process. In an example embodiment, the first insulating layer 101 may have etch selectivity relative to the bottom protrusion pattern 160. In a wet etching process, the first dross 101S can be removed. Therefore, the first dross 101S may not remain after the etching process.

[0126] A recessed portion 160R may be formed on the top surface 160a of the bottom protrusion pattern 160. The recessed portion 160R may be connected to the first opening 101X. The bottom surface of the central region of the recessed portion 160R may be located at a lower level than the bottom surface of the edge regions. For example, the bottom surface of the recessed portion 160R may have a concave shape. Figure 8F As shown, the recessed portion 160R may have an undercut portion 160U. For example, the undercut portion 160U may be a laterally extended portion of the recessed portion 160R. The shape of the recessed portion 160R may not be limited to the example shown, but may be varied. For example, the undercut portion 160U may not be formed.

[0127] Reference Figure 8G and Figure 8H A first seed layer 115Z, a second resist pattern 192, and a first redistribution pattern 110 can be formed. First, the first seed layer 115Z can be formed on the top surface 160a of the bottom protrusion pattern 160, the inner surface of the recessed portion 160R of the bottom protrusion pattern 160, the inner surface of the first opening 101X, and the top surface of the first insulating layer 101. The first seed layer 115Z can be formed by a deposition process. The first seed layer 115Z may include a first lower portion 1151, a second lower portion 1152, and an upper portion 1155. The first lower portion 1151, the second lower portion 1152, and the upper portion 1155 can be compared with previously referenced... Figure 1C The first lower portion 1151, the second lower portion 1152, and the upper portion 1155 of the first seed pattern 115 described are identical. The first seed layer 115Z on the inner surface of the undercut portion 160U may correspond to the first lower portion 1151 of the first seed layer 115Z. The first seed layer 115Z on the first insulating layer 101 may correspond to the upper portion 1155 of the first seed layer 115Z.

[0128] The second thickness T12 of the first seed layer 115Z on the inner surface of the undercut portion 160U may be less than the first thickness T11 of the first seed layer 115Z on the first insulating layer 101. For example, the second thickness T12 may be 30% to 80% of the first thickness T11.

[0129] exist Figure 8DIn an example embodiment where the first scum 101S remains on the bottom bump pattern 160, the resistance between the bottom bump pattern 160 and the first seed layer 115Z can be increased. According to an example embodiment conceived in the present invention, since in reference... Figure 8E and Figure 8F The process of forming the recessed portion 160R removes the first scum 101S, thus improving the electrical characteristics between the bottom protrusion pattern 160 and the first seed layer 115Z. Furthermore, the first seed layer 115Z can be robustly coupled to the bottom protrusion pattern 160.

[0130] A second resist pattern 192 may be formed on the first seed layer 115Z. Forming the second resist pattern 192 may include coating the top surface of the first seed layer 115Z with a photoresist material. Then, a second guide opening 192X may be formed by patterning the second resist pattern 192. The patterning of the second resist pattern 192 may be performed by an exposure and development process. The second guide opening 192X may vertically overlap with the first opening 101X and the recessed portion 160R. The second guide opening 192X may be formed such that its width is greater than the width of its corresponding first opening 101X. The second guide opening 192X may be formed to expose the first seed layer 115Z.

[0131] The first redistribution pattern 110 can be formed by performing an electroplating process in which the first seed layer 115Z is used as an electrode. The first redistribution pattern 110 can be formed in the first opening 101X to cover the first seed layer 115Z. For example, the first redistribution pattern 110 can fill the first opening 101X. The first redistribution pattern 110 can be formed to fill the lower region of the second guide opening 192X, but may not be exposed on the top surface of the second resist pattern 192. A separate planarization process may not be performed during the formation of the first redistribution pattern 110. Therefore, the process for forming the first redistribution pattern 110 can be simplified. The first redistribution pattern 110 may include a first through-hole portion 110V and a first conductive portion 110W.

[0132] Reference Figure 8I The second resist pattern 192 can be removed to expose the top surface of the first portion of the first seed layer 115Z. The removal of the second resist pattern 192 can be performed using a stripping process.

[0133] Reference Figure 8I and Figure 8JThe first exposed portion of the first seed layer 115Z can be removed to form the first seed pattern 115. The removal of the first portion of the first seed layer 115Z can be performed by an etching process. The etching process can be a wet etching process. In the etching process, the first redistribution pattern 110 can have etching selectivity relative to the first seed layer 115Z. A second portion of the first seed layer 115Z can be disposed on the bottom surface of the first redistribution pattern 110 and can be unexposed to the etching process. After the etching process, the second portion of the first seed layer 115Z can form the first seed pattern 115.

[0134] Reference Figure 8K The second insulating layer 102 may be formed on the first insulating layer 101 to cover the first insulating layer 101 and the first redistribution pattern 110. The formation of the second insulating layer 102 may be performed by a coating process.

[0135] The second opening 102X can be formed by patterning the second insulating layer 102 via an exposure and development process. The second opening 102X can be disposed in the second insulating layer 102 to expose a portion of the top surface 110a of the first redistribution pattern 110. A second slag 102S can be left on the exposed portion of the top surface 110a of the first redistribution pattern 110. The second slag 102S may include residues of the second insulating layer 102 or process residues. As an example, the second slag 102S may include a photopolymer.

[0136] Reference Figure 8L The first recessed portion 110R can be formed by performing an etching process on the exposed top surface 110a of the first redistribution pattern 110. For example, the etching process may include a wet etching process. The second slag 102S can be removed during the etching process.

[0137] A first recessed portion 110R may be formed on the top surface 110a of the first redistribution pattern 110. The first recessed portion 110R may be connected to the second opening 102X. The bottom surface of the central region of the first recessed portion 110R may be located at a lower level than the bottom surface of the edge regions. For example, the bottom surface of the first recessed portion 110R may have a concave shape. The first recessed portion 110R may have a first undercut portion 110U. For example, the first undercut portion 110U may be a laterally extended portion of the first recessed portion 110R. As another example, the first undercut portion 110U may not be formed.

[0138] Reference Figure 8MA second seed layer 125Z, a third resist pattern 193, and a second redistribution pattern 120 can be formed. First, the second seed layer 125Z can be formed on the top surface of the first redistribution pattern 110, the inner surface of the first recessed portion 110R of the first redistribution pattern 110, the inner surface of the second opening 102X, and the top surface of the second insulating layer 102. The second seed layer 125Z can be formed by a deposition process.

[0139] The fourth thickness of the second seed layer 125Z on the first undercut portion 110U may be less than the third thickness of the second seed layer 125Z on the second insulating layer 102. For example, the fourth thickness may be 30% to 80% of the third thickness. The second seed layer 125Z on the first undercut portion 110U may be... Figure 1E The second seed layer 125Z on the second insulating layer 102 can correspond to the second lower part 1252 of the second seed pattern 125. Figure 1E The upper part 1255 of the second seed pattern 125 corresponds to the second seed layer 125Z on the first undercut portion 110U. The second seed layer 125Z on the first undercut portion 110U can represent a second seed layer 125Z covering a portion of the inner surface of the first undercut portion 110U.

[0140] As a result of forming the first recessed portion 110R, no residue is left between the first redistribution pattern 110 and the second seed layer 125Z. Figure 8K The second scum 102S. Therefore, the electrical characteristics between the first redistribution pattern 110 and the second seed layer 125Z can be improved. The second seed layer 125Z can be robustly bonded to the first redistribution pattern 110.

[0141] Reference Figure 8N The third resist pattern 193 can be removed to expose the top surface of the first portion of the second seed layer 125Z. The removal of the third resist pattern 193 can be performed via a stripping process. The second seed pattern 125 can be formed by removing the exposed first portion of the second seed layer 125Z via an etching process. The second portion of the second seed layer 125Z can be disposed on the bottom surface of the second redistribution pattern 120 and can be kept out of exposure to the etching process. After the etching process, the second portion of the second seed layer 125Z can form the second seed pattern 125.

[0142] Reference Figure 8O The third insulating layer 103, the third seed pattern 135, and the third redistribution pattern 130 can be formed on the second insulating layer 102. This can be achieved through... Figures 8D to 8JThe third insulating layer 103, third seed pattern 135, and third redistribution pattern 130 are formed using the same method as the first insulating layer 101, first seed pattern 115, and first redistribution pattern 110. For example, the third insulating layer 103 can be formed with a third opening 103X exposing the top surface 120a of the second redistribution pattern 120. An etching process can be performed on the second redistribution pattern 120 exposed through the third opening 103X to form a second recessed portion 120R on the top surface 120a of the second redistribution pattern 120. The bottom surface of the second recessed portion 120R may have a concave shape. The second recessed portion 120R may also have a second undercut portion 120U. The second undercut portion 120U may be a laterally extended portion of the second recessed portion 120R.

[0143] The formation of the third seed pattern 135 and the third redistribution pattern 130 may include: forming a third seed layer (not shown) on the top surface of the third insulating layer 103 in the second recessed portion 120R and the third opening 103X; performing an electroplating process using the third seed layer as an electrode; and etching a portion of the third seed layer.

[0144] As a result of the electroplating process, a third redistribution pattern 130 may be formed in the third opening 103X and the second recess 120R. The third redistribution pattern 130 may include a third conductive portion 130W and a third through portion 130V. By etching the third seed layer, a third seed pattern 135 may be formed between the second redistribution pattern 120 and the third redistribution pattern 130, and between the third redistribution pattern 130 and the third insulating layer 103.

[0145] Reference Figure 8P A fourth insulating layer 104, a fourth seed pattern 145, and a fourth redistribution pattern 140 can be formed on the third insulating layer 103. This can be achieved through... Figures 8D to 8J The fourth insulating layer 104, fourth seed pattern 145, and fourth redistribution pattern 140 are formed using the same method as the first insulating layer 101, first seed pattern 115, and first redistribution pattern 110. For example, the fourth insulating layer 104 may be formed with a fourth opening 104X exposing the top surface of the third redistribution pattern 130. An etching process may be performed on the third redistribution pattern 130 exposed through the fourth opening 104X to form a third recessed portion 130R on the top surface of the third redistribution pattern 130. For example, the bottom surface of the third recessed portion 130R may have a concave shape. The third recessed portion 130R may also have a third undercut portion 130U. The third undercut portion 130U may be a laterally extended portion of the third recessed portion 130R.

[0146] The formation of the fourth seed pattern 145 and the fourth redistribution pattern 140 may include: forming a fourth seed layer (not shown) in the fourth opening 104X and the third recessed portion 130R and on the top surface of the fourth insulating layer 104; performing an electroplating process using the fourth seed layer as an electrode; and etching a portion of the fourth seed layer.

[0147] As a result of the electroplating process, a fourth redistribution pattern 140 can be formed in the fourth opening 104X and the third recess 130R. The fourth redistribution pattern 140 may include a fourth conductive portion 140W and a fourth through portion 140V. By etching the fourth seed layer, a fourth seed pattern 145 can be formed between the third redistribution pattern 130 and the fourth redistribution pattern 140, and between the fourth redistribution pattern 140 and the fourth insulating layer 104.

[0148] Reference Figure 8Q A fifth insulating layer 105, a solder pad seed pattern 155, and a bonding pad 150 can be formed on the fourth insulating layer 104. This can be achieved through... Figures 8D to 8J The fifth insulating layer 105, the pad seed pattern 155, and the bonding pad 150 are formed using the same method as the first insulating layer 101, the first seed pattern 115, and the first redistribution pattern 110. For example, the fifth insulating layer 105 may be formed with a fifth opening 105X exposing the top surface of the fourth redistribution pattern 140. An etching process may be performed on the fourth redistribution pattern 140 exposed through the fifth opening 105X to form a fourth recessed portion 140R on the top surface of the fourth redistribution pattern 140. For example, the bottom surface of the fourth recessed portion 140R may have a concave shape. The fourth recessed portion 140R may also have a fourth undercut portion 140U. The fourth undercut portion 140U may be a laterally extended portion of the fourth recessed portion 140R.

[0149] The formation of the pad seed pattern 155 and the bonding pad 150 may include: forming a third seed layer (not shown) in the fifth opening 105X and the fourth recess 140R and on the top surface of the fifth insulating layer 105; performing an electroplating process using the pad seed layer as an electrode; and etching a portion of the pad seed layer.

[0150] As a result of the electroplating process, bonding pads 150 can be formed in the fifth opening 105X and the fourth recess 140R. Pad seed patterns 155 can be formed between the fourth redistribution pattern 140 and the bonding pads 150, and between the bonding pads 150 and the fifth insulating layer 105. The redistribution substrate 100 can be manufactured using the above method.

[0151] Reference Figure 8RA semiconductor chip 200 with chip pads 205 can be fabricated. The semiconductor chip 200 can be disposed on a fifth insulating layer 105 such that the chip pads 205 are aligned with the bonding pads 150. A bonding bump 250 can be formed between the semiconductor chip 200 and the redistribution substrate 100. The bonding bump 250 can be coupled to the chip pads 205 and the bonding pads 150.

[0152] A molding layer 400 may be formed on the fifth insulating layer 105 to seal the semiconductor chip 200. The molding layer 400 may further extend into the gap region between the fifth insulating layer 105 and the semiconductor chip 200 to seal the bonding protrusion 250.

[0153] Reference Figure 8S The bottom surface 101b of the first insulating layer 101 and the bottom surface of the bottom protrusion seed pattern 165 can be exposed by removing the release layer 990 and the carrier substrate 900 from the first insulating layer 101. The removal of the release layer 990 and the carrier substrate 900 can be performed by physical methods.

[0154] Refer in sequence Figure 8S and Figure 8T The bottom bump seed pattern 165 can be removed to expose the bottom surface 160b of the bottom bump pattern 160. The removal of the bottom bump seed pattern 165 can be performed by an etching process. The etching process can be a wet etching process. After the etching process, the bottom bump pattern 160 and the first insulating layer 101 remain. Because the bottom bump seed pattern 165 has been removed, the bottom surface 160b of the bottom bump pattern 160 can be located at a higher level than the bottom surface 101b of the first insulating layer 101.

[0155] Return to reference Figure 1A and Figure 1B Solder pattern 500 may be formed on the exposed bottom surface 160b of bottom protrusion pattern 160. Formation of solder pattern 500 may include performing a solder ball attachment process.

[0156] Solder pattern 500 and bottom bump seed pattern 165 (for example, see...) Figure 8S The bonding strength between the solder pattern 500 and the bottom bump seed pattern 165 may be relatively weak. For example, the bonding strength between the solder pattern 500 and the bottom bump pattern 160 may be weaker than the bonding strength between the solder pattern 500 and the bottom bump pattern 160. In an exemplary embodiment of the present invention, since the bottom bump seed pattern 165 is removed and the solder pattern 500 is formed on the bottom bump pattern 160, the solder pattern 500 can directly contact the bottom bump pattern 160. Therefore, the solder pattern 500 can be robustly coupled to the bottom bump pattern 160. The semiconductor package 10 can be manufactured by the above process.

[0157] For the sake of simplicity, although a method for manufacturing only one semiconductor package 10 has been shown and described, the method for manufacturing the semiconductor package 10 is not limited to this chip-level manufacturing. For example, the semiconductor package 10 can be manufactured at the chip level, panel level, or wafer level.

[0158] For the sake of brevity, in the following text, Figure 9 , Figure 10A and Figure 10B as well as Figure 11 In this context, the first conductive layer to the third conductive layers 1501, 1502 and 1503 of the bonding pad 150 are no longer shown as separate components.

[0159] Figure 9 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0160] Reference Figure 9 The semiconductor package 13 may include a package substrate 800, a redistribution substrate 100, a solder pattern 500, a first semiconductor chip 210, a chip stack 2000, bonding bumps 250, and / or a molding layer 400. The redistribution substrate 100, solder pattern 500, and molding layer 400 may be coupled with... Figures 1A to 1C , Figure 1E and Figure 1F The redistribution substrate 100, solder pattern 500, and molding layer 400 in the example are the same or substantially the same. The bonding protrusion 250 may include a first bonding protrusion 251 and a second bonding protrusion 252.

[0161] Package substrate 800 may include a printed circuit board. Package substrate 800 may include metal lines 820 and metal pads 810. Metal lines 820 may be disposed in package substrate 800. Coupling with package substrate 800 may mean coupling with metal lines 820. Metal pads 810 may be disposed on the top surface of package substrate 800 and may be electrically connected to metal lines 820. External coupling terminals 850 may be disposed on the bottom surface of package substrate 800 and may be coupled to metal lines 820. External electrical signals may be delivered to metal lines 820 through external coupling terminals 850. Solder balls may be used as external coupling terminals 850. External coupling terminals 850 may be formed of at least one metallic material (e.g., solder), or may include at least one metallic material (e.g., solder).

[0162] A redistribution substrate 100 may be disposed on a package substrate 800. The redistribution substrate 100 may be used as an insertion substrate. A solder pattern 500 may be aligned with and coupled to the metal pads 810 of the package substrate 800. The redistribution substrate 100 may be electrically connected to the package substrate 800 via the solder pattern 500.

[0163] The first semiconductor chip 210 can be mounted on the top surface of the redistribution substrate 100. A first bonding protrusion 251 can be located between the chip pad 215 and the bonding pad 150 of the first semiconductor chip 210. The first semiconductor chip 210 can be coupled with… Figure 1A and Figure 1B The semiconductor chip 200 is the same as or substantially the same as the semiconductor chip 200, and the arrangement, function, and material of the first bonding protrusion 251 are similar to those of the semiconductor chip 200. Figure 1A and Figure 1B The engagement protrusions 250 are the same or substantially the same. The spacing of the first engagement protrusions 251 may be smaller than the spacing of the external coupling terminals 850.

[0164] A chip stack 2000 can be mounted on the top surface of the redistribution substrate 100. The chip stack 2000 can be configured to be laterally spaced from the first semiconductor chip 210. The chip stack 2000 may include a plurality of second semiconductor chips 220 sequentially stacked. Each second semiconductor chip 220 can be coupled with… Figure 1A and Figure 1B The first semiconductor chip 210 is identical or similar to the first semiconductor chip 200. However, the second semiconductor chip 220 may be a semiconductor chip of a different type than the first semiconductor chip 210. For example, the first semiconductor chip 210 may be one of a logic chip, a buffer chip, and a system-on-a-chip (SOC), and each of the second semiconductor chips 220 may be another of a logic chip, a memory chip, a buffer chip, and a system-on-a-chip (SOC). The memory chip may include a high-bandwidth memory (HBM) chip. For example, the bottommost second semiconductor chip 220 of the second semiconductor chips 220 may be a logic chip, and the remaining second semiconductor chips 220 of the second semiconductor chips 220 may be HBM chips. However, the bottommost second semiconductor chip 220 of the second semiconductor chips 220 may be a logic chip of a different type than the first semiconductor chip 210. As an example, the bottommost second semiconductor chip 220 of the second semiconductor chips 220 may be a controller chip, and the first semiconductor chip 210 may include an ASIC chip or an application processor (AP) chip. The ASIC chip may include an application-specific integrated circuit (ASIC).

[0165] Each second semiconductor chip 220 may include a lower pad 225, a through-electrode 227, and an upper pad 226. The lower pad 225 and the upper pad 226 may be distributed on the bottom and top surfaces of the second semiconductor chip 220. At least one of the lower pad 225 and the upper pad 226 may be electrically connected to an integrated circuit of the second semiconductor chip 220. The through-electrode 227 may be disposed in the second semiconductor chip 220 and may be coupled to the lower pad 225 and the upper pad 226. The uppermost second semiconductor chip 220 may include the lower pad 225 and may not include the through-electrode 227 and the upper pad 226. An insert protrusion 229 may be located between adjacent pairs of second semiconductor chips 220 and may be coupled to the lower pad 225 and the upper pad 226, respectively. Therefore, multiple second semiconductor chips 220 may be electrically connected to each other. The insert protrusion 229 may include solder, a pillar, or a protrusion. The insert protrusion 229 may be formed of at least one metallic material or may include at least one metallic material.

[0166] As another example, the insert protrusion 229 can be omitted. In some example embodiments, the lower pad 225 and upper pad 226 of the adjacent second semiconductor chip 220 can be directly bonded to each other.

[0167] The second bonding bump 252 can be located between the lowermost second semiconductor chip 220 and the redistribution substrate 100, and can be coupled to the lower pad 225 and the corresponding bonding pad 150 of the lowermost second semiconductor chip 220. Therefore, the second semiconductor chip 220 can be electrically connected to the first semiconductor chip 210 and the solder pattern 500 through the redistribution substrate 100. The arrangement, function, and material of the second bonding bump 252 can be compared with... Figure 1A and Figure 1B The arrangement, function, and materials of the engagement protrusions 250 are the same or substantially the same. The spacing of the second engagement protrusions 252 may be smaller than the spacing of the external coupling terminals 850.

[0168] In an example embodiment, a plurality of chip stacks 2000 may be provided. The chip stacks 2000 may be spaced apart from each other laterally. A first semiconductor chip 210 may be positioned between the chip stacks 2000. Therefore, the length of the electrical path between the first semiconductor chip 210 and the chip stacks 2000 can be reduced.

[0169] A first bottom filler layer 410 may be disposed in a first gap region between the redistribution substrate 100 and the first semiconductor chip 210 to seal the first bonding protrusion 251. The first bottom filler layer 410 may be formed of at least one insulating polymer (e.g., an epoxy polymer), or may include at least one insulating polymer (e.g., an epoxy polymer). A second bottom filler layer 420 may be disposed in a second gap region between the redistribution substrate 100 and the chip stack 2000 to seal the corresponding second bonding protrusion 252. The second bottom filler layer 420 may be formed of at least one insulating polymer (e.g., an epoxy polymer), or may include at least one insulating polymer (e.g., an epoxy polymer). Unlike that shown in the figures, the second bottom filler layer 420 may be omitted, and the first bottom filler layer 410 may extend into the region between the second gap regions to seal the first bonding protrusion 251 and the second bonding protrusion 252. A third bottom filler layer 430 may be disposed between adjacent second semiconductor chips 220 to seal the insert protrusion 229. The third bottom filler layer 430 may be formed of at least one insulating polymer (e.g., an epoxy polymer) or may include at least one insulating polymer (e.g., an epoxy polymer).

[0170] A molding layer 400 may be disposed on the redistribution substrate 100 to cover the side surfaces of the first semiconductor chip 210 and the second semiconductor chip 220. The molding layer 400 may be configured to expose the top surface of the first semiconductor chip 210 and the top surface of the uppermost second semiconductor chip 220. Unlike the figures shown, the molding layer 400 may cover the top surface of the first semiconductor chip 210 and the top surface of the uppermost second semiconductor chip 220. As another example, the first bottom fill layer 410 and the second bottom fill layer 420 may be omitted, and the molding layer 400 may extend into the first gap region and the second gap region.

[0171] The conductive plate 770 may also be disposed on the top surface of the first semiconductor chip 210, the top surface of the chip stack 2000, and the top surface of the molding layer 400. The conductive plate 770 may further extend to the side surface of the molding layer 400. The conductive plate 770 can protect the first semiconductor chip 210 and the chip stack 2000 from the influence of the external environment. For example, the conductive plate 770 may be configured to absorb external physical impacts. The conductive plate 770 may be formed of or may include a material with high thermal conductivity and may be used as a heat sink or heat fin. For example, the conductive plate 770 may be used to rapidly dissipate heat generated by the redistribution substrate 100, the first semiconductor chip 210, or the second semiconductor chip 220 during operation of the semiconductor package 13. The conductive plate 770 may be formed of or may include a conductive material and may be used as an electromagnetic wave shielding layer. For example, the conductive plate 770 may be used to reduce or prevent electromagnetic interference (EMI) problems between the first semiconductor chip 210 and the second semiconductor chip 220. The conductive plate 770 can be grounded through the redistributed substrate 100, which in some example embodiments can reduce or prevent damage to the first semiconductor chip 210 or the second semiconductor chip 220 by electrostatic discharge (ESD).

[0172] Although not shown, a third semiconductor chip may be additionally mounted on the redistribution substrate 100. Unlike that shown in the figures, the molding layer 400 may be omitted.

[0173] References can be used Figure 7 The redistributed substrate 100' described herein is used to fabricate a semiconductor package 13. In some example embodiments, the bonding bumps 250, the first underfill layer 410, and the second underfill layer 420 may be omitted. The arrangement relationship between the redistributed substrate 100' and the first semiconductor chip 210 and the second semiconductor chip 220 may be as follows: Figure 7 The arrangement relationship between the redistributed substrate 100' and the semiconductor chip 200 is the same or substantially the same.

[0174] Figure 10A This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention. Figure 10B It is shown Figure 10A An enlarged sectional view of part VI.

[0175] Reference Figure 10A and Figure 10B The semiconductor package 14 may include a lower semiconductor package 20 and an upper semiconductor package 22. The lower semiconductor package 20 may include a redistribution substrate 100, a solder pattern 500, bonding bumps 250, a first lower semiconductor chip 210A, a second lower semiconductor chip 220A, a molding layer 400, and a conductive structure 310. The redistribution substrate 100, solder pattern 500, and molding layer 400 may be coupled with… Figures 1A to 1C , Figure 1E and Figure 1F The redistribution substrate 100, solder pattern 500 and molding layer 400 in the example are the same or substantially the same.

[0176] The second semiconductor chip 220A may be laterally spaced from the first semiconductor chip 210A. The second semiconductor chip 220A may be a semiconductor chip 200 of a different type than the first semiconductor chip 210A. For example, the first semiconductor chip 210A may include one of a logic chip, a memory chip, and a power management chip, and the second semiconductor chip 220A may be another of the same. The logic chip may include an ASIC chip or an application processor (AP) chip. The power management chip may include a power management integrated circuit (PMIC). As an example, the first semiconductor chip 210A may be a power management chip, and the second semiconductor chip 220A may be an ACIS chip. Each of the first semiconductor chip 210A and the second semiconductor chip 220A may be associated with a reference... Figure 1A and Figure 1B The semiconductor chip 200 described is similar. Unlike that shown in the figures, at least one of the first lower semiconductor chip 210A and the second lower semiconductor chip 220A may be omitted. As another example, a third semiconductor chip (not shown) may be additionally mounted on the top surface of the redistribution substrate 100.

[0177] The engaging protrusion 250 may include a first engaging protrusion 251A and a second engaging protrusion 252A. The first engaging protrusion 251A may be associated with a reference. Figure 9 Similar to the first engaging protrusion 251 described, the second engaging protrusion 252A can be compared with the referenced Figure 9 The second bonding protrusion 252 is similar to the one described. The chip pad 215A of the first lower semiconductor chip 210A can be electrically connected to the redistribution substrate 100 via the first bonding protrusion 251A. The chip pad 225A of the second lower semiconductor chip 220A can be electrically connected to the redistribution substrate 100 via the second bonding protrusion 252A. Therefore, the second lower semiconductor chip 220A can be electrically connected to the first lower semiconductor chip 210A via the redistribution substrate 100.

[0178] The conductive structure 310 may be disposed on the top surface of the redistribution substrate 100 and may be coupled to a corresponding bonding pad 150. The conductive structure 310 may be laterally spaced from the first lower semiconductor chip 210A and the second lower semiconductor chip 220A. When viewed in a plan view, the conductive structure 310 may be disposed on an edge region of the redistribution substrate 100. In an example embodiment, metal pillars may be disposed on the redistribution substrate 100 to form the conductive structure 310. In other words, the conductive structure 310 may be a metal pillar. The conductive structure 310 may be electrically connected to the redistribution substrate 100. For example, the conductive structure 310 may be electrically connected to the first lower semiconductor chip 210A, the second lower semiconductor chip 220A, or the solder pattern 500 through the redistribution substrate 100. The conductive structure 310 may be formed of at least one metallic material (e.g., copper) or may include at least one metallic material (e.g., copper).

[0179] A molding layer 400 can be disposed on the top surface of the redistribution substrate 100 to cover the first lower semiconductor chip 210A and the second lower semiconductor chip 220A. The molding layer 400 can seal the side surfaces of the conductive structure 310. The side surfaces of the molding layer 400 can be aligned with the side surfaces of the redistribution substrate 100. The molding layer 400 can be configured to expose the top surface 310a of the conductive structure 310.

[0180] The lower semiconductor package 20 may further include an upper redistribution layer 600. The upper redistribution layer 600 may be disposed on the top surface of the molding layer 400. The upper redistribution layer 600 may include an upper insulating layer 601, a first upper redistribution pattern 610, a second upper redistribution pattern 620, a first upper seed pattern 615, a second upper seed pattern 625, a bonding seed pattern 655, and an upper bonding pad 650. The upper insulating layer 601 may be stacked on the molding layer 400. The upper insulating layer 601 may include a photopolymer.

[0181] Each of the first upper redistribution pattern 610 and the second upper redistribution pattern 620 may be formed of or comprise a metallic material (e.g., copper). The first upper redistribution pattern 610 may be electrically connected to the top surface 310a of the conductive structure 310. The first upper redistribution pattern 610 may include a through portion of the lowermost upper insulating layer 601 disposed in the upper insulating layer 601, and a conductive portion disposed on the lowermost upper insulating layer 601. A first upper seed pattern 615 may be disposed below the first upper redistribution pattern 610. The first upper seed pattern 615 may be located between the top surface 310a of the conductive structure 310 and the first upper redistribution pattern 610. The first upper seed pattern 615 may be formed of or comprise at least one conductive material (e.g., copper, titanium, and alloys thereof).

[0182] The second upper redistribution pattern 620 may include a through-hole pattern 620V and a wiring pattern 620W. The through-hole pattern 620V may be disposed in a corresponding upper insulating layer 601. The lower portion of the through-hole pattern 620V may include a sixth protrusion 621, and the sixth protrusion 621 may correspond to the lower portion of the through-hole pattern 620V. The sixth protrusion 621 may be disposed in the first upper redistribution pattern 610. The shape of the sixth protrusion 621 may correspond to that of the first protrusion 111 (e.g., see...). Figure 1C ) or the second convex portion 121 (for example, see Figure 1E The shapes of the through-patterns 620V are the same or similar. The bottom surface 620b of the central area of ​​the through-pattern 620V may be located at a lower level than the bottom surface 620b of the edge area. The bottom surface 620b of the through-pattern 620V may have a downwardly convex shape. The sixth convex portion 621 may protrude further laterally.

[0183] Wiring pattern 620W can be placed on and connected to through pattern 620V, with no boundary between them. Wiring pattern 620W can extend to cover a portion of the corresponding upper insulating layer 601. The width of wiring pattern 620W can be greater than the width of through pattern 620V.

[0184] The second upper seed pattern 625 may be located between the first upper redistribution pattern 610 and the second upper redistribution pattern 620. The bottom surface 625b of the second upper seed pattern 625 may be disposed in the first upper redistribution pattern 610. For example, the bottom surface 625b of the second upper seed pattern 625 may be located at a lower level than the top surface 610a of the first upper redistribution pattern 610. The second upper seed pattern 625 may be formed of at least one conductive material (e.g., copper, titanium, and alloys thereof) or may include at least one conductive material (e.g., copper, titanium, and alloys thereof).

[0185] The shape of the second seed pattern 625 can be the same as that of the second seed pattern 125 described above (for example, see...). Figure 1E The second upper seed pattern 625 may include a first lower portion, a second lower portion, and an upper portion. The upper portion of the second upper seed pattern 625 may be located at a higher level than the top surface 610a of the first upper redistribution pattern 610. The upper portion of the second upper seed pattern 625 may be located between the side surface of the through pattern 620V and the upper insulating layer 601 corresponding to the second upper seed pattern 625, and between the bottom surface of the wiring pattern 620W and the upper insulating layer 601. On the bottom surface of the wiring pattern 620W, the upper portion of the second upper seed pattern 625 may have an eleventh thickness T61. The eleventh thickness T61 may be... to Within the range. The first lower portion and the second lower portion of the second upper seed pattern 625 can be located between the first upper redistribution pattern 610 and the second upper redistribution pattern 620. The first lower portion of the second upper seed pattern 625 can be disposed on the bottom surface 620b of the central area of ​​the through pattern 620V. The second lower portion of the second upper seed pattern 625 can be located between the first lower portion and the upper portion. The bottom surface 625b of the second lower portion of the second upper seed pattern 625 can be located at a higher level than the bottom surface 625b of the first lower portion. The second lower portion of the second upper seed pattern 625 can have a tenth thickness T62. The tenth thickness T62 can be less than the eleventh thickness T61. For example, the tenth thickness T62 can be in the range of 30% to 80% of the eleventh thickness T61. For example, the tenth thickness T62 can be to Within the range.

[0186] The upper bonding pad 650 may be disposed on the topmost layer of the upper insulating layer 601 and may be coupled to the second upper redistribution pattern 620. The upper bonding pad 650 may be disposed in the topmost layer of the upper insulating layer 601 and on the topmost layer of the upper insulating layer 601. The upper bonding pad 650 may include a seventh protrusion 651, and the seventh protrusion 651 may be disposed in the second upper redistribution pattern 620. The shape of the seventh protrusion 651 may be similar to that previously referenced. Figure 1F The fifth protrusion 151 described has the same or similar shape. The bottom surface 650b of the central region of the seventh protrusion 651 may be located at a lower level than the bottom surface 650b of the edge region. The bottom surface 650b of the seventh protrusion 651 may have a downwardly convex shape. The bottom surface 650b of the seventh protrusion 651 may correspond to the bottom surface of the upper bonding pad 650. The seventh protrusion 651 may also protrude laterally.

[0187] The bonding seed pattern 655 may be located between the upper bonding pad 650 and the second upper redistribution pattern 620. The bottom surface 655b of the bonding seed pattern 655 may be disposed within the second upper redistribution pattern 620. For example, the bottom surface 655b of the bonding seed pattern 655 may be located at a lower level than the top surface 620a of the second upper redistribution pattern 620. The bonding seed pattern 655 may be formed of at least one conductive material (e.g., copper, titanium, and alloys thereof) or may include at least one conductive material (e.g., copper, titanium, and alloys thereof).

[0188] The bonding seed pattern 655 may have a thirteenth thickness T71 between the top surface of the topmost layer in the upper insulating layer 601 and the bonding seed pattern 655. The thirteenth thickness T71 may... to Within the range. The joining seed pattern 655 on the edge region of the seventh convex portion 651 may have a twelfth thickness T72. The twelfth thickness T72 may be less than the thirteenth thickness T71. For example, the twelfth thickness T72 may be 30% to 80% of the thirteenth thickness T71. For example, the twelfth thickness T72 may be within the range of... to Within the range.

[0189] like Figure 10A As shown, the upper bonding pad 650 can be electrically connected to the solder pattern 500, the first lower semiconductor chip 210A, or the second lower semiconductor chip 220A via the first upper redistribution pattern 610, the second upper redistribution pattern 620, and the conductive structure 310. Because of the upper redistribution pattern 620, the upper bonding pad 650 does not need to be vertically aligned with the conductive structure 310.

[0190] As another example, a reference can be used. Figure 7 The redistributed substrate 100' described herein is used to fabricate the lower semiconductor package 20. In some example embodiments, the bonding protrusion 250 may be omitted. Furthermore, the arrangement relationship between the redistributed substrate 100' and the first lower semiconductor chip 210A and the second lower semiconductor chip 220A may be as follows: Figure 7 The arrangement relationship between the redistributed substrate 100' and the semiconductor chip 200 is the same or substantially the same.

[0191] The upper semiconductor package 22 may be disposed on the lower semiconductor package 20. For example, the upper semiconductor package 22 may be disposed on the upper redistribution layer 600. The upper semiconductor package 22 may include an upper substrate 710, an upper semiconductor chip 720, and an upper molding layer 730. The upper substrate 710 may be a printed circuit board. As another example, the upper substrate 710 may be a redistribution layer. For example, it may be disposed according to reference to reference. Figures 8A to 8T The upper substrate 710 is manufactured in the same manner as the redistributed substrate 100 described. First connection pads 701 and second connection pads 702 can be respectively disposed on the bottom and top surfaces of the upper substrate 710. Interconnect lines 703 can be disposed in the upper substrate 710 and coupled to the first connection pads 701 and the second connection pads 702. Figure 10A The diagram schematically illustrates an interconnect 703, and the shape and arrangement of the interconnect 703 can be varied. The first connection pad 701, the second connection pad 702, and the interconnect 703 can be formed of a conductive material (e.g., a metallic material), or may include a conductive material (e.g., a metallic material).

[0192] The upper semiconductor chip 720 may be disposed on the upper substrate 710. The upper semiconductor chip 720 may include an integrated circuit (not shown), which may include memory circuitry, logic circuitry, or a combination thereof. The upper semiconductor chip 720 may be a semiconductor chip 200 of a different type than the first lower semiconductor chip 210A and the second lower semiconductor chip 220A. For example, the upper semiconductor chip 720 may be a memory chip. A bump terminal 715 may be located between the upper substrate 710 and the upper semiconductor chip 720 and may be coupled to the second connection pad 702 and the chip pad 725 of the upper semiconductor chip 720. The upper semiconductor chip 720 may be electrically connected to the first connection pad 701 via the bump terminal 715 and the interconnect 703. Unlike that shown in the figures, the bump terminal 715 may be omitted, and the chip pad 725 may be directly bonded to the second connection pad 702.

[0193] The upper molding layer 730 may be disposed on the upper substrate 710 to cover the upper semiconductor chip 720. The upper molding layer 730 may be formed of at least one insulating polymer (e.g., an epoxy polymer) or may include at least one insulating polymer (e.g., an epoxy polymer).

[0194] The upper semiconductor package 22 may also include a heat dissipation structure 790. The heat dissipation structure 790 may include a heat sink, a heat fin, or a thermal interface material (TIM) layer. The heat dissipation structure 790 may be formed of, for example, at least one metallic material. The heat dissipation structure 790 may be disposed on the top surface of the upper molding layer 730. The heat dissipation structure 790 may further extend to cover at least a portion of the side surfaces of the upper molding layer 730.

[0195] The semiconductor package 14 may further include a connection terminal 550. The connection terminal 550 may be located between the upper bonding pad 650 and the first connection pad 701, and may be coupled to the upper bonding pad 650 and the first connection pad 701. Therefore, the upper semiconductor package 22 can be electrically connected via the connection terminal 550 to the first lower semiconductor chip 210A, the second lower semiconductor chip 220A, and the solder pattern 500. The electrical connection of the upper semiconductor package 22 may represent an electrical connection to the integrated circuit in the upper semiconductor chip 720. The connection terminal 550 may include solder, bumps, or combinations thereof. The connection terminal 550 may be formed of at least one solder or may include at least one solder.

[0196] As another example, the upper substrate 710 can be omitted, and the connection terminal 550 can be directly coupled to the chip pad 725 of the upper semiconductor chip 720. In some example embodiments, the upper molding layer 730 can directly contact the top surface of the upper redistribution layer 600. As other examples, the upper substrate 710 and the connection terminal 550 can be omitted, and the chip pad 725 of the upper semiconductor chip 720 can be directly coupled to the upper bonding pad 650.

[0197] Figure 11 This is a cross-sectional view illustrating an exemplary embodiment of a semiconductor package according to a concept of the present invention.

[0198] Reference Figure 11 The semiconductor package 15 may include a lower semiconductor package 21 and an upper semiconductor package 22. The lower semiconductor package 21 may include a redistribution substrate 100, a solder pattern 500, bonding bumps 250, connecting bumps 255, a first lower semiconductor chip 210A, a second lower semiconductor chip 220A, a molding layer 400, and a connecting substrate 300. The redistribution substrate 100, solder pattern 500, bonding bumps 250, and molding layer 400 can be coupled with… Figures 1A to 1C , Figure 1E and Figure 1F The redistribution substrate 100, solder pattern 500, bonding bumps 250, and molding layer 400 in the previous example embodiments are the same as or similar to those in the previous example embodiments. The first lower semiconductor chip 210A and the second lower semiconductor chip 220A may be comparable to those in the previous example embodiments. Figure 10A The first lower semiconductor chip 210A and the second lower semiconductor chip 220A described are the same or substantially the same. The bonding bump 250 may include a first bonding bump 251A and a second bonding bump 252A. The first bonding bump 251A and the second bonding bump 252A may be related to... Figure 10A The first engagement protrusion 251A and the second engagement protrusion 252A described are the same or substantially the same.

[0199] The semiconductor package 15 may further include a first underfill pattern 411 and a second underfill pattern 412. The first underfill pattern 411 may be disposed in a first gap region between the redistribution substrate 100 and the first lower semiconductor chip 210A. The first underfill pattern 411 may be configured to seal the first bonding protrusion 251A. The second underfill pattern 412 may be disposed in a second gap region between the redistribution substrate 100 and the second lower semiconductor chip 220A to seal the second bonding protrusion 252A.

[0200] A connecting substrate 300 may be disposed on the redistribution substrate 100. The connecting substrate 300 may have a substrate aperture 390 configured to pass through the connecting substrate 300. As an example, the connecting substrate 300 may be manufactured with a substrate aperture 390 extending from the top surface to the bottom surface through the printed circuit board. When viewed in a plan view, the substrate aperture 390 may overlap with the central portion of the redistribution substrate 100. A first lower semiconductor chip 210A and a second lower semiconductor chip 220A may be disposed in the substrate aperture 390 of the connecting substrate 300. The first lower semiconductor chip 210A and the second lower semiconductor chip 220A may be spaced apart from the inner surface of the connecting substrate 300.

[0201] The connection substrate 300 may include a base layer 320 and a conductive structure 310. The base layer 320 may include a single layer or multiple layers. The base layer 320 may be formed of at least one insulating material or may include at least one insulating material. For example, the base layer 320 may be formed of at least one of carbon-based materials, ceramics, or polymers, or may include at least one of carbon-based materials, ceramics, or polymers. The conductive structure 310 may be disposed in the base layer 320. The connection substrate 300 may also include a first pad 311 and a second pad 312. The first pad 311 may be disposed on the bottom surface of the conductive structure 310. The second pad 312 may be disposed on the top surface of the conductive structure 310. The second pad 312 may be electrically connected to the first pad 311 through the conductive structure 310. For example, the conductive structure 310, the first pad 311, and the second pad 312 may be formed of at least one of copper, aluminum, tungsten, titanium, tantalum, iron, or alloys thereof, or may include at least one of copper, aluminum, tungsten, titanium, tantalum, iron, or alloys thereof.

[0202] Connecting bump 255 may be located between redistribution substrate 100 and connecting substrate 300. Connecting bump 255 may be located between first pad 311 and corresponding bonding pad 150, and may be coupled to first pad 311 and corresponding bonding pad 150. Conductive structure 310 may be electrically connected to redistribution substrate 100 via connecting bump 255. Connecting bump 255 may include at least one of solder ball, solder bump, or solder pillar. Connecting bump 255 may be formed of at least one metallic material or may include at least one metallic material. Third underfill pattern 431 may be disposed between redistribution substrate 100 and connecting substrate 300 to seal connecting bump 255. Third underfill pattern 431 may be formed of insulating polymer or may include insulating polymer.

[0203] A molding layer 400 may be disposed on the first lower semiconductor chip 210A, the second lower semiconductor chip 220A, and the connecting substrate 300. The molding layer 400 may be located between the first lower semiconductor chip 210A and the second lower semiconductor chip 220A, between the first lower semiconductor chip 210A and the connecting substrate 300, and between the second lower semiconductor chip 220A and the connecting substrate 300. In an example embodiment, the molding layer 400 may be formed by attaching an adhesive insulating film to the top surface of the connecting substrate 300, the top surface of the first lower semiconductor chip 210A and the top surface of the second lower semiconductor chip 220A, and the side surfaces of the first lower semiconductor chip 210A and the second lower semiconductor chip 220A. For example, an Ajinomoto stacked film (ABF) may be used as the adhesive insulating film. As another example, the molding layer 400 may be formed of at least one insulating polymer (e.g., an epoxy polymer) or may include at least one insulating polymer (e.g., an epoxy polymer). As another example, the first bottom fill pattern 411 and the second bottom fill pattern 412 can be omitted, and the molding layer 400 can further extend to the bottom surface of the first lower semiconductor chip 210A and the bottom surface of the second lower semiconductor chip 220A. In an example embodiment where the third bottom fill pattern 431 is omitted, the molding layer 400 can extend into the gap between the redistribution substrate 100 and the connecting substrate 300.

[0204] The lower semiconductor package 21 may further include an upper redistribution layer 600. The upper redistribution layer 600 may be disposed on the molding layer 400 and the interconnect substrate 300. The upper redistribution layer 600 may include an upper insulating layer 601, a first upper redistribution pattern 610 and a second upper redistribution pattern 620, a first upper seed pattern 615 and a second upper seed pattern 625, a bonding seed pattern 655, and an upper bonding pad 650. The upper insulating layer 601, the first upper redistribution pattern 610, the second upper redistribution pattern 620, the first upper seed pattern 615, the second upper seed pattern 625, the bonding seed pattern 655, and the upper bonding pad 650 may be compared with those previously referenced. Figure 10A and Figure 10B The described example embodiments are the same or substantially the same. However, the first upper redistribution pattern 610 may extend into the molding layer 400. The first upper seed pattern 615 may be located between the first upper redistribution pattern 610 and the second pad 312, and between the first upper redistribution pattern 610 and the molding layer 400.

[0205] As another example, a reference can be used. Figure 7The redistributed substrate 100' described herein is used to fabricate a lower semiconductor package 21. In some example embodiments, the bonding bumps 250, connecting bumps 255, and the first underfill pattern to the third underfill patterns 411, 412, and 431 may be omitted. The arrangement relationship between the redistributed substrate 100' and the first lower semiconductor chip 210A and the second lower semiconductor chip 220A may be as follows: Figure 7 The arrangement relationship between the redistributed substrate 100' and the semiconductor chip 200 is the same or substantially the same.

[0206] The upper semiconductor package 22 may be disposed on the lower semiconductor package 21. For example, the upper semiconductor package 22 may be disposed on the upper redistribution layer 600. The upper semiconductor package 22 may include an upper substrate 710, an upper semiconductor chip 720, and an upper molding layer 730. The upper semiconductor package 22 and the connection terminal 550 may be referenced. Figure 10A and Figure 10B The upper semiconductor package 22 and the connection terminal 550 are described as being the same or substantially the same. For example, the connection terminal 550 may be located between the lower semiconductor package 20 and the upper semiconductor package 22. The upper semiconductor package 22 may also include a heat dissipation structure 790.

[0207] According to an exemplary embodiment of the present invention, the through-portion of the first redistribution pattern may have a protruding shape extending into the bottom protrusion pattern. Therefore, the bonding strength between the first redistribution pattern and the bottom protrusion pattern can be increased. The through-portion of the second redistribution pattern may have a protruding shape extending into the first redistribution pattern. Therefore, the bonding strength between the first and second redistribution patterns can be increased. Thus, the durability and reliability of the semiconductor package can be improved.

[0208] While exemplary embodiments of the inventive concept have been clearly shown and described, one of those skilled in the art will understand that variations in form and detail may be made in the exemplary embodiments of the inventive concept without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package comprising: a redistribution substrate having a first surface and a second surface opposite to each other; a semiconductor chip on the first surface of the redistribution substrate; and a solder pattern on the second surface of the redistribution substrate, wherein the redistribution substrate comprises: a bottom bump pattern coupled to the solder pattern; a first redistribution pattern on the bottom bump pattern, the first redistribution pattern comprising a first through portion and a first wire portion; and a first seed pattern between the bottom bump pattern and the first redistribution pattern and on side surfaces of the first through portion and a bottom surface of the first wire portion, wherein a bottom surface of the first seed pattern is at a lower level than a top surface of the bottom bump pattern. the first seed pattern comprises:

2. The semiconductor package of claim 1, wherein, an upper portion on the side surfaces of the first through portion and the bottom surface of the first wire portion; a first lower portion between the bottom bump pattern and a bottom surface of a central region of the first through portion; and a second lower portion in the bottom bump pattern and between the first lower portion and the upper portion, wherein the first seed pattern has a first thickness on the bottom surface of the first wire portion, the second lower portion of the first seed pattern has a second thickness, and the second thickness is less than the first thickness. the second thickness is 30% to 80% of the first thickness.

3. The semiconductor package of claim 2, wherein, a thickness of the bottom bump pattern is greater than a thickness of the first wire portion, and 4. The semiconductor package of claim 2, wherein, The first thickness is in the range of to .

5. The semiconductor package of claim 1, wherein, a bottom surface of the bottom bump pattern directly contacts the solder pattern. the first through portion comprises a convex portion in the bottom bump pattern, and at least a portion of the convex portion directly contacts the bottom bump pattern.

6. The semiconductor package of claim 1, wherein, a top surface of the bottom bump pattern has a concave shape.

7. The semiconductor package of claim 1, wherein, the redistribution substrate further comprises an insulating layer, and the insulating layer contacts the top surface of the bottom bump pattern.

8. The semiconductor package of claim 7, wherein, a bottom surface of the first through portion is at a lower level than a top surface of the bottom bump pattern and has a convex shape.

9. The semiconductor package of claim 1, wherein, the redistribution substrate further comprises an insulating layer covering side surfaces and a top surface of the bottom bump pattern and exposing a bottom surface of the bottom bump pattern, and 10. The semiconductor package of claim 1, wherein, the bottom surface of the bottom bump pattern is at a higher level than a bottom surface of the insulating layer. 11.A semiconductor package comprising: a redistribution substrate; and a semiconductor chip on a first surface of the redistribution substrate, wherein the redistribution substrate comprises: a first redistribution pattern comprising a first through portion and a first wire portion; a second redistribution pattern on the first redistribution pattern, the second redistribution pattern comprising a second through portion and a second wire portion; and a seed pattern between the first redistribution pattern and the second redistribution pattern, wherein a bottom surface of the seed pattern is in the first redistribution pattern, wherein the seed pattern comprises: an upper portion on side surfaces of the second through portion and a bottom surface of the second wire portion; and a lower portion in the first redistribution pattern and between the upper portion and the second redistribution pattern. ​ a first lower portion between the first redistribution pattern and a bottom surface of a central region of the second through portion; and a second lower portion in the first redistribution pattern and between the first lower portion and the upper portion, wherein a thickness of the second lower portion of the seed pattern is less than a thickness of the seed pattern on the bottom surface of the second wire portion.

12. The semiconductor package of claim 11, wherein, The thickness of the second lower portion of the seed pattern is 30% to 80% of the thickness of the seed pattern on the bottom surface of the second wire portion.

13. The semiconductor package of claim 11, further comprising a solder pattern on a second surface of the redistribution substrate, wherein the second surface being opposite to the first surface, the redistribution substrate comprising: a bottom bump pattern coupled to the solder pattern; and a lower seed pattern between the bottom bump pattern and the first redistribution pattern to cover a side surface of the first through portion and a bottom surface of the first wire portion, wherein a bottom surface of the lower seed pattern is at a lower level than a top surface of the bottom bump pattern.

14. The semiconductor package of claim 13, wherein, a lower portion of the second through portion is in the first redistribution pattern, and at least a portion of the lower portion of the second through portion directly contacts the first redistribution pattern.

15. The semiconductor package of claim 11, wherein, the second through portion further comprises a convex portion in the first redistribution pattern, and a bottom surface of a central region of the convex portion is at a lower level than a bottom surface of an edge region of the convex portion.

16. The semiconductor package of claim 11, wherein, a bottom surface of the first lower portion of the seed pattern is at a lower level than a bottom surface of the second lower portion of the seed pattern.

17. The semiconductor package of claim 11, wherein, a top surface of the first redistribution pattern has an upper convex shape.

18. A semiconductor package, comprising: a redistribution substrate having a first surface and a second surface opposite to each other; a semiconductor chip on the first surface of the redistribution substrate; and a solder pattern on the second surface of the redistribution substrate, wherein the redistribution substrate comprises: a bottom bump pattern coupled to the solder pattern; a first redistribution pattern on the bottom bump pattern, the first redistribution pattern comprising a first through portion and a first wire portion; a first seed pattern between the bottom bump pattern and the first redistribution pattern; a second redistribution pattern on the first redistribution pattern, the second redistribution pattern comprising a second through portion and a second wire portion; a second seed pattern between the first redistribution pattern and the second redistribution pattern; a third redistribution pattern on the second redistribution pattern, the third redistribution pattern comprising a third through portion and a third wire portion; a third seed pattern between the second redistribution pattern and the third redistribution pattern; and a bond pad electrically connected to the third redistribution pattern, wherein a bottom surface of the first seed pattern is in the bottom bump pattern, a bottom surface of the second seed pattern is in the first redistribution pattern, a bottom surface of the third seed pattern is in the second redistribution pattern, the first seed pattern comprising: an upper portion on a side surface of the first via portion and a bottom surface of the first wire portion; a first lower portion between the bottom bump pattern and a bottom surface of a central region of the first via portion; and a second lower portion in the bottom bump pattern and between the first lower portion and the upper portion of the first seed pattern, the second seed pattern includes: an upper portion on a side surface of the second via portion and a bottom surface of the second wire portion; a first lower portion between the first redistribution pattern and a bottom surface of a central region of the second via portion; and a second lower portion in the first redistribution pattern and between the first lower portion and the upper portion of the second seed pattern, the third seed pattern includes: an upper portion on a side surface of the third via portion and a bottom surface of the third wire portion; a first lower portion between the second redistribution pattern and a bottom surface of a central region of the third via portion; and a second lower portion in the second redistribution pattern and between the first lower portion and the upper portion of the third seed pattern, a first thickness of the first seed pattern on the bottom surface of the first wire portion is greater than a second thickness of the second lower portion of the first seed pattern, a third thickness of the second seed pattern on the bottom surface of the second wire portion is greater than a fourth thickness of the second lower portion of the second seed pattern, and a fifth thickness of the third seed pattern on the bottom surface of the third wire portion is greater than a sixth thickness of the second lower portion of the third seed pattern.

19. The semiconductor package of claim 18, wherein, the second thickness is 30% to 80% of the first thickness, the fourth thickness is 30% to 80% of the third thickness, and the sixth thickness is 30% to 80% of the fifth thickness.

20. The semiconductor package of claim 18, wherein, the redistribution substrate further includes an insulating layer to cover a side surface of the bottom bump pattern and expose a bottom surface of the bottom bump pattern, the bottom surface of the bottom bump pattern is at a higher level than a bottom surface of the insulating layer, and the solder pattern directly contacts the bottom surface of the bottom bump pattern.

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