Semiconductor device

Abstract

Signal quality degradation is suppressed. A semiconductor device includes a wiring substrate including first to third bonding pads; a chip stack including a plurality of semiconductor chips stacked on the wiring substrate in a stepped manner, the semiconductor chips each having first, second, and third connection pads, the plurality of first to third connection pads being connected in series via a plurality of first to third bonding wires and being connected in series with the first to third bonding pads to thereby form first to third transmission paths; and at least one termination resistor selected from a group consisting of a first termination resistor connected with the first and second transmission paths and a second termination resistor connected with the first and third transmission paths, and disposed on the chip stack.

Description

[0001] REFERENCE TO RELATED APPLICATION

[0002] This application is based on and incorporates herein by reference the prior application in the Japanese Patent Application No. 2020-151299 filed on September 9, 2020, the contents of the prior application being hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0004] A semiconductor device such as a large scale integrated circuit (LSI) has a chip stack having a plurality of semiconductor chips stacked on a wiring substrate. The chip stack is electrically connected to the wiring substrate by bonding wires. SUMMARY

[0005] One embodiment provides a semiconductor device in which reduction in signal quality is suppressed.

[0006] The semiconductor device of an embodiment has a wiring substrate including a first bonding pad electrically connected to a signal terminal, a second bonding pad electrically connected to a power supply terminal, and a third bonding pad electrically connected to a ground terminal; a chip stack including a plurality of semiconductor chips stacked on the wiring substrate in steps, the semiconductor chips each having a first connection pad, a second connection pad, and a third connection pad, the plurality of first connection pads being connected in series via a plurality of first bonding wires and connected in series to the first bonding pad to thereby form a first transmission path, the plurality of second connection pads being connected in series via a plurality of second bonding wires and connected in series to the second bonding pad to thereby form a second transmission path, the plurality of third connection pads being connected in series via a plurality of third bonding wires and connected in series to the third bonding pad to thereby form a third transmission path; and at least one terminal resistor selected from a group consisting of a first terminal resistor connected to the first transmission path and the second transmission path and a second terminal resistor connected to the first transmission path and the third transmission path, and provided on the chip stack.

[0007] According to the above structure, a semiconductor device in which reduction in signal quality is suppressed can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional schematic view for explaining a configuration example of a semiconductor device.

[0009] Figure 2 is a plan view for explaining a configuration example of a semiconductor device.

[0010] Figure 3 is an enlarged view of a part of Figure 2 .

[0011] Figure 4 is a schematic view for explaining another configuration example of the semiconductor device.

[0012] Figure 5 is a schematic view for explaining another configuration example of the semiconductor device.

[0013] Figure 6 is an equivalent circuit diagram of the semiconductor storage device.

[0014] Figure 7 is a view showing an example of an EYE pattern of a signal input and output via a signal terminal.

[0015] Figure 8 is a cross-sectional schematic view for explaining another configuration example of the semiconductor device.

[0016] Figure 9 is a top view schematic view for explaining another configuration example of the semiconductor device.

[0017] Figure 10 is an enlarged view of a part of Figure 9 .

[0018] Figure 11 is a schematic view for explaining another configuration example of the semiconductor device.

[0019] Figure 12 is a schematic view for explaining another configuration example of the semiconductor device.

[0020] Figure 13 is a schematic view for explaining another planar shape of the first wiring and the second wiring.

[0021] Figure 14 is a schematic view for explaining another configuration example of the semiconductor device.

[0022] Figure 15 is a schematic view for explaining another configuration example of the semiconductor device. DETAILED DESCRIPTION

[0023] Hereinafter, the embodiments will be described with reference to the drawings. The relationship between the thickness and the planar size of each constituent element, the ratio of the thickness of each constituent element, and the like described in the drawings are sometimes different from the actual ones. In addition, in the embodiments, substantially identical constituent elements are denoted by the same reference numerals and appropriate description is omitted.

[0024] In this specification, "connection" includes not only a physical connection but also an electrical connection unless specifically specified otherwise.

[0025] (First Embodiment)

[0026] A configuration example of a semiconductor device will be described below. Figure 1 is a cross-sectional view for illustrating a configuration example of a semiconductor device. Figure 2 is a plan view for illustrating a configuration example of a semiconductor device. The semiconductor device 100 is provided with a wiring substrate 1, a chip stack 2, a plurality of terminal resistors 3, and an insulating resin layer 4.

[0027] The wiring substrate 1 has a plurality of external connection terminals 11 provided on a first surface la and a plurality of bonding pads 12 provided on a second surface lb on the opposite side of the first surface. Examples of the wiring substrate 1 include a printed wiring board (PWB).

[0028] The plurality of external connection terminals 11 include signal terminals, power supply terminals, and ground terminals. The external connection terminals 11 are formed using, for example, gold, copper, solder, or the like. The external connection terminals 11 can also be formed using, for example, a lead-free solder of a tin-silver system or a tin-silver-copper system. Alternatively, the external connection terminals 11 can be formed using a laminate of a plurality of metal materials. In addition, in the example shown in Figure 1 , the external connection terminals 11 are formed using conductive balls, but the external connection terminals 11 can also be formed using bumps.

[0029] The plurality of bonding pads 12 are connected to the plurality of external connection terminals 11 via internal wiring of the wiring substrate 1. The plurality of bonding pads 12 include first bonding pads 121 electrically connected to the signal terminals, second bonding pads 122 connected to the power supply terminals, and third bonding pads 123 electrically connected to the ground terminals. The plurality of bonding pads 12 contain a metal element such as copper, silver, gold, or nickel. The plurality of bonding pads 12 can be formed, for example, by forming a plating film containing the above-described material using an electrolytic plating method or the like. Alternatively, the plurality of bonding pads 12 can be formed using a conductive paste.

[0030] The chip stack 2 contains a plurality of semiconductor chips 20. Examples of the semiconductor chips 20 include memory chips. The plurality of semiconductor chips 20 are stacked on the second surface lb of the wiring substrate 1 in a stepped manner. In other words, the plurality of semiconductor chips 20 partially overlap each other. The plurality of semiconductor chips 20 are adhered to each other with, for example, an adhesive layer such as a chip adhesive film. Figure 1 The chip stack 2 shown in the drawing has four semiconductor chips 20, but the number of semiconductor chips 20 is not limited to Figure 1 the number shown in the drawing.

[0031] The plurality of semiconductor chips 20 each has a plurality of connection pads 21. The plurality of semiconductor chips 20 is connected via a plurality of bonding wires 22. The plurality of connection pads 21 includes first connection pads 211, second connection pads 212, and third connection pads 213. The plurality of bonding wires 22 includes a plurality of first bonding wires 221, a plurality of second bonding wires 222, and a plurality of third bonding wires 223.

[0032] The plurality of first connection pads 211 in the plurality of semiconductor chips 20 is connected in series via the plurality of first bonding wires 221 and connected in series with the first bonding pad 121, thereby forming a first transmission path.

[0033] The plurality of second connection pads 212 in the plurality of semiconductor chips 20 is connected in series via the plurality of second bonding wires 222 and connected in series with the second bonding pad 122, thereby forming a second transmission path.

[0034] The plurality of third connection pads 213 in the plurality of semiconductor chips 20 is connected in series via the plurality of third bonding wires 223 and connected in series with the third bonding pad 123, thereby forming a third transmission path.

[0035] The bonding wire 22 contains a metal element such as gold, silver, copper, aluminum, or the like.

[0036] A plurality of terminal resistors 3 is provided on the chip stack 2. The plurality of terminal resistors 3 includes a first chip resistor 31 and a second chip resistor 32. These chip resistors are mounted on the chip stack 2, for example, via an adhesive layer. The first chip resistor 31 is connected to the first transmission path and the second transmission path. The second chip resistor 32 is connected to the first transmission path and the third transmission path. By using the above-described chip resistors, for example, the area of the terminal resistor 3 can be reduced. The resistance value of the terminal resistor 3 is not particularly limited and is, for example, 50 Ω or more.

[0037] Figure 3 is an enlarged view of a part of Figure 2 . The first chip resistor 31 has a first electrode pad 311 connected to the first transmission path and a second electrode pad 312 connected to the second transmission path. The second chip resistor 32 has a first electrode pad 321 connected to the first transmission path and a second electrode pad 322 connected to the third transmission path.

[0038] The semiconductor device 100 can have at least one terminal resistor 3. Figure 4 and Figure 5 is a schematic view for illustrating another configuration example of the semiconductor device 100. The semiconductor device 100 has, for example, no first chip resistor 31 as shown in Figure 4 , or has, for example, no second chip resistor 32 as shown in Figure 5does not have the second chip resistor 32 as shown. For the parts other than these different points, the description of the semiconductor device 100 shown in FIG. 1 can be appropriately cited. Figure 1 and Figure 2 the semiconductor device 100 shown in FIG. 1.

[0039] The insulating resin layer 4 covers the chip stack 2, the bonding wire 22, and the terminal resistor 3. The insulating resin layer 4 contains an inorganic filler material such as silicon oxide (SiO2), and is formed by a molding method such as transfer molding, compression molding, injection molding, or the like using a sealing resin in which the inorganic filler material is mixed with an organic resin or the like.

[0040] In the semiconductor device of the present embodiment, by matching the resistance value of the first chip resistor 31, the resistance value of the second chip resistor 32, or the combined resistance value of the first chip resistor 31 and the second chip resistor 32 with the characteristic impedance of the first transmission path, the reflected wave of the signal via the signal terminal is suppressed.

[0041] Here, in order to explain the suppression effect of the terminal resistor 3 on the reflected wave, reference is made to Figure 6 and Figure 7 The relationship between the connection structure of the memory and the memory controller of the semiconductor storage device and the reduction in signal quality is explained. Figure 6 is an equivalent circuit diagram of the semiconductor storage device. Figure 7 is a diagram showing an example of an EYE pattern of a signal input and output via a signal terminal.

[0042] The semiconductor storage device is provided with a memory and a memory controller 5 composed of the chip stack 2. The chip stack 2 has a capacitance component Cl and an inductance component LI. The memory controller 5 has a capacitance component C2 and an inductance component L2. The chip stack 2 and the memory controller 5 are electrically connected via the wiring substrate 1. These elements form the above-described first transmission path.

[0043] In the semiconductor storage device, a reflected wave of a signal is generated via the first transmission path, for example, at the time of readout. As a result, for example, the deviation of the signal becomes large, and the EYE pattern 6 is deformed. The higher the transmission speed between the chip stack 2 and the memory controller 5, the more pronounced the above-described phenomenon.

[0044] On the other hand, as shown in Figure 6 the terminal resistor 3 is connected to the first transmission path, and the resistance value of the terminal resistor 3 is matched with the characteristic impedance of the first transmission path, whereby the reflected wave of the signal can be suppressed. As a result, the deformation of the EYE pattern 6 can be suppressed. Therefore, the reduction in signal quality can be suppressed.

[0045] In one of the existing semiconductor devices, a device in which a terminal resistor is connected to a signal line connected to a single semiconductor chip is known. However, in the case where a plurality of semiconductor chips are stacked as in the semiconductor device of the present embodiment, if the characteristic impedance of a transmission path constituted by a conductor electrically connecting between the semiconductor chips and a connection pad of the semiconductor chip is not matched with the resistance value of the terminal resistor, it is difficult to suppress a reflected wave of a signal.

[0046] In addition, as another of the existing semiconductor devices, a device using on-die termination (ODT) in which a terminal resistor is built in an input circuit including an input element in a semiconductor chip is known. However, in the case where the characteristic impedance of a transmission path constituted by a conductor electrically connecting between the semiconductor chips and a connection pad of the semiconductor chip is as small as 10 Ω or less, the circuit size of the ODT becomes large, and the size of the semiconductor chip becomes large. In addition, with the ODT, if a switching circuit of a termination mode and a resistance value adjustment circuit of the ODT are not incorporated at the stage of circuit design, switching of the termination mode and adjustment of the resistance value of the ODT cannot be performed, and thus flexible changes cannot be made after the circuit design.

[0047] In contrast, in the semiconductor device of the present embodiment, by providing a terminal resistor connected to a first transmission path including a wire bonding connecting between a plurality of semiconductor chips on the chip stack, each semiconductor chip does not need to have any terminal resistor. Thus, the degree of freedom of the circuit design of the semiconductor chip can be improved.

[0048] (Second Embodiment)

[0049] The following describes another configuration example of the semiconductor device. Figure 8 is a cross-sectional view for explaining another configuration example of the semiconductor device. Figure 9 is a plan view for explaining another configuration example of the semiconductor device. The semiconductor device 100 includes a wiring substrate 1, a chip stack 2, a plurality of terminal resistors 3, and an insulating resin layer 4. The wiring substrate 1, the chip stack 2, and the insulating resin layer 4 are the same as those of the semiconductor device of the first embodiment, and thus the description thereof is omitted, and the description of the first embodiment can be appropriately referred to.

[0050] A plurality of terminal resistors 3 are provided on the chip stack 2. The plurality of terminal resistors 3 include a first wiring 33 and a second wiring 34. These wirings are formed on the surface of the chip stack 2 by a method such as sputtering or plating. The wirings contain a material such as gold, silver, copper, titanium, chromium, or the like. The first wiring 33 is connected to the first transmission path and the second transmission path. The second wiring 34 is connected to the first transmission path and the third transmission path. By using the above-described wirings, for example, the resistance value of the terminal resistor 3 can be easily adjusted.

[0051] Figure 10 is an enlarged view of a part of Figure 9 . The first wiring 33 has one end connected to the first transmission path and the other end connected to the second transmission path. The second wiring 34 has one end connected to the first transmission path and the other end connected to the third transmission path.

[0052] The semiconductor device 100 only needs to have at least one terminal resistor 3. Figure 11 and Figure 12 are schematic diagrams for explaining other configuration examples of the semiconductor device 100. The other configuration examples of the semiconductor device 100 do not have the first wiring 33 as illustrated in Figure 11 , or do not have the second wiring 34 as illustrated in Figure 12 . As for the parts other than these different points, the explanation of the semiconductor device 100 illustrated in Figure 8 and Figure 9 can be appropriately referred to.

[0053] Figures 9 to 12 The planar shape of the first wiring 33 and the second wiring 34 illustrated in Figure 13 has a ring shape, but the planar shape of the first wiring 33 and the second wiring 34 is not particularly limited.

[0054] Figure 14 and Figure 15 are schematic diagrams for explaining other configuration examples of the semiconductor device 100. The other configuration examples of the semiconductor device 100 do not have the first wiring 33 having a meandering shape as illustrated in Figure 14 , or do not have the second wiring 34 having a meandering shape as illustrated in Figure 15 . As for the parts other than these different points, the explanation of the semiconductor device 100 illustrated in Figure 8 and Figure 9 can be appropriately referred to.

[0055] In the semiconductor device of this embodiment, the resistance value of the first wiring 33, the resistance value of the second wiring 34, or the resistance value of the parallel combination of the first wiring 33 and the second wiring 34 is matched with the characteristic impedance of the first transmission path, thereby suppressing a reflected wave of a signal via the signal terminal. Thus, it is possible to suppress a decrease in signal quality.

[0056] In addition, in the semiconductor device of this embodiment, a terminal resistance connected to the first transmission path including the bonding wire connecting the plurality of semiconductor chips is provided above the chip stack, and thus each semiconductor chip does not need to have any terminal resistance. Thus, it is possible to improve the degree of freedom of the circuit design of the semiconductor chip.

[0057] The several embodiments of the present application are described, but these embodiments are suggested as examples, and are not intended to limit the scope of the application. These new embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made within the scope of the gist of the application. These embodiments and modifications thereof are included in the scope and gist of the application, and are included in the scope of the application and equivalents thereof recited in the claims.

Claims

1. A semiconductor device comprising: a first bonding pad electrically connected to a signal terminal; a second bonding pad electrically connected to a power supply terminal; and a third bonding pad electrically connected to a ground terminal; a chip stack including a plurality of semiconductor chips stacked on the wiring substrate in a stepped manner, the semiconductor chips each having a first connection pad, a second connection pad, and a third connection pad, a plurality of the first connection pads being connected in series via a plurality of first bonding wires and connected in series to the first bonding pad, thereby forming a first transmission path, a plurality of the second connection pads being connected in series via a plurality of second bonding wires and connected in series to the second bonding pad, thereby forming a second transmission path, and a plurality of the third connection pads being connected in series via a plurality of third bonding wires and connected in series to the third bonding pad, thereby forming a third transmission path; and a first termination resistor and a second termination resistor provided on the chip stack, the first termination resistor being connected to the first transmission path and the second transmission path, and the second termination resistor being connected to the first transmission path and the third transmission path. A wiring substrate comprising:

2. The semiconductor device according to claim 1, wherein a resistance value of the first termination resistor matches a characteristic impedance of the first transmission path, and a resistance value of the second termination resistor matches the characteristic impedance of the first transmission path.

3. The semiconductor device according to claim 1, wherein a combined resistance value of the first termination resistor and the second termination resistor matches the characteristic impedance of the first transmission path.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first termination resistor includes a first chip resistor having a first electrode pad connected to the first transmission path and a second electrode pad connected to the second transmission path, and the second termination resistor includes a second chip resistor having a third electrode pad connected to the first transmission path and a fourth electrode pad connected to the third transmission path.

5. The semiconductor device according to any one of claims 1 to 3, wherein the first termination resistor includes a first wiring having one end connected to the first transmission path and the other end connected to the second transmission path, and the second termination resistor includes a second wiring having one end connected to the first transmission path and the other end connected to the third transmission path.

6. The semiconductor device according to any one of claims 1 to 3, wherein the plurality of semiconductor chips each do not have a termination resistor. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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