Display panel and display device

Abstract

Embodiments of the present disclosure provide a display panel and a display device, which relate to the field of display technology and are used to solve the problem of improving the transparency of a transparent display device. The display panel has a display area, and the display area includes a plurality of sub-display areas distributed at intervals, and a sub-display area includes at least two sub-pixel areas. The display panel includes a substrate, an insulating stack structure, and an encapsulation layer. The insulating stack structure includes a plurality of insulating dielectric layers stacked on a substrate, and the insulating stack structure has a plurality of first isolation grooves on a surface away from the substrate, and at least one first isolation groove is arranged along the circumference of the sub-display area. The encapsulation layer is arranged on a side of the insulating stack structure away from the substrate, and a portion of the encapsulation layer is located in the plurality of first isolation grooves.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic light-emitting display devices have the advantages of self-luminescence, fast response, wide viewing angle, high brightness, bright colors, and light weight, and therefore have become an important display technology.

[0003] The organic light-emitting display device may be a transparent display device. When the transparent display device displays an image, the user can see the displayed image from the front of the screen and can also see the object on the back of the transparent display device through the screen. Transparent display devices have been widely used in industries such as smart homes, vehicle applications, and military industry.

[0004] However, how to improve the transparency of transparent display devices has become an urgent problem to be solved in the industry. Summary of the invention

[0005] Embodiments of the present invention provide a display panel and a display device, aiming to improve the transparency of a transparent display device.

[0006] To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0007] In a first aspect, a display panel is provided, the display panel having a display area, the display area including a plurality of sub-display areas distributed at intervals, and a sub-display area including at least two sub-pixel areas. The display panel includes a substrate, an insulating stack structure, and an encapsulation layer. The insulating stack structure includes a plurality of insulating dielectric layers stacked on the substrate, and the insulating stack structure has a plurality of first isolation grooves on a surface away from the substrate, and at least one first isolation groove is arranged along the circumference of the sub-display area. The encapsulation layer is arranged on a side of the insulating stack structure away from the substrate, and a portion of the encapsulation layer is located in the plurality of first isolation grooves.

[0008] In some embodiments, at least one of the plurality of insulating dielectric layers is a transmittance enhancing dielectric layer. A transmittance enhancing dielectric layer has a plurality of through grooves, the through grooves penetrate the transmittance enhancing dielectric layer along the thickness direction of the display panel, and a through groove is used to form a first isolation groove.

[0009] In some embodiments, among the multiple insulating dielectric layers, an insulating dielectric layer closest to the encapsulation layer is a transmittance enhancing dielectric layer. Alternatively, among the multiple insulating dielectric layers, each of the N consecutive insulating dielectric layers close to the encapsulation layer is a transmittance enhancing dielectric layer. Two adjacent transmittance enhancing dielectric layers are a first transmittance enhancing dielectric layer and a second transmittance enhancing dielectric layer, and the second transmittance enhancing dielectric layer is located on the side of the first transmittance enhancing dielectric layer away from the substrate. A through groove on the first transmittance enhancing dielectric layer is connected to a through groove on the second transmittance enhancing dielectric layer. Wherein, N is greater than or equal to 2 and less than or equal to the number of insulating dielectric layers in the insulating stack structure.

[0010] In some embodiments, an orthographic projection of a through-groove on the first transmittance enhancing medium layer on the substrate is located within an orthographic projection of a through-groove on the second transmittance enhancing medium layer on the substrate.

[0011] In some embodiments, the multiple insulating dielectric layers include multiple inorganic insulating layers, each of which is an insulating dielectric layer. The multiple insulating dielectric layers also include at least one organic insulating layer, at least one organic insulating layer is located on the side of the multiple inorganic insulating layers away from the substrate, and each organic insulating layer is an insulating dielectric layer. The multiple insulating dielectric layers also include a pixel defining layer, which is located on the side of at least one organic insulating layer away from the substrate, and the pixel defining layer is an insulating dielectric layer. Among the multiple inorganic insulating layers, at least one organic insulating layer and at least one insulating dielectric layer in the pixel defining layer is a transmittance enhancing dielectric layer.

[0012] In some embodiments, the insulating stack structure further includes a plurality of first isolation walls, at least one of which is disposed along the circumference of the sub-display area and is located on a side of at least one first isolation groove disposed along the circumference of the sub-display area away from the sub-display area, and is used to form a sidewall of at least one first isolation groove disposed along the circumference of the sub-display area. Alternatively, the insulating stack structure further includes a plurality of second isolation walls, each of which is located between two adjacent sub-display areas, and the plurality of second isolation walls extend to form an isolation net, which separates the first isolation grooves surrounding different sub-display areas.

[0013] In some embodiments, the first isolation wall includes a first isolation pattern and a second isolation pattern sequentially arranged in a direction away from the substrate, and an orthographic projection of the second isolation pattern on the substrate is located within an orthographic projection of the first isolation pattern on the substrate.

[0014] In some embodiments, the display panel further includes an electrode layer located on a side of the insulating stack structure away from the substrate, the electrode layer includes a plurality of electrode patterns spaced apart from each other, and an electrode pattern covers at least a portion of a sub-display area.

[0015] In some embodiments, the display panel further includes a plurality of signal lines disposed in the display area and on a side of the electrode layer close to the substrate, and each electrode pattern is coupled to a signal line.

[0016] In some embodiments, the display panel further includes a light-emitting functional layer located on a side of the insulating stack structure away from the substrate, the light-emitting functional layer includes a plurality of light-emitting functional patterns spaced apart from each other, and a light-emitting functional pattern covers at least a portion of a sub-display area.

[0017] In some embodiments, the encapsulation layer includes an organic encapsulation layer, and a portion of the organic encapsulation layer is located in the first isolation trench.

[0018] In some embodiments, the insulating stack structure further has at least one second isolation groove on a surface away from the substrate, and the at least one second isolation groove is arranged along the circumference of the display area. A portion of the encapsulation layer is located in the at least one second isolation groove.

[0019] In some embodiments, the display panel further comprises a retaining wall disposed on a side of the insulating stack structure away from the substrate and on a side of the at least one second isolation groove away from the display area, the retaining wall surrounding the display area and the encapsulation layer covering the retaining wall.

[0020] In a second aspect, a display device is provided, comprising the display panel provided by any one of the above embodiments.

[0021] In the display panel provided by the embodiment of the present disclosure, the insulating stack structure is located between the substrate and the encapsulation layer, and a plurality of first isolation grooves are provided on the surface of the insulating stack structure away from the substrate, and at least one first isolation groove is arranged along the circumference of the sub-display area. At the first isolation groove, the thickness of the insulating stack structure is smaller than the thickness at other positions of the insulating stack structure, so the light transmittance of the display panel at the first isolation groove can be higher, thereby improving the transparency of the display panel.

[0022] It can be understood that the display device provided in the second aspect includes the above-mentioned display panel. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the display panel mentioned above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a structural diagram of a display device according to some embodiments;

[0025] Figure 2 is a structural diagram of a display panel according to some embodiments;

[0026] Figure 3A to Figure 3F is a structural diagram of a sub-display area in a display panel according to some embodiments;

[0027] Figure 4 for Figure 2 A cross-sectional view of the display panel along section line AA';

[0028] Figure 5 for Figure 2 A partial enlarged view of area Q1 in the display panel;

[0029] Figure 6 is a top view of a display panel according to some embodiments;

[0030] Figure 7 for Figure 6 A partial enlarged view of area Q2 in the display panel;

[0031] Figure 8 is a top view of a display panel according to some embodiments;

[0032] Fig. 9 for Figure 8 A partial enlarged view of area Q3 in the display panel;

[0033] Fig.10 is a top view of a display panel according to some embodiments;

[0034] Fig.11 for Fig.10 A partial enlarged view of area Q4 in the display panel;

[0035] Fig.12 for Figure 8 A cross-sectional view of the display panel along section line BB';

[0036] Fig.13 for Figure 2 A partial enlarged view of area Q5 in the display panel;

[0037] Fig.14 for Fig.13 A cross-sectional view of the display panel along section line CC';

[0038] Fig.15 for Figure 6 A partial enlarged view of area Q6 in the display panel;

[0039] Fig.16 is a top view of a display panel according to some embodiments;

[0040] Fig.17 is a structural diagram of an electrode pattern and a signal line in a display panel according to some embodiments;

[0041] Fig.18A is a top view of a display panel according to some embodiments;

[0042] Fig.18B for Fig.18A A cross-sectional view of the display panel along section line DD';

[0043] Fig.19 is a top view of a display panel according to some embodiments;

[0044] Fig. 20 for Fig.19 A cross-sectional view of the display panel along section line EE'. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0052] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, "substantially" or "approximately" includes the stated values ​​and averages that are within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0054] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0055] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0056] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0057] An embodiment of the present disclosure provides a display device. Figure 1 is a structural diagram of a display device according to some embodiments. Figure 1 The display device 1 is a product with an image (including: static image or dynamic image, where the dynamic image can be a video) display function. For example, the display device 1 can be any one of: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a home appliance, an information query device (such as business query equipment for e-government, banks, hospitals, electricity, etc.), a monitor, etc.

[0058] The display device 1 may include a display panel 10, and the display device 1 may further include a driving control circuit 20 coupled to the display panel 10. The driving control circuit 20 is configured to provide an electrical signal to the display panel 10. Exemplarily, the driving control circuit 20 may include: a data driving circuit 210 (also referred to as a source driver, Source Driver IC), the data driving circuit 210 is configured to provide a data driving signal (also referred to as a data signal) to the display panel 10. The driving control circuit 20 may also include a timing control circuit 220 (also referred to as a timing controller, TimerControl Register, referred to as TCON) coupled to the data driving circuit 210, etc.

[0059] In some embodiments, the drive control circuit 20 may further include a scan drive circuit 110. In other embodiments, the scan drive circuit 110 may be integrated in the display panel 10, or in other words, the display panel 10 may include the scan drive circuit 110. Since the scan drive circuit 110 is disposed on the display panel 10, the scan drive circuit 110 may also be referred to as a GOA (Gate Driver on Array, a scan drive circuit disposed on an array substrate).

[0060] Specifically, the timing control circuit 220 can be coupled to the scan drive circuit 110, and can also be coupled to the data drive circuit 210. The timing control circuit 220 can be configured to receive a display signal, which includes, for example, a power signal, a video image signal, a communication signal (for example, a signal corresponding to the IIC communication protocol), and a mode control signal (for example, a mode control signal corresponding to the test mode, or a mode control signal corresponding to the normal display mode). Among them, the video image signal is, for example, a MIPI (Mobile Industry Processor Interface) signal, a LVDS (Low-Voltage Differential Signaling) signal. The video image signal may include: image data and a timing control signal. The image data includes, for example, pixel data of multiple sub-pixels, and the pixel data may be RGB data, etc. The timing control signal includes, for example, a data enable signal (Data Enable, which may be referred to as DE), a line synchronization signal (Hsync, which may be referred to as HS), and a field synchronization signal (Vsync, which may be referred to as VS).

[0061] The timing control circuit 220 may also be configured to output a first control signal and image data to the data driving circuit 210 and output a second control signal to the scan driving circuit 110 in response to the display signal. The first control signal is configured to control the working timing of the data driving circuit 210, and the second control signal is configured to control the working timing of the scan driving circuit 110.

[0062] The data driving circuit 210 may be configured to convert the received image data into data signals for a plurality of light emitting devices E (to be described below) in the display panel 10, and output the data signals to a pixel driving circuit DC (to be described below) coupled to the corresponding light emitting devices E according to the working sequence determined by the first control signal. The scanning driving circuit 110 is configured to output scanning signals to the plurality of pixel driving circuits DC according to the working sequence determined by the second control signal.

[0063] Some embodiments of the present disclosure also provide a display panel. The display panel can be used as a display panel in a display device provided in any of the above embodiments. Of course, the display panel can also be applied to other display devices, which is not limited by the embodiments of the present disclosure.

[0064] See also Figure 1 The display panel 10 may be one of an OLED (Organic Light Emitting Diode) display panel, a QLED (Quantum Dot Light Emitting Diodes) display panel, and a micro LED (including MiniLED or MicroLED, LED is a light emitting diode) display panel.

[0065] Continue to see Figure 1 The display panel 10 may include a plurality of light emitting devices E. The display panel 10 may also include a plurality of pixel driving circuits DC. A light emitting device E (eg, each light emitting device E) may be coupled to a pixel driving circuit DC.

[0066] The light emitting device E may be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or a light emitting diode (LED).

[0067] The pixel driving circuit DC can be configured to provide an electrical signal (such as a driving voltage or a driving current) to the light-emitting device E coupled to the pixel driving circuit DC in response to the received scanning signal and data signal, so as to drive the light-emitting device E to emit light, so that the display panel 10 can display the picture.

[0068] The pixel driving circuit DC may include multiple transistors and at least one (e.g., one; or, for example, multiple) capacitor. For example, the pixel driving circuit DC may have a structure such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C". Here, "T" represents a transistor, such as a thin film transistor. The number before "T" represents the number of transistors. "C" represents a capacitor, and the number before "C" represents the number of capacitors.

[0069] Figure 2 is a structural diagram of a display panel according to some embodiments. Figure 3A to Figure 3C FIG. 1 is a structural diagram of a sub-display area in a display panel according to some embodiments. It should be noted that: Figure 2 Only the structure of the display area of ​​the display panel is shown, while the structure of the peripheral area is omitted, for example, the scan driving circuit is omitted.

[0070] See also Figure 2 The display panel 10 has a display area AA and a peripheral area SA. The peripheral area SA may be located on at least one side (eg, one side; or all around, i.e., including upper and lower sides and left and right sides) of the display area AA.

[0071] See also Figure 2 and Figure 3A to Figure 3D , the display area AA includes a plurality of sub-display areas K distributed at intervals. A sub-display area K (e.g., each sub-display area K) includes at least two (e.g., three; for example, four; for example, eight) sub-pixel areas P. In the display panel 10, a plurality of (e.g., all) sub-display areas K may be distributed in an array. For example, a plurality of sub-display areas K distributed along the X-axis direction may be a row of sub-display areas, and a plurality of sub-display areas K distributed along the Y-axis direction may be a column of sub-display areas, and the X-axis direction is perpendicular to the Y-axis direction and both are parallel to the extension direction of the display panel 10.

[0072] A sub-pixel region P (for example, each sub-pixel region P) can emit light. Specifically, at least a portion of a light-emitting device can be located in a sub-pixel region P, and the light-emitting device can emit light, so that the sub-pixel region P can emit light.

[0073] See also Figure 3A to Figure 3D, a sub-display area K (for example, each sub-display area K) may include a plurality of sub-pixel areas P. The plurality of sub-pixel areas P may include a plurality of sub-pixel areas P with different luminous colors. By adjusting the luminous brightness of the sub-pixel areas P of different colors in the sub-display area K, a display of multiple colors can be achieved through color combination and superposition, thereby achieving full-color display of the display panel 10. Exemplarily, the plurality of sub-pixel areas P of a sub-display area K include three sub-pixel areas P with different luminous colors, for example, a first sub-pixel area P1, a second sub-pixel area P2, and a third sub-pixel area P3, and the first sub-pixel area P1, the second sub-pixel area P2, and the third sub-pixel area P3 can emit three primary colors of light, respectively, for example, the first sub-pixel area P1 can emit red light, the second sub-pixel area P2 can emit green light, and the third sub-pixel area P3 can emit blue light.

[0074] In some possible implementations, see Figure 3A and Figure 3B , a sub-display area K includes three sub-pixel areas P. For example, the sub-display area K may include a first sub-pixel area P1, a second sub-pixel area P2, and a third sub-pixel area P3. Figure 3C and Figure 3E , a sub-display area K includes four sub-pixel areas P. For example, the sub-display area K may include a first sub-pixel area P1, a third sub-pixel area P3, and two second sub-pixel areas P2. Figure 3D and Figure 3F , a sub display area K includes eight sub pixel areas P, specifically, the sub display area K may include two first sub pixel areas P1, two third sub pixel areas P3 and four second sub pixel areas P2.

[0075] It is understandable that the plurality of sub-pixel regions P in a sub-display region K of the display panel may also have other arrangements, which are not limited in the embodiments of the present disclosure.

[0076] Figure 4 for Figure 2 A cross-sectional view of the display panel along the section line AA'. Figure 4 The display panel 10 includes a substrate 110. The substrate 110 may provide a basis for other structures in the display panel 10. The substrate 110 may be rigid or flexible. When the substrate 110 is a rigid substrate, the material forming the rigid substrate may be glass. When the substrate 110 is a flexible substrate, the material forming the flexible substrate may be PI (polyimide), PET (polyethylene terephthalate), ultra-thin glass, etc.

[0077] In some embodiments, the substrate 110 is a flexible substrate. For example, the material of the substrate 110 may include PI. At this time, in the process of manufacturing the display panel 10, the substrate 110 may be manufactured on a rigid substrate, and then other structures of the display panel 10 may be manufactured on the substrate 110. The rigid substrate may provide support in the manufacture of the display panel 10. Afterwards, the display panel 10 may be peeled off from the rigid substrate to form the display panel 10. Exemplarily, the rigid substrate may be a glass substrate.

[0078] In addition, the substrate 110 may be a transparent substrate. For example, the material of the substrate 110 includes PI, and the PI material may be transparent, so that the substrate 110 may be a transparent substrate. In this way, the light transmittance of the display panel 10 may be improved, and the transparency of the display panel 10 may be improved.

[0079] The display panel 10 may further include a buffer layer 120. The buffer layer 120 may be disposed on the substrate 110 and in contact with the substrate 110. The buffer layer 120 may be configured to block water vapor and foreign particles in the substrate 110, reduce damage to the light-emitting device caused by the water vapor and foreign particles in the substrate 110, and thereby extend the service life of the display panel 10. The material of the buffer layer 120 includes, for example, SiO2 or SiOC.

[0080] Continue to see Figure 4 The display panel 10 may include a first electrode layer 131, a second electrode layer 132, and a light emitting layer 133 located between the first electrode layer 131 and the second electrode layer 132. The display panel 10 may also include one or more light emitting functional layers 134 located between the first electrode layer 131 and the second electrode layer 132. The first electrode layer 131, the second electrode layer 132, the light emitting layer 133, and the one or more light emitting functional layers 134 may form a plurality of light emitting devices E.

[0081] The first electrode layer 131 may be disposed on a side of the second electrode layer 132 close to the substrate 110. The first electrode layer 131 may include a plurality of first electrodes 131p, and a first electrode 131p (e.g., each first electrode 131p) may be configured as an electrode of a light emitting device E, such as an anode. The material of the first electrode layer 131 may include a metal compound, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0082] The second electrode layer 132 may include a plurality of second electrodes 132p, and a second electrode 132p (e.g., each second electrode 132p) may be configured as an electrode (e.g., a cathode) of a light-emitting device E. The material of the second electrode layer 132 may include a metal or an alloy, such as a metal such as magnesium (Mg), titanium (Ti), silver (Ag), or an alloy formed by a plurality of metals. The material of the second electrode layer 132 may also include a metal compound, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second electrode layer 132 may be transparent or translucent. In this way, the second electrode layer 132 may allow the light emitted by the light-emitting layer 133 to be emitted through the second electrode layer 132. At this time, the light-emitting device E may be a top-emitting light-emitting device.

[0083] The light-emitting layer 133 may include a plurality of light-emitting patterns 133p, and a light-emitting pattern 133p (for example, each light-emitting pattern 133p) may be located between a first electrode 131p and a second electrode 132p of a light-emitting device E. The light-emitting pattern 133p may emit light, for example, the light-emitting pattern 133p may emit red light, green light, blue light or white light. The material of the light-emitting pattern 133p may include an organic light-emitting material. It should be noted that, in this article, the orthographic projection of the pattern (for example, the light-emitting pattern) on the substrate may have a closed outer contour.

[0084] A light-emitting functional layer 134 (for example, each light-emitting functional layer 134) may be one of a hole injection layer, a hole transport layer, an electron blocking layer, an electron injection layer, an electron transport layer, and a hole blocking layer. When the light-emitting functional layer 134 is one of a hole injection layer, a hole transport layer, and an electron blocking layer, the light-emitting functional layer 134 may be located between the light-emitting layer 133 and the first electrode layer 131. When the light-emitting functional layer 134 is one of an electron injection layer, an electron transport layer, and a hole blocking layer, the light-emitting functional layer 134 may be located between the light-emitting layer 133 and the second electrode layer 132.

[0085] For example, see Figure 4 The display panel 10 includes two light-emitting functional layers 134, namely, a light-emitting functional layer 134a and a light-emitting functional layer 134b. The light-emitting functional layer 134a is located between the first electrode layer 131 and the light-emitting layer 133, and the light-emitting functional layer 134a may be a hole transport layer. The light-emitting functional layer 134b is located between the second electrode layer 132 and the light-emitting layer 133, and the light-emitting functional layer 134b may be an electron transport layer.

[0086] Referring to the above description, the display panel 10 further includes a plurality of pixel driving circuits. Figure 4 The display panel 10 may include a semiconductor layer 140 and a plurality of conductor layers 150 stacked together. The semiconductor layer 140 and the plurality of conductor layers 150 may form a plurality of pixel driving circuits in the display panel 10.

[0087] Specifically, the semiconductor layer 140 may be disposed on the substrate 110. Exemplarily, the semiconductor layer 140 may be disposed on a side of the buffer layer 120 away from the substrate 110. Referring to the above description, a pixel driving circuit (e.g., each pixel driving circuit) in the display panel 10 may include a plurality of transistors T, and a transistor T (e.g., each transistor T) may be, for example, a thin film transistor. A transistor T (e.g., each transistor T) may be, for example, Figure 4 Specifically, the semiconductor layer 140 may include an active layer Ta of a plurality of transistors T.

[0088] A plurality of conductor layers 150 may be stacked on the substrate 110. For example, the plurality of conductor layers 150 may be disposed on a side of the semiconductor layer 140 away from the substrate 110, and disposed on a side of the plurality of light emitting devices E close to the substrate 110.

[0089] The plurality of conductor layers 150 may include a first conductor layer 151, and the first conductor layer 151 may include gates Tg of a plurality of transistors T. The first conductor layer 151 may also include a plate of a capacitor in each pixel driving circuit. The first conductor layer 151 may also include one or more signal lines in each pixel driving circuit, for example, one or more signal lines extending along the Y-axis direction and coupled to the scan driving circuit.

[0090] The plurality of conductor layers 150 may further include a second conductor layer 152. The second conductor layer 152 may include another plate of a capacitor in each pixel driving circuit, and may also include one or more signal lines in each pixel driving circuit, for example, one or more signal lines extending along the Y-axis direction and coupled to the scan driving circuit.

[0091] The plurality of conductor layers 150 may further include a third conductor layer 153 and / or a fourth conductor layer 154. The third conductor layer 153 and the fourth conductor layer 154 may include one or more signal lines in each pixel driving circuit, for example, one or more signal lines extending along the X-axis direction and coupled to the data driving circuit.

[0092] Continue to see Figure 4 The display panel 10 further includes a plurality of insulating dielectric layers, which are stacked on the substrate 110 to form an insulating stack structure 160. In other words, the display panel 10 further includes an insulating stack structure 160, which includes a plurality of insulating dielectric layers stacked on the substrate 110. Exemplarily, the insulating stack structure 160 may be disposed on the substrate 110 and disposed on a side of the second electrode layer 132 close to the substrate 110.

[0093] In some embodiments, the plurality of insulating dielectric layers may include a plurality of inorganic insulating layers 161, each of which is an insulating dielectric layer. As described above, the plurality of conductor layers 150 may be stacked, and an inorganic insulating layer 161 may be disposed between two adjacent conductor layers 150 to separate them.

[0094] Exemplarily, the plurality of inorganic insulating layers 161 may include a first inorganic insulating layer 161a, which is disposed between the semiconductor layer 140 and the first conductor layer 151. The first inorganic insulating layer 161a may be configured as a gate insulating layer of the plurality of transistors T. The plurality of inorganic insulating layers 161 may further include a second inorganic insulating layer 161b. The second inorganic insulating layer 161b is disposed between the first conductor layer 151 and the second conductor layer 152, and is configured to separate the first conductor layer 151 and the second conductor layer 152. The plurality of inorganic insulating layers 161 may further include a third inorganic insulating layer 161c. The third inorganic insulating layer 161c is disposed between the second conductor layer 152 and the third conductor layer 153, and is configured to separate the second conductor layer 152 and the third conductor layer 153. The plurality of inorganic insulating layers 161 may further include a fourth inorganic insulating layer 161d. The fourth inorganic insulating layer 161 d is provided between the third conductor layer 153 and the fourth conductor layer 154 , and is configured to separate the third conductor layer 153 from the fourth conductor layer 154 .

[0095] Continue to see Figure 4 Based on the above, the display panel 10 may include a plurality of conductor layers 150 and a plurality of inorganic insulating layers 161, and a plurality of light-emitting devices E may be arranged on a side of the plurality of conductor layers 150 and the plurality of inorganic insulating layers 161 away from the substrate 110. In some embodiments, in order to improve the flatness of the plurality of light-emitting devices E and thereby improve the performance of the plurality of light-emitting devices E, the plurality of insulating dielectric layers may further include at least one (for example, one; for example, multiple) organic insulating layers 162, and each organic insulating layer 162 is an insulating dielectric layer. At least one (for example, all) organic insulating layers 162 are located on a side of the plurality of (for example, all) inorganic insulating layers 161 away from the substrate 110, and are arranged on a side of the plurality of light-emitting devices E close to the substrate 110. An organic insulating layer 162 (for example, each organic insulating layer 162) may be configured as a planarization layer, which may make the light-emitting device E arranged on the side of the organic insulating layer 162 away from the substrate 110 relatively flat.

[0096] Exemplarily, the plurality of organic insulating layers 162 may include a first organic insulating layer 162a and a second organic insulating layer 162b. The first organic insulating layer 162a may be disposed between the fourth inorganic insulating layer 161d and the fourth conductor layer 154, so that the fourth conductor layer 154 may be relatively flat. The second organic insulating layer 162b may be disposed between the fourth conductor layer 154 and the plurality of light-emitting devices E, specifically, the second organic insulating layer 162b may be disposed between the fourth conductor layer 154 and the first electrode layer 131, so that the plurality of light-emitting devices E may be relatively flat, thereby improving the performance of the plurality of light-emitting devices E.

[0097] In some embodiments, the plurality of insulating dielectric layers may include a pixel defining layer 163, which is an insulating dielectric layer. The pixel defining layer 163 may be disposed on the substrate 110. Specifically, the pixel defining layer 163 may be disposed on a side of the first electrode layer 131 away from the substrate 110, and on a side of the second electrode layer 132 close to the substrate 110.

[0098] The pixel defining layer 163 has a plurality of openings H. An opening H may be configured to define a sub-pixel region. Exemplarily, a sub-pixel region (e.g., each sub-pixel region) may be directly opposite to an opening H. For example, at least a portion (e.g., part; or, for example, all) of an orthographic projection of a sub-pixel region (e.g., each sub-pixel region) on the substrate 110 may overlap with an orthographic projection of an opening H on the substrate 110.

[0099] Continue to see Figure 4 The display panel 10 further includes an encapsulation layer 170. The encapsulation layer 170 may be disposed on a side of the insulating stack structure 160 away from the substrate 110. The encapsulation layer 170 may also be disposed on a side of the plurality of light-emitting devices E away from the substrate 110, for example, the encapsulation layer 170 may be disposed on a side of the second electrode layer 132 away from the substrate 110. The encapsulation layer 170 may cover the plurality of light-emitting devices E to isolate the light-emitting devices E from external water vapor and oxygen, thereby reducing damage to the light-emitting devices E by external water vapor and oxygen.

[0100] In some embodiments, the encapsulation layer 170 may have a stacked structure. Exemplarily, the encapsulation layer 170 may include an organic encapsulation layer 173. The encapsulation layer 170 may also include a first inorganic encapsulation layer 171 and a second inorganic encapsulation layer 172. The organic encapsulation layer 173 may be disposed between the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172.

[0101] The material of the organic encapsulation layer 173 may include an organic material. The organic encapsulation layer 173 may be configured as a planarization layer, which may make the surface of the display panel 10 away from the substrate 110 relatively flat. The organic encapsulation layer 173 may also be configured to relieve stress of the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172.

[0102] The first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172 may be configured to separate the light-emitting device E from external water vapor and oxygen, which may reduce the damage of external water vapor and oxygen to the light-emitting device E. In addition, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172 may enclose the organic encapsulation layer 173, for example, the orthographic projection of the organic encapsulation layer 173 on the first inorganic encapsulation layer 171 may be located inside the first inorganic encapsulation layer 171, and / or, the orthographic projection of the organic encapsulation layer 173 on the second inorganic encapsulation layer 172 may be located inside the second inorganic encapsulation layer 172. In this way, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 172 may be configured to separate the organic encapsulation layer 173 from external water vapor and oxygen, which may reduce the damage of external water vapor and oxygen to the organic encapsulation layer 173, and may improve the structural stability of the display panel.

[0103] See also Figure 2 and Figure 4 A surface 160 ′ of the insulating stack structure 160 away from the substrate 110 has a plurality of first isolation trenches S1 .

[0104] At a first isolation trench S1 (e.g., each first isolation trench S1), the thickness of the insulating stack structure 160 (e.g., the dimension of the insulating stack structure along the Z-axis direction, where the Z-axis direction is perpendicular to the X-axis direction and perpendicular to the Y-axis direction) is smaller than the thickness at other positions of the insulating stack structure 160. Exemplarily, a portion of one or more insulating dielectric layers in the insulating stack structure 160 may be removed to form the first isolation trench S1 on a surface 160' of the insulating stack structure 160 away from the substrate 110.

[0105] Continue to see Figure 4 , a portion of the encapsulation layer 170 may be located in a plurality of (e.g., all) first isolation grooves S1. Exemplarily, the material of the organic encapsulation layer 173 includes an organic material, so the organic encapsulation layer 173 may be a film layer having a relatively flat surface and uneven thickness. Based on this, the encapsulation layer 170 including the organic encapsulation layer 173 may fill a portion or all of a first isolation groove S1 (e.g., each first isolation groove S1).

[0106] Based on the above, since the surface 160' of the insulating stack structure 160 away from the substrate 110 has a plurality of first isolation grooves S1, the thickness of the insulating stack structure 160 at the first isolation grooves S1 is smaller than the thickness at other positions of the insulating stack structure 160. Therefore, the light transmittance of the display panel 10 at the first isolation grooves S1 can be higher, so that the transparency of the display panel can be improved. In addition, a first isolation groove S1 (for example, each first isolation groove S1) can be filled with an encapsulation layer 170. Compared with the insulating stack structure 160, the transparency of the encapsulation layer 170 can be better. Therefore, the light transmittance of the first isolation groove S1 filled with the encapsulation layer 170 can be higher, so that the display panel 10 provided with the first isolation groove S1 can have a higher transparency.

[0107] Figure 5 for Figure 2 A partial enlarged view of area Q1 in the display panel. Figure 6 is a top view of a display panel according to some embodiments. Figure 7 for Figure 6 A partial enlarged view of area Q2 in the display panel. Figure 8 is a top view of a display panel according to some embodiments, Fig. 9 for Figure 8 A partial enlarged view of area Q3 in the display panel. Fig.10 is a top view of a display panel according to some embodiments, Fig.11 for Fig.10 A partial enlarged view of area Q4 in the display panel. It should be noted that compared with Figure 2 The display panel in Figure 6 In the display panel of the embodiment, except for the shape of the first isolation groove, the other structures can be the same. Figure 8 The display panel in Fig.10 In the display panel, except for the shape of the first isolation groove, the rest of the structures can be the same.

[0108] See also Figure 2 , Figure 5~Figure 11 Among the multiple first isolation grooves S1 of the display panel 10, at least one (for example, one; for example, multiple) first isolation grooves S1 are arranged along the circumference of a sub-display area K. It can also be said that one or more first isolation grooves S1 are arranged around a sub-display area K (for example, each sub-display area K) (including both sides along the X-axis direction and both sides along the Y-axis direction).

[0109] It should be noted that, in this article, an isolation trench (such as the first isolation trench or the second isolation trench) may be a trench having two side walls disposed opposite to each other and extending in a certain direction. It can also be said that, for an isolation trench, along a direction perpendicular to the extending direction of the isolation trench, the isolation trench has two side walls disposed opposite to each other.

[0110] Based on the above, see Figure 2 , Figure 5 , Figure 8 and Fig. 9 In some embodiments, a plurality of first isolation grooves S1 are disposed around a sub-display area K (for example, each sub-display area K). Exemplarily, four first isolation grooves S1 are disposed around a sub-display area K, wherein each first isolation groove S1 may be a long strip groove extending along the X-axis direction or the Y-axis direction, and is disposed on one side of the sub-display area K (for example, one side along the X-axis direction or one side along the Y-axis direction). In some possible implementations, see Figure 2 and Figure 5 For a sub-display area K, a plurality of first isolation grooves S1 around it may be isolated from each other. In other possible implementations, see Figure 8 and Fig. 9 For a sub-display area K, a plurality of first isolation grooves S1 around it may be interconnected.

[0111] See also Figure 6 , Figure 7 , Fig.10 and Fig.11 In some other embodiments, a first isolation groove S1 is disposed around a sub display area K (eg, each sub display area K), and the first isolation groove S1 surrounds the sub display area K.

[0112] Continue to see Figure 2 , Figure 5~Figure 11 Since at least one (for example, one; for example, multiple) first isolation grooves S1 are arranged along the circumference of the sub-display area K, that is, one or more first isolation grooves S1 can be arranged around a sub-display area K, the light transmittance of the display panel 10 can be high around the sub-display area K, so that the display panel 10 can have high transparency. Further, in the display panel 10, one or more first isolation grooves S1 can be arranged around each sub-display area K, so that the light transmittance of the display panel 10 can be further improved, and then the transparency of the display panel 10 can be improved.

[0113] See also Figure 4 In some embodiments, for an insulating dielectric layer in the insulating stack structure 160 , the insulating dielectric layer may have a plurality of through-grooves ST. It should be noted that, in this context, a film layer having a through-groove may mean that the through-groove penetrates the film layer in the thickness direction of the display panel 10 .

[0114] A through-slot ST can be used to form a first isolation slot S1. Exemplarily, when another insulating dielectric layer is provided on the side of the insulating dielectric layer with the through-slot ST away from the substrate 110, the sidewall of the through-slot ST can be covered by the other insulating dielectric layer, and the first isolation slot S1 can be formed on the surface 160' of the insulating stack structure 160 away from the substrate 110. Exemplarily again, when there is no other insulating dielectric layer on the side of the insulating dielectric layer with the through-slot ST away from the substrate 110, the through-slot ST can be at least a portion (for example, a portion; for example, the whole) of the first isolation slot S1, and it can also be said that the through-slot ST forms the first isolation slot ST.

[0115] Continue to see Figure 4 Compared with the insulating dielectric layer having a groove that does not penetrate the insulating dielectric layer, when the insulating dielectric layer has one or more through grooves ST, since the through grooves ST penetrate the insulating dielectric layer, the light transmittance of the insulating dielectric layer at the through grooves ST is higher. Based on this, the insulating dielectric layer having multiple through grooves ST can be called a transmittance enhancing dielectric layer. Based on the above, it can also be said that a transmittance enhancing dielectric layer (for example, each transmittance enhancing dielectric layer) has multiple through grooves ST, and a through groove ST (for example, each through groove ST) penetrates the transmittance enhancing dielectric layer along the thickness direction of the display panel 10 (for example, parallel to the Z-axis direction).

[0116] See also Figure 4 Based on the above description, in some embodiments, among the multiple (e.g., all) insulating dielectric layers of the insulating stack structure 160, at least one (e.g., one; or, for example, multiple) insulating dielectric layer is a transmittance enhancing dielectric layer. In this way, the light transmittance of the display panel 10 at the first isolation groove S1 can be further improved, and thus the transparency of the display panel 10 can be further improved.

[0117] Continue to see Figure 4 In some embodiments, among the multiple (e.g., all) insulating dielectric layers of the insulating stack structure 160, an insulating dielectric layer closest to the encapsulation layer 170 is a transmittance enhancing dielectric layer. Exemplarily, referring to the above description, among the multiple (e.g., all) insulating dielectric layers of the insulating stack structure 160, an insulating dielectric layer closest to the encapsulation layer 170 may be a pixel defining layer 163, and the pixel defining layer 163 may be a transmittance enhancing dielectric layer.

[0118] When an insulating dielectric layer located in the middle of the insulating stack structure 160 is a transmittance enhancing dielectric layer, another insulating dielectric layer is provided on the side of the transmittance enhancing dielectric layer away from the substrate 110, and the other insulating dielectric layer may be an organic insulating layer. The material of the organic insulating layer may include an organic material, so similar to the organic encapsulation layer, the organic insulating layer may also be a film layer with a relatively flat surface and uneven thickness. Based on this, when an organic insulating layer is provided on the side of the transmittance enhancing dielectric layer away from the substrate 110, the organic insulating layer may fill part or all of the through groove ST of the transmittance enhancing dielectric layer, so that the depth of the first isolation groove S1 formed by the through groove ST is small, or it can be said that the thickness of the display panel 10 at the first isolation groove S1 may be large. In contrast, since the insulating dielectric layer closest to the encapsulation layer 170 is a transmittance enhancing dielectric layer, there may be no other insulating dielectric layer in the first isolation groove S1 formed by the through groove ST of the transmittance enhancing dielectric layer, and only part of the encapsulation layer 170 is provided. In this way, the thickness of the insulating stack structure 160 at the first isolation groove S1 can be relatively small, so that the light transmittance of the display panel 10 at the first isolation groove S1 can be improved, thereby improving the transparency of the display panel 10 .

[0119] Continue to see Figure 4 In other embodiments, among multiple (for example, all) insulating dielectric layers of the insulating stack structure 160, each of the N consecutive insulating dielectric layers close to the encapsulation layer 170 is a transmittance enhancing dielectric layer, where N is greater than or equal to 2 and less than or equal to the number of insulating dielectric layers in the insulating stack structure 160.

[0120] Furthermore, among the N transmittance enhancing medium layers, two adjacent transmittance enhancing medium layers are a first transmittance enhancing medium layer and a second transmittance enhancing medium layer, the second transmittance enhancing medium layer is located on a side of the first transmittance enhancing medium layer away from the substrate, and a through groove (for example, each through groove) on the first transmittance enhancing medium layer is connected to a through groove on the second transmittance enhancing medium layer.

[0121] Specifically, see Figure 4, the second organic insulating layer 162b is used as the first transmittance enhancing medium layer, and the pixel defining layer 163 is used as the second transmittance enhancing medium layer. It can be understood that the other two adjacent insulating medium layers can also be the first transmittance enhancing medium layer and the second transmittance enhancing medium layer. Since a through groove ST (for example, each through groove ST) on the second organic insulating layer 162b is connected with a through groove ST on the pixel defining layer 163, the depth of the first isolation groove S1 formed by the through groove ST on the second organic insulating layer 162b and the through groove ST on the pixel defining layer 163 can be larger, that is, the thickness of the display panel 10 at the first isolation groove S1 can be smaller, which can improve the light transmittance of the display panel 10 at the first isolation groove S1, thereby improving the transparency of the display panel. In addition, a portion of the second organic insulating layer 162b and a portion of the pixel defining layer 163 can be removed through an etching process (i.e., a single exposure and development process), so that the through groove ST on the second organic insulating layer 162b and the through groove ST on the pixel defining layer 163 can be connected. In this way, compared with separately removing a portion of the second organic insulating layer 162b and a portion of the pixel defining layer 163, the manufacturing process of the display panel 10 is relatively simple, and the yield of the display panel 10 can be improved.

[0122] Continue to see Figure 4 In some possible implementations, the continuous N insulating dielectric layers close to the encapsulation layer 170 may be continuous N layers among the pixel defining layer 163, the second organic insulating layer 162b, and the first organic insulating layer 162a. Since the material of each of the first organic insulating layer 162a, the second organic insulating layer 162b, and the pixel defining layer 163 may include PI (polyimide), PI easily causes the problem of yellowing of the film layer. Based on this, since the continuous N insulating dielectric layers among the first organic insulating layer 162a, the second organic insulating layer 162b, and the pixel defining layer 163 are transmittance enhancing dielectric layers, that is, the continuous N insulating dielectric layers among the first organic insulating layer 162a, the second organic insulating layer 162b, and the pixel defining layer 163 may have one or more through grooves, therefore, the problem of yellowing of the first organic insulating layer 162a, the second organic insulating layer 162b, and the pixel defining layer 163 may be improved, and the transparency of the display panel 10 may be improved.

[0123] Continue to see Figure 4In some embodiments, the orthographic projection of a through groove ST (for example, each through groove ST) on the first transmittance enhancing medium layer on the substrate 110 is located within the orthographic projection of a through groove ST on the second transmittance enhancing medium layer on the substrate 110. Still taking the second organic insulating layer 162b as the first transmittance enhancing medium layer and the pixel defining layer 163 as the second transmittance enhancing medium layer as an example, the orthographic projection of a through groove ST on the second organic insulating layer 162b on the substrate 110 may be located within the orthographic projection of a through groove ST on the pixel defining layer 163 on the substrate 110.

[0124] Since the orthographic projection of a through groove ST (for example, each through groove ST) on the first transmittance enhancing medium layer on the substrate 110 is located within the orthographic projection of a through groove ST on the second transmittance enhancing medium layer on the substrate 110, the through grooves ST of N consecutive (for example, all) insulating medium layers can be intersected and form a first isolation groove S1 with an inverted trapezoidal cross section. In other words, for a side wall of the first isolation groove S1, along the direction from the substrate 110 to the light emitting device E (for example, the positive direction of the Z axis), the side wall of the first isolation groove S1 can gradually tilt in a direction away from the center of the first isolation groove S1. In this way, the process of forming the first isolation groove S1 on the insulating stack structure 160 can be relatively simple.

[0125] Continue to see Figure 4 , and referring to the above description, in some embodiments, the plurality of (e.g., all) insulating dielectric layers in the insulating stack structure 160 include a plurality of inorganic insulating layers 161, for example, a first inorganic insulating layer 161a, a second inorganic insulating layer 161b, a third inorganic insulating layer 161c, and a fourth inorganic insulating layer 161d, and each inorganic insulating layer 161 is an insulating dielectric layer. The plurality of (e.g., all) insulating dielectric layers in the insulating stack structure 160 also include at least one (e.g., one; for example, multiple) organic insulating layer 162, for example, a first organic insulating layer 162a and a second organic insulating layer 162b. At least one (e.g., all) organic insulating layer 162 is located on a side of the plurality of (e.g., all) inorganic insulating layers 161 away from the substrate 110. Each inorganic insulating layer 162 is an insulating dielectric layer. Furthermore, multiple (eg, all) insulating dielectric layers in the insulating stack structure 160 further include a pixel defining layer 163 . The pixel defining layer 163 is located on a side of at least one (eg, all) organic insulating layer 162 away from the substrate 110 . The pixel defining layer 163 is an insulating dielectric layer.

[0126] Furthermore, at least one (for example, one; for example, multiple) insulating dielectric layer among the multiple (for example, all) inorganic insulating layers 161 , at least one (for example, all) organic insulating layers 162 and the pixel defining layer 163 is a transmittance enhancing dielectric layer.

[0127] Exemplarily, each insulating dielectric layer in the insulating stack structure 160 is a transmittance enhancing dielectric layer, and further, a through groove in each transmittance enhancing dielectric layer can be connected with the through grooves of other transmittance enhancing dielectric layers. In this way, the first isolation groove S1 formed by the through grooves of all transmittance enhancing dielectric layers can penetrate the insulating stack structure 160, and the thickness of the insulating stack structure 160 at the first isolation groove S1 can be relatively small, which can further improve the light transmittance of the display panel 10 at the first isolation groove S1, thereby further improving the transparency of the display panel.

[0128] In addition, see Figure 2 and Figure 4 Since at least one (for example, one; for example, multiple) first isolation grooves S1 are arranged along the circumference of the sub-display area K, that is, one or more first isolation grooves S1 can be arranged around a sub-display area K. Therefore, when the encapsulation layer 170 is manufactured, the encapsulation layer 170 can be wrapped along the sub-display area K. For example, the encapsulation layer 170 can cover two side surfaces of the light-emitting device E that are relatively arranged along the X-axis direction and two side surfaces that are relatively arranged along the Y-axis direction. In this way, the encapsulation effect can be improved and the life of the display panel 10 can be further improved.

[0129] In addition, referring to the above description, in some embodiments, the encapsulation layer 170 includes an organic encapsulation layer 173, and a portion of the organic encapsulation layer 173 may be located in one or more first isolation grooves S1. In this way, in the process of manufacturing the organic encapsulation layer 173, a portion of the organic encapsulation layer material may flow into the one or more first isolation grooves S1, so that less organic encapsulation layer material may extend to the peripheral area SA, and the size of the frame of the display panel 10 may be reduced.

[0130] Fig.12 for Figure 8 A cross-sectional view of the display panel along the section line BB'. Figure 8~Figure 12 In some embodiments, the insulating stack structure 160 further includes a plurality of first isolation walls W1. At least one (e.g., one; for example, multiple) first isolation walls W1 are disposed along the circumference of a sub-display area K. It can also be said that at least one (e.g., one; for example, multiple) first isolation walls W1 are disposed around a sub-display area K (e.g., each sub-display area K) (including both sides along the X-axis direction and both sides along the Y-axis direction).

[0131] Further, for a sub-display area K (for example, each sub-display area K), at least one (for example, all) first isolation walls W1 arranged in the circumference of the sub-display area K are located on a side of at least one (for example, all) first isolation grooves S1 arranged in the circumference of the sub-display area K away from the sub-display area K. In addition, at least one (for example, all) first isolation walls W1 arranged in the circumference of the sub-display area K are used to form a side wall S1' of at least one (for example, all) first isolation grooves S1 arranged in the circumference of the sub-display area K.

[0132] See also Fig. 9 In some embodiments, a plurality of first isolation walls W1 are disposed around a sub-display area K (for example, each sub-display area K). Exemplarily, four first isolation walls W1 are disposed around a sub-display area K, wherein each first isolation wall W1 may be a long strip wall extending along the X-axis direction or the Y-axis direction, and is disposed on one side of the sub-display area K (for example, one side along the X-axis direction or one side along the Y-axis direction).

[0133] See also Fig.10 and Fig.11 In some other embodiments, a first isolation wall W1 is disposed around a sub display area K (eg, each sub display area K), and the first isolation wall W1 surrounds the sub display area K.

[0134] Based on the above, since at least one first isolation wall W1 is arranged along the circumference of a sub-display area K, that is, for a sub-display area K (for example, each sub-display area K), at least one first isolation wall W1 is arranged around the sub-display area K, and the at least one first isolation wall W1 around the sub-display area K can be used to form the sidewall of at least one first isolation groove S1 around the sub-display area K. Based on this, by removing a portion of one or more insulating dielectric layers in the insulating stack structure 160, multiple first isolation grooves S1 and multiple first isolation walls W1 can be formed simultaneously. In this way, the manufacturing process of the display panel 10 can be relatively simple.

[0135] In addition, see Figure 8 and Fig.10Since at least one first isolation wall W1 is arranged around a sub-display area K (for example, each sub-display area K), two first isolation walls W1 may be arranged between two adjacent sub-display areas K. The two first isolation walls W1 may be formed by removing a portion of one or more insulating dielectric layers in the insulating stack structure 160. Based on the above, while forming the two first isolation walls W1, a groove may also be formed between the two first isolation walls W1, and the sidewalls of the groove may be formed by the two first isolation walls W1. In this way, the insulating stack structure 160 may have more grooves on the surface away from the substrate 110, which may further improve the transparency of the display panel. In addition, a portion of the organic encapsulation layer 173 may also be located in the above-mentioned groove, that is, in the process of manufacturing the organic encapsulation layer, the organic encapsulation layer material may also flow into the groove, which may further improve the encapsulation effect and further reduce the frame size of the display panel 10.

[0136] See also Fig.12 In some embodiments, the first isolation wall W1 includes a first isolation pattern W1a and a second isolation pattern W1b which are sequentially arranged in a direction away from the substrate 110 (for example, the positive direction of the Z axis). Exemplarily, the second isolation pattern W1b is located on a side of the first isolation pattern W1a away from the substrate 110, and the first isolation pattern W1a and the second isolation pattern W1b are in contact.

[0137] It should be noted that, in this context, the orthographic projection of a pattern (eg, the first isolation pattern W1 a or the second isolation pattern W1 b ) on the substrate 110 may have a closed outer contour.

[0138] In some possible implementations, the first isolation pattern W1a may be included in an insulating dielectric layer (hereinafter referred to as the first insulating dielectric layer for distinction), that is, the material of the first isolation pattern W1a is the same as the material of the first insulating dielectric layer, and the thickness of the first isolation pattern W1a (for example, the dimension along the Z-axis direction) is substantially the same as the thickness of the first insulating dielectric layer (for example, the dimension along the Z-axis direction). Similarly, the second isolation pattern W1b may be included in another insulating dielectric layer (hereinafter referred to as the second insulating dielectric layer for distinction), that is, the material of the second isolation pattern W1b is the same as the material of the second insulating dielectric layer, and the thickness of the second isolation pattern W1b (for example, the dimension along the Z-axis direction) is substantially the same as the thickness of the second insulating dielectric layer (for example, the dimension along the Z-axis direction). The second insulating dielectric layer may be located on a side of the first insulating dielectric layer away from the substrate 110, and the second insulating dielectric layer may be in contact with the first insulating dielectric layer.

[0139] Furthermore, the orthographic projection of the second isolation pattern W1b on the substrate 110 is located within the orthographic projection of the first isolation pattern W1a on the substrate 110. In this way, the first isolation wall W1 can have a relatively stable structure. In addition, the manufacturing process of the first isolation wall W1 can be relatively simple. For example, a portion of the first insulating dielectric layer and the second insulating dielectric layer can be removed by an etching process (i.e., a single exposure and development process) to form the first isolation pattern W1a and the second isolation pattern W1b, so that the orthographic projection of the second isolation pattern W1b on the substrate 110 is located within the orthographic projection of the first isolation pattern W1a on the substrate 110. In this way, the manufacturing process of the first isolation wall W1 can be relatively simple.

[0140] Fig.13 for Figure 2 A partial enlarged view of area Q5 in the display panel. Fig.14 for Fig.13 A cross-sectional view of the display panel along section line CC'. Fig.15 for Figure 6 A partial enlarged view of area Q6 in the display panel.

[0141] See also Figure 13~Figure 15 In some embodiments, the insulating stack structure 160 includes a plurality of second isolation walls W2. Each second isolation wall W2 is located between two adjacent sub-display areas K. Exemplarily, a portion of the insulating stack structure 160 located between two adjacent sub-display areas K may form a second isolation wall W2. For example, for two adjacent sub-display areas K, a portion of the insulating stack structure 160 located between the two sub-display areas K may form a second isolation wall W2, and, along a direction perpendicular to the arrangement direction of the two sub-display areas K, a size of the second isolation wall W2 is less than or equal to a size of each of the two sub-display areas K.

[0142] Further, multiple (e.g., all) second isolation walls W2 in the insulating stack structure 160 extend to form an isolation network IN. Exemplarily, each of the multiple (e.g., all) second isolation walls W2 in the insulating stack structure 160 may extend along the X-axis direction or the Y-axis direction to form an isolation network IN. The isolation network IN may separate all first isolation trenches S1 surrounding different sub-display areas K. Exemplarily, for a sub-display area K (e.g., each sub-display area K), the isolation network IN may form a side wall of each first isolation trench S1 in at least one (e.g., all) first isolation trenches S1 surrounding the sub-display area K.

[0143] Continue to see Figure 13~Figure 15 Since the display panel 10 includes the isolation network IN, the structural stability of the display panel 10 can be better, so that the display panel 10 can have a better ability to resist external forces.

[0144] Fig.16 FIG. 1 is a top view of a display panel according to some embodiments. It should be noted that for the sake of simplicity of the drawings, Fig.16 Only a plurality of sub-display areas and an electrode layer are shown, and other structures are omitted, for example, a plurality of first isolation grooves are omitted.

[0145] See also Figure 4 and Fig.16 , and referring to the above description, the display panel 10 may include an electrode layer 132, which may be the second electrode layer described above. In some embodiments, the second electrode layer 132 may include a plurality of electrode patterns EP spaced apart from each other. An electrode pattern EP (e.g., each electrode pattern EP) covers at least a portion (e.g., a portion; or, for example, the entirety) of a sub-display region K.

[0146] It should be noted that, in this article, the orthographic projection of a pattern (such as an electrode pattern or a light-emitting function pattern) on the substrate may have a closed outer contour.

[0147] In some possible implementations, an electrode pattern EP (for example, each electrode pattern EP) covers a portion of a sub-display area K. Exemplarily, an electrode pattern EP may cover a portion of sub-pixel areas in a sub-display area K. For example, an electrode pattern EP may cover a sub-pixel area in a sub-display area K. For another example, an electrode pattern EP may cover a portion of sub-pixel areas in a sub-display area K, and the number of these sub-pixel areas is half the number of all sub-pixel areas in the sub-display area K. In other possible implementations, an electrode pattern EP (for example, each electrode pattern EP) may cover all of a sub-display area K, or in other words, an electrode pattern EP (for example, each electrode pattern EP) may cover all of the sub-pixel areas in a sub-display area K.

[0148] Based on the above, for a sub-display area K, the electrode pattern EP (e.g., each electrode pattern EP) covering the sub-display area K may include a second electrode of at least one (e.g., one; or, for example, all) light-emitting devices located in the sub-display area K. It can also be said that in a sub-display area K, the second electrodes of multiple (e.g., all) light-emitting devices may be interconnected to form an electrode pattern EP.

[0149] In the related art, the second electrode layer in the display panel can be a continuous film layer covering the display area of ​​the display panel. The continuous film layer may reduce the light transmittance of the display panel and affect the transparency of the display panel. Fig.16 In the display panel 10 , since the plurality of electrode patterns EP in the second electrode layer 132 are arranged at intervals from each other, the light transmittance of the display panel 10 can be higher, and the transparency of the display panel 10 can be improved.

[0150] See also Figure 4 and Fig.16 In some embodiments, the display panel 10 further includes a plurality of signal lines 180. The plurality of (for example, all) signal lines 180 are disposed in the display area AA and are disposed on a side of the second electrode layer 132 close to the substrate 110. Exemplarily, the plurality of (for example, all) signal lines 180 may be included in a conductor layer 150. In some possible implementations, a signal line 180 (for example, each signal line 180) may extend along the X-axis direction. In this case, the signal line 180 may be included in the third conductor layer 153 or the fourth conductor layer 154, and the signal line 180 may be parallel or substantially parallel to other signal lines in the third conductor layer 153 or the fourth conductor layer 154.

[0151] Further, see Fig.16 , each electrode pattern EP is coupled to a signal line 180. Exemplarily, a plurality of electrode patterns EP corresponding to a row of sub-display areas K in the display panel 10 may be coupled to a signal line 180. In this way, an electrical signal may be written to the second electrodes of a plurality of (e.g., all) light-emitting devices corresponding to a row of sub-display areas K through a signal line 180.

[0152] Fig.17 FIG. 1 is a structural diagram of an electrode pattern and a signal line, showing the coupling method of the electrode pattern and the signal line. Fig.17 The display panel may further include a plurality of connection patterns CP, and a plurality of (for example, all) connection patterns CP may be included in the first electrode layer 131. In other words, a plurality of (for example, all) connection patterns CP are disposed in the same layer as the first electrodes of the plurality of light-emitting devices. An electrode pattern EP (for example, each electrode pattern EP) may contact the connection pattern CP, and the connection pattern CP may contact the signal line 180, so that the electrode pattern EP may be coupled to the signal line 180.

[0153] Continue to see Fig.16 In some possible implementations, multiple (e.g., all) signal lines 180 in the display panel 10 may be coupled to each other. For example, the display panel 10 further includes a connection line 190 disposed in the peripheral area SA. The connection line 190 may be coupled to multiple (e.g., all) signal lines 180 in the display panel 10, so that multiple (e.g., all) signal lines 180 in the display panel 10 may be coupled to each other. An electrical signal may be transmitted to the multiple signal lines 180 through the connection line 190, so that the second electrodes of multiple (e.g., all) light-emitting devices in the display panel 10 may be written with the same electrical signal.

[0154] Continue to see Fig.16In some possible implementations, the data driving circuit 210 may be disposed on one side of the display panel 10, for example, on one side of the display panel 10 along the X-axis direction. The connecting line 190 may be located in the peripheral area SA of the display panel 10 and on one side of the display area AA close to the data driving circuit 210.

[0155] In addition, in the related art, the second electrodes of all the light-emitting devices in the display panel can be interconnected to form a continuous film layer. Furthermore, in order to write electrical signals to the continuous film layer, connecting wires can be set around the display area of ​​the display panel (i.e., the peripheral area), and the continuous film layer can contact the connecting wires in the peripheral area, thereby realizing writing electrical signals to the continuous film layer through the connecting wires. In order to ensure the stability of the electrical connection between the continuous film layer and the connecting wires, the width of the connecting wires coupled to the continuous film layer may be relatively large, which will result in a larger frame size of the display panel. In contrast, see Fig.16 In the display panel 10, since the display panel 10 includes a plurality of signal lines 180, a plurality of electrode patterns EP may be coupled to the plurality of signal lines 180 in the display area AA. Thus, a connection line with a larger width may not be provided in the peripheral area SA of the display panel 10, and the border size of the display panel 10 may be reduced.

[0156] Fig.18A is a top view of a display panel according to some embodiments. Fig.18B for Fig.18A A cross-sectional view of the display panel along the section line DD' in FIG. It should be noted that for the sake of simplicity of the drawings, Fig.18A Only a plurality of sub-display areas and a light-emitting functional layer are shown, while other structures are omitted, such as other light-emitting functional layers and a plurality of first isolation grooves.

[0157] See also Fig.18A and Fig.18B , and referring to the above description, the display panel 10 may include one or more light-emitting functional layers 134. The one or more light-emitting functional layers 134 may be located on a side of the insulating stacked structure 160 away from the substrate 110. In some embodiments, a light-emitting functional layer 134 (e.g., each light-emitting functional layer 134) includes a plurality of light-emitting functional patterns FP spaced apart from each other, and a light-emitting functional pattern FP (e.g., each light-emitting functional pattern FP) covers at least a portion (e.g., a portion; for example, the entirety) of a sub-display area K.

[0158] The relationship between a light-emitting functional pattern FP and a sub-display area K can refer to the above description of the relationship between an electrode pattern and a sub-display area, which will not be repeated here. Further, referring to the above description, the pixel defining layer 163 can have a plurality of openings H, and an opening H can be directly opposite to a sub-pixel area. Based on this, it can also be said that a light-emitting functional pattern FP can cover one or more openings H.

[0159] Similar to the second electrode layer, since the plurality of light emitting function patterns FP in the light emitting function layer 134 are arranged at intervals from each other, the light transmittance of the display panel 10 can be higher, and the transparency of the display panel 10 can be improved.

[0160] Fig.19 is a top view of a display panel according to some embodiments, Fig. 20 for Fig.19 A cross-sectional view of the display panel along the section line EE' in FIG. It should be noted that for the sake of simplicity of the drawings, Fig.19 Only one second isolation trench is shown, Fig. 20 One or more insulating dielectric layers in the insulating stack structure are omitted.

[0161] See also Fig.19 and Fig. 20 In some embodiments, in the display panel 10, the insulating stack structure 160 further has at least one (e.g., one; for example, multiple) second isolation grooves S2 on the surface away from the substrate 110. At least one (e.g., all) second isolation grooves S2 are arranged along the circumference of the display area AA. It can also be said that at least one second isolation groove S2 is arranged around the display area AA (e.g., including both sides along the X-axis direction and both sides along the Y-axis direction). In some possible implementations, a second isolation groove S2 (e.g., each second isolation groove S2) surrounds the display area AA.

[0162] Further, the encapsulation layer 170 may extend to the second isolation trench S2 , and a portion of the encapsulation layer 170 is located in at least one (eg, one; or, for example, a plurality of) second isolation trenches S2 .

[0163] Based on the above, in the process of manufacturing the organic encapsulation layer 173 , the organic encapsulation layer material can flow into the second isolation groove S2 , so that the encapsulation effect can be improved and the frame size of the display panel 10 can be further reduced.

[0164] Continue to see Fig.19 and Fig. 20In some embodiments, the display panel 10 further includes a barrier wall BW. The barrier wall BW may be disposed on a side of the insulating stack structure 160 away from the substrate 110, and disposed on a side of at least one (e.g., all) second isolation trenches S2 away from the display area AA. The barrier wall BW may surround the display area AA. The material of the barrier wall BW may include polystyrene (PS).

[0165] Furthermore, the encapsulation layer 170 may extend to the barrier wall BW, and the encapsulation layer 170 may cover the barrier wall BW.

[0166] Based on the above, the barrier wall BW can be configured to block the organic encapsulation layer 173 within the area surrounded by the barrier wall BW, which can reduce the organic encapsulation layer 173 from further extending in the direction away from the display area AA toward the barrier wall BW. In this way, the encapsulation effect can be improved and the frame size of the display panel 10 can be further reduced.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: A display area is provided, wherein the display area includes a plurality of sub-display areas distributed at intervals, and a sub-display area includes at least two sub-pixel areas; The display panel comprises: substrate; a buffer layer, disposed on the substrate and in contact with the substrate; An insulating stack structure, comprising a plurality of insulating dielectric layers stacked on the substrate, a plurality of first isolation grooves being provided on a surface of the insulating stack structure away from the substrate, at least one of the first isolation grooves being provided along the circumference of the sub-display area; one first isolation groove being provided around the sub-display area; or a plurality of first isolation grooves being provided around the sub-display area, the first isolation grooves extending along the boundaries of the sub-display area, and a plurality of first isolation grooves around the same sub-display area being separated from each other; The encapsulation layer is arranged on a side of the insulating stack structure away from the substrate, and a portion of the encapsulation layer is located in the plurality of first isolation grooves; the transparency of the encapsulation layer is greater than the transparency of the insulating stack structure.

2. The display panel according to claim 1, characterized in that: At least one of the plurality of insulating dielectric layers is a transmittance enhancing dielectric layer; A transmittance enhancing medium layer has a plurality of through grooves, and a through groove penetrates the transmittance enhancing medium layer along the thickness direction of the display panel, and the through groove is used to form a first isolation groove.

3. The display panel according to claim 2, characterized in that: Among the multiple insulating dielectric layers, an insulating dielectric layer closest to the encapsulation layer is the transmittance enhancing dielectric layer; Alternatively, among the plurality of insulating dielectric layers, each of the N consecutive insulating dielectric layers close to the encapsulation layer is the transmittance enhancing dielectric layer; The two adjacent transmittance enhancing medium layers are a first transmittance enhancing medium layer and a second transmittance enhancing medium layer, and the second transmittance enhancing medium layer is located on the side of the first transmittance enhancing medium layer away from the substrate; a through groove on the first transmittance enhancing medium layer is connected with a through groove on the second transmittance enhancing medium layer; wherein N is greater than or equal to 2 and less than or equal to the number of insulating medium layers in the insulating stack structure.

4. The display panel according to claim 3, characterized in that: An orthographic projection of a through groove on the first transmittance enhancing medium layer on the substrate is located within an orthographic projection of a through groove on the second transmittance enhancing medium layer on the substrate.

5. The display panel according to any one of claims 2 to 4, characterized in that: The plurality of insulating dielectric layers include: A plurality of inorganic insulating layers, each inorganic insulating layer being an insulating dielectric layer; at least one organic insulating layer, the at least one organic insulating layer being located on a side of the plurality of inorganic insulating layers away from the substrate, each organic insulating layer being an insulating dielectric layer; A pixel defining layer, located on a side of the at least one organic insulating layer away from the substrate, the pixel defining layer being an insulating dielectric layer; The plurality of inorganic insulating layers, the at least one organic insulating layer and at least one insulating medium layer in the pixel defining layer are transmittance enhancing medium layers.

6. The display panel according to claim 1, characterized in that: The insulating stack structure further includes a plurality of first isolation walls, at least one of which is arranged along the circumference of the sub-display region and is located on a side of the at least one first isolation trench away from the sub-display region and is used to form a sidewall of the at least one first isolation trench; or, The insulating stack structure further includes a plurality of second isolation walls, each of which is located between two adjacent sub-display areas. The plurality of second isolation walls extend to form an isolation net, and the isolation net separates the first isolation grooves surrounding different sub-display areas.

7. The display panel according to claim 6, characterized in that: The first isolation wall includes a first isolation pattern and a second isolation pattern sequentially arranged in a direction away from the substrate, and the orthographic projection of the second isolation pattern on the substrate is located within the orthographic projection of the first isolation pattern on the substrate.

8. The display panel according to claim 1, characterized in that: Also includes: The electrode layer is located on a side of the insulating stack structure away from the substrate, and the electrode layer includes a plurality of electrode patterns arranged at intervals from each other, and an electrode pattern covers at least a portion of a sub-display area.

9. The display panel according to claim 8, characterized in that: Also includes: A plurality of signal lines are arranged in the display area and on a side of the electrode layer close to the substrate, and each electrode pattern is coupled to a signal line.

10. The display panel according to claim 1, characterized in that: Also includes: The light-emitting functional layer is located on a side of the insulating stack structure away from the substrate, and the light-emitting functional layer includes a plurality of light-emitting functional patterns arranged at intervals from each other, and a light-emitting functional pattern covers at least a portion of a sub-display area.

11. The display panel according to claim 1, characterized in that: The encapsulation layer includes an organic encapsulation layer, and a portion of the organic encapsulation layer is located in the first isolation trench.

12. The display panel according to claim 1, characterized in that: The insulating stack structure further has at least one second isolation groove on a surface away from the substrate, and the at least one second isolation groove is arranged along the circumference of the display area; A portion of the encapsulation layer is located in the at least one second isolation trench.

13. The display panel according to claim 12, characterized in that: Also includes: A retaining wall is arranged on a side of the insulating stack structure away from the substrate and on a side of the at least one second isolation groove away from the display area, and the retaining wall surrounds the display area; The encapsulation layer covers the retaining wall.

14. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 13.

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