Display substrate and display device

Abstract

An embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes: a substrate, a driving circuit layer disposed on the substrate, a color filter layer disposed on a side of the driving circuit layer away from the substrate, and a light-emitting structure layer disposed on a side of the color filter layer away from the substrate; wherein, the driving circuit layer includes: a light-shielding layer located in a sub-pixel and a metal oxide layer disposed on a side of the light-shielding layer away from the substrate, and an overlapping area of a positive projection of the color filter layer on the substrate and a positive projection of the metal oxide layer on the substrate is greater than an overlapping area of a positive projection of the color filter layer on the substrate and a positive projection of the light-shielding layer on the substrate.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and in particular, to a display substrate and a display device. Background Art

[0002] An organic light-emitting diode (OLED) display device is an active light-emitting display device, which has the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, etc. With the continuous development of display technologies, OLED technology is increasingly applied to transparent displays. Transparent display is an important personalized display field in display technologies, which performs image display in a transparent state. The viewer can not only see the image in the display device, but also see the scene behind the display device. However, some transparent display products have the problem of sub-pixel light leakage. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the scope of protection of the claims.

[0004] In a first aspect, embodiments of the present disclosure provide a display substrate, including: a substrate, a driving circuit layer disposed on the substrate, a color filter layer disposed on a side of the driving circuit layer away from the substrate, and a light-emitting structure layer disposed on a side of the color filter layer away from the substrate; wherein, the driving circuit layer includes: a light-shielding layer in a sub-pixel and a metal oxide layer disposed on a side of the light-shielding layer away from the substrate, and an overlapping area of a positive projection of the color filter layer on the substrate and a positive projection of the metal oxide layer on the substrate is larger than an overlapping area of a positive projection of the color filter layer on the substrate and a positive projection of the light-shielding layer on the substrate.

[0005] In a second aspect, embodiments of the present disclosure provide a display device, including: the display substrate described in the above embodiments.

[0006] For the display substrate and the display device provided by the embodiments of the present disclosure, through the design of overlapping the positive projection of the color filter layer on the substrate and the positive projection of the light-shielding layer on the substrate, thus, the white light generated by the organic light-emitting layer of the sub-pixel leaks out from the edge of the color filter layer through diffuse reflection or refraction of the cathode and other film layers, and will be directed to the light-shielding layer, and thus, is blocked by the light-shielding layer. In this way, the problem of sub-pixel light leakage can be avoided, and further, the problem of color unevenness caused by light leakage can be avoided, and the display quality can be improved.

[0007] Other features and advantages of the present disclosure will be described in the following description, and, in part, will be obvious from the description, or will be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0008] Other aspects will be apparent upon reading and understanding the accompanying drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure.

[0010] Figure 1 It is a schematic structural diagram of a display substrate;

[0011] Figure 2 It is a schematic structural diagram of a display device;

[0012] Figure 3 It is a schematic diagram of a pixel structure in a display substrate;

[0013] Figure 4 It is an equivalent circuit schematic diagram of a pixel driving circuit;

[0014] Figure 5 It is a schematic plan view of a display substrate in an exemplary embodiment of the present disclosure;

[0015] Figure 6 It is Figure 5 A schematic cross-sectional structure diagram of the shown display substrate along the A-A' direction;

[0016] Figure 7 It is Figure 5 An equivalent circuit schematic diagram of the pixel driving circuit in the four sub-pixels shown;

[0017] Figure 8 It is a schematic structural diagram of a first conductive layer in an exemplary embodiment of the present disclosure;

[0018] Figure 9A It is a schematic structural diagram after forming a second conductive layer in an exemplary embodiment of the present disclosure;

[0019] Figure 9B It is Figure 9A A schematic structural diagram of the second conductive layer in

[0020] Figure 10A It is a schematic structural diagram after forming a metal oxide layer in an exemplary embodiment of the present disclosure;

[0021] Figure 10B It is Figure 10A A schematic structural diagram of the metal oxide layer in

[0022] Figure 11ASchematic diagram of the structure after forming the third conductive layer in an exemplary embodiment of the present disclosure;

[0023] Figure 11B is Figure 11A Schematic diagram of the structure of the third conductive layer in;

[0024] Figure 12 Schematic diagram of the structure after forming the third insulating layer in an exemplary embodiment of the present disclosure;

[0025] Figure 13A Schematic diagram of the structure after forming the fourth conductive layer in an exemplary embodiment of the present disclosure;

[0026] Figure 13B is Figure 13A Schematic diagram of the structure of the fourth conductive layer in;

[0027] Figure 14 Schematic diagram of the structure after forming the fourth insulating layer in an exemplary embodiment of the present disclosure;

[0028] Figure 15A Schematic diagram of the structure after forming the red color filter unit in an exemplary embodiment of the present disclosure;

[0029] Figure 15B is Figure 15A Schematic diagram of the structure of the red color filter unit in;

[0030] Figure 15C Schematic diagram of the structure after forming the green color filter unit in an exemplary embodiment of the present disclosure;

[0031] Figure 15D is Figure 15C Schematic diagram of the structure of the green color filter unit in;

[0032] Figure 15E Schematic diagram of the structure after forming the blue color filter unit in an exemplary embodiment of the present disclosure;

[0033] Figure 15F is Figure 15E Schematic diagram of the structure of the blue color filter unit in;

[0034] Figure 16 Schematic diagram of the structure after forming the fifth insulating layer in an exemplary embodiment of the present disclosure;

[0035] Figure 17A Schematic diagram of the structure after forming the fifth conductive layer in an exemplary embodiment of the present disclosure;

[0036] Figure 17B is Figure 17A Schematic diagram of the structure of the fifth conductive layer in;

[0037] Figure 18ASchematic diagram of the structure after forming the pixel definition layer in an exemplary embodiment of the present disclosure;

[0038] Figure 18B is Figure 18A Schematic diagram of the structure of the pixel definition layer in [the figure];

[0039] Figure 19 Schematic diagram of the overlapping region between the color filter layer and the light-shielding layer in the display substrate in an exemplary embodiment of the present disclosure. Detailed implementation manners

[0040] Multiple embodiments are described herein, but the description is exemplary rather than restrictive, and there can be more embodiments and implementation solutions within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the exemplary embodiments, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0041] When describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps herein, the method or process should not be limited to the specific order of the steps. As will be understood by those of ordinary skill in the art, other step sequences are also possible. Therefore, the specific order of the steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure.

[0042] In the drawings, sometimes for clarity, the sizes of the components, the thicknesses of the layers, or the areas are exaggerated. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0043] The ordinal numbers such as "first", "second", and "third" in this specification are set to avoid confusion of the components, rather than to limit in terms of quantity.

[0044] In the exemplary embodiments of the present disclosure, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to has a specific orientation, is constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure. The positional relationships of the constituent elements are appropriately changed according to the directions describing the constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0045] In the exemplary embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0046] In the exemplary embodiments of the present disclosure, "electrically connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the connectable constituent elements. The "element having a certain electrical effect" can be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, an inductor, or a capacitor.

[0047] In the exemplary embodiments of the present disclosure, a transistor refers to an element that includes at least three terminals: a gate electrode (gate or control electrode), a drain electrode (drain electrode terminal, drain region, or drain), and a source electrode (source electrode terminal, source region, or source). The transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0048] In the exemplary embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate electrode (gate or control electrode), one of the poles is directly described as the first pole and the other as the second pole. Among them, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged with each other.

[0049] In the exemplary embodiments of the present disclosure, the transistors may all be thin film transistors (TFTs), field effect transistors (FETs), or other devices with the same characteristics. For example, the thin film transistors used in the embodiments of the present disclosure may include, but are not limited to, oxide transistors (Oxide TFTs) or low temperature poly-silicon thin film transistors (Low Temperature Poly-silicon TFTs, LTPS TFTs), etc. For example, the thin film transistors may be selected from thin film transistors with a bottom gate structure or a top gate structure, as long as they can achieve the switching function. Here, the embodiments of the present disclosure do not make any limitations in this regard.

[0050] In the exemplary embodiments of the present disclosure, "film" and "layer" may be interchanged. For example, sometimes the "conductive layer" may be changed to the "conductive film". Similarly, sometimes the "insulating film" may be changed to the "insulating layer".

[0051] In the exemplary embodiments of the present disclosure, triangles, rectangles, trapezoids, pentagons, hexagons, etc. are not strictly defined and may be approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons, or approximate hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, rounded edges, and deformations, etc.

[0052] In the exemplary embodiments of the present disclosure, "about" means not strictly defining the boundary and allowing values within the process and measurement error ranges.

[0053] In the exemplary embodiments of the present disclosure, the "integral structure" may refer to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same lithography process to form a connected structure, and their materials may be the same or different.

[0054] In the exemplary embodiments of the present disclosure, the first direction DR1 may refer to the extending direction of the data signal lines or the column direction, etc. in the display area, the second direction DR2 may refer to the extending direction of the scan signal lines or the row direction, etc. in the display area, and the third direction DR3 may refer to the thickness direction of the display panel or the direction perpendicular to the plane of the display panel, etc. Among them, the first direction DR1 intersects with the second direction DR2, and the first direction DR1 intersects with the third direction DR3. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other, and the first direction DR1 and the third direction DR3 may be perpendicular to each other. Here, the embodiments of the present disclosure do not make any limitations in this regard.

[0055] In some white light evaporation bottom-emitting OLED display products, in order to obtain a larger aperture ratio, a transparent pixel structure is usually adopted, and the design distance between the pixel define layer (PDL) and the light-shielding layer in the driving circuit layer is often relatively close. It has been found by the inventors of the present disclosure that: as Figure 1 shown, when displaying monochromatic RGB (red, green, blue), in the area circled by the dashed line in Figure 1 , the white light generated by the organic light-emitting layer of the sub-pixel will be diffusely reflected or refracted through the cathode and other film layers and leak out from the edge of the color filter unit, resulting in a light leakage problem in the RGB sub-pixels, thereby causing an RGB color unevenness problem, and further affecting the display image quality.

[0056] Figure 2 FIG. is a schematic structural diagram of a display device. As Figure 2 shown, the display device may include: a timing controller, a data signal driver, a scan signal driver, and a pixel array. The timing controller is respectively connected to the data signal driver and the scan signal driver. The data signal driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least one scan signal line, at least one data signal line, and a pixel driving circuit.

[0057] In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, and may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3,... and Dn. For example, the data signal driver may sample the gray value using the clock signal and apply the data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3,... and Sm by receiving the clock signal, the scan start signal, etc. from the timing controller. For example, the scan signal driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of the clock signal, where m may be a natural number.

[0058] Figure 3 It is a schematic plan view of a display substrate. As Figure 3 shown, the display substrate may include: a plurality of pixel units P arranged in a matrix, and at least one of the plurality of pixel units P may include: a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, a third sub-pixel P3 that emits third-color light, and a fourth sub-pixel P4 that emits fourth-color light. The four sub-pixels may all include a circuit unit and a light-emitting device. The circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting devices in each sub-pixel are respectively connected to the pixel driving circuit of the corresponding sub-pixel, and the light-emitting devices are configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the corresponding sub-pixel.

[0059] In an exemplary embodiment, the first sub-pixel P1 may be a red (Red, R) sub-pixel that emits red light, the second sub-pixel P2 may be a white (White, W) sub-pixel that emits white light, the third sub-pixel P3 may be a green (Green, G) sub-pixel that emits green light, and the fourth sub-pixel P4 may be a blue (Blue, B) sub-pixel that emits blue light. Here, the embodiments of the present disclosure do not limit this.

[0060] In an exemplary embodiment, the shape of the sub-pixel may be a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, or other polygons, etc. Here, the embodiments of the present disclosure do not limit this.

[0061] In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal side-by-side manner to form an RWGB pixel arrangement. Alternatively, the four sub-pixels may be arranged in a square (Square), diamond (Diamond), or vertical side-by-side manner, etc. Here, the embodiments of the present disclosure do not limit this.

[0062] In an exemplary embodiment, the pixel driving circuit may be a 3T1C (i.e., including: three transistors and one capacitor unit), 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, etc. Here, the embodiments of the present disclosure do not limit this.

[0063] In an exemplary embodiment, taking the pixel driving circuit adopting a 3T1C structure as an example, Figure 4 It is a schematic equivalent circuit diagram of a pixel driving circuit. As Figure 4As shown, the pixel driving circuit may include: three transistors (a first transistor T1, a second transistor T2, and a third transistor T3), one storage capacitor C, and six signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a compensation signal line Se, a first power supply line VDD, and a second power supply line VSS). Among them, the first transistor T1 may be a switching transistor, the second transistor T2 may be a driving transistor, and the third transistor T3 may be a compensation transistor. A first electrode plate of the storage capacitor C is coupled to a second electrode of the second transistor T2, and a second electrode plate of the storage capacitor C is coupled to a gate electrode of the second transistor T2. The storage capacitor C is used to store the potential of the gate electrode of the second transistor T2. The gate electrode of the first transistor T1 is coupled to the first scan signal line S1, a first electrode of the first transistor T1 is coupled to the data signal line D, and a second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2. The first transistor T1 is configured to receive a data signal transmitted by the data signal line D under the control of the first scan signal line S1, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, a first electrode of the second transistor T2 is coupled to the first power supply line VDD, and a second electrode of the second transistor T2 is coupled to a first electrode of the light-emitting device. The second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by its gate electrode. The gate electrode of the third transistor T3 is coupled to the second scan signal line S2, a first electrode of the third transistor T3 is coupled to the compensation signal line Se, and a second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2. The third transistor T3 is configured to extract the threshold voltage Vth and mobility of the second transistor T2 in response to a compensation timing to compensate for the threshold voltage Vth.

[0064] In an exemplary embodiment, the light-emitting device may be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). The first electrode of the OLED is coupled to the second electrode of the second transistor T2, and the second electrode of the OLED is coupled to the second power supply line VSS. The OLED is configured to emit light with a corresponding brightness in response to the current at the second electrode of the second transistor T2.

[0065] In an exemplary embodiment, the signal of the first power supply line VDD is a continuously provided high-level signal, and the signal of the second power supply line VSS is a low-level signal. The first transistor T1 to the third transistor T3 may be P-type transistors, or may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product.

[0066] The exemplary embodiments of the present disclosure provide a display substrate, which may include: a substrate, a driving circuit layer disposed on the substrate, a color filter layer disposed on a side of the driving circuit layer away from the substrate, and a light-emitting structure layer disposed on a side of the color filter layer away from the substrate; wherein, the driving circuit layer includes: a light-shielding layer in a sub-pixel and a metal oxide layer disposed on a side of the light-shielding layer away from the substrate, and an overlapping area of a positive projection of the color filter layer on the substrate and a positive projection of the metal oxide layer on the substrate is greater than an overlapping area of a positive projection of the color filter layer on the substrate and a positive projection of the light-shielding layer on the substrate. Thus, by adopting the design of overlapping the positive projection of the color filter layer on the substrate and the positive projection of the light-shielding layer on the substrate, white light generated by the organic light-emitting layer of the sub-pixel leaks out from the edge of the color filter layer through diffuse reflection or refraction by the cathode and other film layers, and will be incident on the light-shielding layer, and thus, can be blocked by the light-shielding layer, so as to avoid the light leakage problem of the sub-pixel, and further, can avoid the color unevenness problem caused by light leakage, and can improve the display quality. Moreover, a transparent metal oxide layer is used as one electrode plate of the storage capacitor. Thus, since light can pass through the transparent metal oxide layer and exit, the storage capacitor can be disposed in the light-emitting area, and the pixel aperture ratio can be effectively increased.

[0067] Hereinafter, taking four sub-pixels of the display substrate and taking the pixel driving circuit in each sub-pixel adopting a 3T1C structure as an example, the structure and manufacturing process of the display substrate provided in the exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0068] Figure 5 It is a schematic structural diagram of the display substrate in the exemplary embodiments of the present disclosure, Figure 6 is Figure 5 a cross-sectional schematic diagram of the display substrate along the A-A' direction, Figure 7 is Figure 5 an equivalent circuit schematic diagram of the pixel driving circuit in the four sub-pixels shown. Among them, in Figure 5 the structure of the driving circuit layer in the four sub-pixels of a bottom-emission display substrate and some film layers in the light-emitting structure layer are schematically shown, and in Figure 6 the structure of one sub-pixel in the display substrate is schematically shown as an example.

[0069] In an exemplary embodiment, as Figures 5 to 7 shown, in a direction parallel to the display substrate, a plurality of sub-pixels may include: a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 sequentially arranged along a second direction DR2. Among them, each sub-pixel may include: a pixel driving circuit, and the pixel driving circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C. In the following description, a sub-pixel refers to an area where a pixel driving circuit is disposed.

[0070] In an exemplary embodiment, as Figures 5 to 7 shown, in a plane perpendicular to the display substrate, the display substrate may include: a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a color filter (CF) layer 401 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a light-emitting structure layer 103 disposed on a side of the color filter (CF) layer 401 away from the substrate 101. Among them, the driving circuit layer 102 may include: a light-shielding layer 23 disposed in a sub-pixel and a metal oxide layer 501 disposed on a side of the light-shielding layer 23 away from the substrate 101, and an overlapping area of a positive projection of the color filter layer (CF) 401 on the substrate and a positive projection of the metal oxide layer 501 on the substrate is larger than an overlapping area of a positive projection of the color filter layer 401 on the substrate and a positive projection of the light-shielding layer 23 in the corresponding sub-pixel on the substrate.

[0071] In an exemplary embodiment, the color filter layer 401 is configured to filter light emitted by the light-emitting device to generate light of different colors. For example, the color filter layer 401 may include: a red (R) color filter unit, a green (G) color filter unit, and a blue (B) color filter unit. For example, one color filter unit, the corresponding light-emitting device, and the pixel driving circuit may be divided into one sub-pixel. For example, the red (R) color filter unit, the green (G) color filter unit, and the blue (B) color filter unit respectively correspond to a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Here, the embodiments of the present disclosure do not limit this.

[0072] In an exemplary embodiment, a first overlapping area exists between a positive projection of the red color filter unit on the substrate and a positive projection of the light-shielding layer on the substrate, a second overlapping area exists between a positive projection of the blue color filter unit on the substrate and a positive projection of the light-shielding layer on the substrate, a third overlapping area exists between a positive projection of the green color filter unit on the substrate and a positive projection of the light-shielding layer on the substrate, and the first overlapping area is larger than the second overlapping area, or the first overlapping area is larger than the third overlapping area.

[0073] In an exemplary embodiment, a width of an overlapping area between a positive projection of the color filter layer 401 on the substrate and a positive projection of the light-shielding layer 23 on the substrate in a first direction DR1 may be about 5 micrometers to 350 micrometers. For example, the width of the overlapping area in the first direction DR1 may be 275 micrometers. Here, the embodiments of the present disclosure do not limit this.

[0074] In an exemplary embodiment, as Figures 5 to 7As shown, the display substrate may further include: a pixel driving circuit located in a sub-pixel, and the pixel driving circuit may include: a driving transistor (for example, the second transistor T2 may be a driving transistor), and a positive projection of the color filter layer 401 on the substrate 101 at least partially overlaps with a positive projection of the gate electrode of the driving transistor (for example, the second gate electrode 43 may be the gate electrode of the driving transistor) on the substrate 101.

[0075] In an exemplary embodiment, as Figures 5 to 7 shown, the display substrate may further include: a pixel driving circuit located in a sub-pixel, the pixel driving circuit may include: a storage capacitor C, and the driving circuit layer 102 may further include: a first conductive layer 502 disposed on a side of the light-shielding layer 23 close to the substrate, the first conductive layer 502 may include a first electrode plate 11, the metal oxide layer 501 may include a second electrode plate 34, and a positive projection of the second electrode plate 34 on the substrate 101 at least partially overlaps with a positive projection of the first electrode plate 11 on the substrate 101 to form the storage capacitor C.

[0076] In an exemplary embodiment, as Figures 5 to 7 shown, the light-emitting structure layer 103 may include: a pixel definition layer 302, a pixel opening for defining a light-emitting region is disposed on the pixel definition layer 302, a positive projection of the first electrode plate 11 on the substrate 101 at least partially overlaps with a positive projection of the pixel opening on the substrate 101, and a positive projection of the second electrode plate 34 on the substrate 101 at least partially overlaps with a positive projection of the pixel opening on the substrate 101. Thus, using the transparent metal oxide layer 501 as one electrode plate of the storage capacitor C enables the storage capacitor C to be disposed within the pixel opening, which can effectively increase the pixel aperture ratio.

[0077] In an exemplary embodiment, as Figures 5 to 7 shown, the first electrode plate 11 and the second electrode plate 34 of the storage capacitor C may be made of a transparent conductive material. Thus, since light can be emitted through the transparent storage capacitor, the storage capacitor C can be disposed within the pixel opening, which can effectively increase the pixel aperture ratio.

[0078] In an exemplary embodiment, as Figures 5 to 7 shown, a positive projection of the light-shielding layer 23 on the substrate 101 is spaced apart from a positive projection of the second electrode plate 34 on the substrate 101, that is, there is no overlap between a positive projection of the light-shielding layer 23 on the substrate 101 and a positive projection of the second electrode plate 34 on the substrate 101.

[0079] In an exemplary embodiment, as Figures 5 to 7As shown, the storage capacitor C may include: a first electrode plate 11 and a second electrode plate 34. The light-shielding layer 23 is provided with a light-shielding opening, and the light-shielding opening is configured to expose the surface of the first electrode plate 11.

[0080] In an exemplary embodiment, as Figures 5 to 7 shown, the pixel driving circuit may include: a first transistor T1 (not shown in the figure), a second transistor T2, and a third transistor T3 (not shown in the figure). The second region of the active layer of the first transistor T1 is connected to the second electrode plate 34. The second region of the active layer of the second transistor T2 is connected to the first electrode plate 11 through the light-shielding opening provided in the light-shielding layer 23. The second region of the active layer of the third transistor T3 is connected to the first electrode plate 11.

[0081] In an exemplary embodiment, the positive projection of the second region of the active layer of the first transistor T1 on the substrate at least partially overlaps with the positive projection of the light-shielding layer on the substrate.

[0082] In an exemplary embodiment, the active layer of the first transistor T1 and the second electrode plate may be an integrally connected structure.

[0083] In an exemplary embodiment, as Figures 5 to 7 shown, the positive projection of the active layer of the second transistor T2 (i.e., the second active layer 32) on the substrate 101 is located within the range of the positive projection of the light-shielding layer 23 on the substrate 101. In this way, the light-shielding layer 23 can block the channel region of the second transistor T2, avoid the influence of light on the channel, reduce the leakage current, and thus avoid the influence of light on the transistor characteristics.

[0084] In an exemplary embodiment, the positive projection of the active layer of the third transistor T3 on the substrate and the positive projection of the light-shielding layer on the substrate are spaced apart, that is, there is no overlapping region between the active layer of the third transistor T3 and the light-shielding layer. In this way, it is beneficial to design the channel width-to-length ratio of the third transistor T3 according to relevant requirements.

[0085] In an exemplary embodiment, the positive projection of the active layer of the third transistor T3 on the substrate and the positive projection of the second electrode plate on the substrate are spaced apart, that is, there is no overlapping region between the active layer of the third transistor T3 and the second electrode plate. In this way, it is beneficial to design the channel width-to-length ratio of the third transistor T3 according to relevant requirements.

[0086] In an exemplary embodiment, as Figures 5 to 7As shown, in a plane perpendicular to the display substrate, the driving circuit layer 102 may include: a first conductive layer 502, a second conductive layer 503, a metal oxide layer 501, a third conductive layer, and a fourth conductive layer sequentially disposed on a substrate 101. A first electrode plate 11 is located on the first conductive layer 502, a light-shielding layer 23 is located on the second conductive layer, a second electrode plate 34, an active layer of a first transistor T1 (not shown in the figure), an active layer of a second transistor T2 (i.e., a second active layer 32), and an active layer of a third transistor T3 (not shown in the figure) are located on the metal oxide layer 501. A gate electrode of the first transistor T1 (not shown in the figure), a gate electrode of the second transistor T2 (i.e., a second gate electrode 43), and a gate electrode of the third transistor T3 (not shown in the figure) are located on the third conductive layer. A first pole of the first transistor T1, a second pole of the first transistor T1, a first pole of the second transistor T2, a second pole of the second transistor T2, a first pole of the third transistor T3, and a second pole of the third transistor T3 are located on the fourth conductive layer.

[0087] In an exemplary embodiment, as Figures 5 to 7 shown, the driving circuit layer may further include: a first scan signal line S1, a second scan signal line S2, a first power supply line VDD, a data signal line D, and a compensation signal line Se. The first scan signal line S1 and the second scan signal line S2 are located on the third conductive layer, and the first power supply line VDD, the data signal line D, and the compensation signal line Se are located on the fourth conductive layer.

[0088] In an exemplary embodiment, as Figures 5 to 7 shown, a first sub-pixel P1 and a second sub-pixel P2 are controlled by one first power supply line VDD, and a third sub-pixel P2 and a fourth sub-pixel P4 are controlled by another first power supply line VDD; and, the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 are controlled by one compensation signal line.

[0089] In an exemplary embodiment, as Figures 5 to 7 shown, at least one pixel unit may further include: one first scan signal line S1, one second scan signal line S2, two first power supply lines VDD, four data signal lines D, one compensation signal line Se, and four pixel driving circuits.

[0090] In an exemplary embodiment, as Figures 5 to 7 shown, the first scan signal line S1 and the second scan signal line S2 may extend along a second direction DR2 and be sequentially disposed along a first direction DR1, and the second direction DR2 intersects with the first direction DR1.

[0091] In an exemplary embodiment, as Figures 5 to 7As shown, the first power supply line VDD, the data signal line D, and the compensation signal line Se can extend along the first direction DR1 and are correspondingly arranged along the second direction DR2.

[0092] In an exemplary embodiment, as Figures 5 to 7 shown, four data signal lines D and one compensation signal line Se can be arranged between two first power supply lines VDD. Two of the four data signal lines D are located between the compensation signal line Se and one first power supply line VDD, and the other two of the four data signal lines D are located between the compensation signal line Se and the other first power supply line VDD. In this way, four sub-pixels are formed between the two first power supply lines VDD by arranging four data signal lines D and one compensation signal line Se. Correspondingly, four sub-pixels are also formed between the two compensation signal lines Se by arranging two first power supply lines VDD and four data signal lines D.

[0093] In an exemplary embodiment, as Figures 5 to 7 shown, one first power supply line VDD, two data signal lines D, the compensation signal line Se, the other two data signal lines D, and the other first power supply line VDD can be arranged in sequence along the second direction DR2. A first sub-pixel P1 is formed between one first power supply line VDD and a data signal line D adjacent to the second direction DR2. A second sub-pixel P2 is formed between the compensation signal line Se and a data signal line D adjacent to the opposite direction of the second direction DR2. A third sub-pixel P3 is formed between the compensation signal line Se and a data signal line D adjacent to the second direction DR2. A fourth sub-pixel P4 is formed between the other first power supply line VDD and a data signal line D adjacent to the opposite direction of the second direction DR2.

[0094] In an exemplary embodiment, as Figures 5 to 7 shown, the first scan signal line S1 is connected to the gate electrode of the first transistor T1 in each sub-pixel. The second scan signal line S2 is connected to the gate electrode of the third transistor T3 in each sub-pixel. The data signal line D is connected to the first pole of the first transistor T1 in each sub-pixel. The compensation signal line Se is connected to the first pole of the third transistor T3 in each sub-pixel. The first power supply line VDD is connected to the first pole of the second transistor T2 in each sub-pixel. The second pole of the first transistor T1 in each sub-pixel is connected to the gate electrode of the second transistor T2. The second pole of the second transistor T2 in each sub-pixel is connected to the first pole of the third transistor T3 and the anode of the light-emitting device. The first electrode plate in each sub-pixel is respectively connected to the second pole of the second transistor T2 and the second pole of the third transistor T3. The second electrode plate in each sub-pixel is respectively connected to the second pole of the first transistor T1 and the gate electrode of the second transistor T2.

[0095] In an exemplary embodiment, as Figures 5 to 7 shown, at least one pixel unit may include a plurality of connection lines. The plurality of connection lines at least include two power connection lines 21 extending along a second direction DR2 and two compensation connection lines 22 extending along the second direction DR2. In this way, a one-to-two structure of the first power line and a one-to-four structure of the compensation signal line can be formed. Thereby, the number of signal lines can be saved, the occupied space can be reduced, the structure can be made simple, the layout can be reasonable, the layout space can be fully utilized, the space utilization rate can be improved, and it is beneficial to improve the resolution.

[0096] In an exemplary embodiment, as Figures 5 to 7 shown, one power connection line 21 is disposed in the first sub-pixel P1 and the second sub-pixel P2. The first end of the power connection line 21 is connected to the first power line VDD in the first sub-pixel P1 through a via, and the second end of the power connection line 21 is connected to the second transistor T2 in the second sub-pixel P2 through a via. Another power connection line 21 is disposed in the third sub-pixel P3 and the fourth sub-pixel P4. The first end of the power connection line 21 is connected to the first power line VDD in the fourth sub-pixel P4 through a via, and the second end of the power connection line 21 is connected to the second transistor T2 in the third sub-pixel P3 through a via. In this way, one first power line VDD can supply a power signal to two sub-pixels.

[0097] In an exemplary embodiment, as Figures 5 to 7 shown, one compensation connection line 22 is disposed in the first sub-pixel P1 and the second sub-pixel P2. The first end of the compensation connection line 22 is connected to the compensation signal line Se through a via, and the second end is connected to the third transistor T3 in the first sub-pixel P1 through a via. Another compensation connection line 22 is disposed in the third sub-pixel P3 and the fourth sub-pixel P4. The first end of the compensation connection line 22 is connected to the compensation signal line Se through a via, and the second end is connected to the third transistor T3 in the fourth sub-pixel P4 through a via. In this way, one compensation signal line Se can supply a compensation signal to four sub-pixels.

[0098] In an exemplary embodiment, as Figures 5 to 7 shown, the light-emitting structure layer 103 of each sub-pixel may include a light-emitting device composed of a plurality of film layers. The plurality of film layers may include: an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the pixel driving circuit, the organic light-emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. In some possible implementation manners, the display substrate may include other film layers. Here, the present disclosure does not make any limitation thereto.

[0099] In an exemplary embodiment, the organic light-emitting layer may include: a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a light-emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). For example, the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be common layers connected together. For example, the light-emitting layers of all sub-pixels may be common layers connected together, or may be isolated from each other, and the light-emitting layers of adjacent sub-pixels may have a small overlap.

[0100] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. For example, the substrate 101 may be a glass substrate. Here, the embodiments of the present disclosure do not limit this.

[0101] The following is an exemplary description through the preparation process of the display substrate. The "patterning process" as referred to in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping, and for organic materials, includes processes such as coating organic materials, mask exposure, and development. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, etching can be any one or more of dry etching and wet etching, and the present disclosure does not limit this. A "thin film" refers to a thin film of a certain material made on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process throughout the manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process throughout the manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as referred to in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0102] The following takes four sub-pixels (the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4) of the display substrate as an example to illustrate the preparation process of the display substrate.

[0103] In an exemplary embodiment, the preparation process of the driving circuit layer may include the following steps:

[0104] (1) Form a first conductive layer.

[0105] In one exemplary embodiment, forming the first conductive layer may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film through a patterning process, and forming a first conductive layer on the substrate.

[0106] In one exemplary embodiment, the first conductive layer may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). For example, taking the case where the first conductive layer can be made of ITO, the first conductive layer may be referred to as the first transparent (ITO1) layer.

[0107] In one exemplary embodiment, as Figure 8 shown, the first conductive layer may include: a first electrode plate 11 formed in each sub-pixel. The first conductive layer may further include: a first auxiliary electrode 12 and a second auxiliary electrode 13.

[0108] In one exemplary embodiment, as Figure 8 shown, the first electrode plate 11 in each sub-pixel may include: a main body portion 11-0 and a first portion 11-1 and a second portion 11-2 located on both sides of the main body portion 11-2. For example, the main body portion 11-2 may extend along a first direction DR1 and be configured to form a transparent electrode plate of a storage capacitor. For example, the first portion 11-1 may be disposed on a side opposite to the first direction DR1 of the main body portion 11-0 and connected to the main body portion 11-0, and be configured to be connected to an interlayer connection electrode 24 formed later. For example, the second portion 11-2 may be disposed on a side of the first direction DR1 of the main body portion 11-0 and connected to the main body portion 11-0, and be configured to be connected to a light-shielding layer 23 formed later. For example, chamfers may be provided at corners of at least one of the main body portion 11-0, the first portion 11-1, and the second portion 11-2. For example, the edge of at least one of the main body portion 11-0, the first portion 11-1, and the second portion 11-2 may be a broken line.

[0109] In one exemplary embodiment, the first auxiliary electrode 12 may be disposed in each sub-pixel and be configured to be connected to a power supply connection line 21 formed later to reduce the resistance of the power supply connection line 21. For example, the shape of the first auxiliary electrode 12 may be rectangular, and chamfers may be provided at the corners of the rectangular shape.

[0110] In one exemplary embodiment, the second auxiliary electrode 13 may be disposed in each sub-pixel and be configured to be connected to a compensation connection line 22 formed later to reduce the resistance of the compensation connection line 22. For example, the shape of the second auxiliary electrode 13 may be rectangular. Chamfers may be provided at the corners of the rectangular shape, and the edge of the rectangular shape may be a broken line.

[0111] (2) Form a second conductive layer.

[0112] In one exemplary embodiment, forming the second conductive layer may include: depositing a second conductive thin film on the substrate on which the foregoing structure is formed, patterning the second conductive thin film through a patterning process, and forming a second conductive layer on the substrate.

[0113] In one exemplary embodiment, the second conductive layer may be formed of a metal material. For example, the metal material may include, but is not limited to: any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the metals listed above, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc. The second conductive layer may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0114] In one exemplary embodiment, the second conductive layer may be referred to as a shield (SHL) layer.

[0115] In one exemplary embodiment, as Figure 9A and Figure 9B shown, the second conductive layer may include: a power connection line 21, a compensation connection line 22, and a light-shielding layer 23 and an interlayer connection electrode 24 formed in each sub-pixel.

[0116] In one exemplary embodiment, as Figure 9A and Figure 9B shown, the two power connection lines 21 may be strip-shaped structures extending along the second direction DR2, located on one side of the first direction DR1 of the first electrode plate 11, and arranged in sequence along the second direction DR2. For example, one power connection line 21 may straddle the first sub-pixel P1 and the second sub-pixel P2, and is configured to be connected to the first power line VDD formed in the first sub-pixel P1 subsequently, and provide the power signal output by the first power line VDD to the second transistor T2 of the second sub-pixel P2. Another power connection line 21 may straddle the third sub-pixel P3 and the fourth sub-pixel P3, and is configured to be connected to the first power line VDD formed in the fourth sub-pixel P3 subsequently, and provide the power signal output by the first power line VDD to the second transistor T2 of the third sub-pixel P3.

[0117] In one exemplary embodiment, as Figure 9A and Figure 9BAs shown, the two compensation connection lines 22 may be strip-shaped structures extending along the second direction DR2, and may be sequentially arranged along the second direction DR2. The two compensation connection lines 22 are located on one side of the first electrode plate 11 in the opposite direction of the first direction DR1. For example, one compensation connection line 22 may straddle the first sub-pixel P1 and the second sub-pixel P2, and is configured to be connected to the compensation signal line Se formed subsequently, and provide the compensation signal output by the compensation signal line Se to the third transistor T3 of the first sub-pixel P1. The other compensation connection line 22 may straddle the third sub-pixel P3 and the fourth sub-pixel P3, and is configured to be connected to the compensation signal line Se formed subsequently, and provide the compensation signal output by the compensation signal line Se to the third transistor T3 of the fourth sub-pixel P4.

[0118] In an exemplary embodiment, as Figure 9A and Figure 9B shown, the light-shielding layer 23 may be disposed in each sub-pixel, and is configured to shield the first transistor T1 and the second transistor T2 in the sub-pixel where it is located to prevent light leakage. For example, four light-shielding layers 23 may be sequentially arranged along the second direction DR1.

[0119] In an exemplary embodiment, as Figure 9A and Figure 9B shown, each light-shielding layer 23 may include: a first side 23-1, a second side 23-2, a third side 23-3, and a fourth side 23-4. The first side 23-1 and the third side 23-3 are disposed opposite to each other, and the second side 23-2 and the fourth side 23-4 are disposed opposite to each other. The main body portions of the first side 23-1 and the third side 23-3 may extend along the second direction DR1, and the main body portions of the second side 23-2 and the fourth side 23-4 may extend along the first direction DR2. The first end of the first side 23-1 is connected to the first end of the second side 23-2, the second end of the second side 23-2 is connected to the first end of the third side 23-3, the second end of the third side 23-3 is connected to the second end of the fourth side 23-4, and the first end of the fourth side 23-4 is connected to the second end of the first side 23-1. The first direction DR2 intersects with the second direction DR1.

[0120] In an exemplary embodiment, as Figure 9A and Figure 9B shown, one or more of the first side 23-1, the second side 23-2, the third side 23-3, and the fourth side 23-4 may be in a zigzag shape.

[0121] In an exemplary embodiment, the orthographic projection of the light-shielding layer 23 on the substrate overlaps with the orthographic projection of the color film layer 401 to be subsequently formed in the sub-pixel on the substrate. In this way, light leakage of the sub-pixel can be avoided. For example, the orthographic projection of the first side 23-1 on the substrate is located within the overlapping region. For example, the width of the overlapping region in the first direction DR1 can be about 5 micrometers to 350 micrometers. For example, the width of the overlapping region in the first direction DR1 can be 275 micrometers. Here, the embodiments of the present disclosure do not limit this.

[0122] In an exemplary embodiment, as Figure 9A and Figure 9B shown, the orthographic projection of each light-shielding layer 23 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 in the sub-pixel on the substrate. For example, the orthographic projection of the light-shielding layer 23 on the substrate at least partially overlaps with the orthographic projection of the second part 11-2 of the first electrode plate 11 in the sub-pixel on the substrate, and the light-shielding layer 23 is connected to the second part 11-2 of the first electrode plate 11.

[0123] In an exemplary embodiment, as Figure 9A and Figure 9B shown, each light-shielding layer 23 is provided with a light-shielding opening 25, and the light-shielding layer 23 within the light-shielding opening 25 is removed to expose the surface of the second part 11-2 of the first electrode plate 11 in the sub-pixel. The light-shielding opening 25 is configured to enable the second pole of the subsequently formed second transistor T2 to be connected to the second part 11-2 of the first electrode plate 11 through the light-shielding opening 25 and the fourth via V4, wherein the orthographic projection of the subsequently formed fourth via V4 on the substrate at least partially overlaps with the orthographic projection of the light-shielding opening 25 on the substrate to expose the second part 11-2 of the first electrode plate 11.

[0124] In an exemplary embodiment, the orthographic projection of the light-shielding layer 23 on the substrate and the orthographic projection of the second electrode plate 34 to be subsequently formed in the sub-pixel can be spaced apart, that is, there is no overlapping region between the light-shielding layer 23 and the second electrode plate 42. Here, the embodiments of the present disclosure do not limit this.

[0125] In an exemplary embodiment, as Figure 9A and Figure 9B shown, the shapes of the light-shielding layers 23 of different sub-pixels can be different. Alternatively, the areas of the light-shielding layers 23 of different sub-pixels can be different.

[0126] In an exemplary embodiment, as Figure 9A and Figure 9BAs shown, the interlayer connection electrode 24 can be disposed in each sub-pixel and is configured to be connected to the second pole of the third transistor T3 formed subsequently. Four interlayer connection electrodes 24 can be sequentially disposed along the second direction DR1. For example, the shape of the interlayer connection electrode 24 can be rectangular, and chamfers can be provided at the corners of the rectangular shape.

[0127] In an exemplary embodiment, as Figure 9A and Figure 9B shown, the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 in the corresponding sub-pixel on the substrate. For example, the orthographic projection of the interlayer connection electrode 24 on the substrate at least partially overlaps with the orthographic projection of the first part 11-1 of the first electrode plate 11 in the corresponding sub-pixel on the substrate, and the interlayer connection electrode 24 is connected to the first part 11-1.

[0128] (3) Form a metal oxide layer.

[0129] In an exemplary embodiment, forming the metal oxide layer may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the foregoing structure is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the second conductive layer, and a metal oxide layer provided on the first insulating layer. In an exemplary embodiment, the first insulating layer may be referred to as a buffer layer, and the metal oxide layer may be referred to as an active (ACT) layer.

[0130] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the metal oxide layer may include: a first active layer 31, a second active layer 32, a third active layer 33, and a second electrode plate 34 formed in each sub-pixel.

[0131] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the first active layer 31 serves as the active layer of the first transistor T1, the second active layer 32 serves as the active layer of the second transistor T2, and the third active layer 33 serves as the active layer of the third transistor T3. The first active layer 31, the second active layer 32, and the third active layer 33 all include a channel region and a first region and a second region located on both sides of the channel region.

[0132] In an exemplary embodiment, as Figure 10A and Figure 10BAs shown, the shape of the first active layer 31 can be "L"-shaped, and the first active layer 31 can be located on one side of the second electrode plate 34 in the first direction DR1. The first region 31-1 of the first active layer 31 is located on the side of the channel region away from the second electrode plate 34, and the second region 31-2 of the first active layer 31 is located on the side of the channel region close to the second electrode plate 34. The orthographic projection of the second region 31-2 of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the light-shielding layer 23 on the substrate.

[0133] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the second region 31-2 of the first active layer 31 can be connected to the second electrode plate 34. For example, the first active layer 31 and the second electrode plate 34 can be an integrally connected structure. In this way, compared with separate settings, this setting can make the arrangement of pixels more compact on the premise of meeting the design rules, which helps to improve the resolution of the display substrate.

[0134] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the second region 31-2 of the first active layer 31 in the first sub-pixel P1 and the third sub-pixel P3 is in a zigzag shape extending along the first direction D2, and the zigzag shape protrudes towards the adjacent sub-pixel. The zigzag shape in the first sub-pixel P1 protrudes towards the second sub-pixel P2, and the zigzag shape in the third sub-pixel P31 protrudes towards the fourth sub-pixel P4. Since the second region 31-2 of the first active layer 31 is connected to the second gate electrode through the second pole of the first transistor T1 formed subsequently, realizing the mutual connection between the second pole of the first transistor T1, the second gate electrode and the second electrode plate of the storage capacitor, the connection structure between the first transistor T1 and the storage capacitor in the first sub-pixel P1 and the third sub-pixel P3 is a turning structure protruding towards the adjacent sub-pixel. Here, the embodiments of the present disclosure do not limit this.

[0135] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the orthographic projection of the second region 31-2 of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the light-shielding layer 23 in the corresponding sub-pixel on the substrate.

[0136] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the second active layer 32 can be located on one side of the second electrode plate 34 in the first direction DR1. The orthographic projection of the second active layer 32 on the substrate is spaced from the orthographic projection of the second electrode plate 34 on the substrate, that is, there is no overlapping area between the second active layer 32 and the second electrode plate 34. In this way, it is beneficial to design the channel width-to-length ratio of the second transistor according to relevant requirements.

[0137] In an exemplary embodiment, asFigure 10A and Figure 10B As shown in Figure 10B , the shape of the second active layer 32 may be in an "I" shape.

[0138] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the first region 32-1 of the second active layer 32 is located on the side of the channel region away from the second electrode plate 34. A part of the first region 32-1 of the second active layer 32 close to the channel region has an overlapping area with the projection of the light-shielding layer 23 on the substrate, and a part of the first region 32-1 of the second active layer 32 away from the channel region has an overlapping area with the projection of the second part 11-2 of the first electrode plate 11 on the substrate.

[0139] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the second region 32-2 of the second active layer 32 is located on the side of the channel region close to the second electrode plate 34 and is located within the light-shielding opening 25. The projection of the second region 32-2 of the second active layer 32 on the substrate has an overlapping area with the projection of the light-shielding layer 23 on the substrate.

[0140] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the projection of the second active layer 32 on the substrate is within the range of the projection of the light-shielding layer 23 in the corresponding sub-pixel on the substrate. In this way, the light-shielding layer 23 can block the channel region of the second active layer 32, avoid the influence of light on the channel, reduce the leakage current, and thus avoid the influence of light on the transistor characteristics.

[0141] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the third active layer 33 may be located on the side opposite to the first direction DR1 of the second electrode plate 34. The projection of the third active layer 33 on the substrate is spaced apart from the projection of the second electrode plate 34 on the substrate, that is, there is no overlapping area between the third active layer 33 and the second electrode plate 34, which is beneficial to designing the channel width-to-length ratio of the third transistor according to relevant requirements.

[0142] The first region 33-1 of the third active layer 33 is located on the side of the channel region away from the second electrode plate 34. The projection of the first region 33-1 of the third active layer 33 on the substrate has an overlapping area with the projection of the compensation connection line 22 on the substrate. The second region 33-2 of the third active layer 33 is located on the side of the channel region close to the second electrode plate 34. The projection of the second region 33-2 of the third active layer 33 on the substrate has an overlapping area with the projection of the interlayer connection electrode 24 on the substrate. Here, the embodiments of the present disclosure do not make any limitations in this regard.

[0143] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the shape of the third active layer 33 may be in an "I" shape.

[0144] In an exemplary embodiment, as Figure 10A and Figure 10B shown, the orthographic projection of the second electrode plate 34 in each sub-pixel on the substrate overlaps with the orthographic projection of the first electrode plate 11 in the corresponding sub-pixel on the substrate. The second electrode plate 34 is configured to form another electrode plate of the storage capacitor C, and the first electrode plate 11 and the second electrode plate 34 form the storage capacitor C. For example, the first electrode plate and the second electrode plate may be transparent conductive layers to form a transparent storage capacitor C. Thus, since light can pass through the transparent storage capacitor and exit, the transparent storage capacitor C can be disposed within the pixel aperture, effectively increasing the pixel aperture ratio.

[0145] In an exemplary embodiment, the shape of the second electrode plate 34 may be rectangular. For example, chamfers may be provided at the corners of the rectangular shape. For example, the edges of the rectangular shape may be broken lines. Here, the embodiments of the present disclosure do not limit this.

[0146] In an exemplary embodiment, the metal oxide layer may be made of a metal oxide material. For example, the metal oxide material may include, but is not limited to: oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, etc. For example, the metal oxide layer may be indium gallium zinc oxide (IGZO). For example, the metal oxide layer may be a single layer, a double layer or multiple layers, etc. Here, the embodiments of the present disclosure do not limit this.

[0147] (4) Form a third conductive layer.

[0148] In an exemplary embodiment, forming the third conductive layer may include: sequentially depositing a second insulating film and a third conductive film on the substrate on which the foregoing structure is formed, patterning the third conductive film through a patterning process to form a second insulating layer covering the metal oxide layer, and a third conductive layer disposed on the second insulating layer. For example, the second insulating layer may be referred to as a gate insulation (GI) layer. For example, the third conductive layer may be referred to as a gate metal (GT) layer.

[0149] In an exemplary embodiment, the third conductive layer may be formed of a metallic material. For example, the metallic material may include, but is not limited to, any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the metals listed above, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc. For example, the third conductive layer may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0150] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the third conductive layer may include a first scan signal line S1, a first gate electrode 41, a second scan signal line S2, a third gate electrode 42, a second gate electrode 43, an auxiliary power supply line 44, an auxiliary data line 45, and an auxiliary compensation line 46.

[0151] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the first scan signal line S1 may be a bar-shaped structure extending along the second direction DR2 and located on one side of the first direction DR1 of the second electrode plate 34. The first scan signal line S1 may straddle the first sub-pixel P1 to the fourth sub-pixel P4.

[0152] In an exemplary embodiment, the first scan signal line S1 may be set with a uniform width, and the width is the dimension of the first scan signal line S1 in the first direction DR1.

[0153] In an exemplary embodiment, as Figure 11A and Figure 11B shown, a plurality of through holes may be provided on the first scan signal line S1. The orthographic projection of the plurality of through holes on the substrate overlaps with the orthographic projection of the subsequent formed first power supply line VDD, data signal line D, and compensation signal line Se on the substrate. The plurality of through holes are configured to reduce the parasitic capacitance between the first scan signal line S1 and the first power supply line VDD, data signal line D, and compensation signal line Se.

[0154] In an exemplary embodiment, the first scan signal line S1 may be symmetrically arranged with respect to the vertical axis (for example, the auxiliary compensation line 46 or the compensation signal line Se).

[0155] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the first gate electrode 41 may be provided in each sub-pixel as the gate electrode of the first transistor T1. In each sub-pixel, the orthographic projection of the first gate electrode 41 on the substrate overlaps with the orthographic projection of the first active layer 31 on the substrate. For example, the first gate electrode 41 may be rectangular.

[0156] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the first gate electrode 41 may be located on a side of the first scan signal line S1 close to the second scan signal line S2 and connected to the first scan signal line S1. For example, the first scan signal line S1 and the first gate electrode 41 may be an integrally connected structure. For example, four first gate electrodes 41 may be sequentially arranged along the second direction DR2.

[0157] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the second scan signal line S2 may be a strip-shaped structure extending along the second direction DR2 and located on a side opposite to the first direction DR1 of the second electrode plate 34. The second scan signal line S2 may straddle the first sub-pixel P1 to the fourth sub-pixel P4.

[0158] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the second scan signal line S2 may be set with unequal widths, and the width is the dimension of the second scan signal line S2 along the first direction DR1. For example, the second scan signal line S2 may include a region overlapping with the third active layer 33 and a region not overlapping with the third active layer 33. Among them, the width of the second scan signal line S2 in the region overlapping with the third active layer 33 may be smaller than the width of the second scan signal line S2 in the region not overlapping with the third active layer 33. For example, in the region not overlapping with the third active layer 33, a plurality of through holes may be provided on the second scan signal line S2, and the orthographic projection of the plurality of through holes on the substrate overlaps with the orthographic projection of the subsequent formed first power supply line VDD, data signal line D, and compensation signal line Se on the substrate. The plurality of through holes are configured to reduce the parasitic capacitance between the second scan signal line S2 and the first power supply line VDD, data signal line D, and compensation signal line Se.

[0159] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the orthographic projection of the second scan signal line S2 on the substrate and the orthographic projection of the third active layer 33 in each sub-pixel on the substrate have an overlapping region, and a part of the second scan signal line S2 corresponding to the overlapping region may be used as the third gate electrode 42.

[0160] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the third gate electrode 42 may be provided in each sub-pixel as the gate electrode of the third transistor T3.

[0161] In an exemplary embodiment, the second scan signal line S2 and the first scan signal line S1 may be arranged in parallel.

[0162] In an exemplary embodiment, the second scan signal line S2 may be symmetrically disposed with respect to the vertical axis (e.g., the auxiliary compensation line 46).

[0163] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the second gate electrode 43 may be disposed within each sub-pixel as the gate electrode of the second transistor T2. Within each sub-pixel, the orthographic projection of the second gate electrode 43 on the substrate overlaps with the orthographic projection of the second active layer 32 on the substrate, and the orthographic projection of the second gate electrode 43 on the substrate overlaps with the orthographic projection of the second region 31-2 of the first active layer 31 on the substrate.

[0164] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the second gate electrodes 43 within the first sub-pixel P1 and the fourth sub-pixel P4 may be symmetrically disposed with respect to the vertical axis (e.g., the auxiliary compensation line 46), and the second gate electrodes 43 within the second sub-pixel P2 and the third sub-pixel P3 may be symmetrically disposed with respect to the vertical axis (e.g., the auxiliary compensation line 46).

[0165] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the two auxiliary power supply lines 44 may be strip-shaped structures extending along the first direction DR1. Among them, one auxiliary power supply line 44 may be formed within the first sub-pixel P1, on the side opposite to the second direction DR2 of the second electrode plate 34 of the first sub-pixel P1. The other auxiliary power supply line 44 may be formed within the fourth sub-pixel P4, on the side of the second electrode plate 34 of the fourth sub-pixel P4 in the second direction DR2. For example, the two auxiliary power supply lines 44 may be symmetrically disposed with respect to the vertical axis (e.g., the auxiliary compensation line 46). For example, the auxiliary power supply line 44 is configured to be connected to the first power supply line VDD formed subsequently to form a double-layer wiring, ensuring the reliability of the power signal transmission and reducing the resistance of the first power supply line VDD.

[0166] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the auxiliary data line 45 is a strip-shaped structure extending along the first direction DR1. The auxiliary data line 45 is formed within each sub-pixel. Within the first sub-pixel P1 and the third sub-pixel P3, the auxiliary data line 45 is on the side of the second electrode plate 34 in the second direction DR2. Within the second sub-pixel P2 and the fourth sub-pixel P4, the auxiliary data line 45 is on the side opposite to the second direction DR2 of the second electrode plate 34. The auxiliary data line 45 is configured to be connected to the data signal line formed subsequently to form a double-layer wiring, which can ensure the reliability of the data signal transmission and reduce the resistance of the data signal line.

[0167] In an exemplary embodiment, as Figure 11A and Figure 11B shown, the auxiliary compensation line 46 may be a bar-shaped structure extending along the first direction DR1. The auxiliary compensation line 46 may be formed between the second sub-pixel P2 and the third sub-pixel P3. The auxiliary compensation line 46 is configured to be connected to a subsequently formed compensation signal line to form a double-layer trace, which can ensure the reliability of the compensation signal transmission and reduce the resistance of the compensation signal line.

[0168] In an exemplary embodiment, the main portions of the auxiliary power supply line 44, the auxiliary data line 45, and the auxiliary compensation line 46 may be arranged in parallel.

[0169] In an exemplary embodiment, the auxiliary power supply lines 44 in the first sub-pixel P1 and the fourth sub-pixel P4 may be arranged symmetrically with respect to the vertical axis (e.g., the auxiliary compensation line 46).

[0170] In an exemplary embodiment, this process may further include a conductorization process. Among them, the conductorization process refers to, after forming the third conductive layer pattern, using the third conductive layer as a mask for plasma processing. The regions of the metal oxide layer shielded by the first gate electrode, the second gate electrode, and the third gate electrode serve as the channel regions of the transistor, and the regions of the metal oxide layer not shielded by the third conductive layer are processed into conductorized regions to form the conductorized second electrode plate 34 and the conductorized source-drain regions (i.e., the conductorized first region and the conductorized second region).

[0171] (5) Form the third insulating layer.

[0172] In an exemplary embodiment, forming the third insulating layer may include: depositing a third insulating film on the substrate on which the foregoing structure is formed, and patterning the third insulating film using a patterning process to form the third insulating layer covering the third conductive layer. In an exemplary embodiment, the third insulating layer may be referred to as an interlayer dielectric (ILD) layer.

[0173] In an exemplary embodiment, as Figure 12 shown, a plurality of vias are provided on the third insulating layer, and the plurality of vias may include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0174] In an exemplary embodiment, as Figure 12As shown, the first via hole V1 can be provided in each sub-pixel. For each sub-pixel, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region 31-1 of the first active layer 31 on the substrate, and the third insulating layer and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region 31-1 of the first active layer 31. In an exemplary embodiment, the first via hole V1 is configured to allow the first electrode of the first transistor T1 formed subsequently to be connected to the data signal line D formed subsequently and the first region 31-1 of the first active layer 31 through the via hole.

[0175] In an exemplary embodiment, Figure 12 As shown, the second via hole V2 can be set in each sub-pixel. The orthographic projection of the second via hole V2 in each sub-pixel on the substrate is located within the range of the orthographic projection of the second area 31-2 of the first active layer 31 in the sub-pixel on the substrate, and the orthographic projection of the second via hole V2 on the substrate overlaps at least partially with the orthographic projection of the second gate electrode 43 on the substrate. In an exemplary embodiment, the third insulating layer and the second insulating layer in the second via hole V2 are etched away, and the surface of the second area 31-2 of the first active layer 31 and the surface of the second gate electrode 43 are exposed at the same time. In an exemplary embodiment, the second via hole V2 is a transfer via hole, and the transfer via hole is composed of two half holes, one half hole is formed on the second area 31-2 of the first active layer 31, and the other half hole is formed on the second gate electrode 43, so that the transfer via hole composed of the two half holes simultaneously exposes the surface of the second area 31-2 of the first active layer 31 and the surface of the second gate electrode 43. In an exemplary embodiment, the second via hole V2 is configured to allow the second electrode of the first transistor T1 formed subsequently to be connected to the second gate electrode 43 and the second region 31 - 2 of the first active layer 31 through the via hole.

[0176] In an exemplary embodiment, Figure 12 As shown, the third via hole V3 can be provided in each sub-pixel, and the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area 32-1 of the second active layer 32 on the substrate, and the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area 32-1 of the second active layer 32. In an exemplary embodiment, the third via hole V3 is configured to connect the first power line or the fifth connection electrode formed subsequently to the second active layer 32 through the via hole.

[0177] In an exemplary embodiment, Figure 12As shown, the fourth vias V4 can be disposed in each sub-pixel. The orthographic projection of the fourth vias V4 on the substrate at least partially overlaps with the orthographic projection of the second region 32-2 of the second active layer 32 on the substrate, at least partially overlaps with the orthographic projection of the second portion 11-2 of the first electrode plate 11 on the substrate, and at least partially overlaps with the orthographic projection of the light-shielding opening 25 on the substrate. In an exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer in the fourth vias V4 are etched away, while exposing the surface of the second region 32-2 of the second active layer 32 and the surface of the second portion 11-2 of the first electrode plate 11. In an exemplary embodiment, the fourth vias V4 are configured such that the second pole of the subsequently formed second transistor T2 passes through the vias and is connected to both the second portion 11-2 of the first electrode plate 11 and the second active layer 32.

[0178] In an exemplary embodiment, as Figure 12 shown, the fifth vias V5 can be disposed in each sub-pixel. For each sub-pixel, the orthographic projection of the fifth vias V5 on the substrate at least partially overlaps with the orthographic projection of the first region 33-1 of the third active layer 33 on the substrate, and the orthographic projection of the fifth vias V5 on the substrate at least partially overlaps with the orthographic projection of the compensation connection line 22 on the substrate. In an exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer in the fifth vias V5 are etched away, while exposing the surface of the first region 33-1 of the third active layer 33 and the surface of the compensation connection line 22. In an exemplary embodiment, the fifth vias V5 are configured such that the first pole of the subsequently formed third transistor T3 passes through the vias and is connected to both the compensation connection line 22 and the first region 33-1 of the third active layer 33.

[0179] In an exemplary embodiment, as Figure 12 shown, the sixth vias V6 can be disposed in each sub-pixel. For each sub-pixel, the orthographic projection of the sixth vias V6 on the substrate at least partially overlaps with the orthographic projection of the second region 33-2 of the third active layer 33 on the substrate, and the orthographic projection of the sixth vias V6 on the substrate at least partially overlaps with the orthographic projection of the interlayer connection electrode 24 on the substrate. In an exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer in the sixth vias V6 are etched away, while exposing the surface of the second region 33-2 of the third active layer 33 and the surface of the interlayer connection electrode 24. In an exemplary embodiment, the sixth vias V6 are configured such that the second pole of the subsequently formed third transistor T3 passes through the vias and is connected to both the interlayer connection electrode 24 and the third active layer 33.

[0180] In an exemplary embodiment, as Figure 12As shown, the seventh viaduct V7 can be disposed in the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the seventh viaduct V7 on the substrate is within the range of the orthographic projection of the first end of the power connection line 21 on the substrate. In one exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer in the seventh viaduct V7 are etched away to expose the surface of the first end of the power connection line 21. In one exemplary embodiment, the seventh viaduct V7 is configured to enable a first power line formed subsequently to be connected to the first end of the power connection line 21 through this viaduct.

[0181] In one exemplary embodiment, as Figure 12 As shown, the eighth viaduct V8 can be disposed in the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the eighth viaduct V8 on the substrate is within the range of the orthographic projection of the second end of the power connection line 21 on the substrate. In one exemplary embodiment, the third insulating layer, the second insulating layer, and the first insulating layer in the eighth viaduct V8 are etched away to expose the surface of the second end of the power connection line 21. In one exemplary embodiment, the eighth viaduct V8 is configured to enable a first pole of a second transistor T2 formed subsequently to be connected to the second end of the power connection line 21 through this viaduct.

[0182] In one exemplary embodiment, as Figure 12 As shown, the ninth viaduct V9 can be disposed in the first sub-pixel P1 and the fourth sub-pixel P4. The orthographic projection of the ninth viaduct V9 on the substrate is within the range of the orthographic projection of the auxiliary power line 44 on the substrate. The third insulating layer in the ninth viaduct V9 is etched away to expose the surface of the auxiliary power line 44. In one exemplary embodiment, the ninth viaduct V9 is configured to enable a first power line formed subsequently to be connected to the auxiliary power line 44 through this viaduct. In one exemplary embodiment, there can be a plurality of ninth viaducts V9, and the plurality of ninth viaducts V9 can be arranged in sequence along the first direction DR1 to increase the connection reliability between the first power line and the auxiliary power line 44.

[0183] In one exemplary embodiment, as Figure 12 As shown, the tenth viaduct V10 can be disposed in each sub-pixel. The orthographic projection of the tenth viaduct V10 on the substrate is within the range of the orthographic projection of the auxiliary data line 45 on the substrate. The third insulating layer in the tenth viaduct V10 is etched away to expose the surface of the auxiliary data line 45. In one exemplary embodiment, the tenth viaduct V10 is configured to enable a data signal line formed subsequently to be connected to the auxiliary data line 45 through this viaduct. In one exemplary embodiment, there can be a plurality of tenth viaducts V10. For example, the plurality of tenth viaducts V10 can be arranged in sequence along the first direction DR1 to increase the connection reliability between the data signal line and the auxiliary data line 45.

[0184] In one exemplary embodiment, asFigure 12 As shown, the eleventh viaduct V11 can be disposed between the second sub-pixel P2 and the third sub-pixel P3. The orthographic projection of the eleventh viaduct V11 on the substrate is within the range of the orthographic projection of the auxiliary compensation line 46 on the substrate. The third insulating layer within the eleventh viaduct V11 is etched away to expose the surface of the auxiliary compensation line 46. In one exemplary embodiment, the eleventh viaduct V11 is configured to enable a subsequently formed compensation signal line to be connected to the auxiliary compensation line 46 through this viaduct. In the exemplary embodiment, there may be a plurality of the eleventh viaducts V11. For example, a plurality of the eleventh viaducts V11 may be arranged in sequence along the first direction DR1 to increase the connection reliability between the compensation signal line and the auxiliary compensation line 46.

[0185] (6) Form the fourth conductive layer.

[0186] In one exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on the substrate on which the foregoing structure is formed, and patterning the fourth conductive thin film using a patterning process to form the fourth conductive layer disposed on the third insulating layer.

[0187] In one exemplary embodiment, the fourth conductive layer may be formed of a metal material. For example, the metal material may include but is not limited to any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the metals listed above, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc. For example, the fourth conductive layer may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0188] In one exemplary embodiment, the fourth conductive layer may be referred to as a source-drain metal (SD) layer.

[0189] In one exemplary embodiment, as Figure 13A and Figure 13B shown, the fourth conductive layer may include: a data signal line D, a compensation signal line Se, a first power supply line VDD, a first connection electrode 54, a second connection electrode 55, a third connection electrode 56, a fourth connection electrode 57, and a fifth connection electrode 58.

[0190] In one exemplary embodiment, as Figure 13A and Figure 13BAs shown, the data signal line D can be disposed in each sub-pixel. The main body of the data signal line D extends along the first direction DR1. On one hand, the data signal line D is connected to the first region 31-1 of the first active layer 31 through the first via V1 to write the data signal into the first transistor T1. On the other hand, the data signal line D is connected to the auxiliary data line 45 through a plurality of tenth vias V10, so that the data signal line D and the auxiliary data line 45 form a double-layer routing. Thus, in the exemplary embodiment of the present disclosure, by disposing the data signal line D extending along the first direction DR1 in each sub-pixel, and connecting the data signal line D to the first transistor T1 of this sub-pixel through a via, the data signal is respectively written into the first transistors T1 of the four sub-pixels.

[0191] In one exemplary embodiment, as Figure 13A and Figure 13B shown, the compensation signal line Se can be disposed between the second sub-pixel P2 and the third sub-pixel P3. The main body of the compensation signal line Se extends along the first direction DR1. The compensation signal line Se is connected to the auxiliary compensation line 46 through a plurality of eleventh vias V11, so that the compensation signal line Se and the auxiliary compensation line 46 form a double-layer routing.

[0192] In one exemplary embodiment, as Figure 13A and Figure 13BAs shown, a first protrusion 51 and a second protrusion 52 are provided on the compensation signal line Se. For example, a first end of the first protrusion 51 is connected to the compensation signal line Se, and a second end of the first protrusion 51 extends in the opposite direction of the second direction DR2 to the second sub-pixel P2, and is simultaneously connected to a first region 33-1 of the third active layer 33 and the compensation connection line 22 through a fifth via V5 in the second sub-pixel P2. Thus, on the one hand, the first protrusion 51 can serve as a first pole of the third transistor T3 in the second sub-pixel P2 to write the compensation signal output by the compensation signal line Se into the third transistor T3 of the second sub-pixel P2. On the other hand, the first protrusion 51 can transmit the compensation signal output by the compensation signal line Se to the compensation connection line 22 bridging the first sub-pixel P1 and the second sub-pixel P2, so that the compensation connection line 22 transmits the compensation signal to the third transistor T3 of the first sub-pixel P1. For example, a first end of the second protrusion 52 is connected to the compensation signal line Se, and a second end of the second protrusion 52 extends along the second direction DR2 to the third sub-pixel P3, and is simultaneously connected to a first region 33-1 of the third active layer 33 and the compensation connection line 22 through a fifth via V5 in the third sub-pixel P3. Thus, on the one hand, the second protrusion 52 can serve as a first pole of the third transistor T3 in the pixel driving circuit of the third sub-pixel P3 to write the compensation signal output by the compensation signal line Se into the third transistor T3 of the third sub-pixel P3. On the other hand, the second protrusion 52 can transmit the compensation signal output by the compensation signal line Se to the compensation connection line 22 bridging the third sub-pixel P3 and the fourth sub-pixel P4, so that the compensation connection line 22 transmits the compensation signal to the third transistor T3 of the fourth sub-pixel P4.

[0193] Thus, in the exemplary embodiment of the present disclosure, by providing a compensation signal line Se whose main body portion extends along the first direction DR1 and two compensation connection lines 22 extending along the second direction DR2, the compensation signal is written into the third transistors T3 of the four sub-pixels respectively. Among them, in the second sub-pixel P2 and the third sub-pixel P3, the compensation signal line Se is directly connected to the third transistor T3 through vias respectively. In the first sub-pixel P1 and the fourth sub-pixel P4, the compensation signal line Se is connected to the third transistor T3 through the compensation connection line 22 respectively. By providing one compensation signal line Se to supply the compensation signal to the four sub-pixels, the present disclosure can ensure that the RC delay of the compensation signal is basically the same before being written into the transistor, ensuring display uniformity.

[0194] In one exemplary embodiment, as Figure 13A and Figure 13BAs shown, the first power supply line VDD can be respectively arranged in the first sub-pixel P1 and the fourth sub-pixel P4. The main part of the first power supply line VDD extends along the first direction DR1. On the one hand, a third protrusion 53 can be arranged on the first power supply line VDD. The first end of the third protrusion 53 is connected to the first power supply line VDD, and the second end of the third protrusion 53 is connected to the first region 32-1 of the second active layer 32 through a third via V3 within this sub-pixel. Thus, the third protrusion 53 can serve as the first pole of the second transistor T2, realizing the transmission of the power signal output by the first power supply line VDD to the second transistors T2 of the first sub-pixel P1 and the fourth sub-pixel P4 respectively. On the other hand, the first power supply line VDD is connected to the first end of the power connection line 21 through a seventh via V7, and the second end of the power connection line 21 is connected to the fifth connection electrode 58 through an eighth via V8. The fifth connection electrode 58 is connected to the first region 32-1 of the second active layer 32 through a third via V3 within this sub-pixel. Therefore, the power connection line 21 can transmit the power signal to the second transistors T2 of the second sub-pixel P2 and the third sub-pixel P3 respectively. On yet another hand, the first power supply line VDD is connected to the auxiliary power supply line 44 through a plurality of ninth vias V9, such that the first power supply line VDD and the auxiliary power supply line 44 form a double-layer routing.

[0195] Thus, in the exemplary embodiment of the present disclosure, by arranging two first power supply lines VDD extending along the first direction DR1 and two power connection lines 21 extending along the second direction DR2, the power signal is written into the second transistors T2 of the four sub-pixels respectively. Among them, in the first sub-pixel P1 and the fourth sub-pixel P4, the first power supply line VDD is directly connected to the second transistor T2 through a via. In the second sub-pixel P2 and the third sub-pixel P3, the first power supply line VDD is connected to the second transistor T2 through the fifth connection electrode 58 respectively.

[0196] In an exemplary embodiment, one first power supply line VDD arranged in the first sub-pixel P1 provides a power signal to the first sub-pixel P1 and the second sub-pixel P2, and another first power supply line VDD arranged in the first sub-pixel P4 provides a power signal to the third sub-pixel P3 and the fourth sub-pixel P4.

[0197] In an exemplary embodiment, the first power supply line VDD, the data signal line D, and the compensation signal line Se can be straight lines or broken lines with equal widths, or straight lines or broken lines with unequal widths. The first power supply line VDD, the data signal line D, and the compensation signal line Se adopting straight lines or broken lines with variable widths can not only facilitate the layout of the pixel structure but also reduce the parasitic capacitance.

[0198] In an exemplary embodiment, as Figure 13A and Figure 13BAs shown, the first connection electrode 54 can be respectively disposed in each sub-pixel and can serve as the second pole of the first transistor T1. In an exemplary embodiment, the first connection electrode 54 in each sub-pixel is simultaneously connected to the second region 31-2 of the first active layer 31 and the second gate electrode 43 through the second via V2. Thus, since the second region 31-2 of the first active layer 31 is connected to the second electrode plate 34, the first connection electrode 54 makes the second pole of the first transistor T1, the second gate electrode 43, and the second electrode plate 34 have the same potential, that is, the potential of the first node N1. For example, the first connection electrode 54 can be rectangular in shape.

[0199] In an exemplary embodiment, as Figure 13A and Figure 13B shown, the second connection electrode 55 is respectively disposed in each sub-pixel and can serve as the second pole of the second transistor T2. In an exemplary embodiment, the second connection electrode 55 in each sub-pixel is simultaneously connected to the second region 32-2 of the second active layer 32 and the second part 11-2 of the first electrode plate 11 through the fourth via V4. Thus, the second connection electrode 55 makes the second pole of the second transistor T2 and the first electrode plate 11 have the same potential. For example, the second connection electrode 55 can be rectangular in shape.

[0200] In an exemplary embodiment, as Figure 13A and Figure 13B shown, the third connection electrode 56 is respectively disposed in each sub-pixel and can serve as the second pole of the third transistor T3. In an exemplary embodiment, the third connection electrode 56 in each sub-pixel is simultaneously connected to the second region 33-2 of the third active layer 33 and the interlayer connection electrode 24 through the sixth via V6. Thus, since the interlayer connection electrode 24 is connected to the first part 11-1 of the first electrode plate 11, the third connection electrode 56 makes the second pole of the third transistor T3 and the first electrode plate 11 have the same potential. For example, the third connection electrode 56 can be rectangular in shape.

[0201] Here, since the second connection electrode 55 makes the first electrode plate 11 and the second pole of the second transistor T2 have the same potential, and the third connection electrode 56 makes the first electrode plate 11 and the second pole of the third transistor T3 have the same potential, the second pole of the second transistor T2, the second pole of the third transistor T3, and the first electrode plate 11 have the same potential, that is, the potential of the second node N2.

[0202] In an exemplary embodiment, as Figure 13A and Figure 13BAs shown, the fourth connection electrode 57 serves as the first pole of the third transistor T3. In an exemplary embodiment, one fourth connection electrode 57 may be disposed in the first sub-pixel P1 and serve as the first pole of the third transistor T3 in the first sub-pixel P1, and another fourth connection electrode 57 may be disposed in the fourth sub-pixel P4 and serve as the first pole of the third transistor T3 in the fourth sub-pixel P4. In an exemplary embodiment, the fourth connection electrode 57 in the first sub-pixel P1 is simultaneously connected to the first region 33-1 of the third active layer 33 and the compensation connection line 22 through the fifth via V5 in the first sub-pixel P1. And since the compensation connection line 22 is connected to the compensation signal line Se, the fourth connection electrode 57 in the first sub-pixel P1 can write the compensation signal output from the compensation signal line Se into the third transistor T3 in the first sub-pixel P1. In an exemplary embodiment, the fourth connection electrode 57 in the fourth sub-pixel P4 is simultaneously connected to the first region 33-1 of the third active layer 33 and the compensation connection line 22 through the fifth via V5 in the fourth sub-pixel P4. And since the compensation connection line 22 is connected to the compensation signal line Se, the fourth connection electrode 57 in the fourth sub-pixel P4 can write the compensation signal into the third transistor T3 in the fourth sub-pixel P4. For example, the fourth connection electrode 57 may be rectangular in shape.

[0203] In an exemplary embodiment, as Figure 13A and Figure 13B shown, the fifth connection electrode 58 may serve as the first pole of the second transistor T2. In an exemplary embodiment, one fifth connection electrode 58 may be disposed in the second sub-pixel P2 and serve as the first pole of the second transistor T2 in the second sub-pixel P2, and another fifth connection electrode 58 may be disposed in the third sub-pixel P3 and serve as the first pole of the second transistor T2 in the third sub-pixel P3. In an exemplary embodiment, the first end of the fifth connection electrode 58 is connected to the power supply connection line 21 through the eighth via V8 in the second sub-pixel P2, and the second end of the fifth connection electrode 58 is connected to the first region 32-1 of the second active layer 32 through the third via V3 of this sub-pixel. Thus, since the power supply connection line 21 is connected to the first power supply line VDD, the fifth connection electrode 58 can write the power supply signal into the second transistor T2 in the second sub-pixel P2 and the third sub-pixel P3. For example, the fifth connection electrode 58 may be in a strip shape extending along the first direction DR1.

[0204] (7) Form the fourth insulating layer.

[0205] In an exemplary embodiment, forming the fourth insulating layer may include: coating a fourth insulating thin film on the substrate on which the foregoing structure is formed, patterning the fourth insulating thin film by a patterning process, and forming a fourth insulating layer covering the fourth conductive layer. In an exemplary embodiment, the fourth insulating layer may be referred to as a Passivation (PVX) layer.

[0206] In an exemplary embodiment, as Figure 14 shown, a plurality of vias are formed in the fourth insulating layer, and the plurality of vias may include: the twenty-first via V21 located in each sub-pixel.

[0207] In an exemplary embodiment, as Figure 14 shown, the twenty-first via V21 may be disposed in each sub-pixel, the orthographic projection of the twenty-first via V21 on the substrate is within the range of the orthographic projection of the second connection electrode 55 on the substrate, and the fourth insulating layer within the twenty-first via V21 is removed to expose the surface of the second connection electrode 55. In an exemplary embodiment, the twenty-first via V21 is configured to enable the anode formed subsequently to be connected to the second connection electrode 55 through this via and the thirty-first via V31.

[0208] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer.

[0209] Thus, the driving circuit layer is fabricated on the substrate.

[0210] In an exemplary embodiment, after the driving circuit layer is fabricated, a color filter (CF) layer is fabricated on the driving circuit layer, and the fabrication process of the color filter (CF) layer may include the following steps:

[0211] (9) Forming the color filter layer.

[0212] In an exemplary embodiment, forming the color filter layer 401 may include: as Figure 15A and Figure 15B shown, coating a red filter thin film on the substrate on which the foregoing structure is formed, and forming a red color filter unit 401R by a photolithography process; as Figure 15C and Figure 15D shown, coating a green filter thin film, and forming a green color filter unit 401G by a photolithography process; as Figure 15E and Figure 15F shown, coating a blue filter thin film, and forming a blue color filter unit 401B by a photolithography process. Here, the coating order of the color filter units is only an example, and the color filter layer may be formed in a manner different from the listed order.

[0213] In an exemplary embodiment, as Figures 15A to 15F shown, the red color filter unit 401R may be disposed in the first sub-pixel P1, the green color filter unit 401G may be disposed in the third sub-pixel P3, and the blue color filter unit 401B may be disposed in the fourth sub-pixel P4. Here, the embodiments of the present disclosure are not limited thereto.

[0214] In an exemplary embodiment, as Figures 15A to 15F shown, a first overlapping area exists between the orthographic projection of the red color filter unit 401R on the substrate and the orthographic projection of the light-shielding layer 23 on the substrate, a second overlapping area exists between the orthographic projection of the blue color filter unit 401B on the substrate and the orthographic projection of the corresponding light-shielding layer 23 on the substrate, and a third overlapping area exists between the orthographic projection of the green color filter unit 401G on the substrate and the orthographic projection of the light-shielding layer 23 on the substrate, and the first overlapping area is greater than the second overlapping area or the third overlapping area.

[0215] In an exemplary embodiment, as Figures 15A to 15B shown, at least partial overlap between the orthographic projection of the color filter layer 401 on the substrate and the orthographic projection of the gate electrode of the driving transistor (e.g., the second gate electrode 43) on the substrate may mean that at least partial overlap exists between the orthographic projection of the red color filter unit 401R on the substrate and the orthographic projection of the gate electrode of the driving transistor (e.g., the second gate electrode 43) on the substrate. Here, the embodiments of the present disclosure are not limited thereto.

[0216] In an exemplary embodiment, as Figures 15A to 15F shown, the second sub-pixel P2 is a white sub-pixel, and no color filter unit is provided in the white sub-pixel.

[0217] In an exemplary embodiment, the material of the color filter unit may be a negative photoresist. For example, a negative color photoresist (which may be simply referred to as color resist).

[0218] In an exemplary embodiment, the materials of the red filter film, the green filter film, and the blue filter film may adopt a negative photoresist. In this way, by utilizing the characteristic that the process deviation (CD) is relatively large during the exposure of the negative photoresist, it is possible to achieve at least partial overlap between the orthographic projection of the color filter unit on the substrate and the orthographic projection of the light-shielding layer on the substrate without adding a mask. Thus, it is possible to avoid light leakage of the sub-pixel, and further prevent the color unevenness problem caused by light leakage, and improve the quality of the display screen. Moreover, since no mask is added, it can be well compatible with the current manufacturing process, the process implementation is simple, easy to implement, has high production efficiency, low production cost, and high yield.

[0219] (10) Form a fifth insulating layer.

[0220] In an exemplary embodiment, forming the fifth insulating layer may include: depositing a fifth insulating thin film on the substrate on which the foregoing structure is formed, and patterning the fifth insulating thin film using a patterning process to form the fifth insulating layer covering the color filter unit. In an exemplary embodiment, the fifth insulating layer may be referred to as a planarization (PLN) layer or a resin layer.

[0221] In an exemplary embodiment, as Figure 16 shown, a plurality of vias are formed in the fifth insulating layer, and the plurality of vias may include: the thirty-first via V31 located in each sub-pixel. In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is within the range of the orthographic projection of the second connection electrode 55 on the substrate, and the orthographic projection of the twenty-first via V21 on the substrate is within the range of the orthographic projection of the thirty-first via V31 on the substrate. The fifth insulating layer and the fourth insulating layer within the thirty-first via V31 are removed to expose the surface of the second connection electrode 55. In an exemplary embodiment, the thirty-first via V31 is configured to enable the subsequently formed anode to be connected to the second connection electrode 55 through this via and the twenty-first via V21.

[0222] In an exemplary embodiment, the fifth insulating layer may be made of an organic material, such as resin, etc. It may be a single layer, a multi-layer or a composite layer.

[0223] Thus far, the color filter layer is fabricated on the driving circuit layer.

[0224] In an exemplary embodiment, after the driving circuit layer and the color filter layer are fabricated, a light-emitting structure layer is fabricated on the color filter layer, and the fabrication process of the light-emitting structure layer may include the following steps:

[0225] (11) Forming a fifth conductive layer.

[0226] In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on the substrate on which the foregoing structure is formed, and patterning the fifth conductive thin film using a patterning process to form the fifth conductive layer disposed on the planarization layer.

[0227] In an exemplary embodiment, the fifth conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), etc. It may be a single layer, a multi-layer or a composite layer. For example, taking the fifth conductive layer being formed of ITO as an example, the fifth conductive layer may be referred to as the second transparent (ITO2) layer.

[0228] In an exemplary embodiment, as Figure 17A and Figure 17BAs shown, the fifth conductive layer may include: anodes 301 located in each sub-pixel, and the anodes 301 in each sub-pixel are connected to the second connection electrode 55 through the twenty-first via V21. For example, a protrusion is provided on one side of the anode 301 in each sub-pixel in the first direction DR1, and the protrusion is connected to the second connection electrode 55 through the twenty-first via V21 and the thirty-first via V31. Thus, since the second connection electrode 55 serves as the second pole of the second transistor T2, the connection between the anode 301 and the second transistor T2 can be achieved.

[0229] In one exemplary embodiment, as Figure 17A and Figure 17B shown, the fifth conductive layer may include: a first anode 301R in the first sub-pixel P1, a second anode 301W in the second sub-pixel P2, a third anode 301G in the third sub-pixel P3, and a fourth anode 301B in the fourth sub-pixel P4.

[0230] In one exemplary embodiment, as Figure 17A and Figure 17B shown, the first anode 301R, the second anode 301W, the third anode 301G, and the fourth anode 301B may be in a strip shape extending along the first direction DR1.

[0231] In one exemplary embodiment, the orthographic projection of the anode in each sub-pixel on the substrate may include the orthographic projection of the storage capacitor C in the corresponding sub-pixel on the substrate.

[0232] (12) Form a pixel definition layer.

[0233] In one exemplary embodiment, forming the pixel definition layer may include: as Figure 18A and Figure 18B shown, coating a pixel definition film on the substrate on which the foregoing structure is formed, and patterning the pixel definition film by a patterning process to form the pixel definition layer 302. Wherein, the pixel definition layer 302 may at least include: pixel openings located in each sub-pixel.

[0234] In one exemplary embodiment, as Figure 18A and Figure 18B shown, the pixel definition layer 302 may include: a first pixel opening 302R that exposes the first anode 301R in the first sub-pixel P1, a second pixel opening 302W that exposes the second anode 301W in the second sub-pixel P2, a third pixel opening 302G that exposes the third anode 301G in the third sub-pixel P3, and a fourth pixel opening 302B that exposes the fourth anode 301B in the fourth sub-pixel P4. Here, the embodiments of the present disclosure do not make any limitations in this regard.

[0235] In an exemplary embodiment, the shapes and areas of the pixel apertures of different sub-pixels may be different. In the exemplary embodiment of the present disclosure, by designing four sub-pixels with different aperture ratios, the transmittance of the color filter layers of different sub-pixels can be adapted, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, maximizing the optimization of the lifespan of the four sub-pixel light-emitting devices and ensuring the product lifespan.

[0236] In an exemplary embodiment, as Figure 18A and Figure 18B shown, the pixel definition layer 302 may further include: a partition groove 302A. The shape of the partition groove 302A may be strip-shaped extending along the first direction DR1, and may be disposed between adjacent sub-pixels. The partition groove 302A is configured to reduce light leakage between adjacent sub-pixels.

[0237] In an exemplary embodiment, the pixel definition layer may be made of materials such as polyimide (PI), acrylic, or polyethylene terephthalate (PET). It may be a single layer, multiple layers, or a composite layer. Here, the embodiments of the present disclosure do not limit this.

[0238] In an exemplary embodiment, after preparing the pixel definition layer, the preparation process of the display substrate may further include: forming an organic light-emitting layer. The organic light-emitting layer is connected to the anode through the pixel aperture, and a cathode is formed on the organic light-emitting layer. The cathode is connected to the organic light-emitting layer.

[0239] In an exemplary embodiment, the organic light-emitting layer may be prepared by evaporation or inkjet printing processes. For example, the organic light-emitting layer may be prepared by evaporation using a fine metal mask (FMM), or by evaporation using an open mask, etc.

[0240] Thus far, the light-emitting structure layer is prepared on the color filter structure layer.

[0241] In an exemplary embodiment, the display substrate may further include: a packaging layer disposed on the side of the light-emitting structure layer 103 away from the substrate 101. For example, the packaging layer may include: a first packaging layer, a second packaging layer, and a third packaging layer stacked. For example, the first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second packaging layer may be disposed between the first packaging layer and the third packaging layer. In this way, it can be ensured that external moisture cannot enter the light-emitting structure layer 103.

[0242] In an exemplary embodiment, after preparing the light-emitting structure layer, the preparation process of the display substrate may further include: forming a packaging layer.

[0243] In an exemplary embodiment, as Figures 5 to 18BAs shown, the display substrate provided by the exemplary embodiment of the present disclosure may include:

[0244] A substrate 101;

[0245] A first conductive layer 502 disposed on the substrate 101, and the first conductive layer 502 may include: a first electrode plate 11;

[0246] A second conductive layer 503 disposed on the first conductive layer 502, and the second conductive layer 503 may include: a light-shielding layer 23;

[0247] A first insulating layer 201 covering the second conductive layer 503;

[0248] A metal oxide layer 501 disposed on the first insulating layer 201, and the metal oxide layer may include: a second electrode plate 34 and active layers of three transistors, and the second electrode plate 34 and the first electrode plate 11 form a transparent storage capacitor;

[0249] A second insulating layer 202 covering the metal oxide layer;

[0250] A third conductive layer disposed on the second insulating layer 202, and the third conductive layer may include: a first scan signal line 41, a second scan signal line 42, and gate electrodes of three transistors:

[0251] A third insulating layer 203 covering the third conductive layer, and a plurality of vias are formed in the third insulating layer 203;

[0252] A fourth conductive layer disposed on the third insulating layer 203, and the fourth conductive layer may include: a first power supply line VDD, a data signal line D, a compensation signal line Se, and the first and second poles of three transistors;

[0253] A fourth insulating layer 204 covering the fourth conductive layer, and a plurality of vias are formed in the fourth insulating layer 204;

[0254] A color filter layer 401 disposed on the fourth insulating layer 204;

[0255] A fifth insulating layer 205 covering the color filter unit 401, and a plurality of vias are formed in the fifth insulating layer 205;

[0256] A fifth conductive layer disposed on the fifth insulating layer 205, and the fifth conductive layer may include an anode 301;

[0257] A pixel definition layer 302 covering the fifth conductive layer, and a pixel opening exposing the anode 301 is formed in the pixel definition layer 302;

[0258] An organic light-emitting layer 303 disposed on the pixel definition layer 302, and the organic light-emitting layer 303 is connected to the anode 301 through the pixel opening;

[0259] The cathode 304 disposed on the organic light-emitting layer 303.

[0260] As can be seen from the above, the display substrate provided by the exemplary embodiments of the present disclosure, as Figure 6 and Figure 19 shown, by adopting the design that the orthographic projection of the color filter layer 401 on the substrate 101 overlaps with the orthographic projection of the light-shielding layer 23 on the substrate 101, in the Figure 19 area circled by the dotted line in, the white light generated by the organic light-emitting layer 303 of the sub-pixel (for example, the light indicated by the dotted line with an arrow as Figure 6 shown) leaks out from the edge of the color filter layer 401 through diffuse reflection or refraction of the cathode 304 and other film layers, and will be incident on the light-shielding layer 23, and thus, is blocked by the light-shielding layer 23. In this way, the problem of light leakage of the sub-pixel can be avoided, and further, the problem of color unevenness caused by light leakage can be avoided, and the display quality can be improved. By forming the first electrode plate 11 of the storage capacitor C with the transparent first conductive layer 502 and forming the second electrode plate 34 of the storage capacitor C with the transparent metal oxide layer 501, thus, since light can pass through the transparent storage capacitor C, the storage capacitor C can be disposed in the pixel opening opened in the pixel definition layer 302, the pixel aperture ratio can be increased, and the display quality can be improved.

[0261] The structures of the display substrate listed above and their manufacturing processes are merely exemplary descriptions. Those skilled in the art can change the corresponding structures and increase or decrease the patterning processes according to the actual situation. For example, a pixel unit may include three sub-pixels. Again, for example, the pixel driving circuit may adopt structures such as 5T1C or 7T1C. Here, the embodiments of the present disclosure do not make any limitations in this regard.

[0262] The exemplary embodiments of the present disclosure further provide a method for manufacturing a display substrate. The display substrate may be the display substrate in one or more of the above exemplary embodiments. The manufacturing method may include:

[0263] Step 1: Form a driving circuit layer on the substrate. The driving structure layer includes: a light-shielding layer located in the sub-pixel and a metal oxide layer disposed on a side of the light-shielding layer away from the substrate;

[0264] Step 2: Form a color filter layer on a side of the driving circuit layer away from the substrate. The overlapping area of the orthographic projection of the color filter layer on the substrate and the orthographic projection of the metal oxide layer on the substrate is larger than the overlapping area of the orthographic projection of the color filter layer on the substrate and the orthographic projection of the light-shielding layer on the substrate;

[0265] Step 3: Form a light-emitting structure layer on a side of the color filter layer away from the substrate.

[0266] In an exemplary embodiment, step 2 may include: coating a layer of negative photoresist on a side of the driving circuit layer away from the substrate to form a filter film; and processing the filter film through a photolithography process to form a color film layer.

[0267] As can be seen from the above, in the manufacturing method provided by the exemplary embodiment of the present disclosure, the design of the overlapping positive projections of the color film units on the substrate and the light-shielding layer on the substrate in the manufactured display substrate is such that the white light generated by the organic light-emitting layer of the sub-pixel leaks out from the edge of the color film unit through diffuse reflection or refraction by the cathode and other film layers and irradiates onto the light-shielding layer, and thus, is blocked by the light-shielding layer. In this way, the problem of light leakage of the sub-pixel can be avoided, and further, the problem of color unevenness caused by light leakage can be avoided, and the display quality can be improved.

[0268] The description of the above manufacturing method embodiments is similar to the description of the above display substrate embodiments and has similar beneficial effects to those of the display substrate embodiments. For the technical details not disclosed in the manufacturing method embodiments of the present disclosure, those skilled in the art can refer to the description in the display substrate embodiments of the present disclosure and will not be elaborated here.

[0269] The exemplary embodiment of the present disclosure further provides a display device. The display device may include: the display substrate in one or more of the above exemplary embodiments.

[0270] In an exemplary embodiment, the display substrate may include, but is not limited to: an OLED display substrate, a quantum-dot light-emitting diode (QLED) display substrate, a micro light-emitting diode (Micro LED) display substrate, or a mini light-emitting diode (Mini LED), etc. Here, the embodiments of the present disclosure do not make any limitations in this regard.

[0271] In an exemplary embodiment, the display device may include, but is not limited to: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator, etc. Here, the embodiments of the present disclosure do not make any limitations on the type of the display device. Other essential components of the display device are understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present disclosure.

[0272] The description of the above embodiments of the display device is similar to the description of the above embodiments of the display substrate, and has beneficial effects similar to those of the embodiments of the display substrate. For the technical details not disclosed in the embodiments of the display device of the present disclosure, those skilled in the art may refer to the description in the embodiments of the display substrate of the present disclosure for understanding, and will not be elaborated here.

[0273] Although the embodiments disclosed in the present disclosure are as above, the above content is only an embodiment adopted for the convenience of understanding the present disclosure, and is not used to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present disclosure. However, the scope of patent protection of the present disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, Including: a substrate, a driving circuit layer disposed on the substrate, a color filter layer disposed on a side of the driving circuit layer away from the substrate, and a light-emitting structure layer disposed on a side of the color filter layer away from the substrate; wherein, the driving circuit layer includes: a light-shielding layer in a sub-pixel and a metal oxide layer disposed on a side of the light-shielding layer away from the substrate, and an overlapping area of a positive projection of the color filter layer on the substrate and a positive projection of the metal oxide layer on the substrate is greater than an overlapping area of the positive projection of the color filter layer on the substrate and a positive projection of the light-shielding layer on the substrate; the overlapping area of the positive projection of the color filter layer on the substrate and the positive projection of the light-shielding layer on the substrate is not zero; the color filter layer includes: a red color filter unit, a blue color filter unit, and a green color filter unit, a first overlapping area exists between a positive projection of the red color filter unit on the substrate and a positive projection of the light-shielding layer on the substrate, a second overlapping area exists between a positive projection of the blue color filter unit on the substrate and a positive projection of the light-shielding layer on the substrate, a third overlapping area exists between a positive projection of the green color filter unit on the substrate and a positive projection of the light-shielding layer on the substrate, and the first overlapping area is greater than the second overlapping area or the third overlapping area.

2. The display substrate according to claim 1, characterized in that, Further including: a pixel driving circuit in a sub-pixel, the pixel driving circuit includes: a driving transistor, and at least a part of a positive projection of the color filter layer on the substrate overlaps with a positive projection of a gate electrode of the driving transistor on the substrate.

3. The display substrate according to claim 1, wherein Further including: a pixel driving circuit in a sub-pixel, the pixel driving circuit includes: a storage capacitor, and the driving circuit layer further includes: a first conductive layer disposed on a side of the light-shielding layer close to the substrate, the first conductive layer includes a first electrode plate, the metal oxide layer includes a second electrode plate, and at least a part of a positive projection of the second electrode plate on the substrate overlaps with a positive projection of the first electrode plate on the substrate to form the storage capacitor.

4. The display substrate according to claim 3, wherein, The light-emitting structure layer includes: a pixel definition layer, a pixel opening defining a light-emitting area is disposed on the pixel definition layer, at least a part of a positive projection of the first electrode plate on the substrate overlaps with a positive projection of the pixel opening on the substrate, and at least a part of a positive projection of the second electrode plate on the substrate overlaps with a positive projection of the pixel opening on the substrate.

5. The display substrate according to claim 3, wherein A positive projection of the light-shielding layer on the substrate and a positive projection of the second electrode plate on the substrate are spaced apart.

6. The display substrate according to claim 3, wherein The light-shielding layer is provided with a light-shielding opening, and the light-shielding opening is configured to expose a surface of the first electrode plate.

7. The display substrate according to claim 6, wherein The pixel driving circuit further includes: a first transistor, a second transistor, and a third transistor, a second region of an active layer of the first transistor is connected to the second electrode plate, a second region of an active layer of the second transistor is connected to the first electrode plate through the light-shielding opening, a second region of an active layer of the third transistor is connected to the first electrode plate, and the second transistor is a driving transistor.

8. The display substrate according to claim 7, wherein A positive projection of an active layer of the second transistor on the substrate is located within a range of a positive projection of the light-shielding layer on the substrate.

9. The display substrate according to claim 7, wherein The positive projection of the second region of the active layer of the first transistor on the substrate at least partially overlaps with the positive projection of the light-shielding layer on the substrate.

10. The display substrate according to claim 7, wherein The active layer of the first transistor and the second electrode plate are integrally connected.

11. The display substrate according to claim 7, wherein The positive projection of the active layer of the third transistor on the substrate is spaced from the positive projection of the light-shielding layer on the substrate, and the positive projection of the active layer of the third transistor on the substrate is spaced from the positive projection of the second electrode plate on the substrate.

12. The display substrate according to claim 3, wherein, The first electrode plate and the second electrode plate are made of a transparent conductive material.

13. The display substrate according to claim 1, wherein The light-shielding layer includes: a first side, a second side, a third side, and a fourth side. The first side and the third side are oppositely arranged and extend along the second direction. The second side and the fourth side are oppositely arranged and extend along the first direction. The first end of the first side is connected to the first end of the second side. The second end of the first side is connected to the first end of the fourth side. The second end of the second side is connected to the first end of the third side. The second end of the third side is connected to the second end of the fourth side. The positive projection of the first side on the substrate is within the range of the overlapping region between the positive projection of the color filter layer on the substrate and the positive projection of the light-shielding layer on the substrate. The first direction intersects with the second direction.

14. The display substrate according to claim 13, wherein One or more of the first side, the second side, the third side, and the fourth side are in a polygonal shape.

15. The display substrate according to claim 1, characterized in that, The width of the overlapping region between the positive projection of the color filter layer on the substrate and the positive projection of the light-shielding layer on the substrate in the first direction is 5 micrometers to 350 micrometers.

16. The display substrate according to claim 1, wherein, Further comprising: A pixel driving circuit located in the sub-pixel. The pixel driving circuit includes: a first transistor, a second transistor, a third transistor, and a storage capacitor; In a direction perpendicular to the display substrate, the driving circuit layer includes: a first conductive layer, a second conductive layer, the metal oxide layer, a third conductive layer, and a fourth conductive layer sequentially arranged on the substrate. The first electrode plate of the storage capacitor is located on the first conductive layer. The light-shielding layer is located on the second conductive layer. The second electrode plate of the storage capacitor, the active layer of the first transistor, the active layer of the second transistor, and the active layer of the third transistor are located on the metal oxide layer. The gate electrodes of the first transistor, the second transistor, and the third transistor are located on the third conductive layer. The first pole of the first transistor, the second pole of the first transistor, the first pole of the second transistor, the second pole of the second transistor, the first pole of the third transistor, and the second pole of the third transistor are located on the fourth conductive layer.

17. The display substrate according to claim 16, wherein, The driving circuit layer further includes: a first scan signal line, a second scan signal line, a first power supply line, a data signal line, and a compensation signal line. The first scan signal line and the second scan signal line are located on the third conductive layer. The first power supply line, the data signal line, and the compensation signal line are located on the fourth conductive layer.

18. The display substrate according to claim 1, wherein, The driving circuit layer further includes: a first power line and a compensation signal line extending in a first direction. The display substrate further includes: a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel that are sequentially arranged along a second direction and have different colors. The second sub-pixel is a white sub-pixel. The first sub-pixel and the second sub-pixel are controlled by one first power line, and the third sub-pixel and the fourth sub-pixel are controlled by another first power line. Moreover, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are controlled by one compensation signal line.

19. A display device, characterized in that, Comprising: The display substrate according to any one of claims 1 to 18.

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