Integrated chip for non-invasive blood glucose detection, its fabrication method and wearable device

Abstract

This application discloses an integrated chip for non-invasive blood glucose detection, its fabrication method, and a wearable device. The technical solution of this application integrates an optical transmission component, multiple light source chips with different emission bands, and multiple detectors for detecting different bands into a single chip, forming a monolithic hybrid integrated chip. This technical solution, through multiple light source chips with different emission bands and multiple detectors for detecting different bands, can achieve broadband blood glucose parameter detection, improving resolution and testing accuracy. By arranging the transmission component within the chip, an in-chip transmission optical path design is achieved. Furthermore, single-chip integration can be achieved based on a hybrid integration process of the optical transmission component, light source component, and optical detection component using the same SOI (Single Integrator of Optical Indicators), facilitating device miniaturization and reducing device size and power consumption, making it suitable for the miniaturization and low-power design requirements of wearable devices.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to an integrated chip for non-invasive blood glucose detection, a method for manufacturing the same, and a wearable device thereof. Background Technology

[0002] Blood glucose testing devices can be divided into two categories in terms of usage: the first category is invasive blood glucose testing devices. These devices require the collection of a certain amount of blood when measuring human blood glucose levels. The operation is unchanged, and it can cause certain psychological stress to the person being tested, and it also carries the risk of infection. The second category is non-invasive blood glucose testing devices. These devices determine blood glucose levels by measuring the absorption of specific wavelengths of light by glycosylation in the human body.

[0003] Compared to invasive blood glucose testing devices, non-invasive blood glucose testing devices offer advantages such as safety, ease of operation, and real-time result display, making them the main development direction for blood glucose testing equipment. Currently, non-invasive blood glucose testing devices generally use LEDs as the detection light source, based on visible light spectral analysis to detect blood glucose parameters. However, due to the narrow range of available spectral wavelengths, the resolution of the test results is low, and the data accuracy is insufficient. Summary of the Invention

[0004] In view of this, this application provides an integrated chip for non-invasive blood glucose detection, a method for fabricating the same, and a wearable device, as follows:

[0005] A method for fabricating an integrated chip for non-invasive blood glucose detection, the method comprising:

[0006] A semiconductor substrate is provided, the surface of which has a first insulating layer and a first film layer located on the surface of the first insulating layer facing away from the semiconductor substrate;

[0007] The first film layer is patterned to form a first functional layer, the first functional layer including: an optical modulation component, a first waveguide and an optical detection component;

[0008] A second functional layer is formed on the side of the first film layer away from the semiconductor substrate, and the second functional layer includes: a second waveguide;

[0009] A light source assembly is formed and coupled to an optical transmission component, the optical transmission component including a first waveguide and a second waveguide;

[0010] The optical modulation component and the optical detection component both include doped active structures; the light source component includes multiple light source chips with different emission wavelengths; the optical detection component includes multiple detectors for detecting different wavelengths; and the semiconductor substrate has an output port structure for emitting detection light and collecting reflected detection light.

[0011] Preferably, in the above manufacturing method, the method for forming the first functional layer includes:

[0012] A second insulating layer and a third insulating layer are sequentially formed on the side of the first film layer facing away from the semiconductor substrate;

[0013] The second insulating layer and the third insulating layer are graphically represented;

[0014] Based on the patterned second and third insulating layers, the first film layer is etched to form the first functional layer; wherein, the first functional layer includes multiple waveguide structures with different etching depths to form the first waveguide, the optical modulation component, and the optical detection component;

[0015] A planarized fourth insulating layer is formed on the side of the first insulating layer opposite to the semiconductor substrate, the fourth insulating layer covering the first functional layer.

[0016] Preferably, in the above manufacturing method, the photodetector component includes a MOS capacitor-type photoelectric modulator;

[0017] Before forming the second functional layer, it also includes:

[0018] Remove the third insulating layer to expose the second insulating layer;

[0019] The active structure of the MOS capacitor-type optoelectronic modulator is doped.

[0020] Preferably, in the above manufacturing method, the surface of the first functional layer facing away from the semiconductor substrate has a second insulating layer;

[0021] The method for forming the second functional layer includes:

[0022] A patterned first polysilicon layer is formed on the surface of the second insulating layer away from the first functional layer, the first polysilicon layer including: a window sacrificial layer;

[0023] A fifth insulating layer and a second film layer are sequentially formed on the side of the first polysilicon layer opposite to the first functional layer;

[0024] The second film layer is patterned to form the second functional layer;

[0025] The window sacrificial layer is used to form the ion implantation window of the active structure in the first functional layer.

[0026] Preferably, in the above manufacturing method, the photodetector component includes a MOS capacitor-type photoelectric modulator;

[0027] The first polysilicon layer also includes the gate of the MOS capacitive optoelectronic modulator.

[0028] Preferably, in the above manufacturing method, a patterned first polysilicon layer is provided between the first functional layer and the second functional layer, the first polysilicon layer including: a window sacrificial layer;

[0029] The method for forming the active structure includes:

[0030] An ion implantation window is formed in the insulating layer of the window sacrificial layer away from the first functional layer, and the ion implantation window exposes the window sacrificial layer.

[0031] Remove the window sacrificial layer based on the ion implantation window;

[0032] After removing the window sacrificial layer, ion implantation is performed based on the ion implantation window to dope the active structure below the ion implantation window.

[0033] Preferably, in the above manufacturing method, a patterned first polysilicon layer is provided between the first functional layer and the second functional layer, the first polysilicon layer including: a first coupling sacrificial layer; a second coupling sacrificial layer is provided on the side of the second functional layer opposite to the first functional layer; and a top insulating layer is provided on the side of the second coupling sacrificial layer opposite to the second functional layer.

[0034] The method for coupling the light source component to the transmission component includes:

[0035] A first trench is formed based on the first coupling sacrificial layer, and the first coupling sacrificial layer is removed. The first trench is located above the first waveguide and is used to fix the first light source chip.

[0036] A second trench is formed based on the second coupling sacrificial layer, and the second coupling sacrificial layer is removed. The second trench is located above the second waveguide and is used to fix the second light source chip.

[0037] The first light source chip and the second light source chip emit light in different wavelengths.

[0038] Preferably, in the above manufacturing method, the first functional layer further includes a grating; the second functional layer has a top insulating layer on the side opposite to the second functional layer; and an extended light source component can be disposed on the area of ​​the surface of the top insulating layer opposite to the grating.

[0039] Preferably, in the above manufacturing method, the side of the first functional layer facing away from the semiconductor substrate has an insulating layer, and the second functional layer is located between the two insulating layers;

[0040] The manufacturing method further includes: forming a first wiring layer and a second wiring layer;

[0041] The first wiring layer is located between two adjacent insulating layers and includes multiple first signal lines; the photodetector and the photomodulation components are respectively connected to the corresponding first signal lines through vias; the second wiring layer is located on the side of the top insulating layer away from the second functional layer and includes multiple second signal lines; the second signal lines are connected to the first signal lines through vias, and the second signal lines are used to connect to external circuits.

[0042] This application also provides an integrated chip for non-invasive blood glucose detection, comprising:

[0043] Semiconductor substrate;

[0044] The first insulating layer located on the surface of the semiconductor substrate;

[0045] A first functional layer located on the surface of the first insulating layer opposite to the semiconductor substrate, the first functional layer comprising: an optical modulation component, a first waveguide, and an optical detection component;

[0046] A second functional layer located on the side of the first functional layer opposite to the semiconductor substrate, the second functional layer comprising: a second waveguide;

[0047] A light source component coupled to an optical transmission component;

[0048] The optical modulation component and the optical detection component both include doped active structures; the light source component includes multiple light source chips with different emission wavelengths; the optical detection component includes multiple detectors for detecting different wavelengths; and the semiconductor substrate has an output port structure for emitting detection light and collecting reflected detection light.

[0049] Preferably, in the above-mentioned integrated chip, the light source component includes: a visible light source chip and an infrared light source chip; the light detection component includes: a visible light detector and an infrared light detector.

[0050] Preferably, in the above-mentioned integrated chip, the optical modulation component includes: a MOS capacitor-type optoelectronic modulator;

[0051] A first polysilicon layer is provided between the first functional layer and the second functional layer, and the first polysilicon layer includes the gate of the MOS capacitive optoelectronic modulator;

[0052] The first polysilicon layer is also used to form an ion implantation window for the active structure in the first functional layer.

[0053] Preferably, in the above-mentioned integrated chip, the optical modulation component further includes an MZM type optoelectronic modulator.

[0054] Preferably, in the above-mentioned integrated chip, the first functional layer is a single-crystal silicon layer, and the first waveguide is a silicon waveguide;

[0055] The second functional layer is a silicon nitride layer, and the second waveguide is a silicon nitride waveguide.

[0056] Preferably, in the above-mentioned integrated chip, the second functional layer has a top insulating layer on the side opposite to the first functional layer, and the surface of the top insulating layer has a first trench and a second trench; the first trench is used to fix the first light source chip, and the first light source chip is coupled to the first waveguide below the first trench; the second trench is used to fix the second light source chip, and the second light source chip is coupled to the second waveguide below the second trench.

[0057] Preferably, in the above-mentioned integrated chip, the first functional layer further includes a grating; the second functional layer has a top insulating layer on the side opposite to the first functional layer; the light source assembly is disposed on the top insulating layer; and an extended light source component can be disposed on the area of ​​the surface of the top insulating layer opposite to the grating.

[0058] Preferably, in the above-mentioned integrated chip, the side of the first functional layer facing away from the semiconductor substrate has multiple insulating layers, and the second functional layer is located between the two insulating layers;

[0059] The integrated chip further includes a first wiring layer and a second wiring layer; the first wiring layer is located between two adjacent insulating layers and includes multiple first signal lines; the photodetector and the photomodulation components are respectively connected to the corresponding first signal lines through vias; the second wiring layer is located on the surface of the outermost insulating layer away from the second functional layer and includes multiple second signal lines; the second signal lines are connected to the first signal lines through vias, and the second signal lines are used to connect to external circuits.

[0060] This application also provides a wearable device, including:

[0061] A circuit board, wherein an electrical chip is connected to the circuit board;

[0062] The integrated chip described in any of the above embodiments is fixed on the circuit board and connected to the electrical chip;

[0063] The electrical chip is used to determine the biometric parameters of the target based on the detection signal generated by the light detection component, wherein the biometric parameters include at least blood glucose parameters.

[0064] As described above, the integrated chip, its fabrication method, and wearable device for non-invasive blood glucose detection provided by this application integrate an optical transmission component, multiple light source chips with different emission bands, and multiple detectors for detecting different bands into a single chip, forming a monolithic hybrid integrated chip. This application's technical solution, through multiple light source chips with different emission bands and multiple detectors for detecting different bands, enables broadband blood glucose parameter detection, improving resolution and testing accuracy. By arranging the transmission component within the chip, an in-chip transmission optical path design is achieved. Furthermore, single-chip integration can be achieved using a hybrid integration process of the optical transmission component, light source component, and optical detection component based on the same SOI (Silicon-On-Insulator) substrate, facilitating device miniaturization and reducing device size and power consumption, making it suitable for the miniaturization and low-power design requirements of wearable devices. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0066] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0067] Figures 1-27 A process flow diagram of a manufacturing method provided in an embodiment of this application;

[0068] Figure 28 A schematic diagram of the structure of an integrated chip for non-invasive blood glucose detection provided in an embodiment of this application;

[0069] Figure 29 This is a schematic diagram of the structure of a wearable device provided in an embodiment of this application. Detailed Implementation

[0070] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0071] As described in the background section, conventional non-invasive blood glucose testing devices generally use LEDs as the detection light source and detect blood glucose parameters based on visible light spectral analysis. However, due to the narrow range of available spectral wavelengths, the resolution of the detection results is low and the data accuracy is insufficient.

[0072] In view of this, embodiments of this application provide an integrated chip for non-invasive blood glucose detection, a method for manufacturing the same, and a wearable device, wherein the manufacturing method includes:

[0073] A semiconductor substrate is provided, the surface of which has a first insulating layer and a first film layer located on the surface of the first insulating layer facing away from the semiconductor substrate;

[0074] The first film layer is patterned to form a first functional layer, the first functional layer including: an optical modulation component, a first waveguide and an optical detection component;

[0075] A second functional layer is formed on the side of the first film layer away from the semiconductor substrate, and the second functional layer includes: a second waveguide;

[0076] A light source assembly is formed and coupled to an optical transmission component, the optical transmission component including a first waveguide and a second waveguide;

[0077] The optical modulation component and the optical detection component both include doped active structures; the light source component includes multiple light source chips with different emission wavelengths; the optical detection component includes multiple detectors for detecting different wavelengths; and the semiconductor substrate has an output port structure for emitting detection light and collecting reflected detection light.

[0078] The technical solution of this application can achieve broadband blood glucose parameter detection by using different light source chips with multiple emission bands and multiple detectors for detecting different bands, thereby improving resolution and test accuracy. By laying out the transmission components within the chip, the transmission optical path design within the chip is realized. Moreover, the optical transmission components, light source components and optical detection components can be integrated into a single chip based on the same SOI, which facilitates device miniaturization, reduces device size and power consumption, and is suitable for the miniaturization and low power consumption design requirements of wearable devices.

[0079] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0080] like Figures 1-27 As shown, Figures 1-27 This application provides a process flow diagram of a fabrication method for preparing an integrated chip suitable for non-invasive blood glucose detection. The fabrication method includes:

[0081] Step S11: As Figure 1 As shown, a semiconductor substrate 100 is provided, the surface of which has a first insulating layer 101 and a first film layer 102 located on the surface of the first insulating layer 101 opposite to the semiconductor substrate 100.

[0082] In this embodiment of the application, the integrated chip is fabricated directly using an SOI wafer. The first insulating layer 101 is silicon oxide with a thickness ranging from 1μm to 3μm, and the first film layer 102 is monocrystalline silicon with a thickness ranging from 150nm to 500nm.

[0083] Step S12: As Figures 2-6 As shown, the first film layer 102 is patterned to form a first functional layer, which includes an optical modulation component, a first waveguide, and an optical detection component.

[0084] In step S12, the method for forming the first functional layer includes:

[0085] First, such as Figure 2 As shown, a second insulating layer 103 and a third insulating layer 104 are sequentially formed on the side of the first film layer 102 facing away from the semiconductor substrate 100.

[0086] A thermal oxide layer, with a thickness of 5 nm to 50 nm, can be grown on the surface of the first film layer 102 to serve as the second insulating layer 103. A SiN layer, with a thickness of 10 nm to 200 nm, can then be deposited on the surface of the second insulating layer 103 using a deposition process such as LPCVD. In this embodiment, all oxide layers are silicon oxide.

[0087] Then, as Figure 3 As shown, the second insulating layer 103 and the third insulating layer 104 are patterned. A photoresist layer can be formed on the surface of the third insulating layer 104 using a photolithography process. After patterning the photoresist based on a mask, the second insulating layer 103 and the third insulating layer 104 are etched based on the photoresist.

[0088] For example Figure 4 As shown, based on the patterned second insulating layer 103 and the third insulating layer 104, the first film layer 102 is etched to form the first functional layer; wherein, the first functional layer includes multiple waveguide structures with different etching depths to form the first waveguide, the optical modulation component and the optical detection component.

[0089] like Figure 5 As shown, Figure 5 This is a schematic diagram illustrating the etching principle of the first film layer 102 provided in an embodiment of this application. Figure 5 In the figure, (a) shows a shallowly etched waveguide structure, (b) shows a deeply etched waveguide unit, and (c) shows a fully etched waveguide unit. By etching three different waveguide structures with different etching depths on the first film layer 102, various optical chip structures can be constructed using the same first film layer 102, including but not limited to those used to fabricate optical detection components, optical modulation components, and first waveguides.

[0090] Finally, as Figure 6 and Figure 7 As shown, a planarized fourth insulating layer 105 is formed on the side of the first insulating layer opposite to the semiconductor substrate, and the fourth insulating layer 105 covers the first functional layer. Specifically, as... Figure 6 As shown, an oxide layer is formed as the fourth insulating layer 105 in the first functional layer using deposition processes such as CVD. The waveguide units etched in the first film layer 102 can be sidewall oxidized before the fourth insulating layer 105 is deposited and filled. Figure 7 As shown, the fourth insulating layer 105 is planarized by CMP process, so that the surface of the fourth insulating layer 105 is flush with the surface of the third insulating layer 104.

[0091] Step S13: As Figures 8-17As shown, a second functional layer is formed on the side of the first film layer away from the semiconductor substrate, and the second functional layer includes: a second waveguide;

[0092] like Figure 8 and Figure 9 As shown, the photodetector assembly includes a MOS capacitor-type photoelectric modulator 1021; before forming the second functional layer, it further includes: first as shown in the figure Figure 8 As shown, the third insulating layer 104 is removed, exposing the second insulating layer 103; and so on. Figure 9 As shown, the active structure of the MOS capacitive optoelectronic modulator 1021 is doped. When a SiN layer is used as the third insulating layer 104, the third insulating layer 104 can be removed using dry etching and hot phosphoric acid etching cleaning processes.

[0093] As described above, the surface of the first functional layer facing away from the semiconductor substrate 100 has a second insulating layer 103; in step S13, the method for forming the second functional layer includes:

[0094] Step S21: As Figures 10-13 As shown, a patterned first polysilicon layer 106 is formed on the surface of the second insulating layer 103 opposite to the first functional layer. The first polysilicon layer 106 includes a window sacrificial layer 1061.

[0095] Before forming the first polysilicon layer 106, the fourth insulating layer 105 can be planarized so that the surfaces of the fourth insulating layer 105 and the second insulating layer 103 are flush.

[0096] Specifically, for example Figure 10 As shown, Figure 10 As shown, a first polysilicon layer 106 is formed on the surface of the third insulating layer 105, and then... Figure 11 and Figure 12 As shown, mask 107 is used to etch the first polysilicon layer, patterning the first polysilicon layer 106, while retaining the undoped first polysilicon layer above the active structure as a window sacrificial layer 1061. Finally, as... Figure 13 As shown, after removing the mask 107, an oxide layer 108 is filled in the etched area of ​​the first polysilicon layer 106 and planarized so that the oxide layer 108 is flush with the first polysilicon layer 106. The oxide layer 108 can be formed by CVD process and planarized by CMP process.

[0097] In the subsequent ion implantation process, the window sacrificial layer 1061 is used to form the ion implantation window of the active structure in the first functional layer.

[0098] The first polysilicon layer 106, with a thickness of 20nm-300nm, can be formed using LPCVD technology. The etched first polysilicon layer 106 includes: a window sacrificial layer 1061, a gate 1062 of the MOS capacitive optoelectronic modulator 1021, and a first coupling sacrificial layer 1063. The first polysilicon layer 106 is also deposited on the back side of the semiconductor substrate 100, and needs to be removed from the back side of the semiconductor substrate 100.

[0099] Step S22: As Figure 14 and Figure 15 As shown, a fifth insulating layer 109 and a second film layer 110 are sequentially formed on the side of the first polysilicon layer 106 opposite to the first functional layer.

[0100] First, such as Figure 14 As shown, another oxide layer, serving as the fifth insulating layer 109, can be formed on the surface of the first polysilicon layer 106 and the oxide layer 108 using a CVD process. The fifth insulating layer 109 is a high-temperature thermal oxide layer with a dense film. During the subsequent high-temperature annealing process for forming the second waveguide, and in subsequent active processes such as silicide processing and Ge epitaxial processing, it can act as a good barrier layer against contamination diffusion, preventing diffusion into the SOI waveguide structure (i.e., the waveguide structure of the first functional layer) and avoiding the degradation of transmission loss in the SOI waveguide structure due to diffusion. The thickness of the fifth insulating layer 109 is 10nm-300nm.

[0101] For example Figure 15 As shown, a silicon nitride waveguide layer is formed on the surface of the fifth insulating layer 109 as the second film layer 110 using PECVD or LPCVD processes. The thickness of the silicon nitride waveguide layer is 100nm-1000nm. During the formation of the silicon nitride waveguide layer, it can be grown in segments multiple times, resulting in a second film layer comprising multiple stacked sub-film layers. This reduces film layer stress, increases film layer thickness, and improves the uniformity of RI (refractive index parameter) distribution. After forming the silicon nitride waveguide layer, it undergoes furnace annealing at a temperature of 800°C-1200°C to remove and reduce Si-H and NH bonds in the silicon nitride waveguide layer during the deposition process, thereby reducing the transmission loss of the silicon nitride waveguide layer. The annealing time ranges from 0.5 hours to several hours and can be performed in multiple stages.

[0102] Step S23: As Figure 16 As shown, the second film layer 110 is graphically represented to form the second functional layer.

[0103] The second film layer 110 can be patterned using photolithography to form the second waveguide with the desired pattern structure. Annealing of the silicon nitride waveguide layer can be performed before or after patterning the second film layer 110. The mechanism for reducing transmission loss is the same whether annealing is performed after etching or before etching the silicon nitride waveguide layer.

[0104] Optionally, the second functional layer includes multiple second waveguides with different etching depths. For example, the second functional layer can be configured to include a partially etched second waveguide WG1 and a fully etched second waveguide WG2. The partially etched second waveguide WG1 is set to a thickness of 150nm-250nm to form good single-mode conditions for visible light, thus enabling subsequent spectral analysis in the visible light band. The fully etched second waveguide WG2 can form good single-mode conditions for the near-infrared NIR and mid-infrared MIR bands of infrared light, thus enabling subsequent spectral analysis in the near-infrared NIR and mid-infrared MIR bands of infrared light. In particular, the dry etching process of the silicon nitride waveguide layer will result in a certain amount of over-etching of the underlying oxide layer. Since the etching gas of SiN material has a very low etching ratio to polysilicon, the first polysilicon layer can also serve as an etching protection layer for the silicon nitride waveguide layer, preventing damage to the underlying critical SOI waveguide structure during the etching process of the silicon nitride waveguide layer.

[0105] Step S14: As Figures 17-27 As shown, a light source assembly is formed and coupled to an optical transmission component, the optical transmission component including a first waveguide and a second waveguide, forming as shown... Figure 27 The chip structure shown.

[0106] The optical modulation component and the optical detection component both include doped active structures; the light source component includes multiple light source chips with different emission wavelengths; the optical detection component includes multiple detectors for detecting different wavelengths; and the semiconductor substrate has an output port structure for emitting detection light and collecting reflected detection light.

[0107] As described above, a patterned first polysilicon layer 106 is provided between the first functional layer and the second functional layer. The photodetector component includes a MOS capacitive photoelectric modulator 1021. The first polysilicon layer 106 also includes a gate 1062 of the MOS capacitive photoelectric modulator 1021. The first polysilicon layer 106 includes a 1061 window sacrificial layer. Based on this, the method for forming the active structure includes:

[0108] Step S31: As Figures 17-20 As shown, an ion implantation window K is formed in the insulating layer on the side of the window sacrificial layer 1061 opposite to the first functional layer, and the ion implantation window K exposes the window sacrificial layer 1061.

[0109] Specifically, firstly, as shown in Figure 17, a planarized sixth insulating layer 111 is formed on the side of the second functional layer opposite to the first functional layer.

[0110] An oxide layer is formed using CVD process as the sixth insulating layer 111. The sixth insulating layer 111 covers the second waveguide and fills the hollow area between the second functional layers. The sixth insulating layer 111 is then planarized using CMP process. After planarization, the minimum distance between the second functional layer and the sixth insulating layer is 50nm-500nm.

[0111] For example Figure 18 As shown in the embodiment of this application, the fabrication method further includes: forming a patterned second polysilicon layer 112 on the planarized surface of the sixth insulating layer 111, which serves as an etching barrier layer for forming trenches for placing the light source component in subsequent processes. The thickness of the second polysilicon layer 112 is 20nm-300nm, and the second polysilicon layer 112 with the desired pattern structure is formed by photolithography.

[0112] The patterned second polysilicon layer 112 can serve as a deep etching barrier layer to open the thicker oxide layer above the waveguide in subsequent processes, forming deep trenches to facilitate the placement of light source chips in the light source assembly. The light source chips include compound light source chips, such as visible or infrared light source chips based on III-V InP semiconductor lasers (LDs), VCSELs (vertical cavity surface-emitting lasers), or GaSb mid-infrared light source chips, to construct a monolithic integration of visible / infrared / mid-infrared light sources.

[0113] It should be noted that in other methods, the second polysilicon layer 112 may not be set, and the etching depth of the deep trench can be controlled by controlling parameters such as etching rate.

[0114] For example Figure 19 As shown, an oxide layer 113 is formed covering the sixth insulating layer 111 and the second polysilicon layer 112. The oxide layer 113 can be formed by a deposition process.

[0115] For example Figure 20As shown, an ion implantation window K is formed to expose the window sacrificial layer 1061 through an etching process. The insulating layer above the window sacrificial layer 1061 can be removed by photolithography and dry etching. When using the dry ion etching process in CMOS technology, a very high etching selectivity ratio can be achieved between the oxide layer and polysilicon. When etching the oxide layer above the window sacrificial layer 1061, an etching gas (including CF4 and / or CHF3) with a high oxide / polysilicon selectivity ratio and an etching process are selected to etch away the oxide layer above the window sacrificial layer 1061. The etching stops at the window sacrificial layer 1061, and this etching process results in a certain amount of etching on the window sacrificial layer 1061.

[0116] Step S32: As Figure 21 As shown, the window sacrificial layer 1061 is removed based on the ion implantation window K.

[0117] When etching away the window sacrificial layer 1061, an etching gas (including HBr) and etching process with a high selectivity ratio for the polysilicon / oxide layer are selected to etch away the remaining window sacrificial layer 1061.

[0118] Step S33: As Figure 22 As shown, after removing the window sacrificial layer 1061, ion implantation is performed based on the ion implantation window K to dope the active structure below the ion implantation window K.

[0119] The technical solution of this application forms an ion implantation window K through the first polysilicon layer 106, so as to complete the process integration scheme for active structure ion implantation in SOI waveguide structure.

[0120] The optical detection component includes an MZM (Mach-Zehnder) type photoelectric modulator 1022. The optical detection component also includes a visible light detector 1023 and an infrared light detector 1024. Figure 22 For ease of illustration, the visible light detector 1023 and the MZM-type optoelectronic modulator 1022 are shown based on the same waveguide structure. Clearly, the positions of the detector and modulator can be arranged based on the waveguide structure layout requirements in the first functional layer, and are not limited to... Figure 22 As shown.

[0121] The visible light detector 1023 includes a silicon PN junction photodiode and / or a silicon avalanche photodiode (APD). The infrared light detector 1024 can be a Ge photodiode (PD).

[0122] Based on the ion implantation window K, during ion implantation, ion implantation is performed on the active structures corresponding to the MZM type photoelectric modulator 1022, visible light detector 1023 and infrared light detector 1024 located below the ion implantation window K, so as to achieve doping of the corresponding active structures.

[0123] In this application's technical solution, the first polysilicon layer 106 can be reused as an etching barrier layer to form the ion implantation window K etch barrier insulating layer, ensuring etching quality. A high etching selectivity can be achieved using the oxide layer and polysilicon. By sequentially removing the oxide layer above the window sacrificial layer 1061 and the window sacrificial layer 1061 through dry ion etching, the etching stop position can be accurately controlled, ensuring etching quality.

[0124] Based on the ion implantation window K, after ion implantation is completed, the fabrication method further includes: forming an epitaxial growth layer for the infrared photodetector 1024. Specifically, as follows... Figure 23 As shown, the patterned active structure of the infrared photodetector 1024 is doped, and a groove C is formed on the active structure of the infrared photodetector 1024 doped. Figure 24 As shown, an epitaxial growth layer 114 for an infrared photodetector 1024 is formed within the groove C. When the infrared photodetector 1024 can be a Ge photodiode, its epitaxial growth layer is a Ge layer. Before forming the groove C, an oxide layer with a thickness of 10nm-300nm is deposited on the surface of the second insulating layer 103 exposed at the bottom of the ion implantation window. This oxide layer increases the thickness of the insulating layer above the active structure of the infrared photodetector 1024, preventing the epitaxial growth layer 114 outside the groove C from diffusing downwards and affecting the SOI waveguide structure below.

[0125] After forming the epitaxial growth layer 114 of the infrared photodetector 1024, an oxide layer is formed to fill the ion implantation window K. This oxide layer covers the insulating layer (the aforementioned oxide layer 113) outside the ion implantation window K. Then, the oxide layer on the chip surface is planarized using a CMP process.

[0126] After completing the ion implantation window K-filling and planarization process, a multilayer metal interconnect of the chip is formed. Specifically, the first functional layer has an insulating layer on the side facing away from the semiconductor substrate, and the second functional layer is located between two insulating layers; as shown... Figure 25As shown, the fabrication method further includes forming a first wiring layer 116 and a second wiring layer 117. The first wiring layer 116 is located between two adjacent insulating layers and includes multiple first signal lines; the photodetector and the photomodulation components are respectively connected to the corresponding first signal lines 116 through vias; the second wiring layer 117 is located on the surface of the top insulating layer 115 opposite to the second functional layer and includes multiple second signal lines; the second signal lines are connected to the first signal lines through vias, and the second signal lines are used to connect to external circuits.

[0127] The first functional layer has multiple insulating layers on the side facing away from the semiconductor substrate. Based on wiring requirements, the first wiring layer 116 can be positioned between any two insulating layers. Multi-layer metal interconnection of the chip can be achieved through CMOS and silicon photonics chip processes, which will not be elaborated further in this application.

[0128] In the embodiments of this application, such as Figure 25 As shown, a patterned first polysilicon layer 106 is provided between the first functional layer and the second functional layer. The first polysilicon layer 106 includes a first coupling sacrificial layer 1063. The second functional layer has a second coupling sacrificial layer on the side opposite to the first functional layer, and the second polysilicon layer 112 includes a second coupling sacrificial layer 1121. The second coupling sacrificial layer 1121 has a top insulating layer 115 on the side opposite to the second functional layer. Based on this, the method for coupling the light source assembly and the transmission assembly includes:

[0129] First, such as Figure 26As shown, a first trench 118 is formed based on the first coupling sacrificial layer 1063. After removing the first coupling sacrificial layer 1063, the first trench 118 is located above the first waveguide and is used to fix the first light source chip 119. The oxide layer above the first coupling sacrificial layer 1063 is removed by photolithography and dry etching, and then the remaining first coupling sacrificial layer 1063 is etched away using a dry etching process with a high polysilicon / oxide selectivity to form the first trench 118. The process is the same as the process for forming the ion implantation window K and will not be described again here. After forming the first trench 118, the first light source chip 119 is bonded in the first trench 118 using a die-to-wafer bonding process, fixing it in the first trench 118 and coupling the light source chip to the waveguide. For example, after the visible light source chip is fixed in the second trench 120 on the SOI wafer using inter-wafer bonding technology, the visible light source is coupled into the SiN waveguide through butt-coupling or evanescent-field coupling. The light is then transmitted through the SiN waveguide to the optical modulation component in the chip for processing, forming the desired characteristic wavelength light source. Finally, it is transmitted to the light output port structure through the SiN edge coupler. The SOI waveguide structure below the first polysilicon layer 106 can serve a heat dissipation function, enhancing the thermal reliability of the visible light source chip.

[0130] For example Figure 27 As shown, a second trench 120 is formed based on the second coupling sacrificial layer 1121. After removing the second coupling sacrificial layer 1121, the second trench 120 is located above the second waveguide and is used to fix the second light source chip 121. This process is the same as the principle of forming the first trench 118, and will not be described again in this embodiment.

[0131] Similarly, using an inter-wafer bonding process, the second light source chip 121 is bonded and fixed in the second trench 120, coupling the light source chip to the waveguide. For example, an InP infrared light chip or a GaSb infrared light source chip, after being fixed in the second trench structure 120 on the SOI wafer using an inter-wafer bonding process, allows infrared light to be coupled into the SiN waveguide or SOI waveguide via end-face coupling or evanescent wave coupling. After processing by the SiN waveguide, SOI waveguide, and optical components such as modulators, the desired characteristic wavelength light source is formed; specifically, for example, a characteristic wavelength optical frequency comb signal is formed, and then exported from the optical port structure through a SiN edge coupler, and then illuminated into the biological sample or human skin after passing through external optical microlenses and other optical elements. The infrared light source chip is integrated using the same scheme to enhance the spectral detection performance for specific wavelength bands. Specifically, the light emitted from the light source chip is converted into a characteristic wavelength optical frequency comb signal by an optical modulation component, and the required biological parameters are determined based on the absorption spectrum of the target at the characteristic wavelength band.

[0132] The first light source chip 119 and the second light source chip 120 emit light in different wavelengths. Since the first waveguide of single-crystal silicon can transmit infrared light, the first light source chip 119 is designated as an infrared light source chip. Since the second waveguide of silicon nitride can transmit both visible and infrared light, the second light source chip 121 is designated as a visible light source chip. The visible light source chip includes visible light LD and / or VCSEL chips. The infrared light source chip includes III-V group or GaSb detector chips.

[0133] In this embodiment, the visible light source chip emits full-spectrum visible light to achieve biological parameter detection across the entire visible light spectrum. The infrared light source chip emits infrared light including one or more of the far-infrared, near-infrared, and mid-infrared bands to achieve biological parameter detection in the infrared band. The integrated chip described in this embodiment is not limited to blood glucose parameter detection; it can also determine biological components, such as the proportion of fat and protein, based on spectral analysis of the detected light, such as the absorption of characteristic waves.

[0134] like Figure 27 As shown, the first functional layer further includes a grating 1025; the second functional layer has a top insulating layer 115 on the side opposite to the second functional layer; the area on the surface of the top insulating layer 115 opposite to the grating 1025 can also be provided with an extended light source component, thereby enabling the extension of the subsequent detection light band of the integrated chip.

[0135] Based on the above embodiments, another embodiment of this application provides an integrated chip for non-invasive blood glucose detection. The integrated chip can be fabricated using the fabrication method described in the above embodiments. Figure 28 As shown, Figure 28This application provides a schematic diagram of the structure of an integrated chip for non-invasive blood glucose detection, the integrated chip comprising:

[0136] Semiconductor substrate 100;

[0137] The first insulating layer 101 is located on the surface of the semiconductor substrate 100;

[0138] A first functional layer is located on the surface of the first insulating layer 101 on the side opposite to the semiconductor substrate 100. The first functional layer includes: an optical modulation component, a first waveguide, and an optical detection component. As described above, the first functional layer can be fabricated based on the first film layer 102.

[0139] A second functional layer is located on the side of the first functional layer opposite to the semiconductor substrate 100. The second functional layer includes a second waveguide. As described above, the second functional layer can be fabricated based on the second film layer 110.

[0140] A light source component coupled to an optical transmission component;

[0141] The optical modulation component and the optical detection component both include doped active structures; the light source component includes multiple light source chips with different emission wavelengths; the optical detection component includes multiple detectors for detecting different wavelengths; and the semiconductor substrate has an output port structure 122 for emitting detection light and collecting reflected detection light. The output port structure 122 can be configured based on the layout of the transmission optical path within the chip, therefore the output port structure 122 is not limited to... Figure 28 The layout positions are shown in the diagram.

[0142] Optionally, the light source component includes a visible light source chip and an infrared light source chip; the light detection component includes a visible light detector and an infrared light detector, so the integrated chip can realize the detection of biological parameters in the visible light band and the detection of biological parameters in the infrared light band.

[0143] Optionally, the optical modulation component includes: a MOS capacitive photoelectric modulator 1021; a first polysilicon layer 106 is provided between the first functional layer and the second functional layer, the first polysilicon layer 106 including the gate 1062 of the MOS capacitive photoelectric modulator. Furthermore, as described in the above embodiments, the first polysilicon layer 106 is also used to form an ion implantation window for the active structure in the first functional layer.

[0144] In the integrated chip, the optical modulation component further includes an MZM-type optoelectronic modulator 1022. Therefore, the integrated chip can select one or more of the MOS capacitor-type optoelectronic modulator 1021 and the MZM-type optoelectronic modulator 1022 for characteristic wave modulation.

[0145] In the integrated chip, the first functional layer is a single-crystal silicon layer, the first waveguide is a silicon waveguide, and it can transmit infrared light; the second functional layer is a silicon nitride layer, the second waveguide is a silicon nitride waveguide, and it can transmit infrared light and visible light.

[0146] In this embodiment, the second functional layer has a top insulating layer 115 on the side opposite to the first functional layer. The surface of the top insulating layer 115 has a first trench 118 and a second trench 120. The first trench 118 is used to fix the first light source chip 119, and the first light source chip 119 is coupled to the first waveguide below the first trench 118. The second trench 120 is used to fix the second light source chip 121, and the second light source chip 121 is coupled to the second waveguide below the second trench 120.

[0147] In this embodiment, the first functional layer further includes a grating 1025; the second functional layer has a top insulating layer 115 on the side opposite to the first functional layer; the area on the surface of the top insulating layer 115 opposite to the grating 1025 can also be provided with an extended light source component, thereby enabling the extension of the subsequent detection light band of the integrated chip.

[0148] In the integrated chip, the first functional layer has multiple insulating layers on the side facing away from the semiconductor substrate, and the second functional layer is located between the two insulating layers.

[0149] The integrated chip further includes a first wiring layer 116 and a second wiring layer 117; the first wiring layer 116 is located between two adjacent insulating layers and includes multiple first signal lines; the photodetector component and the photomodulation component are respectively connected to the corresponding first signal lines through vias; the second wiring layer 117 is located on the surface of the outermost insulating layer away from the second functional layer and includes multiple second signal lines; the second signal lines are connected to the first signal lines through vias, and the second signal lines are used to connect to external circuits.

[0150] The integrated chip can cover light from the visible to the near-infrared and mid-infrared range, and can extend to the terahertz wavelength. It can infer biological parameters such as blood glucose levels based on the degree of attenuation of light as it penetrates specific tissues in the human body.

[0151] The integrated chip is a monolithic hybrid integrated chip solution, which adopts a general CMOS process platform and typical optical chip structure and process. It can integrate semiconductor light-emitting chips and detection components of various bands such as visible light analysis (Vis), near-infrared / infrared spectroscopy analysis (NIR / IR), and mid-infrared (MIR) on the same SOI wafer, thereby constructing a SOI-SiN-InP-GaSb monolithic hybrid integrated chip that can be used for non-invasive blood glucose detection.

[0152] One important application of the integrated chip is its ability to be integrated and packaged with electrical chips and various optical components to achieve non-destructive detection of human blood glucose. Human blood glucose levels are stable in specific locations, and specific glycosides have different absorption rates for specific wavelengths of near-infrared light. By analyzing the attenuated spectral absorption of visible / near-infrared / infrared / mid-infrared light across a wide band, the human blood glucose level can be inferred. This application's technical solution considers the need to integrate semiconductor light-emitting chips and detection chips for various bands, such as visible light analysis (Vis), near-infrared / infrared spectral analysis (NIR / IR), and mid-infrared (MIR), into a size-constrained wearable device, maintaining a small size and low power consumption. Therefore, it proposes a truly single-chip integration solution and a monolithic hybrid integration chip structure, based on SOI wafer monolithic hybrid integration technology. This achieves on-chip integration of multi-band spectral analysis, reducing the size of the non-destructive human blood glucose detector, lowering costs, and enabling its use in hospitals, communities, and home environments.

[0153] Based on the integrated chip described in the above embodiments, another embodiment of this application also provides a wearable device, such as... Figure 29 As shown, Figure 29 This application provides a schematic diagram of the structure of a wearable device, which includes:

[0154] Circuit board 23, wherein an electrical chip 22 is connected to the circuit board 23;

[0155] The integrated chip 21 described in the above embodiment is fixed on the circuit board 23 and connected to the electrical chip 22; the integrated chip 21 and the electrical chip 22 are electrically connected through the circuit in the circuit board 23.

[0156] The electronic chip 22 is used to determine the biometric parameters of the target based on the detection signal generated by the light detection component, wherein the biometric parameters include at least blood glucose parameters. The wearable device includes, but is not limited to, smart bracelets, smartwatches, etc. Figure 29 In the diagram, the arrow represents the detection light reflected by the integrated chip 21, and the dashed arrow represents the light returned by the target collected by the integrated chip 21.

[0157] Various electrical chips 22 with logic control and analysis functions can be used, including: TIA (transimpedance amplifier) ​​chips, A / D (analog-to-digital) converter chips, DSP (digital signal processing and numerical analysis) chips, and communication chips, etc.

[0158] After the detection light emitted by the integrated chip 21 illuminates the target (such as human tissue), it can collect the detection light returned by the target, including any type of return detection light reflected, scattered, or transmitted from the target. In the photosensitive chip of the light detection component, the absorption spectrum is analyzed and detected, and the characteristic spectral information of the collected detection light is converted into corresponding electrical signals. The TIA chip amplifies these characteristic spectral electrical signals and filters out noise. The A / D conversion chip converts the amplified electrical signals into digital signals. The DSP chip analyzes and processes the digital signals to obtain biological parameters. The communication chip enables communication between the wearable device and external devices.

[0159] In particular, each chip in the electrical chip 22 can be 2.5D or 3D packaged through glass or silicon-based adapter boards, and together with some optical components such as reflectors 24 and microlenses 25, they can be packaged into small standard modules; thereby realizing the miniaturization of the device, maintaining a small size and power consumption, and realizing the application of wearable devices such as health bracelets or watches.

[0160] The light returning from the target is focused by the target mirror and reflected by the reflector 24, then enters the integrated optical chip 21. After wavelength modulation and decoupling processing within the integrated chip, such as typical optical chip components like arrayed waveguide gratings (AWG), the light becomes discrete signals of individual wavelengths. These signals are then detected and analyzed by optical detection components within the integrated chip, such as silicon PN junction detection diodes, silicon APD diodes, or GePDs. Finally, the absorption spectrum data that can characterize the required biological parameters is analyzed by the electrical chip 22.

[0161] In conventional wearable devices, light is typically shone onto the skin via LEDs, and the returned scattered light is monitored to measure pulse and even blood oxygen levels. However, the sensors in these devices are not medical-grade and can only perform spectral analysis in the visible light band, resulting in low detection accuracy. While it's possible to fabricate separate chips for visible light LEDs and detectors, infrared emitters and detectors, and mid-infrared emitters and detectors using individual processes and packaging them into separate optical paths, thus increasing the detection spectral range, the chip system becomes complex and bulky, making miniaturization and wearable integration difficult. Integrating semiconductor light-emitting and detector chips for various wavelengths, such as visible light analysis (Vis), near-infrared / infrared spectral analysis (NIR / IR), and mid-infrared (MIR), into a size-constrained wearable bracelet or watch while maintaining a small size and low power consumption is extremely challenging.

[0162] The integrated chip described in this application embodiment can serve as a high-precision optical sensor and also as a spectrophotometer for visible and infrared spectral analysis. It can non-invasively probe beneath the skin to analyze components such as blood, thereby monitoring a wider range of human indicators. It offers a broad spectral range for analysis and high accuracy in its detection and analysis results. By integrating multiple light source components and optical detection components into a single semiconductor chip, miniaturization is achieved, allowing integration into wearable bracelets and watches for continuous, 24 / 7 monitoring of biometric data such as blood glucose. The wearable device described in this application embodiment can achieve continuous, non-invasive monitoring of multi-modal bioparameters, such as lactate, glucose, hydration, blood pressure, and core body temperature.

[0163] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0164] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0165] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0166] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating an integrated chip suitable for non-invasive blood glucose detection, characterized in that, The manufacturing method includes: A semiconductor substrate is provided, the surface of which has a first insulating layer and a first film layer located on the surface of the first insulating layer facing away from the semiconductor substrate; The first film layer is patterned to form a first functional layer, the first functional layer including: an optical modulation component, a first waveguide and an optical detection component; A second functional layer is formed on the side of the first film layer away from the semiconductor substrate, and the second functional layer includes: a second waveguide; A light source assembly is formed and coupled to an optical transmission component, the optical transmission component including a first waveguide and a second waveguide; The optical modulation component and the optical detection component both include doped active structures; the light source component includes multiple light source chips with different emission wavelengths; the optical detection component includes multiple detectors for detecting different wavelengths; and the semiconductor substrate has an output port structure for emitting detection light and collecting reflected detection light. The photodetector includes a MOS capacitive photoelectric modulator; a first polysilicon layer is provided between the first functional layer and the second functional layer, and the first polysilicon layer includes the gate of the MOS capacitive photoelectric modulator.

2. The manufacturing method according to claim 1, characterized in that, The method for forming the first functional layer includes: A second insulating layer and a third insulating layer are sequentially formed on the side of the first film layer facing away from the semiconductor substrate; The second insulating layer and the third insulating layer are graphically represented; Based on the patterned second and third insulating layers, the first film layer is etched to form the first functional layer; wherein, the first functional layer includes multiple waveguide structures with different etching depths to form the first waveguide, the optical modulation component, and the optical detection component; A planarized fourth insulating layer is formed on the side of the first insulating layer opposite to the semiconductor substrate, the fourth insulating layer covering the first functional layer.

3. The manufacturing method according to claim 2, characterized in that, Before forming the second functional layer, the following is also included: Remove the third insulating layer to expose the second insulating layer; The active structure of the MOS capacitor-type optoelectronic modulator is doped.

4. The manufacturing method according to claim 1, characterized in that, The surface of the first functional layer facing away from the semiconductor substrate has a second insulating layer; The method for forming the second functional layer includes: A patterned first polysilicon layer is formed on the surface of the second insulating layer away from the first functional layer, the first polysilicon layer including: a window sacrificial layer; A fifth insulating layer and a second film layer are sequentially formed on the side of the first polysilicon layer opposite to the first functional layer; The second film layer is patterned to form the second functional layer; The window sacrificial layer is used to form the ion implantation window of the active structure in the first functional layer.

5. The manufacturing method according to claim 1, characterized in that, The first polysilicon layer includes: a window sacrificial layer; The method for forming the active structure includes: An ion implantation window is formed in the insulating layer of the window sacrificial layer away from the first functional layer, and the ion implantation window exposes the window sacrificial layer. Remove the window sacrificial layer based on the ion implantation window; After removing the window sacrificial layer, ion implantation is performed based on the ion implantation window to dope the active structure below the ion implantation window.

6. The manufacturing method according to claim 1, characterized in that, The first polysilicon layer includes: a first coupling sacrificial layer; the second functional layer has a second coupling sacrificial layer on the side opposite to the first functional layer; the second coupling sacrificial layer has a top insulating layer on the side opposite to the second functional layer; The method for coupling the light source component to the transmission component includes: A first trench is formed based on the first coupling sacrificial layer, and the first coupling sacrificial layer is removed. The first trench is located above the first waveguide and is used to fix the first light source chip. A second trench is formed based on the second coupling sacrificial layer, and the second coupling sacrificial layer is removed. The second trench is located above the second waveguide and is used to fix the second light source chip. The first light source chip and the second light source chip emit light in different wavelengths.

7. The manufacturing method according to claim 1, characterized in that, The first functional layer further includes a grating; the second functional layer has a top insulating layer on the side opposite to the second functional layer; the area on the surface of the top insulating layer opposite to the grating can also be provided with an extended light source component.

8. The manufacturing method according to claim 1, characterized in that, The first functional layer has an insulating layer on the side facing away from the semiconductor substrate, and the second functional layer is located between the two insulating layers; The manufacturing method further includes: forming a first wiring layer and a second wiring layer; The first wiring layer is located between two adjacent insulating layers and includes multiple first signal lines; the photodetector and the photomodulation components are respectively connected to the corresponding first signal lines through vias; the second wiring layer is located on the side of the top insulating layer away from the second functional layer and includes multiple second signal lines; the second signal lines are connected to the first signal lines through vias, and the second signal lines are used to connect to external circuits.

9. An integrated chip for non-invasive blood glucose detection, characterized in that, include: Semiconductor substrate; The first insulating layer located on the surface of the semiconductor substrate; A first functional layer located on the surface of the first insulating layer opposite to the semiconductor substrate, the first functional layer comprising: an optical modulation component, a first waveguide, and an optical detection component; A second functional layer located on the side of the first functional layer opposite to the semiconductor substrate, the second functional layer comprising: a second waveguide; A light source component coupled to an optical transmission component; The optical modulation component and the optical detection component both include doped active structures; the light source component includes multiple light source chips with different emission wavelengths; the optical detection component includes multiple detectors for detecting different wavelengths; and the semiconductor substrate has an output port structure for emitting detection light and collecting reflected detection light. The photodetector includes a MOS capacitor-type photoelectric modulator; a first polysilicon layer is provided between the first functional layer and the second functional layer, and the first polysilicon layer includes the gate of the MOS capacitor-type photoelectric modulator; The light source component includes a visible light source chip and an infrared light source chip; the light detection component includes a visible light detector and an infrared light detector.

10. The integrated chip according to claim 9, characterized in that, The first polysilicon layer is also used to form an ion implantation window for the active structure in the first functional layer.

11. The integrated chip according to claim 10, characterized in that, The optical modulation component also includes an MZM type optoelectronic modulator.

12. The integrated chip according to claim 9, characterized in that, The first functional layer is a single-crystal silicon layer, and the first waveguide is a silicon waveguide; The second functional layer is a silicon nitride layer, and the second waveguide is a silicon nitride waveguide.

13. The integrated chip according to claim 9, characterized in that, The second functional layer has a top insulating layer on the side opposite to the first functional layer, and the surface of the top insulating layer has a first trench and a second trench; the first trench is used to fix the first light source chip, and the first light source chip is coupled to the first waveguide below the first trench. The second trench is used to fix the second light source chip, and the second light source chip is coupled to the second waveguide below the second trench.

14. The integrated chip according to claim 9, characterized in that, The first functional layer further includes a grating; the second functional layer has a top insulating layer on the side opposite to the first functional layer; the light source assembly is disposed on the top insulating layer; an extended light source component can also be disposed on the surface of the top insulating layer opposite to the grating.

15. The integrated chip according to claim 9, characterized in that, The first functional layer has multiple insulating layers on the side facing away from the semiconductor substrate, and the second functional layer is located between the two insulating layers; The integrated chip further includes a first wiring layer and a second wiring layer; the first wiring layer is located between two adjacent insulating layers and includes multiple first signal lines; the photodetector and the photomodulation components are respectively connected to the corresponding first signal lines through vias; the second wiring layer is located on the surface of the outermost insulating layer away from the second functional layer and includes multiple second signal lines; the second signal lines are connected to the first signal lines through vias, and the second signal lines are used to connect to external circuits.

16. A wearable device, characterized in that, include: A circuit board, wherein an electrical chip is connected to the circuit board; The integrated chip as described in any one of claims 9-15, wherein the integrated chip is fixed on the circuit board and connected to the electrical chip; The electrical chip is used to determine the biometric parameters of the target based on the detection signal generated by the light detection component, wherein the biometric parameters include at least blood glucose parameters.

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