image sensor

Abstract

An image sensor includes a pixel configured to operate in a high conversion gain mode and a low conversion gain mode during a readout period, and a correlated double sampling circuit configured to generate a comparison signal based on a ramp signal and a pixel voltage received from the pixel. The correlated double sampling circuit includes a comparator configured to receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on receiving a low conversion gain reset signal or a low conversion gain image signal as the pixel voltage, and receive the ramp signal through a third input node based on receiving a high conversion gain reset signal or a high conversion gain image signal as the pixel voltage, and compare the ramp signal with the pixel voltage and output a comparison signal corresponding to a comparison result.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0115525, filed on September 9, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of this disclosure relate to an image sensor, and more specifically, to an image sensor supporting dual conversion gain and a method of operating the same. Background Technology

[0004] An image sensor is a device that captures two-dimensional or three-dimensional images of an object. Image sensors use photoelectric conversion elements to generate images of objects, which react according to the intensity of light reflected from the object. With the recent development of complementary metal-oxide-semiconductor (CMOS) technology, CMOS image sensors using CMOS are widely used. Recently, to increase the dynamic range of image sensors, dual conversion gain technology, in which one pixel has two conversion gains, has been developed. Summary of the Invention

[0005] One or more exemplary embodiments of this disclosure provide an image sensor and a method of operating the same, which is capable of processing pixel signals of pixels with double conversion gain within a frame and reducing circuit area.

[0006] According to one aspect of this disclosure, an image sensor is provided, comprising: a pixel configured to operate in a high conversion gain (HCG) mode and a low conversion gain (LCG) mode during a readout period, and sequentially outputting an LCG reset signal, an HCG reset signal, an HCG image signal, and an LCG image signal as a pixel voltage; and a correlated double sampling (CDS) circuit configured to generate a comparison signal based on a ramp signal and the pixel voltage received from the pixel, wherein the CDS circuit includes a comparator configured to: receive the pixel voltage through a first input node; receive the ramp signal through a second input node based on the received LCG reset signal or LCG image signal as a pixel voltage; and receive the ramp signal through a third input node based on the received HCG reset signal or HCG image signal as a pixel voltage; and compare the ramp signal with the pixel voltage and output a comparison signal corresponding to the comparison result.

[0007] According to one aspect of this disclosure, an image sensor is provided, comprising: a pixel configured to operate in HCG mode and LCG mode during a readout cycle, and sequentially outputting an LCG reset signal, an HCG reset signal, an HCG image signal, and an LCG image signal to column lines as a pixel voltage; a current source electrically connected to the column lines and configured to provide a bias current flowing through a driving transistor of the pixel; and a bias current controller configured to adjust the bias current based on the pixel voltage based on a transition from the pixel's LCG mode to HCG mode.

[0008] According to one aspect of this disclosure, an image sensor is provided, comprising: a pixel configured to operate in HCG mode and LCG mode during a readout period, and sequentially outputting an LCG reset signal, an HCG reset signal, an HCG image signal, and an LCG image signal as pixel voltages; a CDS circuit configured to compare a ramp signal with the pixel voltages received from the pixel and generate a comparison signal; and a counter circuit configured to generate HCG pixel values ​​and LCG pixel values ​​based on the comparison signal received from the CDS circuit and a count code, the count code having a code value that increases over time, wherein the counter circuit includes a latch configured to latch the code value of the count code at the time of a level transition of the comparison signal and output the code value as a count value with respect to the comparison signal; a first memory configured to store a first count value output from the latch; a second memory configured to store a second count value output from the latch after outputting the first count value; and a calculator configured to perform calculations on one of a third and a fourth count value output from the latch and one of the first and second count values. Attached Figure Description

[0009] The exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating an image sensor according to an embodiment of the present disclosure;

[0011] Figure 2 This is a circuit diagram illustrating an example implementation of pixels according to an embodiment of the present disclosure;

[0012] Figure 3 This is a timing diagram of an image sensor according to an embodiment of the present disclosure;

[0013] Figure 4 This is a circuit diagram illustrating a CDS circuit according to an embodiment of the present disclosure;

[0014] Figure 5 It shows that it is applied to Figure 4Timing diagram of the switching signals and input node voltages of the CDS circuit;

[0015] Figures 6A to 9 The operation of the CDS circuit according to the switching signal applied to the CDS circuit is shown;

[0016] Figure 10 This is a diagram illustrating a pixel array of an image sensor according to an embodiment of the present disclosure;

[0017] Figure 11 This is a circuit diagram illustrating a current source and a bias current controller disposed in a pixel array according to an embodiment of the present disclosure;

[0018] Figure 12 This is a timing diagram of a bias current controller according to an embodiment of the present disclosure;

[0019] Figures 13A to 13C The operation of the bias current controller according to the switching signal applied to the bias current controller is shown;

[0020] Figure 14 This is a diagram illustrating a counter circuit according to an embodiment of the present disclosure;

[0021] Figure 15 It is shown Figure 14 The timing diagram of the counter circuit operation;

[0022] Figure 16 This is a diagram illustrating a counter circuit according to an embodiment of the present disclosure;

[0023] Figure 17 It is shown Figure 16 The timing diagram of the counter circuit operation;

[0024] Figure 18 and Figure 19 It is a block diagram of an electronic device including a multi-camera module; and

[0025] Figure 20 yes Figure 18 Detailed block diagram of the camera module. Detailed Implementation

[0026] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 This is a block diagram illustrating an image sensor 100 according to an embodiment of the present disclosure.

[0028] The image sensor 100 can be mounted on an electronic device with image or light sensing capabilities. For example, the image sensor 100 can be mounted on electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, personal computers (PCs), personal digital assistants (PDAs), portable multimedia players (PMPs), navigation devices, etc. Additionally, the image sensor 100 can be mounted on electronic devices provided as components of vehicles, furniture, manufacturing facilities, doors, and various measuring devices.

[0029] Image sensor 100 may include pixel array 110, line driver 120, ramp signal generator 130, counter code generator 140, analog-to-digital converter (ADC) circuit 150, data output circuit 180, and timing controller 190. Image sensor 100 may also include signal processor 195.

[0030] The pixel array 110 may include multiple row lines RL, multiple column lines CL, and multiple pixels PX connected to the multiple row lines RL and multiple column lines CL and arranged in a matrix. A current source CS may be connected to each of the multiple column lines CL.

[0031] Each of the plurality of pixels PX may include at least one photoelectric conversion element, which can be used to sense light and output an image signal as an electrical signal based on the sensed light. For example, the photoelectric conversion element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode.

[0032] Each of the plurality of pixels PX can detect light in a specific spectral region. For example, the plurality of pixels PX may include: red pixels that convert light in the red spectral region into an electrical signal; green pixels that convert light in the green spectral region into an electrical signal; and blue pixels that convert light in the blue spectral region into an electrical signal. However, this disclosure is not limited thereto, and the plurality of pixels PX may also include white pixels. As another example, the plurality of pixels PX may include pixels combined in different color configurations, such as yellow pixels, cyan pixels, and green pixels.

[0033] An array of color filters that transmits light in a specific spectral region can be disposed on the upper part of a plurality of pixels PX, and the color that can be sensed by the corresponding pixel can be determined based on the color filters disposed on the upper part of each of the plurality of pixels PX. However, this disclosure is not limited thereto, and in embodiments, a specific photoelectric conversion element can convert light of a specific wavelength band into an electrical signal based on the level of the electrical signal applied to the photoelectric conversion element.

[0034] In the pixel array 110 according to the example embodiment, pixel PX may have dual conversion gain. Dual conversion gain includes low conversion gain and high conversion gain. Here, conversion gain represents the accumulation at the floating diffusion node FD( Figure 2 The conversion rate of charge to voltage in the photoelectric conversion element (PDE) is as follows: The charge generated by the photoelectric conversion element can be transferred to and accumulated in the floating diffusion node (FD), and the charge accumulated in the floating diffusion node (FD) can be converted into voltage according to the conversion gain. The conversion gain can vary depending on the capacitance of the floating diffusion node (FD); when the capacitance increases, the conversion gain can decrease, and when the capacitance decreases, the conversion gain can increase.

[0035] The pixel PX can operate in either a high-capacitance, low-conversion-gain (LCG) mode with a floating diffuse node FD or a low-capacitance, high-conversion-gain (HCG) mode with a floating diffuse node FD. Even with the same charge accumulated in the floating diffuse node FD, the voltage of the floating diffuse node FD in HCG mode can be higher than that in LCG mode. (Further details will follow.) Figure 2 The configuration of pixel PX and the operation of pixel PX according to the conversion gain mode are described in detail.

[0036] In the first image data generated when the multiple pixels PX of the pixel array 110 operate in HCG mode, dark areas can be clearly represented, and in the second image data generated when the multiple pixels PX of the pixel array 110 operate in LCG mode, bright areas can be clearly represented.

[0037] In an embodiment, during a frame scanning the pixel array 110, each of the plurality of pixels PX can operate continuously in HCG mode and LCG mode during the corresponding readout period. Therefore, a first image data corresponding to the HCG mode and a second image data corresponding to the LCG mode can be generated during a frame period. The first and second images can be merged to generate a one-shot image with a high dynamic range that clearly defines bright areas (high-brightness areas) and dark areas (low-brightness areas). Thus, the double conversion gain within a frame can be referred to as the scene-intra-scene double conversion gain, and hereinafter, the double conversion gain mentioned in this disclosure refers to the scene-intra-scene double conversion gain.

[0038] The current source CS can provide a bias current Ib to the pixel PX (e.g., the selected pixel) connected to the corresponding column line CL. Here, the bias current refers to the current output (or applied) from the driving transistor DX of the pixel PX.

[0039] In an embodiment, the image sensor 100 may further include a plurality of bias current controllers to increase or decrease the bias current when the transition mode of the pixel PX changes during the readout cycle (e.g., from LCG mode to HCG mode or from HCG mode to LCG mode), and the plurality of bias current controllers may be connected to a plurality of column lines CL respectively. When the transition mode of the pixel PX changes, the bias current Ib may change, and the amount of the bias current Ib may increase or decrease depending on whether the pixel PX is operating in LCG mode or HCG mode. For example, when the pixel PX is operating in HCG mode, the amount of the bias current Ib may be less than the amount of the bias current Ib provided when the pixel PX is operating in LCG mode.

[0040] The row driver 120 can drive the pixel array 110 on a row-by-row basis. The row driver 120 can decode row control signals (e.g., address signals) received from the timing controller 190 and can select at least one of the row lines constituting the pixel array 110 in response to the decoded row control signals. For example, the row driver 120 can generate a selection signal for selecting one row from a plurality of rows. Additionally, the pixel array 110 can output pixel signals, such as pixel voltages, from the row selected according to the selection signal provided from the row driver 120. The pixel signals may include reset signals and image signals.

[0041] The row driver 120 can send control signals for outputting pixel signals to the pixel array 110, and the pixel PX can output pixel signals in response to the control signals. In an embodiment, the row driver 120 can generate control signals for controlling the pixel PX to operate continuously in HCG mode and LCG mode during the readout cycle, and provide the control signals to the pixel array 110.

[0042] The ramp signal generator 130 can generate a ramp signal (e.g., a ramp voltage) whose level rises or falls at a predetermined slope under the control of the timing controller 190. The ramp signal RAMP can be provided to each of the plurality of correlated double sampling (CDS) circuits 160 disposed in the ADC circuit 150.

[0043] The counter code generator 140 can generate a counter code CCD under the control of the timing controller 190. The counter code CCD can be provided to each of the plurality of counter circuits (CNTR) 170. In an embodiment, the counter code generator 140 can be implemented as a Gray code generator. The counter code generator 140 can generate a plurality of code values ​​as a counter code CCD having a resolution based on a set number of bits. For example, when a 10-bit code is set, the counter code generator 140 can generate a counter code CCD comprising 1024 code values ​​that increase or decrease sequentially.

[0044] The ADC circuit 150 may include multiple CDS circuits 160 and multiple counter circuits 170. The ADC circuit 150 can convert pixel signals (e.g., pixel voltages) input from the pixel array 110 into pixel values ​​as digital signals. Each pixel signal received through each of the multiple column lines CL can be converted into a pixel value as a digital signal by the CDS circuit 160 and the counter circuit 170.

[0045] The CDS circuit 160 compares the pixel signal received via column line CL with the ramp signal RAMP and outputs the comparison result. The CDS circuit 160 can output a comparison signal that transitions from a first level (e.g., logic high) to a second level (e.g., logic low) when the level of the ramp signal RAMP is the same as the level of the pixel signal. The timing of the level transition of the comparison signal can be determined based on the level of the pixel signal.

[0046] The CDS circuit 160 can sample and hold the pixel signal provided from the pixel PX according to the CDS method, double sample the level of a specific noise (e.g., a reset signal) and the level according to the image signal, and generate a comparison signal based on the level corresponding to the difference between the levels.

[0047] In an embodiment, the CDS circuit 160 may include one or more comparators. The comparators may be implemented as, for example, operational transconductance amplifiers (OTA) (or differential amplifiers). The CDS circuit 160 may include an input stage that receives a ramp signal RAMP and a pixel signal, and the input stage may include a first transistor that receives the ramp signal RAMP, a second transistor that receives the pixel signal and operates when pixel PX operates in LCG mode, and a third transistor that receives the pixel signal and operates when pixel PX operates in HCG mode. Additionally, the CDS circuit 160 may include multiple switches that allow one of the second and third transistors to operate according to the transition mode of pixel PX and perform an auto-zeroing operation according to the transition mode. Here, the auto-zeroing operation can remove reset noise of the pixel signal, the internal offset of the CDS circuit 160, and the offset voltage that changes according to the transition mode of pixel PX.

[0048] The counter circuit 170 can count the level transition times of the comparison signal output from the CDS circuit 150 and output a count value. In an embodiment, the counter circuit 170 may include a latch circuit and an operation circuit. The latch circuit can receive a count code CCD from the count code generator 140 and a comparison signal from the CDS circuit 160, and latch the code value of the count code CCD during the level transition times of the comparison signal. The latch circuit can latch a code value corresponding to a reset signal (e.g., a reset value) and a code value corresponding to an image signal (e.g., an image signal value). The operation circuit can calculate the reset value and the image signal value to generate an image signal value from which the reset level of pixel PX has been removed. The counter circuit 170 can output the image signal value from which the reset level has been removed as a pixel value. The counter circuit 170 may include: a circuit (e.g., a latch circuit, a memory, etc.) that stores a reset value (e.g., an LCG reset value) corresponding to the operation of pixel PX in LCG mode and a reset value (e.g., an HCG reset value) corresponding to the operation of pixel PX in HCG mode; and a selector that selectively outputs one of the LCG reset value and the HCG reset value and provides the output reset value to the operation circuit.

[0049] In an example embodiment, the image sensor 100 includes a counter code generator 140, and the counter circuit 170 includes circuitry for latching the code value of the counter code CCD received from the counter code generator 140; however, this disclosure is not limited thereto. In embodiments, the image sensor 100 does not include a separate counter code generator 140, and the counter circuit 170 may include an incrementing counter, an increment / decrementing counter, or a bit-by-bit inverting counter whose count value increments sequentially based on a counting clock signal provided from a timing controller 190 and operating circuitry.

[0050] The data output circuit 180 can temporarily store pixel values ​​output from the ADC circuit 150 and subsequently output the pixel values. The data output circuit 180 may include multiple column memories (BF) 181 and a column decoder 182. The column memories 181 can store pixel values ​​received from the counter circuit 170. In an embodiment, each of the multiple column memories 181 may be located within the counter circuit 170. Multiple pixel values ​​stored in the multiple column memories 181 can be output as image data IDT under the control of the column decoder 182.

[0051] The timing controller 190 can output control signals to each of the line driver 120, ramp signal generator 130, counter code generator 140, ADC circuit 150, and data output circuit 180 to control the operation or timing of each of the line driver 120, ramp signal generator 130, counter code generator 140, ADC circuit 150, and data output circuit 180.

[0052] The signal processor 195 can perform noise reduction, gain adjustment, waveform shaping, interpolation, white balance, gamma adjustment, edge enhancement, binning, and other processing on the image data. In an embodiment, when the pixel array 110 operates in HCG and LCG modes during a frame period, the signal processor 195 can receive first image data according to the HCG mode and second image data according to the LCG mode from the data output circuit 180, and merge the first and second image data to generate an image with high dynamic range. In an embodiment, the signal processor 195 can be located in an external processor of the image sensor 100.

[0053] Figure 2 This is a circuit diagram illustrating an embodiment of a pixel PX according to an embodiment of the present disclosure.

[0054] A pixel PX may include a photodiode PD, multiple transistors (e.g., a transfer transistor TX, a reset transistor RX, a drive transistor DX, a select transistor SX, and a gain control transistor CGX (or a switching gain control transistor)) and a capacitor C. L A capacitor C can be formed by floating diffusion nodes (FD). H (For example, parasitic capacitors). Capacitor C L It can be a passive element with fixed or variable capacitance, or a parasitic capacitor formed by the source / drain of the gain control transistor CGX, or a parasitic capacitor formed in other pixel PX that can be connected to the source / drain of the gain control transistor CGX.

[0055] A photodiode (PD) converts incident light into an electrical signal. The PD generates charge based on the light intensity. The amount of charge generated by the PD varies depending on the image capture environment (low or high brightness). For example, the amount of charge generated by the PD can reach its full-well capacity (FWC) in a high-brightness environment, while it will not reach FWC in a low-brightness environment.

[0056] The reset transistor RX, the transfer transistor TX, the select transistor SX, and the gain control transistor CGX can operate in response to control signals (e.g., reset control signal RS, transfer control signal TS, select signal SEL, and gain control signal CGS) provided by the row driver 120.

[0057] The reset transistor RX can be turned on in response to the reset control signal RS applied to the gate terminal to reset the floating diffusion node FD based on the pixel power supply voltage VDDP. At this time, the gain control transistor CGX can be turned on together based on the gain control signal CGS received from the gate terminal, so that the power supply voltage VDDP can be applied to the floating diffusion node FD, and the floating diffusion node FD can be reset.

[0058] The transfer transistor TX can be turned on in response to a transfer control signal TS applied to its gate terminal, and can transfer the charge generated by the photodiode PD to the floating diffusion node FD. The charge can accumulate in the floating diffusion node FD. In other words, the charge can accumulate in the capacitor C formed by the floating diffusion node FD. H In the middle, or when the gain control transistor CGX is turned on, charge can accumulate in capacitor C. H and capacitor C L middle.

[0059] The charge accumulated in the floating diffusion node (FD) can generate a voltage. In other words, the charge accumulated in the floating diffusion node (FD) can be converted into a voltage. The conversion gain (e.g., the unit of conversion gain can be μV / e) can be determined by the capacitance of the floating diffusion node (FD) and can be inversely proportional to the size of the capacitance. When the capacitance of the floating diffusion node (FD) increases, the conversion gain can decrease, and when the capacitance decreases, the conversion gain can increase.

[0060] The driving transistor DX can operate as a source follower based on the bias current Ib generated by the current source CS connected to the column line CL, and the pixel voltage VPIX can be obtained by selecting the output of transistor SX and the voltage corresponding to the voltage of the floating diffusion node FD.

[0061] Select transistor SX selects pixel PX. Select transistor SX can be turned on in response to a select signal SEL applied to its gate terminal to output the pixel voltage VPIX (or current) from the drive transistor DX to the column line CL. The pixel voltage VPIX can be supplied to (…) via the column line CL. Figure 1 ADC circuit 150.

[0062] The gain control transistor CGX can be turned on or off based on the gain control signal CGS received at the gate terminal. When the gain control transistor CGX is off, the floating diffusion node FD can be turned on or off through capacitor C. H It has a capacitor, and when the gain control transistor CGX is turned on, the capacitor C... L It can be connected to the floating diffusion node FD, and the floating diffusion node FD can be connected to the capacitor C. H and capacitor C LBecause it has a capacitor, the capacitance can be increased. The conversion gain of the gain control transistor CGX when it is in the off state can be higher than the conversion gain of the gain control transistor CGX when it is in the on state. The mode in which the gain control transistor CGX is in the off state can be called HCG mode, and the mode in which the gain control transistor CGX is in the on state can be called LCG mode.

[0063] As described above, pixel PX can operate in either HCG or LCG mode depending on the on or off state of gain control transistor CGX. In HCG mode, because the conversion gain of pixel PX can be increased, the gain of the circuitry (e.g., ADC circuit 150) that processes the pixel voltage VPIX output from pixel PX can be relatively reduced. Therefore, the image sensor ( Figure 1 The signal-to-noise ratio (SNR) of the image sensor 100 can be increased, thus reducing the minimum sensible light intensity and improving its low-light sensing performance. In LCG mode, the floating diffusion node (FD) capacitance of the pixel PX is larger, allowing for an increase in the free float capacitance (FWC). Therefore, the high-light sensing performance of the image sensor 100 can be improved.

[0064] As described above, because the pixel PX provides dual conversion gain to sense both low and high light levels, the dynamic range of the image sensor 100 can be extended (or increased). Additionally, as referenced above... Figure 1 The described pixel PX can operate continuously in HCG mode and LCG mode during the readout cycle, and the image sensor 100 (e.g., the signal processor 195) Figure 1 The first image according to the HCG mode can be merged with the second image according to the LCG mode to generate an image with high dynamic range.

[0065] Figure 3 This is a timing diagram of an image sensor 100 according to an embodiment of the present disclosure. Figure 3 It is from Figure 2 Timing diagram of image sensor 100 when reading pixel signals at pixel PX.

[0066] During one readout cycle (or horizontal cycle), data can be obtained from pixel array 110 ( Figure 1 Multiple pixels PX arranged in at least one row of a (in the middle) read multiple pixel voltages VPIX (or multiple currents). In other words, each of the multiple pixels PX can output a pixel voltage VPIX during the readout cycle, and the pixel voltage VPIX can be converted from analog to digital by the corresponding CDS circuit 160 and counter circuit 170 of the ADC circuit 150.

[0067] Refer to together Figure 2 and Figure 3The select signal SEL can be active (e.g., logic high) during the readout cycle, and the select transistor SX can be turned on in response to the select signal SEL, allowing pixel PX to be connected to column line CL. Here, the active level of the signal represents the level at which the transistor to which the signal is applied can be turned on. In this disclosure, it is assumed that logic high is an active level and logic low is an inactive level.

[0068] The readout period can be divided into a first sub-period SP1 to a fourth sub-period SP4 based on the pixel signal output from pixel PX. According to the gain control signal CGS, pixel PX can operate in LCG mode during the first sub-period SP1 and the fourth sub-period SP4, and in HCG mode during the second sub-period SP2 and the third sub-period SP3. As described above, pixel PX can have a dual-conversion gain.

[0069] During the first sub-cycle SP1, a reset signal corresponding to the reset level of pixel PX (e.g., the voltage of the reset floating diffusion node FD) can be read, and since pixel PX operates in LCG mode during the first sub-cycle SP1, an LCG reset signal indicating the reset level in LCG mode can be read.

[0070] In response to the active levels of the reset control signal RS and the gain control signal CGS, the reset transistor RX and the gain control transistor CGX can be turned on, and the floating diffusion node FD can be reset. An LCG reset signal corresponding to the reset voltage of the floating diffusion node FD can be output as the pixel voltage VPIX, and the LCG reset signal can be converted from analog to digital. When the CDS circuit 160 ( Figure 1 When the ramp signal RAMP is compared with the pixel voltage VPIX and the comparison result is output as the comparison signal, the counter circuit 170 ( Figure 1 (in the middle) can latch the count code based on the received comparison signal to generate a count value (e.g., LCG reset value) corresponding to the LCG reset signal.

[0071] During the second sub-cycle SP2, the reset signal corresponding to the reset level of pixel PX can be read, and since pixel PX operates in HCG mode during the second sub-cycle SP2, the HCG reset signal indicating the reset level in HCG mode can be read.

[0072] When the gain control signal CGS transitions to an inactive level (e.g., logic low), the gain control transistor CGX can be turned off, and pixel PX can switch to HCG mode. When the gain control signal CGS transitions from logic high to logic low, the coupling capacitance of the floating diffusion node FD can be changed, thus changing the voltage of the floating diffusion node FD. For example, a coupling capacitor can be formed between the row line RL to which the gain control signal CGS is applied and the floating diffusion node FD. When the gain control signal CGS changes, the coupling capacitance can change. Therefore, the offset voltage ΔV varies depending on the amount of change in the coupling capacitance. FD The voltage that can be applied to the floating diffuser node FD. In this case, the offset voltage ΔV FD It can be a positive voltage or a negative voltage, and as... Figure 3 As shown, the pixel voltage VPIX can be determined based on the offset voltage ΔV of the floating diffusion node FD. FD Increase or decrease. In other words, the pixel voltage VPIX (i.e., the HCG reset signal) of the second sub-cycle SP2 can have an offset voltage ΔV from the floating diffusion node FD. FD The value obtained by applying the LCG reset signal to the first sub-cycle SP1.

[0073] During the third sub-cycle SP3, pixel PX can operate in HCG mode, and the HCG image signal corresponding to the signal level of pixel PX can be read. When the transmission control signal TS transitions to an active level (e.g., logic high), the charge generated by photodiode PD can be transferred to and stored in the floating diffusion node FD. The driving transistor DX can output the image signal based on the voltage of the floating diffusion node FD according to the amount of charge transferred from photodiode PD. Because pixel PX operates in HCG mode, the HCG image signal can be output as the pixel voltage VPIX, and it can be converted from analog to digital.

[0074] During the fourth sub-cycle SP4, pixel PX can operate in LCG mode and the LCG image signal corresponding to the signal level of pixel PX can be read. When the gain control signal CGS transitions to an active level (e.g., logic high), the gain control transistor CGX can be turned on, and pixel PX can switch to LCG mode. In this case, the coupling capacitance of the floating diffusion node FD can be changed again. In other words, the coupling capacitance of the floating diffusion node FD can be the same as that of the first sub-cycle SP1, and the offset voltage ΔV applied to the floating diffusion node FD during the second sub-cycle SP2 can be removed. FDWhen the transmission control signal TS transitions to an active level (e.g., logic high), the remaining charge generated in the photodiode PD (e.g., the remaining charge that was not transferred to the floating diffusion node FD during the third sub-cycle SP3) can be transferred to the floating diffusion node FD and stored therein. The voltage of the floating diffusion node FD can be varied according to changes in the conversion gain and the amount of additional charge transferred to the photodiode PD during the fourth sub-cycle SP4. An LCG image signal corresponding to the voltage of the floating diffusion node FD can be output as a pixel voltage VPIX, and this signal can be converted from analog to digital.

[0075] The reset level of pixel PX can be different for each of the multiple pixels PX, and can vary over time. Furthermore, the conversion circuitry (e.g., CDS circuit 160 and counter circuit 170) that converts the pixel voltage VPIX into a digital value can have different offsets between columns. Therefore, deviations may occur between read image signals (i.e., pixel values).

[0076] The image sensor 100 can first read a reset signal during the readout period, and then read an image signal based on the reset signal using the CDS method. The reset signal is subtracted from the read image signal to generate the actual image signal (i.e., a pixel value indicating the amount of charge generated by the photodiode PD). Therefore, deviations between pixel values ​​can be reduced. When providing in-scene double conversion gain, a reset signal and an image signal corresponding to HCG and LCG modes, respectively, can be read from pixel PX during the readout period, and actual image signals (e.g., HCG pixel values ​​and LCG pixel values) can be generated relative to the HCG and LCG modes.

[0077] Therefore, as described above, during the first sub-cycle SP1, pixel PX can operate in LCG mode and read the LCG reset signal (referred to as LCG reset ADC); during the second sub-cycle SP2, pixel PX can operate in HCG mode and read the HCG reset signal (referred to as HCG reset ADC); during the third sub-cycle SP3, the HCG image signal (e.g., HCG signal voltage) can be read (referred to as HCG signal ADC); during the fourth sub-cycle SP4, pixel PX can operate in LCG mode and read the LCG image signal (e.g., LCG signal voltage) (referred to as LCG signal ADC). As described above, the LCG reset signal, HCG reset signal, HCG image signal, and LCG image signal can be read sequentially during the readout cycle, and this readout method can be referred to as the Reset-Reset-Signal-Signal (RRSS) readout method.

[0078] As described above, the HCG reset level and the LCG reset level can be different. Therefore, in order to read the HCG image signal and the LCG image signal according to the CDS method, the CDS circuit 160 can perform an automatic zeroing operation during the first sub-cycle SP1 and the second sub-cycle SP2 to sample and hold the LCG reset signal and the HCG reset signal. Then, during the third sub-cycle SP3, the HCG image signal is sampled based on the HCG reset signal, and during the fourth sub-cycle SP4, the LCG image signal is sampled based on the LCG reset signal.

[0079] In addition, in order to subtract the count values ​​of the HCG reset signal and the LCG reset signal from the count values ​​of the read HCG image signal and the read LCG image signal respectively, the counter circuit 170 can store the count values ​​of the LCG reset signal and the HCG reset signal, and selectively use the count values ​​of the HCG reset signal and the LCG reset signal during the third sub-cycle SP3 when the HCG image signal is read and the fourth sub-cycle SP4 when the LCG image signal is read.

[0080] In another embodiment, the image sensor 100 can adjust the HCG reset level to be equal to the LCG reset level. In this embodiment, when the LCG mode changes to the HCG mode during the second sub-cycle SP2, the image sensor 100 can increase or decrease the bias current Ib of the current source CS based on the pixel voltage VPIX output from the pixel PX, so that the HCG reset level is the same as the LCG reset level.

[0081] According to the example embodiment, even if the conversion mode of the pixel PX switches between LCG mode and HCG mode during the readout period to generate high-quality image data in order to provide dual conversion gain, the CDS circuit, bias current controller and counter circuit according to the embodiments of the present disclosure described below can also be provided.

[0082] Figure 4 This is a circuit diagram showing a CDS circuit 160a according to an embodiment of the present disclosure.

[0083] Reference Figure 4 The CDS circuit 160a may include an input stage 161, a switching stage 162, an output stage 163, a current source CSa, and first to third capacitors C1, C2, and C3. Figure 4 In this circuit, CDS circuit 160a includes a comparator (e.g., an OTA circuit), which includes a current source CSa, an input stage 161, and an output stage 163. However, CDS circuit 160a is not limited to this; CDS circuit 160a may also include circuitry connected to output stage 163 (e.g., an OTA circuit, a buffer, an inverter, an amplifier, etc.).

[0084] The current source CSa can provide the bias current that determines the operating point of the CDS circuit 160a. The input stage 161 may include first to third transistors T1, T2, and T3, and first to third capacitors C1, C2, and C3, one end of each of the first to third transistors T1, T2, and T3 may be connected to the current source CSa. The first to third transistors T1, T2, and T3 may be NMOS transistors.

[0085] The ends of the first to third capacitors C1, C2 and C3 can be connected to the gate terminals of the first to third transistors T1, T2 and T3 respectively (i.e., the first input node to the third input node INN, INPL and INPH).

[0086] The pixel voltage VPIX can be applied to the other end of the first capacitor C1. The first capacitor C1 can DC block the pixel voltage VPIX, sample and hold the AC signal of the pixel voltage VPIX, and provide the AC signal to the first transistor T1. The first capacitor C1 can be used to correct the offset of the CDS circuit 160a and the change in the reset level of the pixel voltage VPIX.

[0087] The ramp signal RAMP can be applied to the other end of the second capacitor C2. The second capacitor C2 can DC block the ramp signal RAMP to provide the AC signal of the ramp signal RAMP to the second transistor T2. The second capacitor C2 can be used to correct the offset of the CDS circuit 160a and the level change of the ramp signal VPIX. In addition, the second capacitor C2 can maintain the LCG reset level.

[0088] The ramp signal RAMP can be applied to the other end of the third capacitor C3. The third capacitor C3 can DC block the ramp signal RAMP to provide the AC signal of the ramp signal RAMP to the third transistor T3. The third capacitor C3 can be used to correct the offset of the CDS circuit 160a and the level change of the ramp signal VPIX. In addition, the third capacitor C3 can maintain the HCG reset level.

[0089] Output stage 163 can be implemented as a current mirror circuit including a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 and the fifth transistor T5 can be PMOS transistors. A supply voltage VDDP can be applied to one end of the fourth transistor T4 and the fifth transistor T5. The other end of the fourth transistor T4 can be connected to the comparator node RN, and the other end of the fifth transistor T5 can be connected to the output node ON. The gate terminals of the fourth transistor T4 and the fifth transistor T5 can be connected to the intermediate node MN, and the gate terminals of the fourth transistor T4 and the fifth transistor T5 can be connected to either the comparator node RN or the output node ON.

[0090] Switch stage 162 may include first switch SW1 through seventh switch SW7. Each of the first switch SW1 through seventh switch SW7 may be implemented as an NMOS or a PMOS.

[0091] The first switch SW1 can be connected between the second transistor T2 and the comparator node RN, and can be turned on or off in response to an LCG switch signal. The first switch SW1 can be turned on in response to a valid level of the LCG switch signal indicating LCG mode, and can connect the second transistor T2 to the comparator node RN. Therefore, the second transistor T2 can operate in LCG mode.

[0092] The second switch SW2 can be connected between the third transistor T3 and the comparator node RN, and can be turned on or off in response to the HCG switch signal. The second switch SW2 can be turned on in response to a valid level of the HCG switch signal indicating the HCG mode, and can connect the third transistor T3 to the comparator node RN. Therefore, the third transistor T3 can operate in HCG mode.

[0093] The third switch SW3 can be connected between the first input node INN and the output node ON, and can be turned on or off in response to the AZ1 switch signal. The third switch SW3 can be turned on in response to the valid level of the AZ1 switch signal indicating the first auto-zero cycle, so as to connect the first input node INN to the output node ON.

[0094] The fourth switch SW4 can be connected between the second input node INPL and the comparator node RN, and can be turned on or off in response to the AZ1 switch signal. The fourth switch SW4 can be turned on in response to a valid level of the AZ1 switch signal indicating the first auto-zero cycle, so as to connect the second input node INPL to the comparator node RN.

[0095] The fifth switch SW5 can be connected between the fourth input node INPH and the comparator node RN, and can be turned on or off in response to the AZ2 switch signal. The fifth switch SW5 can be turned on in response to a valid level of the AZ2 switch signal indicating the second auto-zero cycle, so as to connect the third input node INPH to the comparator node RN.

[0096] The sixth switch SW6 can be connected between the comparator node RN and the gate terminals of the fourth transistor T4 and the fifth transistor T5, and can be turned on or off in response to the PS switch signal. The seventh switch SW7 can be connected between the output node ON and the gate terminals of the fourth transistor T4 and the fifth transistor T5, and can be turned on or off in response to the AZ2 switch signal. The PS switch signal and the AZ2 switch signal can have opposite phases. In other words, the PS switch signal can be a complementary signal to the AZ2 switch signal. Therefore, the sixth switch SW6 and the seventh switch SW7 can operate complementaryly. The PS switch signal can be active during the readout cycle, but it can be inactive during the second auto-zero cycle when the AZ2 switch signal is active. Therefore, the sixth switch SW6 can connect the gate terminals of the fourth transistor T4 and the fifth transistor T5 to the comparator node RN during the readout cycle, but the seventh switch SW7 can connect the gate terminals of the fourth transistor T4 and the fifth transistor T5 to the output node ON during the second auto-zero cycle.

[0097] Figure 5 It shows that it is applied to Figure 4 Timing diagram of the switching signals and input node voltages of the CDS circuit 160a. Figures 6A to 9 The operation of CDS circuit 160a according to the switching signal applied to the CDS circuit is shown.

[0098] For ease of description, the provided ( Figure 2 The control signals for pixel PX and the voltage of the floating diffusion node FD. (Refer to the above.) Figure 3 The first sub-cycle SP1 to the fourth sub-cycle SP4 of the readout cycle, the reset signal RS, the gain control signal CGS, and the transmission control signal TS are described, so their detailed descriptions will be omitted.

[0099] Reference Figure 5 The LCG reset ADC can be performed during the first sub-cycle SP1. The LCG and PS switch signals can have active levels, while the HCG and AZ2 switch signals can have inactive levels. The interval from time t0 to time t1 can be the first auto-zero interval AZL. The AZ1 switch signal can have an active level. Therefore, the CDS circuit 160a can perform a first auto-zero operation during the first auto-zero interval AZL, such as... Figure 6AAs shown, the first switch SW1, the third switch SW3, the fourth switch SW4, and the sixth switch SW6 can be turned on. The first transistor T1, the second transistor T2, and the output stage 163 can form an OTA. The first input node INN and the output node ON can be connected. The second input node INPL and the comparator node RN can be connected to each other. The gate terminals of the fourth transistor T4 and the fifth transistor T5 can be connected to the comparator node RN.

[0100] like Figure 6B As shown, in the first automatic zeroing interval AZL, the first input node INN can be the negative input terminal of OTA, the second input node INPL can be the positive input terminal of OTA, the comparison node RN can be the negative output terminal of OTA, and the output node ON can be the positive output terminal of OTA.

[0101] The pixel voltage VPIX (i.e., the LCG reset signal) can be applied to the first input node INN through the first capacitor C1, and the ramp signal RAMP can be applied to the second input node INPL through the second capacitor C2. When the first input node INN and the output node ON are connected to each other, and the second input node INPL and the comparator node RN are connected to each other, the voltages of the first input node INN, the second input node INPL, the comparator node RN, and the output node ON can be equal to the first auto-zero voltage level, and the reset noise of the pixel voltage VPIX and the offset of the CDS circuit 160a can be removed. Here, the first auto-zero voltage level can be determined based on the level of the LCG reset signal applied to the CDS circuit 160a as the pixel voltage VPIX, the level of the ramp signal RAMP, and the offset of the CDS circuit 160a.

[0102] Afterwards, the AZ1 switch signal can transition to an inactive level at time t1, such as... Figure 7 As shown, the third switch SW3 and the fourth switch SW4 can be disconnected. The first input node INN and the output node ON can be disconnected from each other, and the second input node INPL and the comparator node RN can be disconnected from each other. Therefore, sampling of the signals applied to the first input node INN and the second input node INPL, namely the LCG reset signal and the ramp voltage RAMP, can be terminated, and the first auto-zero voltage level in LCG mode can be stored in the second capacitor C2.

[0103] The LCG reset signal can be read during a period determined by the LCG reset signal from time t1 to time t2. The ramp signal RAMP can decrease at a predetermined slope, and the voltage of the second input node INPL can decrease at a predetermined slope according to the ramp signal RAMP. The CDS circuit 160a can output a comparison signal indicating the time from when the ramp signal RAMP begins to decrease to when the voltage of the first input node INN is the same as the voltage of the second input node INPL.

[0104] The HCG reset ADC can be performed during the second sub-cycle SP2. At time t2, the HCG switch signal can transition to an active level, and the LCG switch signal can transition to an inactive level. Figure 8A As shown, the second switch SW2 can be turned on, and the first switch SW1 can be turned off. The first transistor T1, the third transistor T3, and the output stage 163 can form an OTA.

[0105] The interval from time t2 to time t3 can be the second auto-zero interval AZH. During the second auto-zero interval AZH, the AZ2 switch signal can be active, and the PS switch signal can be inactive. Therefore, during the second auto-zero interval AZH, the CDS circuit 160a can perform the second auto-zero operation, and the fifth switch SW5 and the seventh switch SW7 can be turned on. The third input node INPH and the comparator node RN can be connected to each other, and the gate terminals of the fourth transistor T4 and the fifth transistor T5 can be connected to the output node ON.

[0106] like Figure 8B As shown, in the second automatic zeroing interval AZH, the first input node INN can be the positive input terminal of OTA, the third input node INPH can be the negative input terminal of OTA, the comparison node RN can be the positive output terminal of OTA, and the output node ON can be the negative output terminal of OTA.

[0107] Pixel voltage VPIX (i.e., by adjusting the offset voltage ΔV) FD The HCG reset signal obtained by adding the LCG reset signal can be applied to the first input node INN through the first capacitor C1. The first input node INN can have the offset voltage ΔV applied to it. FD The voltage level obtained by applying the first automatic zeroing voltage level. For example, when the offset voltage ΔV FD When the value is negative, the second auto-zero voltage level can be lower than the first auto-zero voltage level.

[0108] The voltage of the first input node INN can be equal to the voltages of the comparator node RN and the third input node INPH. Therefore, by adjusting the offset voltage ΔV... FDThe voltage level obtained by applying the first auto-zero voltage level can be determined as the second auto-zero voltage level.

[0109] When the gain control signal CGS transitions from an active level to an inactive level at time t2, the coupling capacitance of the floating diffusion node FD can be changed, and the voltage of the floating diffusion node FD can be changed (decreased or increased). This can be achieved by adjusting the voltage change of the floating diffusion node FD (i.e., the offset voltage ΔV). FD This is used to change the pixel voltage VPIX. In this case, it may be difficult to predict the offset voltage ΔV. FD Furthermore, it can vary for each pixel PX. When an offset voltage ΔV is applied... FD When a pixel voltage VPIX (e.g., a negative offset voltage or a positive offset voltage) is applied to the CDS circuit 160a, and when the CDS circuit 160a, which has stored a first auto-zero level according to the LCG reset level, is based on the applied offset voltage ΔV FD When the pixel voltage VPIX is operating, the pixel voltage VPIX can be lower than the lowest level of the ramp signal RAMP, or it can be higher than the highest level of the ramp signal RAMP. Therefore, the voltage of the first input node INN, which varies according to the pixel voltage VPIX, can be lower than the lowest level of the second input node INPL, which varies according to the ramp signal RAMP, or it can be higher than the highest level of the second input node INPL, and the output voltage VOUT transition time may not occur. In addition, the input range of the CDS circuit 160a may be very narrow.

[0110] However, as described above, the CDS circuit 160a according to an embodiment of this disclosure can operate in HCG mode during the second auto-zero interval AZH (from time t2 to time t3) and includes a third transistor T3 connected to the third input node INPH, and performs the second auto-zero operation. Therefore, the voltages of the first input node INN and the third input node INPH can be equal to the voltages of the offset voltage ΔV. FD The second auto-zero voltage level is obtained by applying the first auto-zero voltage level.

[0111] Continue to refer to Figure 5 At time t3, the PS switch signal can transition to an active level, and the AZ2 switch signal can transition to an inactive level. Therefore, as... Figure 9As shown, the fifth switch SW5 and the seventh switch SW7 can be turned off, and the sixth switch SW6 can be turned on. The gate terminals of the fourth transistor T4 and the fifth transistor T5 can be connected to the comparator node RN, and the third input node INPH and the comparator node RN can be disconnected from each other. Therefore, sampling of the HCG reset signal applied to the first input node INN can be terminated, and the second auto-zero voltage level in HCG mode can be stored in the third capacitor C3.

[0112] The HCG reset signal can be read during the defined period from time t3 to time t4. The ramp signal RAMP can decrease at a predetermined slope, and the voltage of the third input node INPH can decrease at a predetermined slope based on the ramp signal RAMP. The CDS circuit 160a can output a comparison signal indicating the time from the start of the ramp signal RAMP's decrease to the time when the voltage of the first input node INN equals the voltage of the third input node INPH.

[0113] The HCG signal ADC can be executed during the third sub-cycle SP3 (from time t4 to time t8). The comparator circuit 160a can have the same connectivity during the third sub-cycle SP3 as before time t4, and can sample the pixel voltage VPIX (i.e., the HCG image signal) based on the second auto-zero voltage level. The voltage of the first input node INN can vary according to the pixel voltage VPIX, and the voltage of the third input node INPH can vary according to the ramp signal RAMP. The CDS circuit 160a can output a comparator signal indicating the time from the start of the ramp signal RAMP's decline to the time when the voltage of the first input node INN equals the voltage of the third input node INPH.

[0114] The LCG signal ADC can be executed during the fourth sub-cycle SP4. At time t8, the LCG switch signal can transition to an active level, and the HCG switch signal can transition to an inactive level. Therefore, as... Figure 7 As shown, the second switch SW2 can be turned off, the first switch SW1 can be turned on, and the first transistor T1, the second transistor T2, and the output stage 163 can constitute an OTA. The first auto-zero voltage level in LCG mode is stored in the second capacitor C2, so the comparator circuit 160a can sample the pixel voltage VPIX (i.e., the LCG image signal) based on the first auto-zero voltage level. The voltage of the first input node INN can vary according to the pixel voltage VPIX, and the voltage of the second input node INPL can vary according to the ramp signal RAMP. The CDS circuit 160a can output a comparator signal indicating the time from when the ramp signal RAMP begins to fall until the voltage of the first input node INN is equal to the voltage of the second input node INPH.

[0115] As referenced above Figures 4 to 9 The CDS circuit 160a described according to an embodiment of the present disclosure may include a first transistor T1 connected to a first input node INN and a second transistor T2 connected to a second input node INPL, operating as a differential input pair of OTA in LCG mode; and a first transistor T1 and a third transistor T3 connected to a third input node INPH, operating as a differential input pair of OTA in HCG mode. The CDS circuit 160a can determine a first auto-zero voltage level in LCG mode by performing a first auto-zero operation based on an LCG reset signal during a first auto-zero interval, and in HCG mode by adjusting the offset voltage ΔV included in the HCG reset level during a second auto-zero interval. FD The second automatic zeroing voltage level is determined by applying the first automatic zeroing voltage level.

[0116] like Figure 4 As shown, in the CDS circuit 160a according to an embodiment of the present disclosure, the input stage 161 may include a differential input pair comprising two transistors (e.g., a first transistor T1 and a second transistor T2) and a pair of capacitors (e.g., a first capacitor C1 and a second capacitor C2), and may also include a third transistor T3 and a third capacitor C3. Therefore, compared to a CDS circuit comprising two differential input pairs and two pairs of capacitors (i.e., two input stages) for receiving HCG signals (e.g., HCG reset signals and HCG image signals) and LCG signals (e.g., LCG reset signals and LCG image signals), respectively, the size of the CDS circuit 160a can be reduced.

[0117] Figure 10 This is a diagram illustrating a pixel array 110a of an image sensor according to an embodiment of the present disclosure. For ease of description, one column of the pixel array 110a is shown.

[0118] Reference Figure 10 The pixel array 110a may include multiple pixels PX, a current source CS, and a bias current controller BCC. Figure 10 For ease of description, a column line CL and components connected to the column line CL (e.g., multiple pixels PX, current source CS, and bias current controller BCC) are shown, but this disclosure is not limited thereto, and as referenced Figure 1 As described, pixel array 110a may include multiple column lines CL and components respectively connected to the multiple column lines CL.

[0119] The driving transistor DX of pixel PX can operate as a source follower based on a bias current Ib supplied from the current source CS. Since a pixel PX is selected from among the multiple pixels PX connected to the column line CL, the bias current Ib can flow through the driving transistor DX of the selected pixel PX. In other words, the bias current Ib can be the drain current of the driving transistor DX.

[0120] The gain control signal CGS can be received through one of the multiple row lines RL, and coupling capacitors Cc1 and Cc2 can be formed between the row line RL and other nodes. When pixel PX switches from LCG mode to HCG mode or vice versa, the coupling capacitance changes with the gain control signal CGS. Offset voltage ΔV FD The voltage applied to the floating diffusion node FD can be adjusted by changing the coupling capacitance and injecting random charge. The offset voltage ΔV FD It can be a positive or negative voltage. The pixel voltage VPIX is controlled by the offset voltage ΔV. FD This can be changed, and the LCG reset signal and HCG reset signal output by the pixel voltage VPIX can be different.

[0121] In the example embodiment, when pixel PX switches from LCG mode to HCG mode or vice versa, the bias current controller BCC can adjust the bias current Ib of the current source CS based on the pixel voltage VPIX, thereby eliminating the offset voltage ΔV from the pixel voltage VPIX. FD Therefore, the LCG reset signal can be maintained to be basically the same as the HCG reset signal.

[0122] For example, when pixel PX switches from LCG mode to HCG mode, and when the voltage of the floating diffusion node FD decreases by the offset voltage ΔV FD At this time, the pixel voltage VPIX can also decrease. In this case, the bias current controller BCC can reduce the bias current Ib based on the decrease in pixel voltage VPIX. As the bias current Ib decreases, the pixel voltage VPIX can increase. As described above, the bias current controller BCC can adjust the bias current Ib based on negative feedback operation, thereby preventing the pixel voltage VPIX from increasing due to the offset voltage ΔV. FD But there has been a substantial change.

[0123] Figure 11 This is a circuit diagram illustrating a current source CS and a bias current controller BCC disposed in a pixel array according to an embodiment of the present disclosure. For ease of description, some configurations of selected pixels PX are shown together, and column lines are omitted.

[0124] Reference Figure 11The current source CS may include a reference transistor Tr and a bias transistor Tb. The reference transistor Tr can generate a reference current Ir based on a first bias voltage Vb1 applied to its gate terminal. The bias transistor Tb can generate a bias current Ib based on a second bias voltage Vb2 applied to its gate terminal. One end of the bias transistor Tb can be connected to the source terminal of the driving transistor DX of the pixel PX, and the other end of the bias transistor Tb can be connected to one end of the reference transistor Tr.

[0125] The bias current controller BCC may include a feedback transistor Tf, an amplifier AMP, a feedback switch SWf, a sampling switch SWS, an automatic zeroing switch SWA, a sampling capacitor Cs, and a storage capacitor Cst.

[0126] The feedback switch SWf can be turned on in response to the effective level of the OFF switch signal. When the feedback switch SWf is turned on, the sampling capacitor Cs can DC block the pixel voltage VPIX, so that the AC signal of the pixel voltage VPIX is provided to the amplifier AMP.

[0127] The automatic zeroing switch SWA can be connected between the first input terminal (-) and the output terminal of the amplifier AMP. It can be turned on in response to the effective level of the AZ switch signal and can perform automatic zeroing operation to eliminate the offset of the amplifier AMP.

[0128] The amplifier AMP amplifies the voltage difference between the input voltage Vin received through the first input terminal (-) and the second bias voltage Vb2 received through the second input terminal (+), and outputs the amplified voltage as the output voltage Vout. The input voltage Vin can be changed according to the voltage stored in the sampling capacitor Cs.

[0129] The sampling switch SWS can be turned on in response to the effective level of the SM switch signal, and can store the output voltage Vout in the storage capacitor Cst. Therefore, the sampling voltage Vs can be the same as the output voltage Vout.

[0130] The feedback transistor Tf generates a feedback current If based on the sampled voltage Vs applied to its gate terminal. The power supply voltage VDDP can be applied to one end of the feedback transistor Tf, and the other end of Tf can be connected to one end of the reference transistor Tr. The sum of the bias current Ib and the feedback current If can be the same as the reference current Ir, which can be constant, while the bias current Ib and the feedback current If can vary according to the sampled voltage Vs. Figure 12 and Figures 13A to 13C The operation of the current source CS and the bias current controller BCC is described in detail.

[0131] Figure 12 This is a timing diagram of the bias current controller BCC according to an embodiment of the present disclosure. Figures 13A to 13C The operation of the bias current controller BCC according to the switching signal applied to the bias current controller BCC is shown.

[0132] For ease of description, the provided ( Figure 2 The control signals for pixel PX and the voltage of the floating diffusion node FD. (Refer to the above.) Figure 3 The first sub-cycle SP1 to the fourth sub-cycle SP4 of the readout cycle, the reset signal RS, the gain control signal CGS, and the transmission control signal TS are described, so their detailed descriptions will be omitted.

[0133] Reference Figure 12 During the first sub-cycle SP1 of the LCG reset ADC, the OFF and SM switch signals can have invalid levels, while the AZ switch signal can have an active level. For example... Figure 13A As shown, the feedback switch SWf and sampling switch SWS can be disconnected, and the auto-zero switch SWA can be turned on. The second bias voltage Vb2 can be received through the first input terminal (+) of the amplifier AMP, and according to the auto-zero operation, the first input terminal (+), the second input terminal (-), and the output terminal of the amplifier AMP can have the voltage level of the second bias voltage Vb2, and the offset of the amplifier AMP can be eliminated. In this case, the sampling voltage Vs can have the voltage level of the second bias voltage Vb2, and the bias current Ib can be the same as the feedback current If.

[0134] At the beginning of the second sub-cycle SP2 of the HCG reset ADC, for example at time t0, the OFF switch signal and the SM switch signal can transition to an active level, while the AZ switch signal can transition to an inactive level. Figure 13B As shown, the feedback switch SWf and the sampling switch SWS can be turned on, and the automatic zeroing switch SWA can be turned off.

[0135] The voltage of the floating diffusion node FD can reduce the offset voltage ΔV FD Furthermore, the pixel voltage VPIX can also reduce the offset voltage ΔV. FD The sampling capacitor Cs samples and holds the AC component of the pixel voltage VPIX. The voltage level of the input voltage Vin can be reduced by the offset voltage ΔV from the first bias voltage Vb1. FDThe amplifier AMP amplifies and outputs the voltage difference between the input voltage Vin and the first bias voltage Vb1. Therefore, the output voltage Vout can be increased. The output voltage Vout can be applied to the feedback transistor Tf as the sampling voltage Vs. Therefore, the feedback current If can be increased, and the bias current Ib can be decreased. The sampling voltage Vs can be stored in the storage capacitor Cst.

[0136] As the bias current Ib decreases, the pixel voltage VPIX and the input voltage Vin can increase, while the output voltage Vout can decrease. Due to the negative feedback operation of the bias current controller BCC, the pixel voltage Vout (e.g., the HCG reset signal) can remain the same as the previous level (e.g., the LCG reset signal).

[0137] Afterwards, the OFF switch signal and the SM switch signal can transition to an invalid level at time t1. For example... Figure 13C As shown, the feedback switch SWf, sampling switch SWS, and auto-zero switch SWA can be disconnected. An HCG reset ADC can be performed after time t1, and an HCG signal ADC can be performed during the third sub-cycle SP3.

[0138] Subsequently, the AZ switch signal can transition to an active level during the fourth sub-cycle SP4 of the LCG signal ADC, and the amplifier AMP can perform an auto-zero operation as described relative to the first sub-cycle SP1. The output voltage Vout and the sampling voltage Vs can have the voltage level of the second bias voltage Vb2, and the bias current Ib can be the same as the feedback current If. The LCG signal ADC can be executed under the same conditions as the first sub-cycle SP4.

[0139] According to reference Figures 10 to 13C The negative feedback operation of the bias current controller BCC according to an embodiment of the present disclosure is described, even if the conversion gain mode of pixel PX changes, the offset voltage ΔV of the floating diffusion node FD. FD The LCG reset signal can be maintained at essentially the same as the HCG reset signal without applying the pixel voltage VPIX.

[0140] When the LCG reset signal differs from the HCG reset signal, two CDS circuits can be used, or the CDS circuit needs to include two differential input pairs to store the auto-zero voltage level based on the LCG reset signal and the auto-zero voltage level based on the HCG reset signal. Therefore, the area of ​​the ADC circuit 150 increases. However, in the pixel array 110a according to an embodiment of this disclosure, since the LCG reset signal is maintained substantially the same as the HCG reset signal according to the negative feedback operation of the bias current controller BCC, the CDS circuit can perform an auto-zero operation during the first sub-cycle SP1 to store the auto-zero voltage level based on the LCG reset signal. Therefore, one CDS circuit including one differential input pair can be used. Thus, the image sensor 100 can read the LCG and HCG signals from the pixel PX supporting dual conversion gain according to the RRSS readout method without increasing the area of ​​the ADC circuit 150. Furthermore, since no auto-zero operation is required during the second sub-cycle SP2, the readout period can be shortened.

[0141] Figure 14 This is a diagram illustrating a counter circuit 170a according to an embodiment of the present disclosure. Figure 15 It is shown Figure 14 The timing diagram of the operation of the counter circuit 170a.

[0142] Reference Figure 14 The counter circuit 170a may include a latch LAT, a first memory MEM1, a second memory MEM2, a selector SLT, and an adder AD. The counter circuit 170a may also include a flip-flop FF. The counter circuit 170a may receive a count code CCD from the count code generator 140 and a comparison signal SCP from the CDS circuit 160, and generates HCG and LCG pixel values ​​based on the count code CCD and the comparison signal SCP. Figure 14 In this embodiment, the counter circuit 170a receives a comparison signal SCP from a CDS circuit 160, but is not limited thereto. In this embodiment, the counter circuit 170a may receive the comparison signal from a CDS circuit that processes LCG signals (e.g., LCG reset signal and LCG image signal) and a CDS circuit that processes HCG signals (e.g., HCG reset signal and HCG image signal).

[0143] In an embodiment, the counter code generator 140 may be a Gray code generator, and a Gray code having a code value that increases over time can be provided to the counter circuit 170a as a counter code CCD. (See also...) Figure 15The counter code generator 140 can output a counter code CCD in response to the count enable signal CNT_EN during the first sub-cycle SP1 to the fourth sub-cycle SP4 of the readout cycle. The code value of the counter code CCD can increase over time. The counter code CCD can include n bits of data (b[n-1:0]) (n is a positive integer equal to or greater than 2). The n bits of data b[n-1:0] of the counter code CCD can be simultaneously provided to the latch LAT.

[0144] The latch (LAT) can receive a comparison signal (SCP) and a counter code (CCD). It latches the code value of the counter code (CCD) at the time of a level transition in the comparison signal (SCP) (e.g., from logic high to logic low), and outputs the latched code value as the count value. The latch (LAT) can be an n-bit latch and can include n 1-bit latches, for example, n cell latches. The count value can include n-bit count data Cb[n-1:0], and the latch (LAT1) can output the n-bit count data Cb[n-1:0] sequentially, one bit at a time.

[0145] The latch LAT can sequentially receive a first comparison signal SCP1 based on the LCG reset signal, a second comparison signal SCP2 based on the HCG reset signal, a third comparison signal SCP3 based on the HCG image signal, and a fourth comparison signal SCP4 based on the LCG image signal from the CDS circuit 160, and can output a first count value to a fourth count value based on the first comparison signal SCP1 to the fourth comparison signal SCP4 respectively. The first count value can be the LCG reset value RST relative to the LCG reset signal. L The second count value can be the HCG reset value RST relative to the HCG reset signal. H The third count value can be the HCG signal value SIG relative to the HCG image signal. H The fourth count value can be the LCG signal value SIG relative to the LCG image signal. L .

[0146] The first memory MEM1 and the second memory MEM2 can be implemented as storage devices such as latches or SRAM. LCG reset value RST L (That is, the first count value) can be stored in the first memory MEM1. In this case, the LCG reset value RST can be stored. L negative value -RST L (Hereinafter referred to as the negative LCG reset value). For example, the LCG reset value RST. L It can be converted to binary code, and the two's complement value of the binary code can be stored in the first memory MEM1. HCG reset value RST H(That is, the second count value) can be stored in the second memory MEM2. In this case, the HCG reset value RST can be stored. H negative value -RST H (Hereinafter referred to as the negative HCG reset value).

[0147] HCG signal value SIG H (That is, the third count value) can be output from latch LAT to adder AD. In this case, selector SLT can select the negative HCG reset value -RST stored in the second memory MEM2. H And reset the negative HCG value -RST H Provided to adder AD. Selector SLT can be implemented as, for example, a multiplexer, and can receive control signals (e.g., selection signals) for selector SLT from timing controller 190.

[0148] Adder A / D can process HCG signal value SIG H and negative HCG reset value - RST H Summation. In this embodiment, the adder AD can be implemented as a 1-bit adder, which can receive the HCG signal value SIG sequentially from the least significant bit (LSB) in 1-bit increments. H and negative HCG reset value - RST H And for the HCG signal value SIG H and negative HCG reset value - RST H Summation. In this case, the carry generated by the summation can be stored in the flip-flop FF and provided to the adder AD when summing the next bit.

[0149] HCG signal value SIG H and negative HCG reset value - RST H SIG summation H -RST H (For example, HCG pixel value PXD) H The data can be stored in the second memory MEM2 and subsequently output as output data Dout when the output switch SWO is turned on. It can be obtained from the timing controller 190 or the column decoder 182. Figure 1 (in) Receives the control signal (e.g., switch signal) of the output switch SWO.

[0150] LCG signal value SIG L (That is, the fourth count value) can be output from latch LAT to adder AD. Selector SLT can select the negative LCG reset value -RST stored in the first memory MEM1. L And reset the negative LCG value to -RST. L Provided to adder AD.

[0151] Adder A / D can process LCG signal value SIG L and negative LCG reset value - RST L Summation. The summation value is SIG. L –RST L (For example, LCG pixel value PXD) L It can be stored in the second memory MEM2 and then output as output data Dout when the output switch SWO is turned on.

[0152] As described above, the counter circuit 170a according to the embodiments of this disclosure can respectively reset the negative LCG value -RST. L and negative HCG reset value - RST H Stored in the first memory MEM1 and the second memory MEM2, and when generating LCG pixel values ​​PXD L and HCG pixel value PXD H When (i.e., when performing an addition operation), the selector SLT can reset the negative LCG value -RST. L and negative HCG reset value - RST H The data is selectively provided to the adder AD. Therefore, a data operation path (e.g., latch LAT, adder AD, and trigger FF) can generate the LCG pixel value PXD. L and HCG pixel value PXD H Therefore, two counter circuits, each including a data operation path, generate LCG pixel values ​​PXD respectively. L and HCG pixel value PXD H Compared to the circuit area under the previous case, the circuit area of ​​the counter circuit 170a can be reduced.

[0153] Figure 16 This is a diagram illustrating a counter circuit 170b according to an embodiment of the present disclosure. Figure 17 It is shown Figure 16 Timing diagram of the operation of counter circuit 170b.

[0154] Reference Figure 16 The counter circuit 170b may include a first counter CB1 and a second counter CB2. The first counter CB1 may include a latch LAT, a first memory MEM1, a second memory MEM2, a first selector SLT1, and an adder AD. The first counter CB1 may also include a flip-flop FF. The second counter CB2 may include a ripple counter RCNT, a third memory MEM3, a fourth memory MEM4, and a second selector SLT2.

[0155] Counter circuit 170b can generate HCG pixel values ​​and LCG pixel values ​​based on the counter code CCD received from counter code generator 140b and the comparison signal SCP received from CDS circuit 160. First counter CB1 can generate the low-order bits of the HCG and LCG pixel values. Second counter CB2 can generate the high-order bits of the HCG and LCG pixel values. For example, when each of the HCG and LCG pixel values ​​includes n bits of data, first counter CB1 can generate the low m bits (m is a positive integer less than n), and second counter CB2 can generate the high (nm) bits. In the following text, Figure 17 In its description, the count value and summation value described in conjunction with the configuration of the first counter CB1 (e.g., latch LAT, first memory MEM1, and second memory MEM2) can represent the LCG reset value RST. L HCG reset value RST H HCG signal value SIG H LCG signal value SIG L HCG pixel value PXD H and LCG pixel value PXD L The lower n bits of the corresponding value, combined with the count value and summation value described by the configuration of the second counter CB2 (e.g., ripple counter RCNT, third memory MEM3, and fourth memory MEM4), can represent the LCG reset value RST. L HCG reset value RST H HCG signal value SIG H LCG signal value SIG L HCG pixel value PXD H and LCG pixel value PXD L The high (nm) bits of the corresponding value.

[0156] Refer to together Figure 17 The counter code generator 140b can output a counter code CCD in response to the count enable signal CNT_EN during the first sub-cycle SP1 to the fourth sub-cycle SP4 of the readout cycle. The code value of the counter code CCD can increase over time. The counter code CCD can include m bits of data b[m-1:0]. The m bits of data b[m-1:0] of the counter code CCD can be simultaneously provided to the latch LAT.

[0157] Operation and reference of the first counter CB1 Figure 15 and Figure 16The operation of the counter circuit 170 described is essentially the same. The counter circuit 170 can generate HCG pixel values ​​and LCG pixel values ​​based on a counting code CCD including n-bit data b[n-1:0]. The first counter CB1 can generate the lower m bits of each of the HCG and LCG pixel values ​​based on a counting code CCD including n-bit data b[n-1:0]. A detailed description of the first counter CB1 will be omitted.

[0158] The latch LAT can provide at least one bit of data (e.g., the m-th bit b[m-1] of the m-bit data b[m-1:0] of the counter code CCD) to the ripple counter RCNT. Each of the m-bit data b[m-1:0] of the counter code CCD can be switched at a predetermined frequency, with the LSB data (i.e., the first bit b[0]) having the highest switching frequency and the m-bit data b[m-1:0] having the lowest switching frequency. The latch LAT can provide the m-th bit of data b[m-1] of the counter code CCD to the ripple counter RCNT until the comparison signal SCP changes from logic high to logic low.

[0159] The second counter CB2 can generate the high (nm) bit data of each of the HCG and LCG pixel values ​​based on the m-th bit data b[m-1] of the counter code CCD received from the latch LAT.

[0160] The ripple counter RCNT generates a count value by counting the number of switches of the m-th bit data b[m-1] of the counting code CCD. The count value may include (nm) bits of count data Cb[n-1:m]. In an embodiment, the ripple counter RCNT can be implemented as a set-reset (SR) trigger (i.e., a trigger with SR functionality).

[0161] Reference Figure 17 The ripple counter RCNT can perform up counting based on the m-th bit data b[m] received in each of the first comparison signals SCP1 to the fourth comparison signal SCP4 during the first sub-cycle SP1 to the fourth sub-cycle SP4, thereby generating the first to fourth count values, which respectively include (nm) bits of count data Cb[n-1:m].

[0162] The ripple counter RCNT can generate a first count value (e.g., LCG reset value RST) for the LCG reset signal during the first sub-cycle SP1. L The ripple counter RCNT can reset the LCG value to RST. L Perform bitwise inversion (BWI). This generates the LCG reset value RST. L negative value -RST L(Hereinafter referred to as the negative LCG reset value), and the negative LCG reset value -RST L It can be stored in the third memory MEM3.

[0163] The ripple counter RCNT can be reset and can generate a second count value (e.g., the HCG reset value RST) with respect to the HCG reset signal during the second sub-cycle SP2. H The ripple counter RCNT can reset the HCG value to RST. H Execute BWI to generate HCG reset value RST H negative value -RST H (Hereinafter referred to as the negative HCG reset value). Negative HCG reset value - RST H It can be stored in the fourth memory MEM4.

[0164] The ripple counter RCNT generates a third count value during the third sub-cycle SP3. The ripple counter RCNT can execute a reset from the negative HCG value -RST. H Start counting upwards and generate the HCG signal value SIG. H and negative HCG reset value - RST H SIG summation H -RST H As the third counting value. The third counting value can be the HCG pixel value PXD. H It can be stored in the fourth memory MEM4, and can then be output as output data Dout when the first output switch SWO1 is turned on.

[0165] During the fourth sub-cycle SP4, the second selector SLT2 can store the negative LCG reset value -RST in the third memory MEM3. L Provided to the ripple counter RCNT. The ripple counter RCNT can be executed from the negative LCG reset value -RST. L Start counting upwards and generate the LCG signal value SIG. L and negative LCG signal value -RST L SIG summation L -RST H As the fourth count value. The fourth count value can be the LCG pixel value PXD. L It is stored in the fourth memory MEM4 and is subsequently output as output data Dout when the second output switch SWO2 is turned on.

[0166] The first output switch SWO1 can be turned on simultaneously with the second output switch SWO2, and the HCG pixel value PXD output from the first counter CB1 will be displayed. H and LCG pixel value PXDL The lower n bits of the output data Dout can be used to construct the HCG pixel value PXD output from the second counter CB2. H and LCG pixel value PXD L It can form the high (mn) bits of the output data Dout.

[0167] As described above, the counter circuit 170b according to embodiments of the present disclosure can generate the low m bits of pixel value data based on the latching operation of the counting code CCD, and generate the high (nm) bits of pixel value data based on the up-counting operation, thereby generating a pixel value including n bits of data (e.g., HCG pixel value PXD). H and LCG pixel value PXD L ).

[0168] Figure 18 and Figure 19 It is a block diagram of an electronic device 1000 including multi-camera modules 1100a, 1100b and 1100c. Figure 20 yes Figure 18 Detailed block diagram of camera module 1100b.

[0169] Reference Figure 18 The electronic device 1000 may include a camera module group 1100, an application processor 1200, a power management integrated circuit (PMIC) 1300, and an external memory 1400.

[0170] Camera module group 1100 may include multiple camera modules 1100a, 1100b, and 1100c. Although an embodiment with three camera modules 1100a, 1100b, and 1100c arranged is shown in the figures, the embodiments are not limited thereto. In some embodiments, camera module group 1100 may be modified to include only two camera modules or to include k camera modules (k is a natural number of 4 or greater).

[0171] In the following text, reference will be made to Figure 20 The detailed configuration of camera module 1100b is described in more detail, but the following description can be applied equally to other camera modules 1100a and 1100c according to the embodiments.

[0172] Reference Figure 20 The camera module 1100b may include a prism 1105, an optical path bending element (OPFE) 1110, an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0173] The prism 1105 may include a reflective surface 1107 of a light-reflecting material that deforms the path of light L incident from the outside.

[0174] In some embodiments, prism 1105 can change the path of light L incident in the first direction X to a second direction Y perpendicular to the first direction X. Additionally, prism 1105 can rotate the reflective surface 1107 of the light-reflecting material relative to the central axis 1106 in direction A, or rotate the central axis 1106 in direction B, to change the path of light L incident in the first direction X to a second direction Y perpendicular to the first direction X. In this case, OPFE 1110 can also move in a third direction Z perpendicular to the first direction X and the second direction Y.

[0175] In some embodiments, as shown, the maximum rotation angle of prism 1105 in the A direction may be equal to or less than 15 degrees in the positive (+) A direction and may be greater than 15 degrees in the negative (-) A direction, but the embodiments are not limited thereto.

[0176] In some embodiments, the prism 1105 can move between 20 degrees, between 10 degrees and 20 degrees, or between 15 degrees and 20 degrees in the positive (+) or negative (-) B direction, wherein the angle of movement can be the same as the angle of movement in the positive (+) or negative (-) B direction, or can be almost similar to the angle of movement within a range of 1 degree.

[0177] In some embodiments, the prism 1105 can move the reflective surface 1107 of the light-reflecting material in a third direction (e.g., the Z direction) parallel to the direction along which the central axis 1106 extends.

[0178] In some embodiments, the camera module 1100b may include two or more prisms through which the path of light L incident in the first direction X may be transformed into a second direction Y perpendicular to the first direction X, or again into the first direction X or a third direction Z, and again into the second direction Y.

[0179] OPFE 1110 may include, for example, a group of m optical lenses (where m is a natural number). The M lenses may be moved in the second direction Y to change the optical zoom ratio of camera module 1100b. For example, when the basic optical zoom ratio of camera module 1100b is Z, and when the m optical lenses included in OPFE 1110 are moved, the optical zoom ratio of camera module 1100b may become 3Z, 5Z, or greater than 5Z.

[0180] Actuator 1130 can move OPFE 1110 or optical lens to a specific position. For example, actuator 1130 can adjust the position of optical lens so that image sensor 1142 is located at the focal length of optical lens for precise sensing.

[0181] Image sensing device 1140 may include image sensor 1142, control logic 1144, and memory 1146. Image sensor 1142 can use light L provided through an optical lens to sense an image of the target. (See reference...) Figures 1 to 17 The image sensor 100 described herein and at least one of its components (e.g., a pixel PX supporting dual conversion gain) Figure 3 (middle), CDS circuit 160a ( Figure 4 (middle), bias current controller BCC ( Figure 11 (middle) and counter circuit 170a ( Figure 14 (middle) or 170b ( Figure 16 The image sensor 1142 can be applied to the image sensor 1142. The image sensor 1142 can generate image data with high dynamic range by merging HCG image data and LCG image data.

[0182] Control logic 1144 can control the overall operation of camera module 1100b and process the sensed images. For example, control logic 1144 can control the operation of camera module 1100b according to the control signal provided through control signal line CSLb, and extract image data corresponding to a specific image (e.g., a person's face, arms, legs, etc. in the image) from the sensed images.

[0183] In some embodiments, control logic 1144 may perform image processing, such as encoding and denoising of the sensed image.

[0184] The memory 1146 may store information such as calibration data 1147 to be used in the operation of the camera module 1100b. Calibration data 1147 may be information used by the camera module 1100b when generating image data using light L provided from an external source, and may include, for example, information about rotation, information about focal length, information about the optical axis, etc. When the camera module 1100b is implemented as a multi-state camera whose focal length changes according to the position of the optical lens, the calibration data 1147 may include information related to the focal length value and autofocus for each position (or state) of the optical lens.

[0185] The storage unit 1150 can store image data sensed by the image sensor 1142. The storage unit 1150 can be disposed outside the image sensing device 1140 and can be implemented as a stack with the sensor chip constituting the image sensing device 1140. In some embodiments, the image sensor 1142 can be configured as a first chip, and the control logic 1144, the storage unit 1150, and the memory 1146 can be configured as a second chip, such that the storage unit 1150 can be implemented as a stack with the first chip and the second chip.

[0186] In some embodiments, the storage unit 1150 may be implemented as an electrically erasable programmable read-only memory (EEPROM), but the embodiments are not limited thereto. In some embodiments, the image sensor 1142 may be configured as a pixel array, and the control logic 1144 may include an analog-to-digital converter and an image signal processor for processing the sensed image.

[0187] Refer to together Figure 18 and Figure 20 In some embodiments, each of the plurality of camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the plurality of camera modules 1100a, 1100b, and 1100c may include the same or different calibration data 1147 depending on the operation of the actuator 1130 included therein.

[0188] In some embodiments, one of the multiple camera modules 1100a, 1100b and 1100c (e.g. 1100b) may include a bent lens type camera module with prism 1105 and OPFE 1110 as described above, and the remaining camera modules (e.g. 1100a and 1100c) may be vertical camera modules without prism 1105 and OPFE 1110, but the embodiments are not limited thereto.

[0189] In some embodiments, one of the plurality of camera modules 1100a, 1100b, and 1100c (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, infrared (IR). In this case, the application processor 1200 may merge image data provided from the depth camera with image data provided from another camera module (e.g., 1100a or 1100b) to generate a 3D depth image.

[0190] In some embodiments, at least two camera modules (e.g., 1100a and 1100b) of the plurality of camera modules 1100a, 1100b, and 1100c may have different fields of view. For example, camera module 1100a may be an ultra-wide camera, camera module 1100b may be a wide camera, and camera module 1100c may be a telephoto camera, but the embodiments are not limited thereto. In this case, for example, the optical lenses of at least two camera modules (e.g., 1100a and 1100b) of the plurality of camera modules 1100a, 1100b, and 1100c may be different from each other, but the embodiments are not limited thereto.

[0191] Additionally, in some embodiments, the multiple camera modules 1100a, 1100b, and 1100c may have different fields of view. In this case, the optical lenses included in the multiple camera modules 1100a, 1100b, and 1100c may also be different from each other, but the embodiments are not limited thereto.

[0192] In some embodiments, the plurality of camera modules 1100a, 1100b, and 1100c can be physically separated and configured from each other. That is, the sensing area of ​​an image sensor 1142 is not divided and used by the plurality of camera modules 1100a, 1100b, and 1100c, but an independent image sensor 1142 can be configured in each of the plurality of camera modules 1100a, 1100b, and 1100c.

[0193] Return to reference Figure 18 The application processor 1200 may include an image processing device 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 may be implemented separately from the multiple camera modules 1100a, 1100b, and 1100c. For example, the application processor 1200 may be implemented as a semiconductor chip separate from the multiple camera modules 1100a, 1100b, and 1100c.

[0194] The image processing apparatus 1210 may include a plurality of sub-image processors 1212a, 1212b and 1212c, an image generator 1214 and a camera module controller 1216.

[0195] The number of multiple sub-image processors 1212a, 1212b and 1212c included in the image processing device 1210 can correspond to the number of multiple camera modules 1100a, 1100b and 1100c.

[0196] Image data generated from camera module 1100a can be provided to sub-image processor 1212a via image signal line ISL1, image data generated from camera module 1100b can be provided to sub-image processor 1212b via image signal line ISL2, and image data generated from camera module 1100c can be provided to sub-image processor 1212c via image signal line ISL2. Such image data transmission can be performed using, for example, a camera serial interface based on the Mobile Industrial Processor Interface (MIPI), but is not limited thereto.

[0197] In some embodiments, a sub-image processor can be configured to correspond to multiple camera modules. For example, as shown, sub-image processors 1212a and 1212c are not implemented separately from each other, but can be integrated and implemented such that the sub-image processor and image data provided from camera modules 1100a and 1100c can be selected by selection elements (e.g., multiplexers), and then provided to the integrated sub-image processor. In this case, sub-image processor 1212b may not be integrated and can receive image data from camera module 1100b.

[0198] In some embodiments, image data generated from camera module 1100a can be provided to sub-image processor 1212a via image signal line ISL1a, image data generated from camera module 1100b can be provided to sub-image processor 1212b via image signal line ISL1b, and image data generated from camera module 1100c can be provided to sub-image processor 1212c via image signal line ISL1c. Furthermore, when image data processed by sub-image processor 1212b can be directly provided to image generator 1214, either the image data processed by sub-image processor 1212a or the image data processed by sub-image processor 1212c can be selected by a selection element (e.g., a multiplexer) and then provided to image generator 1214.

[0199] Each of the sub-image processors 1212a, 1212b and 1212c can perform image processing such as bad pixel correction, 3A adjustment (autofocus correction, auto white balance and auto exposure), noise reduction, sharpening, gamma control, mosaic and so on on the image data provided from the camera modules 1100a, 1100b and 1100c.

[0200] In some embodiments, remosaic signal processing may be performed by each of the camera modules 1100a, 1100b and 1100c, and then provided to the sub-image processors 1212a, 1212b and 1212c, respectively.

[0201] Image data processed by each of the sub-image processors 1212a, 1212b, and 1212c can be provided to the image generator 1214. The image generator 1214 can generate an output image based on image generation information or a pattern signal using the image data provided from each of the sub-image processors 1212a, 1212b, and 1212c.

[0202] Specifically, image generator 1214 can generate an output image by merging at least some of the image data provided from sub-image processors 1212a, 1212b, and 1212c, based on image generation information or a mode signal. Alternatively, image generator 1214 can generate an output image by selecting any one of the image data provided from sub-image processors 1212a, 1212b, and 1212c, based on image generation information or a mode signal.

[0203] In some embodiments, image generation information may include a zoom signal or zoom factor. Additionally, in some embodiments, the mode signal may be, for example, a signal based on a mode selected by the user.

[0204] When the image generation information is a zoom signal (zoom factor) and camera modules 1100a, 1100b, and 1100c have different viewing fields, image generator 1214 can perform different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, image generator 1214 can use the image data output from sub-image processor 1212a and sub-image processor 1212b to generate an output image from the image data output from sub-image processor 1212a and sub-image processor 1212c. When the zoom signal is a second signal different from the first signal, image generator 1214 can use the image data output from sub-image processor 1212c and sub-image processor 1212b to generate an output image from the image data output from sub-image processor 1212a and sub-image processor 1212c. When the zoom signal is a third signal different from the first and second signals, the image generator 1214 does not perform such image data merging. Instead, it selects any one of the image data output from the sub-image processors 1212a, 1212b, and 1212c and generates an output image. However, the embodiment is not limited to this, and the method of processing image data can be modified and implemented as needed.

[0205] Reference Figure 19 In some embodiments, the image processing apparatus 1210 may further include a selector 1213 that selects the outputs of sub-image processors 1212a, 1212b and 1212c and sends the outputs to the image generator 1214.

[0206] In this case, selector 1213 can perform different operations based on the zoom signal or zoom factor. For example, when the zoom signal is the fourth signal (e.g., the zoom ratio is the first ratio), selector 1213 can select any one of the outputs of sub-image processors 1212a, 1212b, and 1212c, and send the selected output to image generator 1214.

[0207] Furthermore, when the zoom signal is a fifth signal different from the fourth signal (e.g., the zoom magnification is a second magnification), selector 1213 can sequentially send p (where p is a natural number of 2 or greater) outputs from sub-image processors 1212a, 1212b, and 1212c to image generator 1214. For example, selector 1213 can sequentially send the outputs of sub-image processors 1212b and 1212c to image generator 1214. Additionally, selector 1213 can sequentially send the outputs of sub-image processors 1212a and 1212b to image generator 1214. Image generator 1214 can generate an output image by merging the sequentially provided p outputs.

[0208] Here, image processing such as depigmentation, video / preview resolution reduction, gamma correction, and high dynamic range (HDR) can be performed in advance by sub-image processors 1212a, 1212b, and 1212c, and the processed image data can then be sent to image generator 1214. Therefore, even if the processed image data is provided to image generator 1214 via a signal line through selector 1213, image merging operations of image generator 1214 can be performed at high speed.

[0209] In some embodiments, the image generator 1214 may receive multiple image data with different exposure times from at least one of a plurality of sub-image processors 1212a, 1212b and 1212c, and perform HDR on the multiple image data to generate merged image data with increased dynamic range.

[0210] The camera module controller 1216 can provide control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 can be provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0211] Based on image generation information including zoom signals or mode signals, any one of the multiple camera modules 1100a, 1100b, and 1100c can be designated as a master camera (e.g., 1100b), and the remaining camera modules (e.g., 1100a and 1100c) can be designated as slave cameras. Such information can be included in control signals and provided to the corresponding camera modules 1100a, 1100b, and 1100c via separate control signal lines CSLa, CSLb, and CSLc.

[0212] The camera modules operating as both master and slave cameras can change according to the zoom factor or operating mode signal. For example, when the field of view of camera module 1100a is wider than that of camera module 1100b and the zoom factor indicates a low zoom ratio, camera module 1100a can operate as the master camera and camera module 1100b can operate as the slave camera. Conversely, when the zoom factor indicates a zoom ratio, camera module 1100b can operate as the master camera and camera module 1100a can operate as the slave camera.

[0213] In some embodiments, control signals provided from camera module controller 1216 to each of camera modules 1100a, 1100b, and 1100c may include a synchronization enable signal. For example, when camera module 1100b is the main camera and camera modules 1100a and 1100c are the slave cameras, camera module controller 1216 may send a synchronization enable signal to camera module 1100b. Camera module 1100b, receiving the synchronization enable signal, may generate a synchronization signal based on the synchronization enable signal and provide the generated synchronization signal to camera modules 1100a and 1100c via synchronization signal line SSL. Camera modules 1100b, 1100a, and 1100c may synchronize with such a synchronization signal to send image data to application processor 1200.

[0214] In some embodiments, control signals provided from camera module controller 1216 to the plurality of camera modules 1100a, 1100b, and 1100c may include mode information based on mode signals. Based on the mode information, the plurality of camera modules 1100a, 1100b, and 1100c may operate in a first operating mode and a second operating mode with respect to sensing speed.

[0215] Multiple camera modules 1100a, 1100b, and 1100c can generate image signals at a first speed (e.g., at a first frame rate) in a first operating mode, encode the image signals at a second speed higher than the first speed (e.g., at a second frame rate higher than the first frame rate), and transmit the encoded image signals to the application processor 1200. In this case, the second speed can be 30 times or less than the first speed.

[0216] Application processor 1200 can store the received image signal (i.e., the encoded image signal) in internal memory 1230 within application processor 1200 or in external memory 1400 outside application processor 1200, and subsequently read from internal memory 1230 or external memory 1400 and decode the encoded image signal, and display image data generated based on the decoded image signal. For example, a corresponding sub-image processor among the plurality of sub-image processors 1212a, 1212b, and 1212c of image processing device 1210 can perform decoding and also perform image processing on the decoded image signal.

[0217] Multiple camera modules 1100a, 1100b, and 1100c can generate image signals at a third speed lower than the first speed (e.g., at a third frame rate lower than the first frame rate) in a second operating mode, and send the image signals to application processor 1200. The image signals provided to application processor 1200 may be unencoded signals. Application processor 1200 may perform image processing on the received image signals, or it may store the image signals in internal memory 1230 or external memory 1400.

[0218] PMIC 1300 can supply power, such as power supply voltage, to each of the multiple camera modules 1100a, 1100b, and 1100c. For example, under the control of application processor 1200, PMIC 1300 can supply a first power to camera module 1100a via power signal line PSLa, a second power to camera module 1100b via power signal line PSLb, and a third power to camera module 1100c via power signal line PSLc.

[0219] The PMIC 1300 can generate power corresponding to each of the plurality of camera modules 1100a, 1100b, and 1100c in response to a power control signal PCON from the application processor 1200, and can also adjust the power level. The power control signal PCON can include a power adjustment signal for each operating mode of the plurality of camera modules 1100a, 1100b, and 1100c. For example, the operating mode can include a low-power mode, and in this case, the power control signal PCON can include information about the camera module operating in the low-power mode and a set power level. The power levels provided to the plurality of camera modules 1100a, 1100b, and 1100c can be the same or different from each other. Furthermore, the power levels can be changed dynamically.

[0220] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor comprising: a pixel configured to operate in a high conversion gain mode and a low conversion gain mode during a readout period, and sequentially output a low conversion gain reset signal, a high conversion gain reset signal, a high conversion gain image signal, and a low conversion gain image signal as a pixel voltage; and a correlated double sampling circuit configured to generate a comparison signal based on a ramp signal and the pixel voltage received from the pixel, wherein the correlated double sampling circuit includes a comparator configured to: receive the pixel voltage through a first input node, receive the ramp signal through a second input node based on receiving the low conversion gain reset signal or the low conversion gain image signal as the pixel voltage, and receive the ramp signal through a third input node based on receiving the high conversion gain reset signal or the high conversion gain image signal as the pixel voltage; and compare the ramp signal with the pixel voltage, and output the comparison signal corresponding to a comparison result. The correlated double sampling circuit further includes:

2. The image sensor of claim 1, wherein, a first capacitor having a first terminal electrically connected to the first input node and a second terminal to which the pixel voltage is applied; a second capacitor having a first terminal electrically connected to the second input node and a second terminal to which the ramp signal is applied; and a third capacitor having a first terminal electrically connected to the third input node and a second terminal to which the ramp signal is applied. The comparator further includes:

3. The image sensor of claim 1, wherein, a current source configured to provide a bias current; an input stage including a first transistor, a second transistor, and a third transistor, wherein a first terminal of each of the first transistor, the second transistor, and the third transistor is electrically connected to the current source, and gate terminals of the first transistor, the second transistor, and the third transistor are connected to the first input node, the second input node, and the third input node, respectively; an output stage including a fourth transistor and a fifth transistor, wherein a power supply voltage is applied to a first terminal of each of the fourth transistor and the fifth transistor, a second terminal of the fourth transistor is electrically connected to a comparison node, a second terminal of the fifth transistor is connected to an output node, and gate terminals of the fourth transistor and the fifth transistor are connected to each other; and a switch configured to control respective connections among the input stage, the output stage, the comparison node, and the output node. The switch includes:

4. The image sensor of claim 3, wherein, a first switch provided between the first input node and the output node; a second switch provided between a second terminal of the second transistor and the comparison node; a third switch provided between a second terminal of the third transistor and the comparison node; a fourth switch provided between the second input node and the comparison node; a fifth switch provided between the third input node and the comparison node; a sixth switch provided between the comparison node and an intermediate node of the output stage; and ​ a seventh switch disposed between the output node and an intermediate node of the output stage.

5. The image sensor of claim 4, wherein, the comparator is further configured to perform a first auto-zero operation based on receiving the low conversion gain reset signal having a first voltage level as the pixel voltage, in which the first switch, the third switch, the fourth switch, and the sixth switch are turned on, and in which the first input node, the second input node, the comparison node, and the output node have a first auto-zero voltage level by the first auto-zero operation.

6. The image sensor of claim 5, wherein, the comparator is further configured to turn off the third switch and the fourth switch after the first auto-zero operation, and compare the low conversion gain reset signal with the ramp signal.

7. The image sensor of claim 5, wherein, the comparator is further configured to perform a second auto-zero operation based on receiving the high conversion gain reset signal having a second voltage level as the pixel voltage, in which the second switch, the fifth switch, and the seventh switch are turned on, and in which the first input node, the third input node, and the comparison node have a second auto-zero voltage level by the second auto-zero operation, and wherein a difference between the first auto-zero voltage level and the second auto-zero voltage level is equal to a difference between the first voltage level and the second voltage level.

8. The image sensor of claim 7, wherein, the comparator is further configured to turn off the fifth switch and the seventh switch after the second auto-zero operation, turn on the sixth switch, compare the high conversion gain reset signal with the ramp signal, and compare the high conversion gain image signal with the ramp signal.

9. The image sensor of claim 8, wherein, the comparator is further configured to turn off the second switch after comparing the high conversion gain image signal with the ramp signal, turn on the first switch, and compare the low conversion gain image signal with the ramp signal.

10. The image sensor of claim 1, further comprising: a count code generator configured to generate a count code having an increased code value; and a counter circuit configured to generate a high conversion gain pixel value and a low conversion gain pixel value based on the count code received from the count code generator and the comparison signal received from the correlated double sampling circuit, wherein the counter circuit includes: a latch configured to latch a code value of the count code at a time of a level transition of the comparison signal, and output the code value as a count value with respect to the comparison signal; a first memory configured to store a first count value output from the latch; a second memory configured to store a second count value output from the latch after output of the first count value; a selector configured to select one of the first count value and the second count value; and a calculator configured to perform a calculation on a third count value or a fourth count value output from the latch and the first count value or the second count value selected by the selector.

11. The image sensor of claim 10, wherein, the latch is further configured to: the first comparison signal corresponding to the low conversion gain reset signal, the second comparison signal corresponding to the high conversion gain reset signal, the third comparison signal corresponding to the high conversion gain image signal, and the fourth comparison signal corresponding to the low conversion gain image signal are sequentially received as the comparison signals, and the first count value according to the first comparison signal, the second count value according to the second comparison signal, the third count value according to the third comparison signal, and the fourth count value according to the fourth comparison signal are sequentially output.

12. The image sensor of claim 11, wherein, The selector is further configured to: select the second count value when the third count value is output from the latch to the calculator, and provide the second count value to the calculator, and select the first count value when the fourth count value is output from the latch to the calculator, and provide the first count value to the calculator.

13. The image sensor of claim 11, wherein, The calculator includes a 1-bit adder, and is configured to perform a 1-bit serial operation on the third count value and the second count value, and perform a 1-bit serial operation on the fourth count value and the first count value.

14. The image sensor of claim 11, wherein, The counter circuit further includes a flip-flop configured to store a carry output from the calculator, and provide the carry to the calculator in the next operation.

15. The image sensor of claim 1, wherein, The pixel includes: a photoelectric conversion element configured to convert a received optical signal into an electric charge; a floating diffusion node electrically connected to the photoelectric conversion element, and configured to store the electric charge; a drive transistor configured to output a voltage corresponding to a voltage of the floating diffusion node; and a gain control transistor configured to be turned on or turned off in response to a conversion gain control signal, wherein the pixel is further configured to operate in the low conversion gain mode based on the gain control transistor being turned on, and operate in the high conversion gain mode based on the gain control transistor being turned off.

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