Multi-chip transceiver testing in radar systems

Abstract

Multi-chip transceiver testing in a radar system is provided. A radar system is provided that includes a first radar transceiver integrated circuit (IC) including transmit signal generation circuitry operable to generate a continuous wave signal and a first transmit channel coupled to the transmit signal generation circuitry to receive the continuous wave signal and transmit a test signal based on the continuous wave signal, and a second radar transceiver IC including a first receive channel coupled to an output of the first transmit channel of the first radar transceiver IC via a loopback path to receive the test signal from the first transmit channel, the second radar transceiver IC operable to measure a phase response in the test signal.

Description

[0001] This application is a divisional application of Chinese patent application 201610828516.4, filed on September 18, 2016, entitled "Test of multi-chip transceiver in radar system". Technical Field

[0002] The embodiments of this disclosure generally relate to radar systems, and more specifically to multi-chip transceiver testing in radar systems. Background Technology

[0003] A new class of safety systems known as Advanced Driver Assistance Systems (ADAS) has been introduced into automobiles to reduce human error. These systems are enabled primarily by intelligent sensors based on millimeter-wave automotive radar. The development of these assistance systems, which can provide functions such as rear-view cameras, electronic stability control, and vision-based pedestrian detection systems, has been partially facilitated by improvements in microcontroller and sensor technologies. Enhanced embedded radar-based solutions enable ADAS designers to achieve complementary safety features.

[0004] In an automotive radar system, one or more radar sensors can be used to detect obstacles around the vehicle and the speed of detected objects relative to the vehicle. The processing unit within the radar system can determine the appropriate actions needed based on the signals generated by the radar sensors, for example, to avoid a collision or reduce indirect damage. Current automotive radar systems are capable of detecting objects and obstacles around the vehicle, the position of any detected object or obstacle relative to the vehicle, and the speed of any detected object or obstacle relative to the vehicle. Through the processing unit, the radar system can, for example, warn the driver of potential hazards, prevent a collision in dangerous situations by controlling the vehicle, take over partial control of the vehicle, or assist the driver in parking the vehicle.

[0005] Automotive radar systems must meet the functional safety specifications of the international standard ISO 26262, entitled "Road Vehicles - Functional Safety". ISO 26262 defines functional safety as the lack of an unreasonable risk arising from the faulty behavior of an electrical / electronic system. Functional safety in automotive radar is the prevention of human injury due to the failure of components in the radar. For automotive radar, the radar should be considered to function properly within a fault tolerance time interval of approximately 100 milliseconds (ms). Therefore, while the vehicle is in operation, a fault in any part of the radar that would cause a degradation in the signal-to-noise ratio (SNR) should be detected and an appropriate response should be performed within approximately 100 ms. Summary of the Invention

[0006] Embodiments of this disclosure relate to methods and apparatus for testing multi-chip transceivers in radar systems. In one aspect, a radar system is provided comprising a first radar transceiver integrated circuit (IC) and a second radar transceiver IC. The first radar transceiver IC includes a transmit signal generating circuit system operable to generate a continuous wave signal and a first transmit channel coupled to the transmit signal generating circuit system to receive the continuous wave signal and transmit a test signal based on the continuous wave signal. The second radar transceiver IC includes a first receive channel coupled via a loopback path to the output of the first transmit channel of the first radar transceiver IC to receive the test signal from the first transmit channel. The second radar transceiver IC is operable to measure the phase response in the test signal.

[0007] In one aspect, a method is provided for measuring the phase response between radar transceiver integrated circuits (ICs) in a radar system, comprising receiving a test signal in a first receive channel of a first radar transceiver IC in the radar system, receiving a test signal from a first transmit channel of a second radar transceiver IC in the radar system, the first transmit channel being coupled to the first receive channel via a loopback path, and measuring the phase response in the test signal of the first radar transceiver IC. Attached Figure Description

[0008] Specific embodiments will now be described by way of example only, with reference to the accompanying drawings:

[0009] Figure 1 This is a block diagram of an exemplary frequency modulated continuous wave (FMCW) radar system with multiple radar transceiver integrated circuits (ICs);

[0010] Figure 2 This is a block diagram of an exemplary radar transceiver IC;

[0011] Figure 3 It is configured to monitor the phase of the radar transceiver signals between chips. Figure 1 A simplified block diagram of an example embodiment of a radar system; and

[0012] Figure 4 This is a flowchart of a method for monitoring the signal phase of radar transceivers between chips using an external feedback method. Detailed Implementation

[0013] Specific embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. For consistency, similar elements in the various figures will be indicated by similar reference numerals.

[0014] Phased array radar systems with enhanced gain and accuracy can be constructed from multiple radar transceiver integrated circuits (ICs), each with multiple receive and transmit channels linked to a master clock signal. In such a system, the source (i.e., reference clock) for the master clock signal used by all ICs can be the clock of one of the ICs, referred to as the master radar transceiver IC. The reference clock is typically a sub-multiple of the actual radar signal (i.e., the signal amplified and transmitted in the transmit channel and used as the down-conversion path for the receive channel by the local oscillator (LO) signal). This reference clock signal is routed to each radar transceiver IC, where it is multiply-upped and buffered before being fed to a node where the signal is split between the transmit and receive channels of the radar transceiver IC.

[0015] In such a radar system, it is important that the phase delay (response) between all transmit and receive channels of all radar transceiver ICs be accurately known and measurable during radar operation in order to extract accurate data from the radar signal, such as the angle of arrival of detected objects. It is possible to measure the phase delay / mismatch between the receive and transmit channels on each transceiver IC, for example, using an internal loopback procedure or a built-in self-test (BIBT) phase detector. An example of an internal loopback procedure is described in co-pending U.S. Patent Application 14 / 870129 (Attorney's No. TI-75598), filed September 30, 2015, which is incorporated herein by reference. As described in detail in U.S. Patent Application 14 / 870129, the internal loopback path couples the transmit channels of the radar transceiver IC to the receive channels of the radar transceiver IC. A test signal generated in the transmit channels and provided to the receive channels via the internal loopback path is used to determine the phase response of each transmit channel. The BIST phase detector can be, for example, a linear mixer that multiplies the output of one transmit channel with the output of another transmit channel. After low-pass filtering, the DC output will be correlated with the phase difference between the channels.

[0016] However, chip-to-chip phase testing techniques (such as internal loopback methods) do not detect unwanted phase shifts introduced by circuitry or interconnects between the master clock injection point and the split point between the transmit and receive channels. This phase shift is common to both the receive and transmit paths and is therefore eliminated by downlink switching operations on the receive channel or by a BIST phase detector across the transmit channel. The ability to detect these potential phase shifts allows for a more comprehensive security monitoring process compared to what can be achieved using only internal loopback schemes or BIST phase detectors.

[0017] When radar systems are used, for example, in operating vehicles, embodiments of this disclosure provide methods for monitoring radar transceiver performance across radar transceiver ICs in a cascaded radar system (i.e., a system in which ICs are linked to a master clock signal, such as a radar system). More specifically, embodiments configure external feedback paths between radar transceiver ICs to enable measurement of the phase response between pairs of radar transceiver ICs when the radar system is operating in test mode. The measured phase response can be used to detect phase mismatch between radar transceiver ICs and take corrective action.

[0018] Figure 1 , Figure 2 and Figure 3 This is a block diagram of an example of a phased array frequency modulated continuous wave (FMCW) radar system 100 configured to measure the phase response between radar transceiver ICs during radar system 100 operation. Figure 1 The top-level architecture of radar system 100 is shown. Figure 2 Showing what is suitable for use as Figure 2 An example of an FMCW radar transceiver IC consisting of a master radar transceiver IC 102 and a slave radar transceiver IC 104. Figure 3 A more detailed view of the configuration of the radar system 100 for phase response measurement between radar transceiver ICs is provided.

[0019] For reference Figure 1 The example radar system 100 includes a main radar transceiver IC 102, two slave radar transceiver ICs 104 and 105, a processing unit 106, and a network interface 108. Each of the main radar IC 102 and the slave radar ICs 104 and 105 has... Figure 2 The example FMCW radar transceiver IC architecture is shown below. Furthermore, the master radar transceiver IC 102 is coupled to slave radar ICs 104 and 105 to synchronize the operation of the slave radar transceiver ICs 104 and 105 with the operation of the master radar transceiver IC 102. The master radar IC 102 and the slave radar ICs 104 and 105 are collectively referred to herein as the front end or radar system front end.

[0020] Processing unit 106 is coupled to master radar transceiver IC 102 and slave radar transceiver ICs 104, 105 via a serial interface to receive data from the radar ICs. In some embodiments, the serial interface may be a high-speed serial interface, such as a low-voltage differential signaling (LVDS) interface. In some embodiments, the serial interface may be a low-speed serial peripheral interface (SPI). See reference... Figure 2In more detail, each radar SOC 102, 104 includes the function of generating multiple digital beat signals (or referred to as de-modulated signals, intermediate frequency (IF) signals, or raw radar signals), which are provided to the processing unit 106 via a high-speed serial interface.

[0021] Processing unit 106 includes functions for processing the received beat signal to determine, for example, the distance, velocity, and angle of any detected object. Processing unit 106 may also include functions for performing post-processing of information related to the detected object, such as tracking the object, determining its speed and direction of motion, etc. As needed, processing unit 106 may include any suitable processor or combination of processors for processing the throughput of applications using radar data. For example, processing unit 106 may include a digital signal processor (DSP), a microcontroller (MCU), a system-on-a-chip (SoC) combining a DSP and an MCU to process both, or a field-programmable gate array (FPGA) and a DSP.

[0022] Processing unit 106 provides control signals to one or more electronic control units in the vehicle via network interface 108 as needed. An electronic control unit (ECU) is a general term for any embedded system in a vehicle that controls one or more electrical systems or subsystems within the vehicle. Types of ECUs include, for example, electronic / engine control modules (ECMs), powertrain control modules (PCMs), transmission control modules (TCMs), brake control modules (BCMs or EBCMs), central control modules (CCMs), central timing modules (CTMs), general electronic modules (GEMs), body control modules (BCMs), and suspension control modules (SCMs).

[0023] Network interface 106 can implement any suitable protocol, such as, for example, Controller Area Network (CAN) protocol, FlexRay protocol, or Ethernet protocol.

[0024] For reference Figure 2 The described example FMCW radar transceiver IC is configured to function as any radar transceiver IC in radar system 100. The radar transceiver IC may include multiple transmit channels 204 for transmitting FMCW signals and multiple receive channels 202 for receiving reflected transmit signals. Furthermore, the number of receive channels may be greater than the number of transmit channels. For example, one embodiment of the radar transceiver IC may have three transmit channels and four receive channels.

[0025] The transmitting channel includes a suitable transmitter and antenna. The receiving channel includes a suitable receiver and antenna. Furthermore, each receiving channel 202 is identical and includes mixers 210 and 212 for mixing the transmitted signal with the received signal to generate a beat signal (i.e., an intermediate frequency (IF) signal); baseband bandpass filters 214 and 216 for filtering the beat signal; variable gain amplifiers (VGAs) 215 and 217 for amplifying the filtered beat signal; and analog-to-digital converters (ADCs) 218 ​​and 220 for converting the analog beat signal into a digital beat signal. The bandpass filters, VGAs, and ADCs of the receiving channel can be collectively referred to as a baseband chain or a baseband filter chain.

[0026] The receive channel 202 is coupled to a digital front end (DFE) 222, which performs decimation filtering on the digital beat signal to reduce the data transmission rate. The DFE 222 can also perform other operations on the digital beat signal, such as DC offset cancellation. The DFE 222 is coupled to a high-speed serial interface (I / F) 224, which transmits the output of the DFE 222 to the processing unit 106 when the radar transceiver IC is operating in normal mode. Furthermore, the DFE 222 is coupled to a control module 228 to provide test signals to the control module 228 when the radar transceiver IC is operating in test mode.

[0027] Control module 228 includes functions for controlling the operation of the radar transceiver IC in normal and test modes. Control module 228 may include, for example, a buffer storing output samples of DFE 222, an FFT (Fast Fourier Transform) engine for calculating the spectral information of the buffer contents, and an MCU executing firmware to control the operation of the radar transceiver IC in normal and test modes. Functional reference for control module 228 is provided. Figure 4 The method will be described in more detail.

[0028] The Serial Peripheral Interface (SPI) 226 provides an interface for communication with the processing unit 106. For example, the processing unit 106 can use the SPI 226 to send control information (such as the timing and frequency of chirp, output power levels, triggering of monitoring functions (such as phase noise monitoring), etc.) to the radar SOC 200. The radar transceiver IC can use the SPI 226, for example, to send inter-chip phase response measurements and results of other monitoring functions to the processing unit 106.

[0029] The programmable timing engine 232 includes receiving linear frequency modulation (LFM) parameter values ​​from the LFM sequence in the radar frame from the control module 228 and generating LFM control signals for transmitting and receiving LFM in the control frame based on the parameter values. The LFM parameters are defined by the radar system architecture and may include, for example, transmitter enable parameters indicating which transmitters are enabled, the LFM frequency start value, the LFM frequency slope, the analog-to-digital converter (ADC) sampling time, the ramp termination time, the transmitter start time, etc.

[0030] The radio frequency synthesizer (SYNTH) 230 includes the function of generating an FMCW signal for transmission based on a linear frequency modulation control signal from the timing engine 232. In some embodiments, SYNTH 230 includes a phase-locked loop (PLL) with a voltage-controlled oscillator (VCO). If the radar transceiver IC is used as a slave radar transceiver IC 104, 105, SYNTH 230 is inactive when the radar system front end is operating in normal mode. Instead, SYNTH 230 in the master radar transceiver IC 102 provides the FMCW signal to be transmitted to the slave radar transceiver ICs 104, 105 via an output buffer 238 of an input buffer 236 coupled to each slave radar transceiver IC 104, 105.

[0031] Multiplexer 231 is coupled to the inputs of SYNTH 230 and input buffer 236. Multiplexer 231 can be configured to select between a signal received in input buffer 236 and a signal generated by SYNTH 230. Output buffer 238 is coupled to the output of multiplexer 231 and can be used to send the signal selected by multiplexer 232 to an external device.

[0032] Clock multiplexer 240 increases the frequency of the transmitted signal to the frequency of mixers 206 and 208. Cleanup PLL 234 operates to increase the signal frequency of an external low-frequency reference clock (not shown) to the frequency of SYNTH 230 and filter out reference clock phase noise from the clock signal.

[0033] Clock multiplexer 240, synthesizer 230, timing generator 232, and clear PLL 234 are examples of a transmit signal generation circuit system. The transmit signal generation circuit system generates a radio frequency (RF) signal as input to the transmit channel and as input to a mixer in the receive channel via the clock multiplexer.

[0034] For reference Figure 3 This illustrates the phase response used for monitoring radar transceiver ICs 102, 104, and 105. Figure 1The radar system is configured such that the receive channels of radar transceiver IC 104 and radar transceiver IC 105 are coupled to the transmit channel of main radar transceiver IC 102 via loopback path 308. When radar transceivers ICs 102, 104, and 105 are operating in test mode, loopback path 308 can be used to provide the test signal generated on the main radar transceiver IC 102 to the coupled receive channels of radar transceivers ICs 104 and 105 via the coupled transmit channels.

[0035] In the described embodiment, the return path 308 includes a switch 310, which can be configured to provide a signal to the antenna of the transmit channel when the main radar transceiver IC 102 is operating in normal mode and to provide a signal to the return path 308 when the main transceiver IC 102 is operating in test mode. In other embodiments, the transmit channel on the main transceiver IC 102 can be dedicated to use only in test mode, in which case the switch 310 is not present and no antenna is required.

[0036] Figure 4 It is used for using external loopback paths (e.g., Figure 3 The flowchart illustrates a method for monitoring the signal phase of inter-chip radar transceivers (using an external feedback path). First, the test path for measuring the signal phase is enabled (400) by a control module on each of the radar transceiver ICs 102, 104, and 105. On the master transceiver IC 102, the test path includes a timing engine, a SYNTH, and a transmit channel coupled to the external feedback path 308. In embodiments where a switch 310 is present, enabling the test path on the master radar transceiver IC 102 involves setting the switch to pass the signal from the transmit channel to the feedback path 308. On the slave transceiver ICs 104 and 105, the test path includes a corresponding receive channel coupled to the feedback path 308. Other receive and transmit channels may be disabled.

[0037] The control module of the main radar transceiver IC 102 further enables the generation of a continuous wave (CW) signal (402), which travels through the transmit channel coupled to the external return path 308 to the receive channel coupled to the return path 308 on the slave radar transceiver ICs 104, 105. A modulation component applies modulation to the CW to generate a CW test signal, such that this signal is separated from the DC signal in each receive channel. The modulation component can be, for example, an on-off keying (OOK) modulator, a binary phase shift keying (BPSK) modulator, a double-sideband (DSB) modulator, or a single-sideband (SSB) modulator.

[0038] For example, the transmit channel may include a signal power amplifier chain coupled to a preamplifier (PPA) of the SYNTH 230 to receive the signal, a modulation component coupled to the PPA to receive the amplified signal, and a power amplifier (PA) coupled to the modulation component to receive the modulated signal. In this configuration, the modulation component may be a BPSK modulator, a DSB modulator, or an SSB modulator. In some embodiments, the modulation component may be coupled in the loopback path at the output of the PA. In this embodiment, the modulation component may also be an OOK modulator.

[0039] The control modules on each of the radar transceiver ICs 104 and 105 collect digital test data signals from the corresponding receive channel via their respective DFEs (404). Data collection from the receive channel on each of the radar transceiver ICs 104 and 105 can be performed simultaneously and synchronously; that is, data collection on each of the radar transceiver ICs 104 and 105 begins at approximately the same time. Furthermore, data collection on each of the transceiver ICs 104 and 105 begins synchronously with respect to signal modulation in the transmit channel.

[0040] The control module on each of the radar transceiver ICs 104 and 105 performs a Fast Fourier Transform (FFT) on the corresponding test data signal and determines the phase θ (406) of the test data signal. For example, in some embodiments, control module 228 performs a Fast Fourier Transform (FFT) on the digital test data signal and determines the phase. This phase can be determined as follows. For ease of interpretation, the following assumptions are made: Ns samples of ADC data are collected at a sampling rate Fs, for example, Ns = 1024 and Fs = 10.24 MHz, and an Ns-point FFT is performed to produce Ns FFT output complex samples (which are referred to as FFTOut[0,1,2,…Ns-1]). The FFT output sample index, which corresponds to the test data signal frequency IF, is given by IF / Fs*Ns. The value of FFTOut[index] is a complex number, denoted by X+jY. The phase θ is given by θ = arctan(Y / X). In other embodiments, in the DFE, the modulation frequency is down-converted to DC, and the phase is extracted via I / Q estimation logic (i.e., the offset of the relevant tone after DC by estimating each of the I and Q paths, respectively).

[0041] The phase value is reported to processing unit 106 (408). Processing unit 106 can use the reported phase value to identify phase response mismatches among radar transceiver ICs 102, 104, and 105. The phase response mismatch between the transmit channel on the master radar transceiver IC 102 and the transmit channel on the slave radar transceiver IC can be calculated as follows:

[0042] Phase mismatch i,j=θ i -θ j

[0043] Where θ i The phase response of the main transmitting channel measured by the above methods and θ j This is the internal phase response from the transmission channel. The internal phase response from the transmission channel can be measured, for example, using a BIST phase detector or an internal feedback process as described in U.S. Patent Application 14 / 870,129.

[0044] Subsequently, the phase mismatch between the other transmit channels on the radar transceiver IC and the transmit channels on the master transceiver IC can be determined relative to the internal phase mismatch between the transmit channels. More specifically, the phase mismatch between the master transmit channel and another transmit channel is the sum of the phase mismatch calculated above and the internal phase mismatch between the phase of the transmit channel used to calculate the aforementioned phase mismatch and the phase of the other transmit channels.

[0045] For example, let dP M1S1 The phase mismatch between the master transmission channel (M1) and the slave transmission channel (S1) is calculated according to the equations above. Furthermore, let dP... S1S2 This refers to the internal phase mismatch between S1 and another slave transmission channel (S2). The phase mismatch between the two slave transmission channels can be calculated according to the equation above, where θ i S1 is the internal phase response of the transmission channel and θ j This is the internal phase response of S2 from the transmitting channel. The phase mismatch between the main transmitting channel M1 and the slave transmitting channel S2 can be calculated as follows:

[0046] dP M1S2 =dP M1S1 +dP S1S2 .

[0047] If a third slave transmission channel (S3) exists, the phase mismatch between the primary transmission channel M1 and the slave transmission channel S3 can be calculated as follows:

[0048] dP M1S3 =dP M1S1 +dP S1S3

[0049] Where dP S1S3 This refers to the internal phase mismatch between S1 and S3 from the transmission channel.

[0050] Other embodiments

[0051] While this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who will benefit from the benefits of this disclosure will understand that other embodiments can be devised without departing from the scope of this disclosure disclosed herein.

[0052] For example, in the embodiments described herein, the phased array radar system has two slave radar transceiver ICs. One of ordinary skill in the art will understand that embodiments in which the radar system includes a single slave radar transceiver IC or more than two slave radar transceiver ICs are also possible.

[0053] In another example, in the embodiments already described herein, the radar transceiver ICs in the front end of the cascaded radar system have a master-slave relationship. One skilled in the art will understand embodiments in which the radar transceiver ICs do not have a master-slave relationship (e.g., an external PLL is used to provide signals to all the radar transceiver ICs).

[0054] In another example, in the embodiment already described herein, one radar transceiver IC provides a test signal to other radar transceiver ICs. One skilled in the art will understand an embodiment in which each radar transceiver IC provides a test signal to the next radar transceiver IC in a “daisychain” configuration.

[0055] In another example, in the embodiment already described herein, the transmit channel for inter-chip phase response measurement is on the main radar transceiver IC. One skilled in the art will understand embodiments in which the transmit channel on another IC of the radar system is used instead.

[0056] In another example, in the embodiment already described herein, the transmit signal generation circuitry includes an radio frequency synthesizer. One of ordinary skill in the art will understand that this circuitry is an embodiment of an open-loop oscillator (RF oscillator) plus a digital-to-analog converter (DAC) or other suitable transmit signal generation circuitry.

[0057] In another example, in the embodiment already described herein, an internal FFT engine in the control module is used to calculate the phase of the received test signal. One skilled in the art will understand embodiments where the phase is measured by an IQ estimation logic block in the DFE.

[0058] In another example, in the embodiment already described herein, the phase measurement processing is performed in the control module of the radar transceiver IC. Those skilled in the art will understand embodiments in which some or all of the phase measurement processing is performed externally to the IC (e.g., via a processing unit or via an external MCU).

[0059] In another example, in the embodiment already described herein, a clock multiplexer is used. One of ordinary skill in the art will understand that in embodiments where the SYNTH operates at the LO frequency rather than a lower frequency, a multiplexer is not required.

[0060] In another example, in the embodiments already described herein, the transmit channel used in the loopback path is dedicated to use in test mode or there is a switch between the transmit channel and the antenna. One of ordinary skill in the art will understand embodiments in which the receive channel used is dedicated to use in test mode or there may be a switch between the corresponding antenna and the receive channel. In such embodiments, the transmit channel coupled to the loopback path may not be dedicated or may be switched.

[0061] Although the method steps are shown and described sequentially herein, one or more steps shown in the accompanying drawings and described herein may be performed simultaneously, in combination, and / or in an order different from that shown in the accompanying drawings and / or described herein. Therefore, the embodiments should not be limited to the specific order of the steps shown in the accompanying drawings and / or described herein.

[0062] Certain terms used throughout the specification and claims refer to specific system components. As will be understood by those skilled in the art, components in a radar system may be referred to by different names and / or may be combined in ways not shown herein without departing from the described function. This document is not intended to distinguish between components with different names rather than different functions. Within the scope of the discussion and claims above, the terms “comprising” and “including” are used in an open-ended manner and should therefore be interpreted as meaning “including but not limited to.” Moreover, the term “coupled” and its derivatives mean indirect, direct, optical, and / or wireless electrical connection. Thus, if a first device is coupled to a second device, for example, the connection may be made by direct electrical connection, indirect electrical connection via other devices and connectors, optical electrical connection, and / or wireless electrical connection.

[0063] Therefore, the scope of the appended claims will cover any such modifications to embodiments that fall within the true scope of this disclosure.

Claims

1. A radar system, comprising: The first radar transceiver integrated circuit, i.e., the first radar transceiver IC, includes a first transmit channel, the first transmit channel including an output; and A second radar transceiver IC includes a first receive channel, the input of which is coupled to the output of the first transmit channel of the first radar transceiver IC via a loopback path, wherein the loopback path does not include an antenna.

2. The radar system according to claim 1, further comprising: A third radar transceiver IC includes a second receive channel coupled to the output of the first transmit channel of the first radar transceiver IC via the return path.

3. The radar system according to claim 1, wherein, The first radar transceiver IC is configured to transmit a test signal at the first transmit channel, and the second radar transceiver IC is configured to: Receive the test signal; Measure the phase response of the test signal; and The phase mismatch between the first transmission channel and the second transmission channel is determined based on the difference between the internal phase responses of the second transmission channel and the first reception channel of the second radar transceiver IC and the phase response of the test signal.

4. The radar system according to claim 3, wherein, The internal phase response of the second transmission channel is determined using one of the internal loopback path of the receive channel coupled to the second radar transceiver IC and the built-in self-test phase detector, namely the BIST phase detector.

5. The radar system according to claim 3, wherein, The phase mismatch between the first transmission channel and the third transmission channel of the second radar transceiver IC is determined to be the sum of the phase mismatch between the second transmission channel and the third transmission channel and the phase response.

6. The radar system of claim 1, wherein the feedback path includes a switch coupled to the output of the first transmit channel, the switch being operable to provide the output signal of the first transmit channel to the antenna of the first transmit channel when the first radar transceiver IC is operating in normal mode and to provide the output signal of the first transmit channel to the feedback path when the first radar transceiver IC is operating in test mode.

7. The radar system of claim 1, wherein the first transmit channel is used only when the first radar transceiver IC is running in test mode to provide a test signal to the feedback path.

8. The radar system of claim 2, wherein the feedback path includes a switch coupled to an input of the second receiving channel, the switch being operable to provide the second receiving channel with a signal received by the antenna of the second receiving channel when the second radar transceiver IC is operating in normal mode, and to provide the second receiving channel with a signal from the feedback path when the second radar transceiver IC is operating in test mode.

9. The radar system of claim 2, wherein the second receiving channel is used only when the second radar transceiver IC is running in test mode to receive test signals from the feedback path.

10. The radar system according to claim 1, wherein the first radar transceiver IC is a master radar transceiver IC, and the second radar transceiver IC is a slave radar transceiver IC.

11. A method for testing multi-chip transceivers in radar systems, comprising: The test signal is transmitted via a return path from the second radar transceiver integrated circuit (IC) in the radar system at the first transmission channel, wherein the return path does not include the antenna; and The test signal is received by the first receiving channel of the first radar transceiver IC in the radar system.

12. The method of claim 11, further comprising: The phase response in the test signal is measured by the first radar transceiver IC; The test signal is received in the second receiving channel of the third radar transceiver IC in the radar system, and the first transmitting channel is coupled to the second receiving channel via the return path; as well as Measure the phase response in the test signal in the third radar transceiver IC.

13. The method of claim 12, further comprising determining the phase mismatch between the first transmit channel and the second transmit channel of the first radar transceiver IC as the difference between the internal phase response of the second transmit channel and the first receive channel and the phase response therebetween.

14. The method according to claim 13, wherein, The internal phase response of the second transmission channel is determined using one of the internal loopback path of the receive channel that couples the second transmission channel to the first radar transceiver IC and the built-in self-test phase detector, namely the BIST phase detector.

15. The method of claim 13, further comprising: The phase mismatch between the first transmission channel and the third transmission channel of the first radar transceiver IC is determined as the sum of the phase mismatch between the second transmission channel and the third transmission channel and the phase response.

16. The method of claim 11, further comprising setting a switch in the feedback path to direct the test signal to the first receiving channel.

17. The method of claim 16, wherein the switch is operable to provide the output signal of the first transmit channel to the antenna of the first transmit channel when the second radar transceiver IC is operating in normal mode and to provide the output signal of the first transmit channel to the feedback path when the second radar transceiver IC is operating in test mode.

18. The method of claim 16, wherein the switch is operable to provide a signal received by the antenna of the first receiving channel to the first receiving channel when the first radar transceiver IC is operating in normal mode and to provide a signal from the feedback path to the first receiving channel when the first radar transceiver IC is operating in test mode.

19. The method of claim 11, wherein the first transmission channel is used only when the second radar transceiver IC is running in test mode.

20. The method of claim 11, wherein the first receiving channel is used only when the first radar transceiver IC is running in test mode.

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