A chip structure and working method thereof

Abstract

The present disclosure is about a chip structure and its working method, wherein the chip structure is applied to a terminal, and includes: a baseband chip, which is arranged in the first area of ​​the chip structure and is used to access the NB network, and the baseband chip includes a baseband microprocessor; an application chip, which is arranged in the second area of ​​the chip structure and is used to run user programs, and the application chip includes an application microprocessor; wherein the baseband chip is electrically connected to the application chip, and the baseband microprocessor and the application microprocessor communicate with each other through an advanced high-performance bus and a MAILBOX. The technical solution of the present disclosure integrates the baseband chip and the application chip in the same chip structure, and the efficiency of inter-core communication is more efficient, which can greatly improve the operating efficiency of the system.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a chip structure and a working method thereof. Background Art

[0002] Currently, most NBIOT (Narrow Band Internet of Things) chips on the market are single-core solutions. The finished product also requires an external MCU (Microcontroller Unit) for data collection and process control, and then sends the data to the NBIOT network through the NBIOT chip. The external MCU increases product costs, and the multi-chip solution increases the chip structure area, thereby increasing costs. Summary of the invention

[0003] In order to overcome the problems existing in the related art, the present disclosure provides a chip structure and a working method thereof.

[0004] According to a first aspect of the present disclosure, a chip structure is provided, which is applied to a terminal, and the chip structure includes:

[0005] A baseband chip, arranged in the first area of ​​the chip structure, for accessing the NB network, the baseband chip comprising a baseband microprocessor;

[0006] An application chip, arranged in the second area of ​​the chip structure, for running a user program, the application chip comprising an application microprocessor;

[0007] The baseband chip is electrically connected to the application chip, and the baseband microprocessor communicates with the application microprocessor via an advanced high-performance bus and MAILBOX.

[0008] According to some embodiments of the present disclosure, the baseband microprocessor is arranged in a first sub-area of ​​the first area, the application microprocessor is arranged in a second sub-area of ​​the second area, and the first sub-area is arranged opposite to the second sub-area.

[0009] According to some embodiments of the present disclosure, the baseband microprocessor includes an ARM CORTEX M4 processor, and the application microprocessor includes an ARM CORTEX M0 processor.

[0010] According to some embodiments of the present disclosure, the baseband chip further includes a baseband peripheral group, and the baseband peripheral group is arranged in a third sub-area of ​​the first area;

[0011] The baseband peripheral group includes one or more baseband peripheral units, and the baseband microprocessor is electrically connected to the baseband peripheral units.

[0012] According to some embodiments of the present disclosure, the application chip further includes an application peripheral group, and the application peripheral group is arranged in a fourth sub-area of ​​the second area;

[0013] The application peripheral group includes one or more application peripheral units, and the application microprocessor is electrically connected to the application peripheral units.

[0014] According to some embodiments of the present disclosure, the chip structure further includes at least one or more of the following units arranged in the third region of the chip structure:

[0015] FLASH memory unit, reset unit, power management unit, bus unit and input / output multiplexer; one or more of the above units are electrically connected to the baseband chip and the application chip respectively.

[0016] According to a second aspect of the present disclosure, a chip operating method is provided, which is applied to a terminal, and the operating method includes:

[0017] Receiving a working instruction for operating the chip, wherein the working instruction includes identification information of a waiting working mode;

[0018] Acquire configuration information, where the configuration information is used to characterize the correspondence between a preset working mode and a working chip, where the working chip includes a baseband chip and an application chip, where the baseband chip is used to access a NB network; and the application chip is used to run a user program;

[0019] Based on the configuration information, the working chip corresponding to the waiting working mode is operated.

[0020] According to some embodiments of the present disclosure, operating the working chip corresponding to the waiting working mode based on the configuration information includes:

[0021] Obtaining identification information in the work order;

[0022] According to the identification information and the correspondence between the preset working mode and the working chip, the working chip corresponding to the waiting working mode is determined, and the working chip is operated.

[0023] According to some embodiments of the present disclosure, the preset working mode includes a first working mode, a second working mode and a third working mode.

[0024] The corresponding relationship between the preset working mode and the working chip includes:

[0025] The baseband chip is operated in the first working mode; the baseband chip and the application chip are operated in the second working mode, and the baseband chip and the application chip are configured to share a FLASH unit;

[0026] The baseband chip and the application chip are operated in the third working mode, and the baseband chip and the application chip are configured to use one FLASH unit respectively.

[0027] The chip structure and working method provided by the present disclosure integrate the baseband chip and the application chip in the same chip structure, so that the baseband chip has an independent baseband microprocessor, and the application chip also has an independent application microprocessor. The baseband chip and the application chip can run independently of each other, thereby opening an independent application microprocessor to the user program, so that the user program in the application chip can run independently without being restricted by the baseband chip, solving the problem of limited flexibility of the single-core CPU. At the same time, since the baseband chip and the application chip are integrated in the same chip structure, the efficiency of inter-core communication is more efficient, which can greatly improve the operating efficiency of the system.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings constituting a part of the present disclosure are used to provide a further understanding of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0030] Figure 1 is a block diagram showing a chip structure according to an exemplary embodiment.

[0031] Figure 2 The figure is a flow chart showing a working method of a chip according to an exemplary embodiment.

[0032] Figure 3 The invention is a block diagram of a computer device according to an exemplary embodiment. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0034] Figure 1A block diagram of a chip structure in an exemplary embodiment of the present disclosure is shown. The chip may belong to an Internet of Things chip, which is applied to a terminal. The terminal may be a device that provides voice and / or data connection to a user. The terminal is also called an intelligent terminal device, wherein the terminal may be a mobile terminal, and may also be called a user equipment (UE), a mobile station (MS), etc. For example, a handheld device with a wireless connection function, a vehicle-mounted device, etc. Examples of terminals may include: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in smart homes, etc.

[0035] like Figure 1 As shown, the chip structure 100 includes: a baseband chip (Baseband Processor, BP) and an application chip (Application Processor, AP).

[0036] like Figure 1 As shown, the baseband chip can be used to receive the NB program, the application chip can be used to run the user program, the baseband chip and the application chip are both arranged on the chip structure 100, the baseband chip is arranged in the first area 101 of the chip structure, and the application chip is arranged in the second area 201 of the chip structure 100, wherein the chip structure 100 can be evenly divided into the first area 101 and the second area 201 on the left and right, so that the baseband chip and the application chip can be arranged correspondingly on the left and right, for the convenience of illustration, as shown in FIG. Figure 1 As shown, the baseband chip is arranged on the left side of the chip structure 100, and the application chip is arranged on the right side of the chip structure 100. Of course, in the actual design process, the chip structure can also be divided into a first area and a second area with two different areas according to actual needs to layout the baseband chip and the application chip, and no specific limitation is made here.

[0037] like Figure 1As shown, the baseband chip and the application chip are electrically connected inside the chip structure 100 (not shown in the figure). When the chip structure is applied to, for example, a terminal communication system, the baseband chip can exchange data with the application chip. The baseband chip has an independent baseband microprocessor 10, and the application chip also has an independent application microprocessor 20, so that the baseband chip and the application chip can run independently of each other. By opening an independent application microprocessor to the user program, the user program in the application chip can run independently without being restricted by the baseband chip, solving the problem of limited flexibility of the single-core CPU. At the same time, since the baseband chip and the application chip are integrated in the same chip structure, the efficiency of inter-core communication is more efficient, which can greatly improve the operating efficiency of the system.

[0038] like Figure 1 As shown, since multiple processors are integrated in the chip structure, each processor is equivalent to a host of the system, and each processor needs to share resources to communicate. Therefore, the baseband microprocessor 10 and the application microprocessor 20 need to communicate, and the distance between the baseband microprocessor 10 and the application microprocessor 20 can be shortened as much as possible. In this embodiment, the baseband microprocessor 10 and the application microprocessor 20 can communicate through the Advanced High-performance Bus (AHB) and MAILBOX. AHB is mainly used for the connection between high-performance units (such as CPU, DMA and DSP, etc.), and can be used as a system bus on the system-level chip. It includes the following features: single clock edge operation, non-three-state implementation, support for burst transmission, support for segmented transmission, support for multiple master controllers, configurable 32-bit to 128-bit bus width; support for byte, half byte and word transmission. The Mailbox method is adopted, and multi-processor communication is mainly carried out by transmitting control information. Different Mails can be defined according to system requirements to implement system behavior. For example, data transmission with a fixed flow rate can be defined, and data transmission with a fixed block can also be defined. The data transmission between the baseband chip and the application chip through the Mailbox is an intra-chip parallel data transmission, so it has good real-time performance and high speed. It is also compatible with interrupt and query modes, thereby reducing the processing time pressure of the control CPU.

[0039] The chip structure disclosed in the present invention is a dual-core single chip structure, so it can save an MCU, thereby reducing costs.

[0040] In an exemplary real-time mode, the baseband microprocessor 10 and the application microprocessor 20 may also include the following data exchange modes: asynchronous serial interface (UART), high-speed serial interface (USB), asynchronous parallel interface (DPRAM) and half-duplex interface (SDIO).

[0041] In an exemplary embodiment, if Figure 1 As shown, in order to shorten the distance between the baseband microprocessor 10 and the application microprocessor 20, the baseband microprocessor 10 and the application microprocessor 20 are both arranged on the upper part of the chip structure, the upper part of the first area 101 of the chip structure 100 can be marked as the first sub-area 1011, the baseband microprocessor 10 can be arranged in the first sub-area 1011, the upper part of the second area 201 of the chip structure 100 is marked as the second sub-area 2011, and the application microprocessor 20 can be arranged in the second sub-area 2011. Since the first sub-area 1011 and the second sub-area 2011 are arranged opposite to each other on the left and right, the straight-line distance between the baseband microprocessor 10 and the application microprocessor 20 is the shortest, so that the chip structure space can be fully utilized and the connection of the lines is convenient.

[0042] In an exemplary embodiment, the baseband microprocessor and the application microprocessor use the Cortex-M processor series. The baseband microprocessor can choose ARM CORTEX M4, and the application microprocessor can choose ARM CORTEX M0. The ARM CORTEX M4 processor core is developed based on the Cortex-M3 core, and its performance is 20% higher than that of the Cortex-M3, to meet the needs of effective and easy-to-use control and signal processing functions. The biggest feature of ARM CORTEXM0 is the low-power design, so CortexM0 only needs a lower running speed to execute the same task, which greatly reduces the dynamic power consumption of the entire chip.

[0043] The chip structure provided by the present disclosure, by providing an independent application microprocessor, enables the user program to run independently without being restricted by the baseband chip.

[0044] In an exemplary embodiment, the baseband chip further includes a baseband peripheral group, which can be arranged in a first area on the same side as the baseband microprocessor, such as Figure 1 As shown, the lower part of the first area 101 is marked as a third sub-area 1012, and the baseband peripheral group can be distributed in the third sub-area 1012, wherein the baseband peripheral group includes one or more baseband peripheral units, such as Figure 1 When the baseband peripheral group includes multiple baseband peripheral units, the baseband peripheral group may include BP_ROM111, HWACC 112, BP_IRAM113, DFE 114, BP_SRAM115, RF116, UART117, SIM118, GPIO119, PLL121, TIMER120, WDT122, and 1-FLASH_CONTROLLER123, and the baseband microprocessor 10 is electrically connected to the above-mentioned baseband peripheral units respectively. Figure 1The distribution of the above-mentioned units is exemplarily shown in FIG. 1 . The above-mentioned units can be distributed according to actual conditions and are not specifically limited here.

[0045] In an exemplary embodiment, the application chip includes an application peripheral group. The application peripheral group is electrically connected to the application microprocessor 20, and the application peripheral group can be arranged in the second area on the same side as the application microprocessor, such as Figure 1 As shown, the lower part of the second area 201 is marked as a fourth sub-area 2022, and the application peripheral group can be distributed in the fourth sub-area 2022, wherein the application peripheral group includes one or more application peripheral units, such as Figure 1 As shown, when the application peripheral group includes multiple application peripheral units, the application peripheral group may include AP_ROM211, AP_SRAM213, TIMER215, OSC217, ADC219, PWM221, UART-2212, GPIO214, WDT216, SPIM218, I2C220, CLK TRIM222, and 2-FLASH_CONTROLLER223; the application microprocessor 20 is electrically connected to the above-mentioned application peripheral units respectively.

[0046] The chip structure disclosed in the present invention also integrates a series of rich peripheral device interfaces to help NB-IoT devices achieve more functions.

[0047] In an exemplary embodiment, if Figure 1 As shown, the chip structure 100 is also provided with at least one or more of the following units for use by the baseband chip and the application chip:

[0048] A memory unit 31 (FLASH), a reset unit 32 (Reset), a power management unit 33 (PMU), a bus unit 34 (LPC), an input / output multiplexer 35 (IPMUX), and an output / input pad 36 (I / OPad).

[0049] like Figure 1 As shown, a third area 103 is provided in the chip structure 100, and the third area 103 can be designed at the bottom of the chip structure 100, below the first area 101 and the second area 102. Units that can be shared by the baseband chip and the application chip are distributed in the third area 103, and the baseband microprocessor 10, the application microprocessor 20, and the flash memory (FLASH memory unit), the power management unit (PMU) and other units are integrated on the same chip structure. The high integration brings a smaller package size, which helps to reduce the cost of the chip to meet the demand for low-cost and small-volume IoT devices.

[0050] The present invention provides a chip working method, which is applied to a terminal. Figure 2The flowchart of a chip working method disclosed in the present invention is exemplified. Figure 2 As shown, the working method of the chip includes:

[0051] Step 110: Receive a working instruction for operating the chip, where the working instruction includes identification information of the waiting working mode.

[0052] like Figure 1 and Figure 2 As shown, the baseband chip and the application chip are integrated in a chip structure 100, forming a dual-core single-core structure, and by setting an independent application microprocessor, the user program can run independently without being restricted by the baseband chip. In this embodiment, the terminal can receive instructions for running the chip, independently control the baseband chip and the application chip, or use them in combination, that is, it is possible to make the two MCUs work at the same time, or use only one of them to work. In this embodiment, the received instruction contains identification information of the working mode to be specified by the chip. The identification information in this embodiment is used to characterize the information of the working mode entered by the specified chip. The identification information can be, for example, identification information corresponding to the working mode.

[0053] Step 120: Acquire configuration information, where the configuration information is used to characterize the correspondence between the preset working mode and the working chip. The working chip includes a baseband chip and an application chip. The baseband chip is used to access the NB network; the application chip is used to run user programs.

[0054] In this embodiment, the chip structure can be applied to the terminal, and the chip can run multiple working modes. The user can set two or more working modes in the operating system for different application scenarios. Due to the different working modes, the number of working chips and chips running can also be different. In this embodiment, the working chip includes a baseband chip and an application chip. The baseband chip is used to access the NB network; the application chip is used to run the user program, and the baseband chip and the application chip can exchange data. The correspondence between the preset working mode of the chip and the working chip can be stored in the configuration information in advance. When the terminal receives the working instruction of the running chip, the configuration information can be obtained from the memory module of the chip structure or other memory modules of the terminal to determine the waiting working mode of the running chip and the working chip corresponding to the waiting working mode according to the configuration information.

[0055] Step 130: Based on the configuration information, operate the working chip corresponding to the waiting working mode.

[0056] After obtaining the configuration information, the working chip to be used in the working mode can be determined according to the correspondence between the preset working modes and the working chips in the configuration information, and the working chip can be operated to enter the specified working mode, thereby adapting to different application scenarios to meet user needs and achieve the best balance between cost and efficiency.

[0057] According to an exemplary embodiment of the present disclosure, this embodiment is a further explanation of step S130 in the above embodiment. In the chip working method, based on the configuration information, running the working chip corresponding to the waiting working mode may include the following steps:

[0058] Step 210: Obtain identification information in the work order.

[0059] Each working mode may have its own corresponding identification information. After receiving the working instruction for running the chip, the identification information in the working instruction is identified and acquired to specify the chip to run the corresponding working mode according to the identification information.

[0060] Step 220: Determine the working chip corresponding to the waiting working mode according to the identification information and the correspondence between the preset working mode and the working chip, and operate the working chip.

[0061] After obtaining the identification information, the standby working mode of the specified chip is determined according to the identification information, and the corresponding working chip is determined according to the correspondence between the preset working mode and the working chip in the configuration information, and the working chip is operated to make the chip enter the corresponding working state.

[0062] According to an exemplary embodiment, most of the contents of the working method of the chip of this embodiment are the same as those of the above embodiments, and the difference between this embodiment and the above embodiments is that the preset working mode includes a first working mode, a second working mode and a third working mode, wherein the correspondence between the preset working mode and the working chip includes: the first working mode corresponds to running the baseband chip; the second working mode corresponds to running the baseband chip and the application chip, and the baseband chip and the application chip are configured to share a FLASH unit; the third working mode corresponds to running the baseband chip and the application chip, and the baseband chip and the application chip use a FLASH respectively.

[0063] Two or more working modes are set in the operating system. In order to distinguish different working modes, the different working modes are represented by the first working mode, the second working mode and the third working mode respectively. Different chips run in each working mode.

[0064] In the first working mode, only the baseband chip can be used as the working chip. The baseband chip can run the NBIOT program, and the external interface is the AT command interface. In the first working mode, the application chip can enter the sleep mode, thereby reducing system power consumption.

[0065] In the second working mode, the baseband chip and the application chip can work at the same time. The baseband chip runs the NBIOT program, and the application chip runs the user program. At the same time, a common FLASH unit is configured for the baseband chip and the application chip. For example, the first FLASH_CONTROLLER123 can be used together, which can save a FLASH unit. In the second working mode, a certain space, such as 64K space, can be allocated from the FLASH unit in the baseband chip to save the program of the application chip. The 64K space can meet the needs of most user programs. In some exemplary embodiments, when the chip is in the second working mode, the BOOT process of the application program can be the following process: the AP_ROM program accesses the FLASH of the baseband chip, copies the FIRMWARE program of the application chip to the AP_SRAM, and then the FIRMWARE of the application chip runs in the AP_SRAM.

[0066] In the third working mode, if Figure 1 As shown, since at least two FLASH are packaged in the chip structure 100, the baseband chip and the application chip can use their own FLASH to store programs and data. The baseband chip can use the first FLASH_CONTROLLER123 unit, and the application chip can use the second FLASH_CONTROLLER223. Therefore, from the perspective of use, it can be considered that two independent MCUs are running, the baseband chip runs the NBIOT program, and the application chip runs the user program, and they are not restricted to each other.

[0067] The working method of the chip disclosed in the present invention can also switch between two or more working modes according to actual needs, and automatically switch the current working mode to another working mode.

[0068] Figure 3 is a block diagram of a computer device 300 for a chip operation method according to an exemplary embodiment. For example, the computer device 300 may be provided as a terminal. Figure 3 The computer device 300 includes a processor 301, and the number of processors can be set to one or more as needed. The computer device 300 also includes a memory 302 for storing instructions that can be executed by the processor 301, such as application programs. The number of memories can be set to one or more as needed. The application programs stored therein can be one or more. The processor 301 is configured to execute instructions to execute the working method of the above-mentioned chip.

[0069] It should be understood by those skilled in the art that the embodiments of the present disclosure may be provided as methods, devices (equipment), or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data), including but not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media generally contain computer-readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0070] The present disclosure is described with reference to flowcharts and / or block diagrams of methods, apparatuses (devices) and computer program products according to embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0071] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 Functions specified in one or more boxes

[0072] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0073] In the present disclosure, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of more restrictions, the elements defined by the sentence "comprising..." do not exclude the presence of other identical elements in the article or device comprising the elements.

[0074] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0075] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the intent of the present disclosure also includes these modifications and variations.

Claims

1. A chip structure, applied to a terminal, characterized in that: The chip structure comprises: A baseband chip, arranged in the first area of ​​the chip structure, for accessing the NB network, the baseband chip comprising a baseband microprocessor, the baseband chip further comprising a baseband peripheral group, the baseband peripheral group being arranged in the third sub-area of ​​the first area; An application chip, arranged in the second area of ​​the chip structure, for running a user program, the application chip comprising an application microprocessor; Among them, the baseband chip is electrically connected to the application chip, and the baseband microprocessor communicates with the application microprocessor through an advanced high-performance bus and MAILBOX; the baseband peripheral group includes one or more baseband peripheral units, and the baseband microprocessor is electrically connected to the baseband peripheral units.

2. The chip structure according to claim 1, characterized in that: The baseband microprocessor is arranged in a first sub-area of ​​the first area, and the application microprocessor is arranged in a second sub-area of ​​the second area. The first sub-area is arranged opposite to the second sub-area.

3. The chip structure according to claim 2, characterized in that: The baseband microprocessor includes an ARM CORTEX M4 processor, and the application microprocessor includes an ARM CORTEX M0 processor.

4. The chip structure according to claim 1, characterized in that: The application chip further includes an application peripheral group, and the application peripheral group is arranged in a fourth sub-area of ​​the second area; The application peripheral group includes one or more application peripheral units, and the application microprocessor is electrically connected to the application peripheral units.

5. The chip structure according to claim 1, characterized in that: The chip structure further includes at least one or more of the following units arranged in the third region of the chip structure: FLASH memory unit, reset unit, power management unit, bus unit and input / output multiplexer; one or more of the above units are electrically connected to the baseband chip and the application chip respectively.

6. A chip working method, applied to a terminal, characterized in that: The working method is applied to the chip structure according to any one of claims 1 to 5, and the working method comprises: Receiving a working instruction for operating the chip, wherein the working instruction includes identification information of a waiting working mode; Acquire configuration information, where the configuration information is used to characterize the correspondence between the preset working mode and the working chip, where the working chip includes a baseband chip and an application chip, where the baseband chip is used to access the NB network; and the application chip is used to run a user program; Based on the configuration information, the working chip corresponding to the waiting working mode is operated.

7. The method according to claim 6, characterized in that The operating the working chip corresponding to the waiting working mode based on the configuration information includes: Obtaining identification information in the work order; According to the identification information and the correspondence between the preset working mode and the working chip, the working chip corresponding to the waiting working mode is determined, and the working chip is operated.

8. The method according to claim 7, characterized in that The preset working modes include a first working mode, a second working mode and a third working mode. The corresponding relationship between the preset working mode and the working chip includes: The baseband chip is operated in the first working mode; the baseband chip and the application chip are operated in the second working mode, and the baseband chip and the application chip are configured to share a FLASH unit; The baseband chip and the application chip are operated in the third working mode, and the baseband chip and the application chip are configured to use one FLASH unit respectively.

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