Semiconductor device and semiconductor memory device

Abstract

The present application relates to a semiconductor device and a semiconductor memory device. The semiconductor device of an embodiment includes: a substrate; a first electrode; a second electrode provided with the first electrode between the substrate and the second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode, in contact with the first electrode, containing at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn) and zinc (Zn), and having a chemical composition different from those of the first electrode and the second electrode; a conductive layer provided between the oxide semiconductor layer and the second electrode, in contact with the second electrode, containing at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O), and having a chemical composition different from those of the first electrode, the second electrode, and the oxide semiconductor layer; a gate electrode; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode.

Description

[0001] Reference to Related Applications

[0002] This application is based on and claims priority pursuant to Japanese Patent Application No. 2020-155889, filed on September 16, 2020, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] An embodiment of the present application relates to a semiconductor device and a semiconductor storage device. BACKGROUND

[0004] An oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer has an excellent characteristic that a channel off-leakage current is extremely small at the time of off operation. Therefore, research is being conducted on application of an oxide semiconductor transistor to a switching transistor of a memory cell of a dynamic random access memory (DRAM).

[0005] For example, when an oxide semiconductor transistor is applied to a switching transistor of a memory cell, the oxide semiconductor transistor is subjected to heat treatment accompanying formation of a wiring formed in an upper layer. Therefore, an oxide semiconductor transistor having stable characteristics with less variation in characteristics even after heat treatment is desired. SUMMARY

[0006] A problem to be solved by the present application is to provide a semiconductor device having stable characteristics.

[0007] A semiconductor device of an embodiment includes: a substrate; a first electrode; a second electrode provided with the first electrode between the substrate and the second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode, in contact with the first electrode, containing at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn) and zinc (Zn), and having a chemical composition different from those of the first electrode and the second electrode; a conductive layer provided between the oxide semiconductor layer and the second electrode, in contact with the second electrode, containing at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O), and having a chemical composition different from those of the first electrode, the second electrode, and the oxide semiconductor layer; a gate electrode; and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode.

[0008] According to the above-described configuration, a semiconductor device having stable characteristics can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0012] Figure 4 (a) and (b) are explanatory diagrams of the operation and effects of the semiconductor device according to the first embodiment.

[0013] Figure 5 This is a schematic cross-sectional view of a first variation of the semiconductor device according to the first embodiment.

[0014] Figure 6 This is a schematic cross-sectional view of a second variation of the semiconductor device according to the first embodiment.

[0015] Figure 7 This is a schematic cross-sectional view of a third variation of the semiconductor device according to the first embodiment.

[0016] Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0017] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0018] Figure 10 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0019] Figure 11 This is a schematic cross-sectional view of a variation of the semiconductor device according to the third embodiment.

[0020] Figure 12 This is an equivalent circuit diagram of the semiconductor memory device according to the fourth embodiment.

[0021] Figure 13 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Detailed Implementation

[0022] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once will sometimes be omitted.

[0023] Furthermore, for convenience, the terms "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" are merely terms indicating relative positional relationships within the diagram, and do not specify positional relationships relative to gravity.

[0024] Qualitative and quantitative analyses of the chemical composition of the components of the semiconductor devices and semiconductor memory devices described in this specification can be performed, for example, using secondary ion mass spectrometry (SIMS), energy-dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Furthermore, measurements of the thickness, inter-component distance, and grain size of the components of the semiconductor devices and semiconductor memory devices can be performed, for example, using transmission electron microscopy (TEM). Additionally, measurements of the carrier concentration of the components of the semiconductor devices and semiconductor memory devices can be performed, for example, using scanning diffusion resistance microscopy (SSRM).

[0025] (First Embodiment) The semiconductor device of the first embodiment includes: a substrate; a first electrode; a second electrode disposed between the first electrode and the substrate; an oxide semiconductor layer disposed between the first electrode and the second electrode and in contact with the first electrode, containing at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al) and tin (Sn) and zinc (Zn), and having a chemical composition different from that of the first electrode and the second electrode; a conductive layer disposed between the oxide semiconductor layer and the second electrode and in contact with the second electrode, containing at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn) and titanium (Ti) and oxygen (O), and having a chemical composition different from that of the first electrode, the second electrode and the oxide semiconductor layer; a gate electrode; and a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode.

[0026] Figure 1 , Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 AA' section view. In Figure 1 In this context, the up-down direction is referred to as the first direction. Figure 1In this context, the left and right directions are referred to as the second direction. The second direction is perpendicular to the first direction.

[0027] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor layer. The transistor 100 is a so-called surrounding gate transistor (SGT), in which a gate electrode surrounds the oxide semiconductor layer in which the channel is formed. The transistor 100 is a so-called vertical transistor.

[0028] The transistor 100 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, a channel layer 16, a contact layer 18, a gate electrode 20, a gate insulating layer 22, and an interlayer insulating layer 24. The gate insulating layer 22 includes a first region 22a and a second region 22b.

[0029] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Channel layer 16 is an example of an oxide semiconductor layer. Contact layer 18 is an example of a conductive layer.

[0030] The silicon substrate 10 is, for example, single-crystal silicon. The silicon substrate 10 is one example of a substrate. The substrate is not limited to a silicon substrate. The substrate may also be, for example, a semiconductor substrate other than a silicon substrate. The substrate may also be, for example, an insulating substrate.

[0031] The lower electrode 12 is disposed on the silicon substrate 10. An interlayer insulating layer 24 is disposed between the silicon substrate 10 and the lower electrode 12. The lower electrode 12 is an example of the first electrode.

[0032] The lower electrode 12 functions as either the source electrode or the drain electrode of the transistor 100.

[0033] The lower electrode 12 is a conductor. The lower electrode 12 may contain, for example, an oxide semiconductor or a metal. The lower electrode 12 may be, for example, an oxide semiconductor containing indium (In) and tin (Sn). The lower electrode 12 may be, for example, a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).

[0034] The lower electrode 12 may also have a multilayer structure of multiple conductors.

[0035] An upper electrode 14 is disposed on a silicon substrate 10. The upper electrode 14 is disposed on a lower electrode 12. The lower electrode 12 is disposed between the silicon substrate 10 and the upper electrode 14. The upper electrode 14 is an example of a second electrode. The direction from the upper electrode 14 toward the lower electrode 12 is a first direction.

[0036] The upper electrode 14 functions as either the source electrode or the drain electrode of the transistor 100.

[0037] The upper electrode 14 is a conductor. The upper electrode 14 may contain, for example, an oxide semiconductor or a metal. The upper electrode 14 may be, for example, an oxide semiconductor containing indium (In) and tin (Sn). The upper electrode 14 may be, for example, a metal containing tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).

[0038] The upper electrode 14 may also have a multilayer structure of multiple conductors.

[0039] Channel layer 16 is disposed on silicon substrate 10. Channel layer 16 is disposed between lower electrode 12 and upper electrode 14. Channel layer 16 is connected to lower electrode 12. Channel layer 16 is an example of an oxide semiconductor layer.

[0040] A channel is formed in the channel layer 16, which becomes a current path when the transistor 100 is turned on.

[0041] Channel layer 16 is an oxide semiconductor. Channel layer 16 may be, for example, amorphous.

[0042] The channel layer 16 contains at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al) and tin (Sn) and zinc (Zn).

[0043] Channel layer 16 contains, for example, indium (In), gallium (Ga), and zinc (Zn). The atomic concentration of zinc (Zn) in channel layer 16 is, for example, more than 5 atomic% and less than 20 atomic%.

[0044] The channel layer 16 has a chemical composition that is different from that of the lower electrode 12 and the upper electrode 14.

[0045] At least a portion of channel layer 16 is an n-type semiconductor. Channel layer 16 contains oxygen vacancies. The oxygen vacancies in channel layer 16 function as donors.

[0046] The length of the channel layer 16 in the first direction is, for example, 80 nm to 200 nm. The width of the channel layer 16 in the second direction is, for example, 20 nm to 100 nm.

[0047] A contact layer 18 is disposed between the channel layer 16 and the upper electrode 14. The contact layer 18 is in contact with the upper electrode 14. The contact layer 18 is, for example, in contact with the channel layer 16. The contact layer 18 is an example of a conductive layer.

[0048] The contact layer 18 has the function of reducing the resistance between the channel layer 16 and the upper electrode 14.

[0049] Contact layer 18 is, for example, an oxide semiconductor.

[0050] The contact layer 18 contains at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn) and titanium (Ti) and oxygen (O).

[0051] Contact layer 18 contains an oxide. Contact layer 18 is, for example, an oxide containing indium (In), tin (Sn), and zinc (Zn).

[0052] The contact layer 18 has a chemical composition different from that of the lower electrode 12, the upper electrode 14, and the channel layer 16.

[0053] Contact layer 18 is, for example, an n-type semiconductor. Contact layer 18 contains oxygen vacancies. The oxygen vacancies in contact layer 18 function as donors.

[0054] The thickness of the contact layer 18 in the first direction is, for example, 5 nm or more and 20 nm or less.

[0055] The oxygen defect density of the contact layer 18 is, for example, higher than that of the channel layer 16. The carrier concentration of the contact layer 18 is, for example, higher than that of the channel layer 16. The resistivity of the contact layer 18 is, for example, lower than that of the channel layer 16.

[0056] The atomic concentration of tin (Sn) in the contact layer 18 is, for example, higher than the atomic concentration of tin (Sn) in the channel layer 16. The atomic concentration of indium (In) in the contact layer 18 is, for example, higher than the atomic concentration of indium (In) in the channel layer 16.

[0057] The gate electrode 20 is disposed around the channel layer 16.

[0058] The gate electrode 20 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 20 contains, for example, tungsten (W).

[0059] The gate length of the gate electrode 20 is, for example, 20 nm or more and 100 nm or less. The gate length of the gate electrode 20 is the length of the gate electrode 20 in the first direction.

[0060] A gate insulating layer 22 is disposed between the channel layer 16 and the gate electrode 20. The gate insulating layer 22 surrounds the channel layer 16.

[0061] The gate insulating layer 22 is, for example, connected to the lower electrode 12. The gate insulating layer 22 is, for example, connected to the contact layer 18.

[0062] The gate insulating layer 22 includes a first region 22a and a second region 22b. A channel layer 16 is disposed between the first region 22a and the second region 22b.

[0063] The gate insulating layer 22 is, for example, an oxide or oxynitride. The gate insulating layer 22 may contain, for example, silicon oxide or aluminum oxide. The thickness of the gate insulating layer 22 is, for example, 2 nm or more but less than 10 nm.

[0064] Alternatively, an oxide layer (not shown) made of a different material than the gate insulating layer 22 can be provided between the channel layer 16 and the gate insulating layer 22.

[0065] An interlayer insulating layer 24 is disposed between the silicon substrate 10 and the lower electrode 12. The interlayer insulating layer 24 is disposed around the lower electrode 12, the upper electrode 14 and the gate electrode 20.

[0066] Interlayer insulating layer 24 is, for example, an oxide, nitride, or oxynitride. Interlayer insulating layer 24 may contain, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0067] When manufacturing transistor 100, after forming lower electrode 12 on silicon substrate 10, channel layer 16, contact layer 18 and upper electrode 14 are formed in sequence.

[0068] The function and effects of the semiconductor device according to the first embodiment will be explained below.

[0069] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess the excellent characteristic of extremely low channel leakage current during cutoff operation. Therefore, the industry is researching applications of OSTs, for example, as switching transistors in DRAM memory cells.

[0070] For example, when oxide semiconductor transistors are used as switching transistors in memory cells, the oxide semiconductor transistors undergo heat treatment during the formation of the wiring on the upper layer. Therefore, it is desirable to realize an oxide semiconductor transistor that exhibits stable characteristics with minimal changes even after heat treatment.

[0071] Figure 3 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 3 It is the semiconductor device of the first embodiment. Figure 1 The corresponding diagram.

[0072] The comparative example semiconductor device is transistor 900. Transistor 900 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The difference between transistor 900 and transistor 100 of the first embodiment is that transistor 900 does not have a contact layer 18.

[0073] The characteristics of the comparative example transistor 900 can change due to the heat treatment applied after the transistor structure is formed. In particular, when heat treatment is performed in an oxygen-containing atmosphere, the asymmetry of the conduction current becomes a problem. The asymmetry of the conduction current refers to the difference in the magnitude of the conduction current when current flows from the upper electrode 14 to the lower electrode 12 and when current flows from the lower electrode 12 to the upper electrode 14.

[0074] In particular, the conduction current in the direction from the lower electrode 12 toward the upper electrode 14 is smaller than the conduction current in the direction from the upper electrode 14 toward the lower electrode 12.

[0075] Figure 4 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. Figure 4 (a) is an energy band diagram near the interface between the upper electrode 14 and the channel layer 16 of the transistor 900 of the comparative example. Figure 4 (b) is an energy band diagram near the interface between the upper electrode 14 and the contact layer 18 of the transistor 100 in the first embodiment. Figure 4 It is the energy band diagram after the transistor structure is formed and then subjected to heat treatment in an oxygen-containing atmosphere.

[0076] like Figure 4 As shown in (a), a Schottky barrier is formed at the interface between the upper electrode 14 and the channel layer 16. In other words, a Schottky diode is formed between the upper electrode 14 and the channel layer 16.

[0077] When transistor 900 is heat-treated in an oxygen-containing atmosphere, oxygen diffuses from the atmosphere into channel layer 16, thereby reducing the density of oxygen defects in channel layer 16 near upper electrode 14. Consequently, the carrier concentration in channel layer 16 near upper electrode 14 decreases. This decrease in carrier concentration in channel layer 16 near upper electrode 14 widens the Schottky barrier.

[0078] On the other hand, the amount of oxygen diffusing into the channel layer 16 near the lower electrode 12 is less than the amount of oxygen diffusing into the channel layer 16 near the upper electrode 14. Therefore, the carrier concentration in the channel layer 16 near the lower electrode 12 decreases less. Consequently, the variation in the width of the Schottky barrier between the channel layer 16 and the lower electrode 12 is smaller.

[0079] Therefore, the conduction current in the direction from the channel layer 16 toward the upper electrode 14 is smaller than the conduction current in the direction from the upper electrode 14 toward the channel layer 16.

[0080] The transistor 100 of the first embodiment has a contact layer 18 provided between the upper electrode 14 and the channel layer 16. For example... Figure 4As shown in (b), in the case of the transistor 100 of the first embodiment, a Schottky barrier is also formed at the interface between the upper electrode 14 and the contact layer 18. In other words, a Schottky diode is formed between the upper electrode 14 and the contact layer 18.

[0081] The carrier concentration in contact layer 18 is higher than that in channel layer 16. Therefore, even during heat treatment in an oxygen-containing atmosphere, and with oxygen diffusing into contact layer 18, the carrier concentration in contact layer 18 does not change significantly. Due to the higher carrier concentration in contact layer 18, the Schottky barrier width at the interface between upper electrode 14 and contact layer 18 is narrower compared to the transistor 900 of the comparative example. Therefore, electrons can easily tunnel through the Schottky barrier from upper electrode 14 toward contact layer 18. In other words, current flows more easily from channel layer 16 toward upper electrode 14 compared to the transistor 900 of the comparative example.

[0082] As a result, even under heat treatment in an oxygen-containing atmosphere, the magnitude of the conduction current is unlikely to differ when current flows from the upper electrode 14 to the lower electrode 12 and when current flows from the lower electrode 12 to the upper electrode 14. Therefore, the asymmetry in the conduction current caused by the heat treatment is suppressed. By suppressing the asymmetry in the conduction current, the characteristic variation of the transistor is also reduced. Therefore, according to transistor 100, an oxide semiconductor transistor can be realized that suppresses the asymmetry in the conduction current after heat treatment and possesses stable characteristics.

[0083] From the viewpoint of making the carrier concentration of the contact layer 18 higher than that of the channel layer 16, it is preferable that the atomic concentration of tin (Sn) contained in the contact layer 18 is higher than that of the atomic concentration of tin (Sn) contained in the channel layer 16.

[0084] From the viewpoint of making the carrier concentration of the contact layer 18 higher than that of the channel layer 16, it is preferable that the atomic concentration of indium (In) contained in the contact layer 18 is, for example, higher than that of indium (In) contained in the channel layer 16.

[0085] (Example of the first variation) Figure 5 This is a schematic cross-sectional view of a first variation of the semiconductor device according to the first embodiment. Figure 5 It is the semiconductor device of the first embodiment. Figure 1 The corresponding diagram.

[0086] A first variation of the semiconductor device in the first embodiment is a transistor 110. The transistor 110 differs from the transistor 100 in the first embodiment in that a channel layer 16 is disposed between the contact layer 18 and the interlayer insulating layer 24.

[0087] According to the transistor 110 of the first variation, the resistance between the contact layer 18 and the channel layer 16 is reduced, and the conduction current is increased compared with the transistor 100 of the first embodiment.

[0088] (Second variation example) Figure 6 This is a schematic cross-sectional view of a second variation of the semiconductor device according to the first embodiment. Figure 6 It is the semiconductor device of the first embodiment. Figure 1 The corresponding diagram.

[0089] A second variation of the semiconductor device in the first embodiment is a transistor 120. The transistor 120 differs from the transistor 100 in the first embodiment in that the contact layer 18 is sandwiched or surrounded by the gate insulating layer 22.

[0090] (Example 3) Figure 7 This is a schematic cross-sectional view of a third variation of the semiconductor device according to the first embodiment. Figure 7 It is the semiconductor device of the first embodiment. Figure 2 The corresponding diagram.

[0091] A third variation of the semiconductor device in the first embodiment is a transistor 130. The transistor 130 differs from the transistor 100 of the first embodiment in that the first region 22a and the second region 22b of the gate insulating layer 22 are separated. The gate electrode 20 of the transistor 130 is also separated into different left and right regions.

[0092] Based on the first embodiment and its variations, an oxide semiconductor transistor is realized that suppresses the asymmetry of the conduction current after heat treatment and has stable characteristics.

[0093] (Second Embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that, in a cross-section parallel to a first direction from the first electrode toward the second electrode and including an oxide semiconductor layer, the first distance between the first region and the second region at the first position is smaller than the second distance between the first region and the second region at the second position, and the distance from the second position to the first electrode is greater than the distance between the first electrode and the first position. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0094] Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0095] The semiconductor device in the second embodiment is a transistor 200. Transistor 100 is an oxide semiconductor transistor in which channels are formed in an oxide semiconductor layer. Transistor 100 is a so-called SGT, wherein the gate electrode surrounds the oxide semiconductor layer in which the channels are formed. Transistor 200 is a so-called vertical transistor.

[0096] The transistor 200 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, a channel layer 16, a contact layer 18, a gate electrode 20, a gate insulating layer 22, and an interlayer insulating layer 24. The gate insulating layer 22 includes a first region 22a and a second region 22b.

[0097] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Channel layer 16 is an example of an oxide semiconductor layer. Contact layer 18 is an example of a conductive layer.

[0098] In transistor 200, in a cross-section parallel to the first direction from lower electrode 12 toward upper electrode 14 and including channel layer 16, the first position ( Figure 8 The first distance between the first region 22a and the second region 22b at point P1 in the diagram ( Figure 8 d1) is less than the second position ( Figure 8 The second distance between region 22a and region 22b at point P2 in the diagram (P2) is... Figure 8 In the case of d2), the distance between the second position and the lower electrode 12 is greater than the distance between the lower electrode 12 and the first position P1.

[0099] The width of the channel layer 16 in the second direction decreases from the upper electrode 14 toward the lower electrode 12. The side surface of the channel layer 16 has a positive cone shape.

[0100] For example, when manufacturing transistor 200, after forming the lower electrode 12, the gate electrode 20, and the interlayer insulating layer 24, a hole pattern is formed to embed the gate insulating layer 22 and the channel layer 16. The aforementioned structure can be formed by controlling the etching process to reduce the lower aperture of the hole during hole pattern formation.

[0101] According to the second embodiment, similar to the first embodiment, an oxide semiconductor transistor can be realized that suppresses the asymmetry of the conduction current after heat treatment and has stable characteristics.

[0102] (Third Embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that it further includes an insulating layer disposed between the first electrode and the second electrode, and is surrounded by an oxide semiconductor layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0103] Figure 9 , Figure 10 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 10 yes Figure 9 BB's sectional view. In Figure 9In this context, the up-down direction is referred to as the first direction. Figure 9 In this context, the left and right directions are referred to as the second direction. The second direction is perpendicular to the first direction.

[0104] The semiconductor device in the third embodiment is a transistor 300. The transistor 300 is an oxide semiconductor transistor in which channels are formed in an oxide semiconductor layer. The transistor 300 is a so-called SGT (Structured Ground Tunneling) transistor, in which a gate electrode surrounds the oxide semiconductor layer in which the channels are formed. The transistor 300 is a so-called vertical transistor.

[0105] The transistor 300 includes a silicon substrate 10, a lower electrode 12, an upper electrode 14, a channel layer 16, a contact layer 18, a gate electrode 20, a gate insulating layer 22, an interlayer insulating layer 24, and a core insulating layer 26. The gate insulating layer 22 includes a first region 22a and a second region 22b.

[0106] Silicon substrate 10 is an example of a substrate. Lower electrode 12 is an example of a first electrode. Upper electrode 14 is an example of a second electrode. Channel layer 16 is an example of an oxide semiconductor layer. Contact layer 18 is an example of a conductive layer. Core insulating layer 26 is an example of an insulating layer.

[0107] A core insulating layer 26 is disposed between the lower electrode 12 and the upper electrode 14. The core insulating layer 26 is surrounded by a channel layer 16. A portion of the channel layer 16 is disposed, for example, between the lower electrode 12 and the core insulating layer 26.

[0108] The core insulating layer 26 is, for example, an oxide, a nitride, or a oxynitride. The core insulating layer 26 may contain, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0109] Transistor 300 incorporates a core insulating layer 26, for example, by thinning the thickness of the channel layer 16 in the second direction. By thinning the channel layer 16, the controllability of the gate electrode 20 over the potential of the channel layer 16 is improved. Therefore, for example, the cutoff characteristics of transistor 300 are improved.

[0110] (Example of variation) Figure 11 This is a schematic cross-sectional view of a variation of the semiconductor device according to the third embodiment. Figure 11 It is the semiconductor device of the third embodiment. Figure 9 The corresponding diagram.

[0111] A variation of the semiconductor device in the third embodiment is transistor 310. The difference between transistor 310 and transistor 100 in the third embodiment is that the channel layer 16 is disposed between the contact layer 18 and the interlayer insulating layer 24.

[0112] According to the modified transistor 310, the resistance between the contact layer 18 and the channel layer 16 is reduced, and the conduction current is increased compared to the transistor 300 of the third embodiment.

[0113] According to the third embodiment and its variations, similar to the first embodiment, an oxide semiconductor transistor can be realized that suppresses the asymmetry of the conduction current after heat treatment and has stable characteristics.

[0114] (Fourth Embodiment) The semiconductor memory device of the fourth embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode and connected to the first electrode, containing at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al) and tin (Sn) and zinc (Zn), and having a chemical composition different from that of the first electrode and the second electrode; a conductive layer disposed between the oxide semiconductor layer and the second electrode and connected to the second electrode, containing at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn) and titanium (Ti) and oxygen (O), and having a chemical composition different from that of the first electrode, the second electrode and the oxide semiconductor layer; a gate electrode; a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode; and a capacitor electrically connected to the first electrode.

[0115] The semiconductor memory device of the fourth embodiment is a semiconductor memory 400. The semiconductor memory device of the fourth embodiment is a DRAM. The semiconductor memory 400 uses the transistor 100 of the first embodiment as a switching transistor for the memory cell of the DRAM.

[0116] Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0117] Figure 12 This is an equivalent circuit diagram of the semiconductor memory device according to the fourth embodiment. Figure 12 The example illustrates a case where there is only one storage unit (MC), but multiple storage units (MCs) can also be configured.

[0118] The semiconductor memory 400 includes a memory cell MC, a word line WL, a bit line BL, and a board line PL. The memory cell MC includes a switching transistor TR and a capacitor CA. Figure 12 The area enclosed by the dashed line is the storage unit MC.

[0119] Word line WL is electrically connected to the gate electrode of switching transistor TR. Bit line BL is electrically connected to one of the source and drain electrodes of switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source and drain electrodes of switching transistor TR. The other electrode of capacitor CA is connected to plate line PL.

[0120] The storage cell MC stores data by storing charge in the capacitor CA. Data writing and reading are performed by turning on the switching transistor TR.

[0121] For example, when the required voltage is applied to the bit line BL, the switching transistor TR is turned on to write data to the memory cell MC.

[0122] In addition, for example, by turning on the switching transistor TR, the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor is detected, and the data of the memory cell MC is read out.

[0123] Figure 13 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Figure 13 This shows a cross-section of the memory cell MC of the semiconductor memory 400.

[0124] The semiconductor memory 400 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, and an interlayer insulating layer 24. The silicon substrate 10 is an example of a substrate.

[0125] The switching transistor TR includes a lower electrode 12, an upper electrode 14, a channel layer 16, a contact layer 18, a gate electrode 20, and a gate insulating layer 22. The lower electrode 12 is an example of a first electrode. The upper electrode 14 is an example of a second electrode. The channel layer 16 is an example of an oxide semiconductor layer. The contact layer 18 is an example of a conductive layer.

[0126] The switching transistor TR has the same construction as the transistor 100 in the first embodiment.

[0127] Capacitor CA is disposed between silicon substrate 10 and switching transistor TR. Capacitor CA is disposed between silicon substrate 10 and lower electrode 12. Capacitor CA is electrically connected to lower electrode 12.

[0128] The capacitor CA includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 is electrically connected to the lower electrode 12. For example, the unit electrode 71 is connected to the lower electrode 12.

[0129] The unit electrode 71 and the plate electrode 72 are, for example, titanium nitride. The capacitor insulating film 73 has, for example, a multilayer structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0130] Gate electrode 20 is electrically connected, for example, to word line WL (not shown). Upper electrode 14 is electrically connected, for example, to bit line BL (not shown). Plate electrode 72 is connected, for example, to plate line PL (not shown).

[0131] In manufacturing the semiconductor memory 400, after forming a capacitor CA on a silicon substrate 10, a switching transistor TR is formed. In forming the switching transistor TR, after forming the lower electrode 12, a channel layer 16, a contact layer 18, and an upper electrode 14 are formed sequentially.

[0132] The semiconductor memory 400 utilizes an oxide semiconductor transistor with extremely low channel leakage current during cutoff operation in the switching transistor TR. Therefore, it achieves DRAM with excellent charge retention characteristics.

[0133] Furthermore, the switching transistor TR of the semiconductor memory 400 has a contact layer 18 between the channel layer 16 and the upper electrode 14. Therefore, the asymmetry of the conduction current caused by the applied heat treatment is suppressed. Consequently, the characteristics of the switching transistor TR are stable, and the characteristics of the semiconductor memory 400 are also stable.

[0134] According to the fourth embodiment, a semiconductor memory has been realized that suppresses the asymmetry of the conduction current after the heat treatment of the switching transistor and has stable characteristics.

[0135] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included in the scope and spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: a substrate; a first electrode; and a second electrode disposed therebetween the first electrode and the substrate; An oxide semiconductor layer, disposed between the first electrode and the second electrode and connected to the first electrode, contains at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn) and zinc (Zn), and its chemical composition differs from that of the first electrode and the second electrode; a conductive layer, disposed between the oxide semiconductor layer and the second electrode and connected to the second electrode, contains at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O), and its chemical composition differs from that of the first electrode, the second electrode, and the oxide semiconductor layer; Gate electrode; A gate insulating layer is disposed between the oxide semiconductor layer and the gate electrode; the carrier concentration of the conductive layer is higher than that of the oxide semiconductor layer.

2. The semiconductor device of claim 1, wherein the gate electrode surrounds the oxide semiconductor layer.

3. The semiconductor device according to claim 1 or 2, further comprising an insulating layer disposed between the first electrode and the second electrode, and surrounded by the oxide semiconductor layer.

4. The semiconductor device of claim 3, wherein a portion of the oxide semiconductor layer is disposed between the first electrode and the insulating layer.

5. The semiconductor device according to claim 1 or 2, wherein the oxide semiconductor layer is in contact with the conductive layer.

6. The semiconductor device according to claim 1 or 2, wherein the carrier concentration of the conductive layer is higher than the carrier concentration of the oxide semiconductor layer.

7. The semiconductor device according to claim 1 or 2, wherein the atomic concentration of tin (Sn) contained in the conductive layer is higher than the atomic concentration of tin (Sn) contained in the oxide semiconductor layer.

8. The semiconductor device according to claim 1 or 2, wherein the atomic concentration of indium (In) contained in the conductive layer is higher than the atomic concentration of indium (In) contained in the oxide semiconductor layer.

9. The semiconductor device according to claim 1 or 2, wherein the gate insulating layer has a first region and a second region, the second region having the oxide semiconductor layer disposed therebetween the first region and the first region, and in a cross-section parallel to a first direction from the first electrode toward the second electrode and including the oxide semiconductor layer, a first distance between the first region and the second region at a first location is less than a second distance between the first region and the second region at a second location, and the distance from the second location to the first electrode is greater than the distance between the first electrode and the first location.

10. The semiconductor device according to claim 1 or 2, wherein the oxide semiconductor layer comprises indium (In), gallium (Ga) and zinc (Zn).

11. A semiconductor device comprising: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode, and connected to the first electrode, comprising at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn) and zinc (Zn), having a chemical composition different from that of the first electrode and the second electrode; and a conductive layer disposed between the oxide semiconductor layer and the second electrode, and connected to the second electrode, comprising at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O), having a chemical composition different from that of the first electrode, the second electrode, and the oxide semiconductor layer; Gate electrode; A gate insulating layer is disposed between the oxide semiconductor layer and the gate electrode; the carrier concentration of the conductive layer is higher than that of the oxide semiconductor layer; the gate insulating layer has a first region and a second region, the oxide semiconductor layer is disposed between the second region and the first region, and in a cross-section parallel to a first direction from the first electrode toward the second electrode and including the oxide semiconductor layer, the first distance between the first region and the second region at the first position is less than the second distance between the first region and the second region at the second position, and the distance from the second position to the first electrode is greater than the distance between the first electrode and the first position.

12. The semiconductor device of claim 11, wherein the gate electrode surrounds the oxide semiconductor layer.

13. The conductor device according to claim 11 or 12, further comprising: an insulating layer disposed between the first electrode and the second electrode, surrounded by the oxide semiconductor layer.

14. The semiconductor device of claim 13, wherein a portion of the oxide semiconductor layer is disposed between the first electrode and the insulating layer.

15. The semiconductor device of claim 11 or 12, wherein the oxide semiconductor layer is in contact with the conductive layer.

16. The semiconductor device of claim 11 or 12, wherein the carrier concentration of the conductive layer is higher than the carrier concentration of the oxide semiconductor layer.

17. The semiconductor device according to claim 11 or 12, wherein the atomic concentration of tin (Sn) contained in the conductive layer is higher than the atomic concentration of tin (Sn) contained in the oxide semiconductor layer.

18. The semiconductor device according to claim 11 or 12, wherein the atomic concentration of indium (In) contained in the conductive layer is higher than the atomic concentration of indium (In) contained in the oxide semiconductor layer.

19. A semiconductor memory device comprising: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode, and connected to the first electrode, containing at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn) and zinc (Zn), having a chemical composition different from that of the first electrode and the second electrode; and a conductive layer disposed between the oxide semiconductor layer and the second electrode, and connected to the second electrode, containing at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti) and oxygen (O), having a chemical composition different from that of the first electrode, the second electrode, and the oxide semiconductor layer; Gate electrode; A gate insulating layer is disposed between the oxide semiconductor layer and the gate electrode; and a capacitor is electrically connected to the first electrode; the carrier concentration of the conductive layer is higher than that of the oxide semiconductor layer.

20. The semiconductor memory device of claim 19, further comprising a substrate, wherein the capacitor is disposed between the substrate and the first electrode.

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