Coprocessor for cryptographic operations

Abstract

Certain examples described herein relate to a coprocessor that allows a processing unit to efficiently perform cryptographic operations. The coprocessor has an arithmetic unit configured to perform discrete binary arithmetic using bit sequences loaded from memory. The coprocessor can be configured for fast, low-power computation of certain functions, including low-level building blocks for cryptographic operations. These functions can include Boolean logic and integer arithmetic. The coprocessor has a set of control registers that can be written by the processing unit to control the coprocessor. Addresses of one or more sources and destinations can be computed by the coprocessor to enable flexible operations. The coprocessor can allow fast computation of many high-level cryptographic operations, including those that are "post-quantum" secure.

Description

TECHNICAL FIELD

[0001] The present invention relates to cryptographic hardware, in particular a co-processor for performing cryptographic operations. The co-processor can be used as part of a cryptographic system-on-a-chip. A method of performing cryptographic operations is also described. BACKGROUND

[0002] Recently, the number of devices connected to computer networks has exploded. For example, Internet connectivity is expanding from computing devices such as desktop and laptop computers to embedded systems within everyday items such as motor vehicles, light bulbs, refrigerators, medical devices, thermostats, and surveillance systems. Telecommunication links allow many low-cost computing devices to report sensor data and / or be controlled worldwide. One problem with these connected devices is that they are often vulnerable to attack and malicious control. For example, hundreds of thousands of embedded devices can be attacked by a malicious party and used to carry out a distributed denial of service attack. In many cases, control over these devices is easily obtained due to poor or limited implementation of cryptographic protocols. As the number and popularity of these connected devices grows, how to protect them is an open question.

[0003] Another consideration when protecting connected computing devices is the possibility of future attacks using quantum computing. Quantum computers have been of primary theoretical interest for many years. However, research implementations of quantum computers are rapidly advancing. Currently available are quantum computers with 50 and 72 qubits, and many research groups are actively working on higher qubit machines. Given the possible reality of quantum computing in the future, recent work has shown that many well-known public key cryptographic systems can be broken by sufficiently powerful quantum computers.

[0004] There is a challenge in implementing cryptographic functions, especially those that are "post-quantum" secure, in that many of these functions are resource intensive. For example, many cryptographic functions involve complex mathematical functions that use long bit length values. These functions often consume a large number of processor cycles and are difficult to implement within low resource embedded devices. Additionally, as end-to-end encryption of both data and communications becomes ubiquitous, these cryptographic functions must also be repeatedly performed at high speed. To be secure is to be slow.

[0005] US 2008 / 0019524 Al describes an apparatus for a low-power AES cipher circuit for an embedded system. The apparatus includes an interface circuit for inputting and outputting data and control commands in cooperation with a general-purpose processor; a code processing unit for performing round operations in an operation order of an add round key operation, a byte substitution key operation, a shift row operation, and a mix column operation; a data memory for storing data input through the interface circuit and operation results processed at the code processing unit; a data selection unit for selecting data input / output to and from the code processing unit and the memory unit; and a control unit for controlling the code processing unit, the memory unit, and the data selection unit so that the round operations of a set round are repeatedly performed on data input from the interface circuit, and the add round key operation is performed on a shift row operation result value and a secret key during a last round.

[0006] It is desirable to provide an efficient implementation of a cryptographic operation. For example, it is desirable to provide an implementation that can be used within low resource embedded systems and / or in high speed data processing operations, while providing the ability to resist attacks in a post-quantum environment. SUMMARY

[0007] Aspects of the application are set out in the accompanying independent claims. Certain variants of the application are then set out in the appended dependent claims. BRIEF DESCRIPTION OF DRAWINGS

[0008] Examples of the application will now be described, by way of example only, with reference to the accompanying drawings in which:

[0009] Figure 1 is a schematic diagram illustrating a co-processor for a cryptographic operation according to one example;

[0010] Figure 2 is a schematic diagram illustrating a cryptographic on-chip system according to one example;

[0011] Figure 3 is a schematic diagram illustrating a co-processor for a cryptographic operation coupled to a system bus within a computing device according to one example;

[0012] Figure 4 is a schematic diagram illustrating the operations of an arithmetic engine according to one example;

[0013] Figure 5A is a schematic diagram illustrating a multi-dimensional data array according to one example;

[0014] Figure 5B is a schematic diagram illustrating how an arithmetic unit can be iteratively applied to a set of multi-dimensional data arrays according to one example;

[0015] Figure 6 is a schematic diagram illustrating how source data can be shifted on input according to one example;

[0016] Figure 7 is a schematic diagram illustrating how a main processing unit and an auxiliary processing unit can access data through a system bus according to one example;

[0017] Figure 8 is a table illustrating a set of example control registers;

[0018] Figure 9 is a flowchart illustrating a method of performing cryptographic operations according to one example; and

[0019] Figure 10 is a table for use with example Boolean operations. DETAILED DESCRIPTION

[0020] Certain examples described herein relate to a co-processor that allows a processing unit to efficiently perform cryptographic operations. The co-processor has an arithmetic unit configured to perform discrete binary arithmetic using bit sequences loaded from memory. These bit sequences can be bit blocks, and so the co-processor can be referred to as a form of “Bit Block Transposer”, i.e. a hardware-assisted system for moving and manipulating bit blocks in memory (where the term “Bit Block Transposer” comes from the “BitBLT” microcode instruction of the Cray Odyssey computer). The co-processor can be configured for fast, low-power computation of certain functions, including low-level building blocks for cryptographic operations. These functions can include Boolean logic and / or integer arithmetic. In this way, the processing unit can efficiently offload resource-intensive computations for cryptographic operations to the co-processor, which operates as a dedicated and secure hardware device. The co-processor can provide low-level bit operations that are atomic from the perspective of the processing unit. Thus, the co-processor can allow fast computation of many high-level cryptographic operations, including those that are “post-quantum” secure.

[0021] In some of the examples described herein, coprocessors can be used in a wide variety of computing systems, from internet servers to embedded devices. In one implementation, a coprocessor can be provided as part of a broader cryptographic system-on-a-chip (SoC), allowing many low-cost embedded devices to implement "post-quantum" cryptography and provide "post-quantum" secure systems. For example, functions implemented by the coprocessor's arithmetic engine can allow for fast execution of code-based or lattice-based cryptographic operations, for example, by offloading many common low-level binary logic functions such as integer addition, subtraction, and multiplication. The coprocessor can be configured or pre-programmed with a set of available functions, which can be selected by the processing unit via function flags or variables in the coprocessor's control registers. The coprocessor may be able to compute certain functions more quickly by avoiding the loading and interpretation of different instructions required by the processing unit. For example, the set of available functions can be hard-configured in a programmable microcircuit system and configured to access data in a source and destination register arrangement, where the data is extracted and stored based on memory addresses generated by an address generator for each iteration of the arithmetic engine. Cryptographic processors can be particularly beneficial when used with embedded and resource-constrained targets.

[0022] Figure 1 Example 100 of cryptographic coprocessor 110 is shown. Figure 1 In this embodiment, the cryptographic coprocessor 110 includes a set of control registers 115, control logic 120, an arithmetic engine 125, and an address generator 130. The cryptographic coprocessor 110 can be implemented using a programmable field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The components of the cryptographic coprocessor 110 can be configured using a hardware description language (HDL). In some cases, different components of the cryptographic coprocessor 110 can be implemented using one or more of dedicated logic circuit systems, ASICs, FPGAs, and firmware instructions. In one scenario, the functionality of the cryptographic coprocessor 110 can be provided through one or more of microcode and firmware updates. In this case, authentication of the microcode may be required to ensure security.

[0023] The cryptographic coprocessor 110 is designed for use with external or main processing units. This is in Figure 2 As shown in Example 200, the cryptographic coprocessor 110 is communicatively coupled to the central processing unit (CPU) 220 via a system bus 230. The system bus 230 may include one or more of a data bus and an address bus. Figure 2The example 200 shows a cryptographic co-processor 110 and a central processing unit 220 forming part of a cryptographic-on-a-chip system 240. This can be embedded into a range of devices from smart cards to server motherboards. Alternatively, the cryptographic co-processor 110 can form part of a motherboard for a computing device such as a server, laptop, tablet or smartphone. The CPU can comprise a microprocessor with one or more processing cores. The CPU can comprise a reduced instruction set computer (RISC) processor such as a RISC-V processor.

[0024] In one example, one or more of the cryptographic co-processor 110 and cryptographic-on-a-chip system 240 can be provided (e.g., packaged) as a discrete unit. For example, the discrete unit can be a self-contained secure microcontroller (e.g., supplied as a smart card, universal serial bus (USB) device, and / or radio frequency identification (RFID) device), an auxiliary cryptographic module or accelerator, a cryptographic trusted platform module (TPM) or hardware security module (HSM). In certain examples, the cryptographic co-processor 110 and CPU 220 can be located in the same place on a circuit board. Thus, one or more of the cryptographic co-processor 110 and cryptographic-on-a-chip system 240 can be provided as a single chip that is easily added to additional computing boards for a wide variety of computing devices.

[0025] Returning to Figure 1The control registers 115 are accessible by an external processing unit (e.g., CPU 220). The external processing unit can write data to the control registers 115 to control the operations of the cryptographic co-processor 110. The control registers 115 can be memory mapped such that they appear to the external processing unit as an addressable portion of memory. Alternatively, the control registers can form part of a set of registers of the external processing unit named a single instruction multiple data (SIMD) or vector register set. In a RISC instruction set architecture (ISA) such as RISC-V, the control registers 115 can be implemented as one or more control and status registers (CSRs) and / or one or more vector extensions, e.g., in the latter case the control registers can be considered as one or more vector registers. The set of control registers can be used to exchange data and control information between the cryptographic co-processor 110 and the external processing unit. The control registers 115 can be used to store one or more of: a status (e.g., busy or waiting for an instruction), a function to be executed, a size of source and / or destination data, a memory location of source and / or destination data, a shift parameter for one or more of an address and data array, an increment parameter, and / or an indicator showing whether a current function is complete. The external processing unit can be configured to read the values stored within the control registers 115 to determine whether an output of a function is available, can receive an interrupt from the cryptographic co-processor, and / or can wait for a predetermined number of clock cycles associated with a function. Different approaches can be used depending on implementation requirements.

[0026] In Figure 1In the example of FIG. 1, control logic 120 reads values written to control registers 115 by an external processing unit and controls the operations of arithmetic engine 125 and address generator 130 based on these values. One of the set of control registers 115 can be configured to store an indication of a function to be performed using arithmetic engine 125. The function can be selected from a set of available functions, where the set of available functions can be pre-configured (e.g., pre-programmed into an ASIC or FPGA, or configured within an ASIC or FPGA). The set of available functions are configured to manipulate one or more sequences of bits read from a data source (hereinafter "source") and store the results of the manipulation as destination data (hereinafter "destination"). For example, the set of available functions can include certain integer arithmetic functions that are frequently used by post-quantum cryptography methods such as lattice-based or code-based cryptography methods. The integer arithmetic functions can include multiplication operations, addition operations, and subtraction operations, performed on one or more sequences of bits that are treated as representing integer values (e.g., 8, 16, or 32-bit integers). In the case of Boolean operations, the sequences of bits can represent integer values, but can be treated as sequences of independent bits (e.g., for bit logic). Different bit length values can be supported. Arithmetic engine 125 can be controlled by control logic 120 to perform the function indicated in control registers 115. The indicated function can be performed on binary data stored in a set (e.g., plurality) of source registers, and the output of the function can be stored in at least one destination register. The set of source registers can be treated as the "source" of the function described above, and the at least one destination register can be treated as the "destination" of the output of the function defined above. The source and destination registers can form part of arithmetic engine 125 and / or can comprise specific locations within internal memory of cryptography co-processor 110.

[0027] In one case, control logic 120 can include one or more additional registers that can be used to store values read from the set of control registers. For example, if the set of control registers 115 are memory mapped to the address space of an external processing unit, a set of secondary control registers can be used to speed up operations. The set of secondary control registers can not be accessible by the external processing unit; instead, they are used internally by cryptography co-processor 110. In this case, when a new operation starts, one or more values in the set of control registers 115 can be copied to the set of secondary control registers. This can avoid the need to re-initialize the set of control registers 115 for each operation. The set of secondary control registers can be used to store a set of "running addresses". For example, if an operation is copying a small block of data to multiple destination addresses, only the destination address parameters need to be updated, and the operation can start separately for each set of updated destination address parameters.

[0028] In practice, control logic 120 can include (system) bus control and chip select logic, as well as signaling for resetting cryptographic coprocessor 110. In some implementations, control logic can also include logic for generating one or more interrupts for an external processing unit. One function of control registers 115 and control logic 120 can provide an interface between the internal logic of cryptographic coprocessor 110 and the host system bus and external processing unit.

[0029] Address generator 130 is adapted to determine a set of source addresses for loading binary data from a memory into the set of source registers and at least one destination address for storing binary data from at least one destination register in a memory. The memory can include an internal memory of cryptographic coprocessor 110 or an externally coupled memory. Address generator 130 can determine the source and destination addresses based on values stored in control registers 115. These values can include a starting address and parameters indicating how to navigate in the memory. In one example explained in more detail later, cryptographic coprocessor 110 can be configured to operate on a multi-dimensional representation of data within a memory and save the result of the function as a similar multi-dimensional representation in the memory. For example, a sequence of memory locations starting at a starting address can be viewed as a flat matrix of height and width as defined by values within control registers 115. In one case, if the function applied by arithmetic engine 125 does not act on all available sources, the source addresses can be determined only for a subset of available sources. For example, address generator 130 can include independent logic for each available source, and in this case only the logic associated with a set of used sources can be activated to determine a set of source addresses,

[0030] Figure 3 Another example of a computing device 300 using cryptographic coprocessor 310 is shown. Computing device 300 can form a standalone computing device or can include a system-on-a-chip implementation as Figure 2 shown. Cryptographic coprocessor 310 is configured in a similar manner as example 100 of Figure 1 Cryptographic coprocessor 310 includes a set of control registers 315, control logic 320, address generator 325, and arithmetic unit 330. In example 300 of Figure 3 cryptographic coprocessor, control registers 315 and internal memory 335 are both coupled to system bus 340 of computing device 300. Figure 3 These are provided by way of example only and it should be noted that different implementations can include different components or combinations of components than those shown.

[0031] In addition to the cryptographic coprocessor 310, the computing device 300 also includes a CPU 350, random access memory (RAM) 355, electrically erasable programmable read-only memory (EEPROM) 360, one or more input / output interfaces 365, a random number generator 370, and possibly other cryptographic modules 375. The CPU 350 may include a RISC processor. The EEPROM 360 may be implemented as any programmable memory and may be configured to store computer program code for operating the computing device 300, for example, it may include flash memory storing firmware for embedded devices or systems-on-a-chip. The RAM 355 may include main memory for the CPU 350. Among other things, one or more input / output interfaces 365 may also include network and communication interfaces as well as peripheral interfaces. The random number generator 370 and other cryptographic modules 375 may each include specific microcircuit systems to generate truly random numbers and execute defined cryptographic algorithms (e.g., SHA-3, AES, etc.). These may be implemented in a similar manner to the cryptographic coprocessor 310, for example, as a specific chip, a programmable FPGA, or an ASIC. Components of computing device 300 can exchange data via system bus 340 and / or wired electrical couplings.

[0032] exist Figure 3 In Example 300, the control register 315 and internal memory 335 of the cryptographic coprocessor 310 are accessible to the CPU 350. For example, the control register 315 and internal memory 335 can be configured as memory-mapped resources of the CPU 350. In this case, the CPU 350 can read and write data to the control register 315 and internal memory 335 in a manner similar to RAM 355 and / or EEPROM 360. In one case, the set of control registers 315 and internal memory 335 can be mapped to the CPU 350's secure address space, such as an address space inaccessible to non-root, non-administrative, or user processes. This can help protect the operation of the cryptographic coprocessor 310. Although the set of control registers 315 and internal memory 335... Figure 3 They are shown as separate components, but they can be implemented by a common set of memory accessible to the CPU 350 (e.g., implemented as different address ranges within memory).

[0033] The cryptographic co-processor 310 can additionally be protected using secure fuses and / or side-channel attack countermeasures. Secure fuses can prevent unauthorized access to the memory of the cryptographic co-processor 310 storing the operating firmware, microcode, etc. For example, control circuitry, sensitive arithmetic operations, and other components can be protected by logic or physical countermeasures that prevent secret information from leaking through electromagnetic emissions, advanced side-channel fluctuations, operation timing, or other unintended side channels or mask secret information. In one case, a physically secure enclosure (for the co-processor) and / or guard logic can be used to detect unacceptable or malicious changes in operating conditions such as input voltage or signals. Circuitry can also use error detection and correction to ensure detection and correction of faults. Upon detection of such an error condition, further operations can be prevented through a secure fuse mechanism. The co-processor can also be configured to immediately erase any secret information contained within internal memory, such as private keys.

[0034] In Figure 3 In the example 300, the address generator 325 is configured to determine a plurality of source and destination addresses within the internal memory 335 for a given iteration of the arithmetic engine 330. The internal memory 335 can be populated with data that will be used to perform a defined number of iterations of a function to be performed by the arithmetic engine 330, and the address generator 325 can determine a different set of source and destination addresses for each iteration. The arithmetic engine 330 can be configured to read or fetch data from a plurality of source addresses as determined by the address generator 325 prior to computing the function. The arithmetic engine 330 can then store the result of the computation to a destination address. In some cases, the arithmetic engine 330 can read and write data from and to a set of temporary registers or cache that can store data as part of a memory transfer. The CPU 350 can be able to read the result of the computation by accessing the destination address in the internal memory 335, or can wait until a plurality of iterations have been completed and read data from a plurality of destination addresses (e.g., a defined block of the internal memory 335).

[0035] Figure 4 An example 400 is shown of how the arithmetic engine processes data as indicated by the address generator. Figure 4The control address generator 425 and the arithmetic unit 430 are shown as separate portions of the control logic 420. Although shown as two separate portions for clarity, they can form part of a single portion of control logic or circuitry. In this example, the arithmetic unit 430 processes a sequence of bits read from memory 435 using a memory address 450 determined by the address generator 425, and outputs a resulting sequence of bits stored in memory using a memory address 455 also determined by the address generator 425. In this example, the arithmetic unit 430 includes three source registers 460 and one destination register 465. These registers are shown as internal registers of the arithmetic unit 430, but can instead comprise a pipeline cache of the cryptographic co-processor. Each function of the set of available functions is configured (e.g., as a programmed HDL function) to read data from the three source registers 460, perform a set of computations, and then output the result to the destination register 465. Data is loaded into the three source registers 460 from a set of three memory locations as indicated by the memory address 450.

[0036] The co-processor can use a word-based addressing system, in which case the memory address 450 can comprise an address of a w-bit word. The word length w can be selected to match the word length of the external processing unit, or can be selected independently of the word length of the external processing unit. For example, w can comprise 32 bits or 64 bits. If the word length of the cryptographic co-processor is greater than the word length of the external processing unit, this can facilitate increased bandwidth. This can be desirable in an embedded use case in which the external processing unit can be limited to 32 bits but the cryptographic co-processor can be configured to have a 64-bit word length. In general, the external system bus, the internal bus(es) used by the co-processor, and the set of control registers, source registers, and / or destination registers can have different bit widths. This can allow the cryptographic co-processor to use faster internal memory.

[0037] The memory address 450 can allow a three w-bit sequence corresponding to each of sources A, B, and C to be loaded into the three source registers 460. Similarly, the memory address 455 can indicate a location in the memory 435 for storing a w-bit output word. In the previous example, the memory 435 can comprise internal memory of the cryptographic co-processor (such as internal memory 335 in Figure 3 ), or external memory (such as RAM 355 in Figure 3 ). Internal memory can be preferable to free up the system bus 340 and / or RAM 355 for use by the CPU 350 while the cryptographic co-processor 310 is computing a function. In Figure 4 , the function can be defined as D = f i (A, B, C), where f iIt is one of k selectable functions. The function i to be used can be indicated by a bit sequence written into the function identifier register within the set of control registers, where the bit sequence represents the function number. In, for example, in an interface of a higher-level programming language used in computer program code executed by an external processing unit, the function identifier value can be set to a list or array of predefined constants.

[0038] exist Figure 4 In instance 400, control logic 420 can be configured to apply address generator 425 and arithmetic engine 430 within a set of iterations. At each iteration, address generator 425 can recalculate memory addresses 450 and 455. Thus, the data loaded into the three source registers 460 may change at each iteration (although it can remain the same for one or more sources depending on the address generation parameters written to the control registers). Destination memory address 455 may also change at each iteration. It should be noted that the generated memory addresses may also be repeated or overlapped with certain path navigation parameters, for example, to allow data to be repeated or overwritten as needed for a specific operation.

[0039] By performing multiple iterations, the arithmetic engine 430 can be configured to apply a selected function to a multidimensional data array associated with each of the three sources (A, B, and C), and output a multidimensional array associated with the destination (D). This multidimensional array... Figure 5A It is illustrated schematically. Figure 5A In an example, the cryptographic coprocessor can be considered to operate on a multidimensional array (i.e., a two-dimensional array) in the form of a data matrix 510 for each of multiple sources. The multidimensional array can be stored in memory 435 as a flat sequence of words, but is still represented as a multidimensional data structure through iteration within a series of nested loops. For example, Figure 5A This illustrates how a two-dimensional word block can have width and height (e.g., measured by multiple words in a first or X dimension and multiple words in a second or Y dimension). The size of each dimension of the multidimensional array can be set by values ​​stored in multiple control registers; for example, a first control register (CRBL_R_SIZX) can store a bit sequence representing the integer size of the word in the first dimension (width), and a second control register (CRBL_R_SIZY) can store a bit sequence representing the integer size of the word in the second dimension (height). Preferably, the set of sources and destinations has a multidimensional array of the same size, as this reduces the number of control parameters that need to be set and simplifies the logic, allowing for rapid implementation on custom circuit systems. However, in other implementations, different sources and destinations can have arrays of different sizes. The size of each dimension can be set to an integer value of 1 or greater.

[0040] Data can be retrieved from a defined multi-dimensional array by iterating over a sequence of words stored in memory using a set of nested loops, the number of nested loops equal to the number of dimensions of the multi-dimensional array. For example, two nested loops can be used to iterate over a sequence of words in memory treated as a two-dimensional matrix. In one example, an address generator determines source and destination addresses representing programmable paths within a corresponding multi-dimensional data array based on values stored within the set of control registers. These values can indicate, for example, a starting address of a first word in memory, and an increment for each of the dimensions. The increments can be positive or negative, enabling a wide variety of custom paths through the multi-dimensional array. The increments can be applied as data is iterated over. For example, an increment in the X direction can be applied during each iteration, e.g., when a row is read, and an increment in the Y direction can be applied after a set of iterations, e.g., at the end of a row.

[0041] For example, consider the sequence "ABCDEFGHIJKLMNOP", where each letter represents a word stored in memory. If the size parameters (e.g., CRBL_R_SIZX and CRBL_R_SIZY) are both 4, consider a matrix of 4 rows of length 4. If the increments are 1 in the X direction and 0 in the Y direction, then during iteration, one word of a row is read at a time, e.g., A, B, C, D. At the end of the row, the Y increment is applied. If the Y increment is set to 0, then nothing happens at the end of the row, and the subsequent iteration starts reading the next row linearly from the position where the previous iteration ended, e.g., D, E, F, G. This can continue so that the data is read as "ABCDDEFGGHIJJKLM", repeating every four words and omitting the last three words. If there is an increment of 1 in both the X direction and the Y direction (e.g., width and height, respectively, in Figure 5A For example, consider the sequence "ABCDEFGHIJKLMNOP", where each letter represents a word stored in memory. If the size parameters (e.g., CRBL_R_SIZX and CRBL_R_SIZY) are both 4, consider a matrix of 4 rows of length 4. If the increments are 1 in the X direction and 0 in the Y direction, then during iteration, one word of a row is read at a time, e.g., A, B, C, D. At the end of the row, the Y increment is applied. If the Y increment is set to 0, then nothing happens at the end of the row, and the subsequent iteration starts reading the next row linearly from the position where the previous iteration ended, e.g., D, E, F, G. This can continue so that the data is read as "ABCDDEFGGHIJJKLM", repeating every four words and omitting the last three words. If there is an increment of 1 in both the X direction and the Y direction (e.g., width and height, respectively, in

[0042] From the perspective of the external processing unit, a set of iterations by the cryptographic co-processor can form part of an atomic operation. For example, the iterations can be instructed with a single instruction of the external processing unit. The set of iterations can be used to perform a single cryptographic operation on a plurality of sources, where the sources have associated multi-dimensional data arrays. This operation can be referred to as a "bit block transfer" (e.g., the co-processor is referred to as a "bit block transferer"). The set of iterations can be synchronized with the clock period of the external processing unit, e.g., the complete set can be performed in one clock period of the external processing unit. This can allow for a significant speed increase, as the same cryptographic operation performed on the external processing unit can require multiple fetches, decodes, and execution cycles on both data and address memory, whereas the cryptographic co-processor can allow the result to be available in accessible memory after a much shorter period of time. In this way, each atomic operation of the cryptographic co-processor can affect at most a set of words constituting a multi-dimensional array, i.e., the destination can comprise a multi-dimensional array of the same size as the sources. In certain instances, the clock frequency of the cryptographic co-processor can be different from the clock frequency of the external processing unit. In these cases, the cryptographic co-processor or the external processing unit can perform individual steps in a single period or multiple periods. The number of steps performed can depend on the memory bandwidth, and in the case of the external processing unit, on the complexity of the instruction.

[0043] Figure 5B An example 520 is shown in which each of the three sources (A, B, C) and the destination (D) have independent address generation logic but in which each is represented as a two-dimensional array as shown in Figure 5A In this case, each matrix shares the same width and height parameters. Navigation on each matrix is then determined by a starting address, as well as X and Y increment parameters (e.g., for both the source and the destination).

[0044] Figure 5B The operation in Figure 4 is analogous to the operation shown in Figure 4 . Block 530 shows that the words of each of the sources A, B, and C are loaded from memory addresses 535 determined by the address generation logic of each source. The address generation logic can form part of the address generator 425 in Figure 5BIn particular, block 555 illustrates how the address generation logic for the source and destination can use an outer loop counter that generates "stride X" and "stride Y" signals based on the values of the X and Y increment parameters. Thus, at each iteration, new data can be loaded at block 530 based on the X and Y increment parameters for the source, and likewise stored at different destination addresses in a similar manner. The X and Y stride increments can be retrieved from control registers CRBL_z_INCX and CRBL_z_INCY, where z can be one of A, B, C, and D. The values stored in these control registers can be arbitrary and signed to provide a highly flexible set of programmable paths. If both are set to 1, then a linear contiguous block of CRBL_R_SIZX words x CRBL_R_SIZY words is processed. The increments can also be set to a constant or a function of another control register value. For example, if CRBL_z_INCX = 1 and CRBL_z_INCY = -CRBL_R_SIZX + 1, then CRBL_R_SIZX words of the same "row" are read CRBL_R_SIZY times. This can allow many different cryptographic computations to be performed with a common hardwired function and different programmable paths. For example, to replicate Figure 5A the read of one or more of the sources A, B, and C in Figure 5A and Figure 5B In the example of A, B, and C, the address generation can be performed by the address generator of the previous example by simultaneously performing the following pseudo-code operations and address generation logic for each of z = {A, B, C, D}:

[0045]

[0046] Performing address generation in parallel for each of the source and destination increases the speed of the coprocessor compared to an external processing unit. Since lattice cryptography is primarily based on linear algebra and matrices, the flexibility of the programmable paths through the data can allow large matrix multiplications and other large algebraic structures to be computed efficiently. Thus, the functions and operations can involve one or more of the following: matrix multiplication and addition, polynomial ring multiplication and addition; large integer multiplication and addition; and finite field multiplication and addition (etc.).

[0047] In certain implementations, the coprocessors described herein can also implement a form of shift control. In these implementations, the coprocessors can provide a mechanism for custom shifting of data loaded into source registers, e.g., data read from a source address computed by an address generator of a previous instance. The shift control can allow for setting a configurable number of bits s by which data of word length w bits can be shifted. This shift can occur prior to the function being applied by the arithmetic engine of the previous instance, and thus provides a more powerful approach to customizing the function without needing to change the base function itself. This allows the cryptographic coprocessors of the described instances to read and combine data in a manner that is not aligned with the w-bit word boundaries. In certain cases, the shift can additionally or alternatively be applied to data associated with a destination. For example, it can be desirable to shift data in a destination register prior to storing at a destination memory address to perform rounding of values stored as binary sequences.

[0048] Figure 6 An instance is shown in which the source and target registers store 32-bit words. This can be the word length of the external processing unit. To implement the shift control, a plurality of shadow registers corresponding to the plurality of source registers is provided. For example, if the source registers include registers A0, B0, and C0 (e.g., similar to those shown in Figure 4 A set of shadow registers including registers A1, B1, and C1 can be provided, e.g., the shadow registers are copies or clones of the source registers. In this case, in response to an instruction to copy data from a plurality of source addresses to respective ones of the plurality of source registers, the coprocessor can be configured to store previous values of the plurality of source registers in the plurality of shadow registers (i.e., A1 = A0, B1 = B0, and C1 = C0).

[0049] Figure 6 An instance is shown in which the source and target registers store 32-bit words. This can be the word length of the external processing unit. To implement the shift control, a plurality of shadow registers corresponding to the plurality of source registers is provided. For example, if the source registers include registers A0, B0, and C0 (e.g., similar to those shown in Figure 6 A 64-bit concatenation of a new word value in the Zth source register, shown as Z0 (where Z is equal to one of A, B, or C), and an old word in the Zth shadow register, shown as Z1, is shown. When shift control is applied, the coprocessor is configured to read a windowed data portion from a combination of the corresponding source and shadow registers, where the set of control registers indicates shift parameters for controlling the position of the windowed data portion. In this case, the shift parameters include a shift left value and a shift right value. The shift left value is applied to the left-most bits of the windowed data portion, and the shift right value is applied to the right-most bits of the windowed data portion. The shift left value is applied to the left-most bits of the windowed data portion, and the shift right value is applied to the right-most bits of the windowed data portion. Figure 6In the example of Figure 6, the control register CRBL_z_CSRL sets the number of bits to right shift the starting position of register Z0. This right shift sets the window of 32 bits that is applied to the 64-bit concatenation of the starting position. This can also be viewed as left shifting the value in source register Z0 by CRBL_z_CSRL bits, and then filling the vacated values with the bit values shifted in from Z1. The result is then read as the value of the source register in place of Z0, i.e., forming the w-bit input to the function (F). There can be three shift control registers CRBL_z_CSRL, for example, Figure 4 There is one shift control register per source in the example of Figure 6. In one case, if the source is provided in matrix form, then during the "Y step" (e.g., every CRBL_R_SIZX steps), the shadow registers (A1, B1, C1) can be zeroed to ensure that bit values do not leak from one row to the next. If the CRBL_z_CSRL register is set to zero, then the original value Z0 is used directly, as described in other examples. If the shift value s is an integer value from 1 to (w-1), then the source register Z0 is left shifted by s bits, while shifting in the "s" most significant bits from Z1 (e.g., equivalent to (z0«s) | z1»(32-s) into C). Figure 5A

[0050] By applying the shift control in the above examples, the cryptographic co-processor can apply custom shifting when loading the original source words (A0, B0, C0) from memory, in a manner that stores their previous values (A1, B1, C1), and then reads the shifted combination of both. The control register defines how the current word and previous word are combined to produce the source word used in the function applied by the arithmetic engine.

[0051] Figure 7 An exemplary architecture 700 is shown in which the cryptographic co-processor has its own internal memory and is communicatively coupled to the system bus. Figure 7 The architecture shown in Figure 6 can be viewed as a schematic variation of the architecture shown in Figure 5. Figure 3 The architecture shown in Figure 6 can be viewed as a schematic variation of the architecture shown in Figure 5.

[0052] The example 700 shows a control CPU 710 and an auxiliary processing unit (APU) 720. The auxiliary processing unit 720 can be a cryptographic co-processor as described in the previous examples. The control CPU 710 can be the main CPU or a general purpose CPU of the architecture 700. In the example of Figure 6, the control CPU 710 and the APU 720 are communicatively coupled by a system bus 730. This system bus 730 can also be used by the main RAM, flash ROM, and other peripherals. Figure 7 Figure 7 ​​A memory 740, composed of a combination of RAM and ROM, is shown as accessible over the system bus 730. At least the control CPU 710 can access this memory 740, e.g., by specifying a memory address and then by reading and writing data at that address, in certain instances, the APU 720 can access the memory 740; but it is generally more preferable for the APU 750 to use its own internal RAM 750. This RAM 750 can be accessed by the APU 720 in the same manner as the control CPU 710 accesses the memory 750.

[0053] In Figure 7 The control CPU 710 controls the APU 720 by writing to a set of memory-mapped control registers, e.g., as described in the previous example. The memory and control registers can be accessed as memory-mapped resources (e.g., using direct memory access (DMA)) or through a memory management unit (MMU). The control CPU 710 is also able to access the dedicated RAM 750 allocated to the APU 720. Once started by the control CPU 710, the APU 720 processes its data independently without interacting with the control CPU 710. While the APU 720 is processing its data, the control CPU 710 can perform other operations and access the memory 740. Since the APU 720 has its own dedicated RAM interface, the processing performed by the APU 720 does not interrupt or slow down the control CPU 710 and the main system bus 730.

[0054] Since the exemplary cryptographic co-processors described herein can operate as memory-mapped peripherals, they can be configured to operate with most CPUs and instruction set architectures (ISAs). In certain cases, it can be desirable to bind the design more closely to a particular CPU, which can be possible. For example, if the CPU is based on a RISC architecture (e.g., RISC-V), the control registers of the cryptographic co-processor can be mapped to the CSR (control and status registers) of the CPU.

[0055] When using its own dedicated memory, the exemplary cryptographic co-processors described herein are able to dedicate all memory accesses to the task at hand, e.g., saturating the memory bandwidth of the internal memory. If the cryptographic processor is to access a memory such as 740 shared with a CPU such as 710, this can not be possible. In a typical two-step or four-step cycle, the cryptographic co-processor is able to load three source words and write a single result word (e.g., two steps for a dual-port RAM or four steps for a single-port RAM). Instruction loading and interpretation, performing arithmetic, incrementing the memory pointer, and checking the loop end condition do not require additional cycles. These functions are performed automatically in hardware. This means that binary operations can be performed at high speed.

[0056] For example, a cryptographic coprocessor may not have its own program code, as it may lack features such as conditional branching. This means that a cryptographic coprocessor may not be Turing complete and therefore needs to work closely with the CPU. Efficient use of a cryptographic coprocessor involves the CPU, while the coprocessor is still completing its previous task, preparing the coprocessor for the next operation (e.g., by loading control registers). Once started, the coprocessor is able to perform block operations on data stored in RAM. If this RAM is accessed via the same bus used by the main CPU, for example, RAM 740, the coprocessor may slow down the CPU's access to the entire bus during runtime. This drawback can be mitigated by using a dedicated secondary bus and... Figure 7 The internal RAM 750 shown is used to avoid this. This architecture also makes it easier to protect access to RAM 750.

[0057] In one test implementation, internal RAM 750 includes 16kB of working memory. Internal RAM 750 is memory-mapped, and a base address offset is defined as the starting address within the address space controlling CPU 710. For example, the base address offset CRBL_BASE_ADDR can be set to, for example, 11000000 (in hexadecimal), where the 16kB of memory extends to address 11003FFF (in hexadecimal). Control registers can be memory-mapped into the address space in a similar manner. The control address offset CRBL_CTRL_ADDR can be defined as the starting address of the control register within the address space controlling CPU 710. The length of each control register can be w bits (e.g., a word). The control register address space can precede or follow the internal memory address space. In the above example, if the control register address space immediately follows the address space allocated to internal RAM 750, the control address offset can be set to 11004000 (i.e., the next address after 11003FFF). In one instance, twenty or more control registers may be included. A set of exemplary 32-bit control registers with number and hexadecimal offset, along with CRBL_CTRL_ADDR, are in Figure 8 As shown in the diagram. Some of these control registers have already been discussed in the examples above. These control registers include: function specifiers or identifiers CRBL_R_OPER; status reads CRBL_R_STAT; and dimensions of the multidimensional array CRBL_R_SIZX and CRBL_R_SIZY (e.g., as shown in the diagram). Figure 5A (as shown); for each of the available source and destination, the starting address CRBL_z_ADDR and the increments CRBL_z_INCX and CRBL_z_INCY for each dimension; and for the source register, the shift control parameter CRBL_z_CSRL (as shown in the reference).Figure 6 In this case, z is one of A, B, C, or D, as shown. Figure 8 The set of control registers defined in the foregoing is provided as an example only, and can vary in actual implementations, e.g., the number of sources can vary, different dimensions can be defined for each source and destination, and / or different shifts can be implemented. There can also be an applied level of abstraction, e.g., the intermediate array structure can be defined such that one or more of the internal memory and control registers can be accessed using a word index i instead of raw memory addresses and / or a set of offsets. For example, the control CPU 710 can be provided with a programming language interface (e.g., a C application programming interface, API) that allows access to the control registers using the crbl_c[n] array (where n is the register number) and / or access to the internal memory using another crbl[i] array (where i is the word index). If the control CPU 710 uses byte addressing, then if the APU 720 uses 32-bit words, the control CPU address CRBL_BASE_ADDR + 4*i can be treated by the APU 720 as the word address i (since 32 bits equals 4 bytes of 8 bits).

[0058] In one case, the internal RAM 750 can comprise a dual-ported memory that allows two access operations per clock cycle of the APU 720. This can thus allow four memory addresses to be read in two clock cycles. In this case, there can be three source registers and one destination (i.e., A, B, C, and D), since the data for these registers can be fetched from memory in two clock cycles. The clock cycles of the APU 720 can be at the same frequency as the control CPU 710, or can vary depending on the implementation. Dual-ported RAM is generally more expensive than single-ported RAM that is typically used in RAM for system memory 740, but can be accommodated inexpensively in the proposed implementation, since only a small amount of memory is needed to perform the functions of the arithmetic engine. In general, the address generator can be configured to determine addresses within the internal dual-ported memory, and the multiple source registers can comprise three internal source registers to allow fast reads from memory.

[0059] Figure 3 and Figure 7 An example of the foregoing shows a general case in which the cryptographic on-chip system comprises a system bus, a central processing unit coupled to the system bus, a system memory coupled to the system bus for use by the central processing unit, and a cryptographic co-processor. The cryptographic co-processor can be configured as described in any of the foregoing examples, including as described for the APU 720, and certain features from one example can be used in conjunction with one or more features of another example, without providing all of the features of these examples.

[0060] Figure 9A method 900 of performing a cryptographic operation is shown. This method can be applicable to any of the previously described coprocessor instances, or another appropriately configured coprocessor. The coprocessor can also be referred to as an auxiliary processing unit. In some cases, the method 900 can be programmed into programmable circuitry, for example using HDL or microcode or low level programming languages. The programmable circuitry can include ROM, FPGA, or programmable ASIC. In some cases, ASCI or the like can be configured to perform the blocks of the method 900. Using specialized programming circuitry, for example rather than a general purpose processing unit, can reduce cost and speed up operations.

[0061] The method 900 includes a first block 910 involving reading values from a set of control registers. These control registers can include the control registers 115 or 315 in Figure 1 or Figure 3 The values in the set of control registers are written according to indications by a host processing unit communicatively coupled to the coprocessor. For example, the CPU 350 or the control CPU 710 can write values to addresses in their address space that is memory mapped to the control registers of the coprocessor. The control registers can be similar to those shown in Figure 8 and the values can include signed or unsigned integer values stored as w-bit words. For example, the size parameters CRBL_R_SIZX and CRBL_R_SIZY can include unsigned (i.e., positive) integers, while the increment parameters CRBL_z_INCX and CRBL_z_INCY can include signed integers (i.e., allowing positive and negative integer values).

[0062] At block 920, a function used by the cryptographic operation is determined. For example, for a lattice or code based cryptographic operation, the function can include one or more of Boolean logic and integer arithmetic (e.g., multiplication, addition, and subtraction). The function can be selected from a set of different available functions based on at least one value in the set of control registers (e.g., a positive w-bit integer stored in the function specifier control register CRBL_R_OPER). The function is not a high level cryptographic operation such as encryption or decryption, or a symmetric key operation, the function is a mathematical base function used in (e.g., repeatedly) these cryptographic operations. As such, the function can correspond to a single line of statement in a high level programming language or a pseudo code for the cryptographic operation. For example, the function can involve multiplication of integer values stored as one or more sequences of bits within each word in memory used by the coprocessor, or addition / subtraction of those sequences implemented as binary arithmetic calculations. The function can be described as a discrete function, as it operates on binary sequences or integers defined by these binary sequences rather than non-integer representations used for approximate continuous calculations.

[0063] At block 930, a set of respective addresses associated with a set of sources and at least one destination is generated. The sources represent the inputs to the function. The destination represents the output of the function. The sources and the destination can have corresponding registers within the cryptographic co-processor (e.g., as internal registers or cache for the performed computation). These corresponding registers can alternatively form part of the internal memory of the co-processor. The generated addresses correspond to one or more of the internal memory of the co-processor and the system memory used by the host processing unit, e.g., memory 335 or 355 of Figure 3 or one of 740 or 750 of Figure 7 As discussed herein, the internal memory of the co-processor is preferred. The addresses are accessible to the host processing unit, e.g., the addresses can form part of the address space of the host processing unit. In one case, the internal memory can comprise a memory mapped resource of the host processing unit. It is also noted that although block 930 is shown before block 940, this is only required for the sources; the determination of the destination address can be performed in parallel with or after blocks 940 and / or 950, as long as it is available for storing the resulting data at block 960.

[0064] At block 940, data is loaded from the generated addresses associated with the set of sources. There can be one or more sources. This data is to be used as input to the function. This can comprise a fetch operation, where the addresses are used to retrieve sequences of bits of word length from memory and store these sequences of bits in a set of (temporary) source registers where the data is retrieved to perform the function. At block 950, the function is executed. This can comprise applying bit manipulations to the sequences of bits stored in the source registers, i.e., the sequences of bits read from memory at block 940. The function can be implemented by executing a set of programmed logic within an FPGA or ASIC. The function can take one or more clock cycles of the co-processor. The output of the function comprises a sequence of bits, e.g., of word length or of w bits, which can be stored in (temporary) destination registers. Block 950 can comprise the operations shown in Figure 4 and / or Figure 5B

[0065] At block 960, the output of the function is stored at the generated addresses associated with the destination. This can comprise transferring the values stored in the destination registers into one or more of the internal memory or the system memory, where the location in one of these memories is determined by the generated addresses.

[0066] At block 970, an indication is provided to the host processing unit that the output is available at the generated addresses associated with the destination. This can comprise a passive indication, e.g., such as a status readout control register, e.g., CRBL_R_STAT in Figure 8 which can be set to a predefined value to indicate that the operation is complete (e.g., this is in Figure 8 ​In some instances, it can be set to zero to indicate that the coprocessor is no longer busy. In other instances, it can provide active indications, such as interrupts to the main processing unit.

[0067] In one scenario, the indication at box 970 is provided only after a set of iterations has been completed. This set of iterations may include zero or more iterations (e.g., not repeating boxes 930 through 960, or as...). Figure 9 As indicated by the dashed arrows, these boxes iterate once or multiple times. The number of iterations in a set can be limited using a value in a control register.

[0068] In one case, method 900 (specifically boxes 930 to 960) is repeated to apply the function to a multidimensional data array associated with each of the multiple sources. This is in Figure 5A and Figure 5B As illustrated in the example. In this case, the multidimensional data array associated with the destination can be stored at multiple generated addresses associated with the destination, for example, storing the location of different parts of the array after each iteration. (See also: Regarding...) Figure 5A and Figure 5B As explained, custom or programmable paths within one or more of multiple multidimensional arrays can be configured via address generation at box 930. For example, the address generated at box 930 can be based on a starting address (such as... Figure 8 CRBL_z_ADDR, where z = {A, B, C, D}) and incremental values ​​for one or more dimensions (such as Figure 8 The value of CRBL_z_INCd is used to determine this, where z = {A, B, C, D} and d = {X, Y}. Therefore, the coprocessor's full operation, or "bit block transfer," can be performed against multiple sources, each defined as a multidimensional array, and providing output in the form of another multidimensional array, the values ​​of which are stored in memory accessible to the main processing unit. The indication at box 970 can be provided when the complete array at the destination is ready to be read.

[0069] In some instances, the coprocessor's operations can be viewed as a pipelined process similar to that of a regular CPU. In these instances, certain operations can be executed in parallel and / or optimized to speed up the coprocessor's operations. For example: at the first step of the pipeline, addresses are generated for the source and / or destination; at the second step of the pipeline, data words are extracted from the source address and optionally shifted (e.g., according to...). Figure 6 In the third step, a function can be executed, for example, D = f i (A,B,C) or (D,Carry) = f i(A, B, C, carry), the latter explained in more detail below; and in the fourth step, D is written to the destination address. If there is only one source A, the fourth step can be performed, for example, concurrently with loading the next value of A, since the previous value is used in the function. If there are three sources A / B / C and a two-port memory is used, the four steps can be performed in two cycles. When optimizing the pipeline and executing the steps in parallel, the address of the (t-3)th iteration can be generated at the first step, the data word of the (t-2)th iteration can be fetched at the second step, the function can be executed on the value of the (t-1)th iteration, and the value D of the tth iteration can be stored at the fourth step. The two-port memory allows reading or writing two addresses in one cycle, so (A, B) can be read in one cycle, and C and D can be read and written in another cycle.

[0070] Generally, method 900 can be viewed as a "bit block transfer" of a cryptographic coprocessor, where each "bit block transfer" operates through a region of a multidimensional array (e.g., via...). Figure 9 (The loop is shown as a dashed line in the middle). If the multidimensional array is such as... Figure 5A The two-dimensional array shown can have CRBL_R_SIZX*CRBL_R_SIZY (i.e., width*height) iterations. Once the region has been worked, new operations can be scheduled, such as a new round of running method 900. If the operation is large integer multiplication, the source multidimensional array can represent the large integers to be multiplied; for example, the width and height can indicate the lengths of the two numbers to be multiplied, respectively. If one or more of the width and height is one, the operation can represent a column or row vector operation.

[0071] Method 900 and its variations can be executed by a coprocessor. On the main processing unit (or CPU) side, the method may include... Figure 9 The series of boxes preceding box 910. At the first box executed by the main processing unit, the cryptographic operation to be performed can be determined. This may include instructions to run known cryptographic algorithms (such as NTRU, Round5, Sabre, XMSS, BIKE, Dilithium, or Kyber). Known cryptographic algorithms may include post-quantum algorithms, i.e., cryptographic algorithms that provide protection against attacks from quantum computers. Generally, cryptographic algorithms may include one or more of the following: lattice-based cryptographic algorithms; code-based cryptographic algorithms; elliptic curve cryptographic algorithms; and homology-based cryptographic algorithms.

[0072] In the second box, the main processing unit can break down cryptographic operations into one or more functions. This could include, for example, compiled and / or machine code executing instruction functions, and / or computer program code executing function calls already adapted for use with the coprocessor. For example, a cryptographic algorithm for encrypting, decrypting, or generating a key may have multiple suboperations involving common kibble or integer arithmetic functions. These functions can then be identified and assigned to the coprocessor. In some cases, the cryptographic coprocessor is simply controlled by writing to said set of control registers (e.g., writing to a specific “GO” register), and this initiates coprocessor operations (or “bit block transfers”). This can be executed using any form of computer program code, including assembly language and low-level coding languages ​​such as C or Rust. The cryptographic coprocessor does not need to be synchronized with the main processing unit; it simply performs the operations and indicates when the results are available. When the results are available and the coprocessor is no longer busy, a new operation can be initiated by writing to the control registers again. Typically, the use of a cryptographic coprocessor requires minimal to no changes to the program flow of high-level cryptographic algorithms.

[0073] Within this method, the main processing unit may repeat a series of sub-frames for each identified function to be executed within the cryptographic algorithm. The first sub-frame may include loading values ​​into the set of control registers of the coprocessor as instructed by the main processing unit. These values ​​are values ​​that can later be read at frame 910 of method 900. The second sub-frame may include loading data into one or more of the coprocessor's internal memory and the system memory used by the main processing unit, as instructed by the main processing unit. For example, the main processing unit may store data at an identified starting address, the range of which is equal to the size of any defined multidimensional array. The main processing unit may load data directly into the coprocessor's internal memory, for example, by accessing the internal memory as a memory-mapped resource and / or the coprocessor may be arranged to retrieve data from memory used by the main processing unit (e.g., for direct use or copying to its own internal memory). For example, in Figure 3 or Figure 7 In this case, the coprocessor can directly access external memory (e.g., 355 or 740) to copy the chunks into internal memory (e.g., 335 or 750). In the third sub-block, the main processing unit is configured to start the coprocessor by loading an initial value into the set of control registers. This may include a Boolean start flag, or it may include writing a non-zero function identifier into the function specifier control register (e.g., ...). Figure 8 (CRBL_R_OPER in the text).

[0074] Following the aforementioned sub-block, method 900 can be executed. During this period, the main processing unit may wait for an indication that can be obtained at the generated address associated with the destination. This may include waiting for the indication described in reference block 970, for example, waiting for a change in the control register value or an interrupt. During the waiting period, the main processing unit can perform other operations. For example, this can enable different parts of the cryptographic algorithm to be efficiently parallelized.

[0075] exist Figure 8 In an exemplary implementation, writing to the CRBL_R_OPER register can initiate coprocessor computation (e.g., initiating method 900), and can also define the coprocessor being processed by multiple sources (e.g., Figure 4 and Figure 5B The functions executed by A, B, and C in the list (e.g., Figure 4 and Figure 5B (F in the text). Figure 8 In the CRBL_R_OPER register, the w-bit function control word specifies what type of logic is used to combine the source input words (e.g., A, B, C) to produce the output word D. The architecture is flexible and can support a different set of functions depending on the configuration. Writing to the CRBL_R_OPER register can be performed after ensuring that the appropriate control values ​​have been written to the set of control registers. In one case, internal variables used by the coprocessor, indicated by the control register values, are loaded only at the start of a coprocessor operation (“bit block transfer”), so changing the variables while the coprocessor is executing has no effect on the coprocessor's operation. This allows for the rapid, sequential execution of a series of coprocessor operations (e.g., “bit block transfers”, where each “bit block transfer” may include method 900). For example, the operation of a second function can be prepared while the coprocessor is executing the first function. In some cases, coprocessor method calls can be defined (e.g., defined as C API calls) to avoid the need for direct writing to the CRBL_R_OPER register. Similar coprocessor method calls can be defined for waiting operations, where the method call will block until all running coprocessor operations are completed, for example, by polling the CRBL_R_STAT status register or waiting for an interrupt. Both coprocessor method calls are executed by the main processing unit.

[0076] The functions applied by the arithmetic engine, as described in the examples herein, may include subfunctions for one or more of code-based and lattice-based cryptography, such as for algorithms as described above. These functions may implement Boolean logic operations, for example, treating source values ​​as bit sequences that can be combined using Boolean logic operations. The functions may also implement integer arithmetic operations, such as one or more of integer multiplication, integer subtraction, and integer addition, where the integer value is defined by a bit sequence stored at a defined word address.

[0077] In some instances, the cryptographic coprocessor described in this document can be configured to evaluate multiple functions and store the corresponding outputs in multiple corresponding destination addresses. For example, the cryptographic coprocessor may include multiple arithmetic engines and / or arithmetic engines capable of evaluating multiple functions simultaneously. In one case, multiple functions can be evaluated in parallel and the outputs stored in corresponding destination addresses. The functions evaluated simultaneously may include different functions. The functions may be set based on a common set of functions. Functions may be selectable via corresponding function identifiers in the set of control registers. In one case, each function may operate on the same set of sources but produce different destination results. In this case, the control logic of the cryptographic coprocessor may be configured to select one of the destinations. This selection may be conditional, for example, based on the values ​​stored in the destination. In another similar variant, there may be shared common memory (e.g., similar to...). Figure 3 Multiple cryptographic coprocessors in the internal memory (335).

[0078] Figure 10 This illustrates how truth tables can be defined for exemplary Boolean logic operations. As mentioned above, this can be achieved using data stored in... Figure 8 The value in the CRBL_R_OPER register is used to set the value. For example, when using a 32-bit word and the value of CRBL_R_OPER is in the form 000000xx (i.e., the high 24 bits are zero), the 8-bit value xx can define a truth table for any 3-input Boolean function, where the Boolean function is applied to the bits of the source (e.g., A, B, and C). Thus, each of these lower 8 bits defines how to generate the output of the destination (D) for a given combination of input bits (e.g., as indicated by words A, B, and C).

[0079] For example, if we consider 8 bits as a set of 1-bit variables "hgfedcba", where the most significant bit ("h") is... Figure 10 The "operand 7" in the code, and the least significant bit ("a") is... Figure 10 The "operational bit 0" is then set. Then, the value of each bit in the 1-bit variable is set to indicate... Figure 10The last three rows of the table show the output of different 1-bit combinations. For example, bit value "a" indicates the result of combining three 0 bits from each of the sources (e.g., 0 or 1), bit value "d" indicates the result of combining 0 from source A and 1 from sources B and C, and bit value "h" indicates the result of combining three 1 bits from each of the sources. Therefore, each of the different 8-bit sequences defines a different truth table. For example, if a bit from each of the sources (A, B, C) equals (1, 0, 1), then the function identifier 0xCC (in hexadecimal) means the sequence "hgfedcba" equals 11001100, and therefore "operation bit 5" ("f") equals 0, and the output of the combination (i.e., D) is 0. In contrast, if the function identifier is 0x80 (in hexadecimal), then this means the sequence "hgfedcba" equals 1000000, i.e., a logical AND operation performed on all three sources. Bit comparisons can be performed in parallel for each bit in the sequence from the source; for example, if the register is 32-bit, 32-bit comparisons can be performed in parallel. If there are n sources, then 2n bits can be used within the function identifier. n The unit digit indicates the truth table. Therefore, the cryptographic coprocessor can implement multiple custom binary logic operations.

[0080] Constants can be assigned to certain values ​​of function specifiers. For example, a mask operation that fills the destination can have a function specifier value of 000000FF, which can be defined as a C constant (CRBL_OP_MASK) for the program in the main processing unit. The constant CRBL_OP_MASK can be used to guarantee that the high-order bits are zero. All zeros (i.e., 00000000) can be a function that simply ignores the input and writes zeros to the destination. The value 000000F0 (e.g., set to the constant CRBL_OP_ASRC) can simply copy the value stored in the source register A to the destination D, and CRBL_R_OPER, set to approximately CRBL_OP_ASRC and CRBL_OP_MASK (i.e., the value and the mask mentioned above), can cause a logical reversal of the same source register to be written to the destination D. Different combinations of constants can be defined to indicate different Boolean operations. For example, if CRBL_OP_BSRC is set to 0x000000CC (copying the value from source register B to destination D) and CRBL_OP_CSRC is set to 0x000000AA (copying the value from source register C to destination register D), then expressions such as (CRBL_OP_ASRC&CRBL_OP_BSRC)^CRBL_OP_CSRC will evaluate to 0x6A and will result in a Boolean operation of (AAND B)XOR C. Boolean operations can be used for a variety of tasks. In particular, Boolean operations can be used for (bit-slicing) implementations of symmetric cryptographic algorithms.

[0081] Another instance of a function that can form part of the aforementioned set of functions is the so-called "row operation" primitive. Row operation primitives allow the coprocessor to quickly add and subtract integer vectors from each other. Different functions can interpret the bit sequences stored in a set of input source registers (e.g., A, B, and C) in different ways. One function can compute D = A + BC, where source registers A, B, and C are interpreted as a compact array of four 8-bit integers. Another function can compute the same set of additions and subtractions, i.e., D = A + BC, but interpret source registers A, B, and C as a compact array of two 16-bit integers. For example, if w = 32 and 8-bit operations are used, four parallel, independent 8-bit arithmetic operations are actually being performed; for example, the second byte of the destination D depends on the second bytes of the source A, B, and C, where any result can be interpreted modulo 256.

[0082] In some instances, the functions applied by the arithmetic engine are stateless. However, to allow long integer arithmetic (e.g., where long means overflow or underflow), an additional "carry" register can be used by the arithmetic engine to store the carry of the arithmetic operation. This can be indicated as (D, carry) = f i (A, B, C, Carry). For example, a function D = A + B – C can be defined with the same sum, but where the source register is interpreted as a full-length w-bit integer. In this case, it may be necessary to set an additional carry variable that can be accessed from the carry register. The carry register may also store negative values ​​indicating "borrowing". When iterating over a multidimensional array (e.g., when performing a step in the Y dimension), the carry register may be reset at the beginning of each row. Each of these row operation primitives may have a different function specifier (i.e., identifier) ​​value. The carry may not be directly read by an external processing unit. In one implementation, the carry register may be cleared at the beginning of each operation (e.g., each execution of method 900) and / or at the end of each row (e.g., when performing a Y increment as described above).

[0083] Another function can be integer multiplication. Similar to row operation primitives, integer multiplication can be performed by using different function specifier values ​​to interpret the source register bit sequences differently. Multiplication functions on three sources (A, B, and C) can include the combination function D = A + B * C. In one case, integers of arbitrary length (e.g., large) can be multiplied in a single operation of the coprocessor (e.g., a single run of method 900). This can use carry. In some integer multiplications, a 2w-bit product can be computed, and this can be split between w bits in the destination register and w bits in the carry register. An equivalent description of the arbitrary-length multiplication function, the combination function D = A + B * C, in the C programming language could be:

[0084] carry+=((uint64_t)a_data)+((uint64_t)b_data)*((uint64_t)c_data);

[0085] d_data = (uint32_t)carry;

[0086] carry >>=32;

[0087] Now, an example of how to configure the above large integer multiplication will be described. This example also shows how the coprocessor can be configured to use a multidimensional array. Assume a low-bit-first large integer representation (but other representations can be configured via function definitions). In this case, an integer defined as “m-1” words of source B is multiplied by an integer defined as n words of source C. Source B is defined starting with CRBL_B_ADDR, where the additional high words are set to zero (i.e., actually a bit sequence of m words), and source C is defined starting with CRBL_C_ADDR. First, the destination array of (n+m-1) words is cleared, and both source A (e.g., as defined by CRBL_A_ADDR) and destination D (e.g., as defined by CRBL_D_ADDR) are configured to point to it. The full product B*C can then be computed by a single operation of the coprocessor (e.g., one iteration of method 900). The configuration can be prepared using the following C code:

[0088] crbl_c[CRBL_A_INCX]=1; / / A: (X)Advance by 1.

[0089] crbl_c[CRBL_A_INCY]=2-m; / / A: (Y)Rewind back, advance by one.

[0090] crbl_c[CRBL_A_CSRL] = 0;

[0091] crbl_c[CRBL_B_INCX]=1; / / B: (X)Advance by 1.

[0092] crbl_c[CRBL_B_INCY]=1-m; / / B: (Y)Rewind all the way back.

[0093] crbl_c[CRBL_B_CSRL] = 0;

[0094] crbl_c[CRBL_C_INCX]=0; / / C: (X)Same value entire row.

[0095] crbl_c[CRBL_C_INCY]=1; / / C:(Y)advance by 1

[0096] crbl_c[CRBL_C_CSRL]=0;

[0097] crbl_c[CRBL_D_INCX]=1; / / D:(X)Same as A,advance by 1.

[0098] crbl_c[CRBL_D_INCY]=2-m; / / D:(Y)Rewind back,advance by one.

[0099] crbl_c[CRBL_R_SIZX]=m; / / Width(B Size+1 zero word).

[0100] crbl_c[CRBL_R_SIZY]=h; / / Height(C size).

[0101] crbl_go(CRBL_OP_M32A); / / Start the multiplication operation.

[0102] crbl_wait(); / / (Wait for it to finish.)

[0103] In the above operation, the destination is first set to 0, and the source register A is used to read back the intermediate values ​​before the final product is ready. As a (hypothetical) example using decimal values, imagine that the values ​​need to be multiplied as 123 * 456, and the word length is a single decimal digit. In this case, B = 123 and C = 456. In the first set of iterations: A = 0, B * C = 3 * 6 = 18, D = 8, carry = 1; A = 0, B * C = 2 * 6 = 12 + 1 = 13, D = 3, carry = 1; and A = 0: B * C = 1 * 6 = 6 + 1 = 7: D = 0, carry = 0. These iterations represent the first row and D = 00738. Now, for the second set of iterations representing the second row, A = D and A and B are rewound. For the second set of iterations, A, C, and D are stepped, and in fact, A and D step through the middle 3 digits. The second set of iterations is therefore performed as follows: A = 3, B*C = 3*5 = 15 + 3 = 18, D = 8, carry-out = 1; A = 7, B*C = 2*5 = 10 + 7 + 1 = 18, D = 8, carry-out = 1; and A = 0, B*C = 1*5 = 5 + 1 = 6, D = 6, carry-out = 0. The second row is now complete, and D = 06888. For the third set of iterations, the step is made through the high 3 digits of A and D: A = 8, B*C = 3*4 = 12 + 8 = 10, D = 0, carry-out = 1; A = 6, B*C = 2*4 = 8 + 6 + 1 = 16, D = 6, carry-out = 1; and A = 0, B*C = 1*4 = 4 + 1 = 5, D = 4, carry-out = 0. After this line, D = 56088 = 123 * 456, which is the final result after a single operation or "bit block transfer". Of course, in reality, the integer is represented in binary rather than decimal, but the steps are similar.

[0104] Some of the examples described herein provide methods and systems for assisting the main processing unit in performing cryptographic operations. These methods and systems allow cryptographic operations to be performed with less processor overhead and lower complexity. Power consumption is also reduced because fewer main processing unit operation cycles are required and the coprocessor can be implemented as a low-power FPGA or ASIC. This provides benefits that may not be achievable by vector or Single Instruction Multiple Data (SIMD) processors. For example, SIMD primarily implements features of the main or external processing unit rather than involving a separate coprocessor, and cryptographic coprocessors do not have machine instructions or an "instruction stream" like in SIMD architectures. Furthermore, in architectures that support SIMD register access, vectors or arrays are treated as part of the CPU's register file; this means that the amount of data that can be stored without loading and storing to main (i.e., external) memory is severely limited, as access to the system bus and main memory is performed through the main or external processing unit.

[0105] Coprocessors are suitable for executing a variety of common cryptographic basis functions, such as arithmetic, like word addition or subtraction, or complex bit manipulation operations consisting of shifting, indirect addressing, and evaluation of multi-input Boolean functions. These common cryptographic basis functions can be designed to support one or more known post-quantum cryptographic algorithms. Coprocessors can be used to help implement post-quantum (i.e., quantum-resistant) cryptography on a wide range of devices, from servers to smart cards. Coprocessors are specifically designed to accelerate cryptographic operations, such as large-scale linear algebra and large integer arithmetic. This differs from comparative floating-point coprocessors, which are designed to operate using bit sequences that define exponents and significant bits but are not suitable for executing common cryptographic basis functions. The basic design of a coprocessor incorporating the aspects described in this example can be flexibly configured to address the implementation challenges of different types of cryptographic algorithms, including helping to quickly support algorithms developed in the future (which may use the same basis functions but in different orders and combinations). The set of functions that can be executed by the coprocessor can be configured according to the needs of the target system; for example, if the smart card only needs to implement a cryptographic algorithm that only requires row operation primitives, then no other functions are needed and a smaller coprocessor can be provided.

[0106] Some of the examples described herein provide a cryptographic architecture and a method for efficiently interfaced with larger processing units, connecting dedicated cryptographic processing units. Some of the examples described herein provide cryptographic methods suitable for implementation on low-resource microcontrollers and embedded devices, and for achieving high-speed, secure data processing. The described cryptographic architecture is independent of the type of processing unit used, and options for different control programs are available through a set of control registers. The cryptographic architecture can be implemented using memory mapping and / or other methods, providing simple or transparent data access to different types of processing units. Some of the examples described herein can be used to implement efficient hardware and / or software implementations of advanced cryptographic algorithms using small base cryptographic functions as “building blocks.” Cryptographic coprocessors can execute fast cryptographic base functions on behalf of processors or microprocessors, thus providing benefits for low-power embedded devices and high-throughput server devices.

[0107] While some instances refer to accessing data within and from specific registers, it should be understood that intermediate data storage devices and / or data structures may actually be used in some implementations, and references to “data in…” may also apply to “data derived from…”, for example, data from one or more intermediate processes in addition to those described. A reference to a set of registers may indicate a reference to one or more registers. Instances characterized as a main processing unit, external processing unit, or central processing unit may also be characterized as multiple such units of the same or different types. For example, a computing system in which a cryptographic coprocessor is implemented may comprise a heterogeneous system with multiple CPUs of different types (e.g., where the CPUs share a common system bus). Furthermore, even though “control” of the coprocessor has been described with respect to an external processing unit, other devices such as disk drives and network interfaces may perform DMA (Direct Memory Access) transfers to areas of memory accessible to the coprocessor. It should also be understood that references to circuitry coupled to certain components may alternatively refer to functionality within those components, such as whether implemented via firmware code and / or dedicated hardware circuitry. The “circuit system” described herein can be implemented in hardware, for example, using digital logic gates or programmable gates in an FPGA, and / or as computer program code loaded from memory and executed by a processor such as a microprocessor. Some of the system components and methods described herein can be implemented using computer program code such as firmware or instruction sets that can be stored on a non-transitory storage medium such as read-only updatable firmware memory.

[0108] The examples above should be understood as exemplary. Other examples are conceivable. For instance, the specific values ​​discussed herein are based on test examples and may vary depending on the implementation (e.g., depending on the microcontroller specification and type, security requirements, and other factors). Although certain components of each example have been described individually, it should be understood that functionality described with reference to one example may be suitable for implementation in another example, and certain components may be omitted depending on the implementation. It should be understood that any feature described with respect to any example may be used alone or in combination with other described features, and may also be used in combination with one or more features of any other example or any combination of any other example. For example, features described with respect to system components may also be adapted to be performed as part of the described method. Furthermore, equivalents and modifications not described above may be employed without departing from the scope of the invention as defined in the appended claims.

Claims

1. A coprocessor (100) for cryptographic operations, the coprocessor (100) being communicatively coupled to an external processing unit, the coprocessor (100) comprising: A set of control registers (115) that can be written to by the external processing unit; An arithmetic engine (125) is used to execute a function on binary data stored in a set of source registers and to store the output of the function in at least one destination register. The function is applied to a set of corresponding bit sequences representing integer values ​​stored in the set of source registers. The function is selected from a set of functions including one or more of Boolean logic and integer arithmetic. Address generator (130) is used to determine a set of source addresses for loading binary data from memory into the set of source registers and at least one destination address for storing binary data from at least one destination register in memory. as well as Control logic (120) is configured to control the operations of the arithmetic engine (125) and the address generator (130) based on values ​​stored in the set of control registers (115), wherein the control logic is configured to select a function from the function set based on at least one value in the set of control registers (115). The coprocessor (100) is configured such that: The function set includes subfunctions for one or more of code-based and lattice-based cryptography. The control logic is configured to apply the arithmetic engine (125) and the address generator (130) within a set of iterations to perform operations on binary data associated with multiple sources and output binary data associated with a destination. Within the set of iterations, the address generator (130) determines a set of source addresses associated with the data matrix of each source and a set of destination addresses associated with the data matrix of the destination, and Within the set of iterations, the arithmetic engine (125) is applied to the data matrices of the plurality of sources to output the data matrix of the destination. The data matrices from the multiple sources and the destination have the same size. The control register (115) includes: A first control register, the first control register storing a bit sequence of integer size in a word representing the width of the matrix in a first dimension; and The second control register stores a bit sequence of integer size in a word representing the height of the matrix in the second dimension. Custom paths within one or more of the multiple matrices are configured using a starting address stored in the set of control registers and incremental values ​​for one or more dimensions, and In each iteration of the set of iterations, the address generator (130) determines the set of source addresses and the set of destination addresses in parallel based on the control register (115) by incrementing the set of source addresses and the at least one destination address.

2. The coprocessor (100) according to claim 1, wherein, At least one set of control registers (115) can be accessed by the external processing unit as a memory-mapped resource.

3. The coprocessor (100) according to claim 1 or claim 2, comprising: Internal memory (335) that is accessible to the external processing unit; Wherein, the set of source addresses and the at least one destination address include addresses within the internal memory (335), and The internal memory (335) can be accessed by the external processing unit as a memory-mapped resource.

4. The coprocessor (100) according to claim 1 or claim 2, comprising: An external memory interface (340) is provided for communicatively coupling the coprocessor (310) to external memory (355, 360), which is the memory of the external processing unit. The set of source addresses and the at least one destination address include addresses within the external memory.

5. The coprocessor (100) according to claim 1, wherein, The address generator (130) determines the source and destination addresses representing the programmable paths within the corresponding data matrix based on the values ​​stored in the set of control registers (115).

6. The coprocessor (100) according to claim 5, wherein, The value stored in the set of control registers (115) indicates: The starting addresses of the plurality of sources; and The positive or negative increment of each of the two dimensions of the data matrix, the increment being applied iteratively to the arithmetic engine (125).

7. The coprocessor (100) according to claim 1 or claim 2, wherein, The address generator (130) is configured to determine the address within the internal dual-port memory, and the set of source registers includes three internal source registers.

8. The coprocessor (100) according to claim 1 or claim 2, comprising: A set of shadow registers, the set of shadow registers corresponding to the set of source registers. In response to an instruction to copy data from the set of source addresses to the corresponding source registers in the set of source registers, the coprocessor (100) is configured to store the previous value in the set of source registers in the set of shadow registers.

9. The coprocessor (100) according to claim 8, wherein, For a given source, the coprocessor (100) is configured to read a windowed portion of data from a combination of the corresponding source register and shadow register, wherein the set of control registers indicates shift parameters for controlling the position of the windowed portion of the data.

10. The coprocessor (100) according to claim 1 or claim 2, wherein, Integer arithmetic includes one or more of integer multiplication, integer subtraction, and integer addition.

11. The coprocessor (100) according to claim 1 or claim 2, wherein, The coprocessor (100) is started by writing a function identifier into the set of control registers (115) by at least one processing unit, the function identifier being used to select the function from the set of functions.

12. The coprocessor (100) according to claim 1 or claim 2, wherein, The coprocessor is configured to evaluate multiple functions and store the corresponding outputs in multiple destination addresses.

13. A cryptographic on-chip system (240), comprising: System bus (230); A central processing unit (220) is coupled to the system bus (230). System memory, which is coupled to the system bus and used by the central processing unit; as well as The coprocessor (100) according to claim 1.

14. The cryptographic on-chip system (240) according to claim 13, wherein, A set of control registers and internal memory of the coprocessor are mapped into the secure address space of the central processing unit.

15. The cryptographic on-chip system (240) according to claim 13 or claim 14, wherein, The coprocessor (110) is protected within the on-chip system using one or more of a secure fuse and side-channel attack countermeasures.

16. A method (900) for performing cryptographic operations, comprising: The auxiliary processing unit reads (910) a value from a set of control registers for the auxiliary processing unit, the value being written according to an instruction from a main processing unit communicatively coupled to the auxiliary processing unit; The auxiliary processing unit determines (920) the function to be used for the cryptographic operation to be performed, the function being selected from a set of functions including one or more of Boolean logic and integer arithmetic based on at least one value in the set of control registers; Generate (930) a set of corresponding addresses associated with a set of sources and at least one destination, the addresses corresponding to one or more of the internal memory of the auxiliary processing unit and the system memory used by the main processing unit, the addresses being accessible by the main processing unit; Data is loaded (940) from the generated address associated with the set of sources; Apply the determined function (950) to the data; The output of the function is stored (960) at the generated address associated with the at least one destination; and Instruct the main processing unit (970) that the output can be obtained at the generated address associated with the destination. The function set includes subfunctions for one or more of code-based and lattice-based cryptography. A set of addresses is generated, data is loaded from the generated addresses, a determined function is applied to the data, and the output of the function is stored at the generated addresses. The process is iterated to apply the function to a data matrix associated with each of the plurality of sources forming the set of sources. The data matrix of the multiple data sources and the data matrix of the destination have the same size. The control register includes: A first control register, the first control register storing a bit sequence of integer size in a word representing the width of the matrix in a first dimension; and The second control register stores a bit sequence of integer size in a word representing the height of the matrix in the second dimension. In this context, custom paths within one or more of the multiple matrices are configured using a starting address stored in the set of control registers and incremental values ​​for one or more dimensions, and In each iteration, the address generator determines the set of source addresses and the at least one destination address in parallel based on the control register by incrementing a set of source addresses and at least one destination address.

17. The method (900) of claim 16, further comprising, prior to the reading step: Determine the cryptographic operations to be performed by the main processing unit; The cryptographic operations are decomposed into one or more functions; For one of the one or more functions: As instructed by the main processing unit, values ​​are loaded into a set of control registers for the auxiliary processing unit; As instructed by the main processing unit, data is loaded into one or more of the internal memory of the auxiliary processing unit and the system memory used by the main processing unit. The auxiliary processing unit is started by loading the initial value into the set of control registers; and Wait for an output indicating that it can be obtained at the destination. in, During the waiting period, the main processing unit can perform other operations.

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