A method, apparatus, system, and media for decoding tlc nand flash

Abstract

This application provides a TLC NAND flash memory decoding method, apparatus, system, and medium. The method includes: performing multiple read operations on a first logical page of the TLC NAND flash memory using a read voltage to obtain multiple read results; performing an XOR operation on the read results to obtain an initial decoding result; obtaining initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND flash memory based on the initial decoding result; correcting the initial LLR values ​​based on the multiple read results to obtain corrected LLR values; and decoding the TLC NAND flash memory based on the corrected LLR values. In other words, it uses data from the same logical page within the same physical page to correct the LLR values, eliminating the need to use data from other logical pages to correct the LLR values, thus achieving correct decoding of the TLC NAND flash memory. This method is simple to implement and improves efficiency and user experience.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a TLC NAND flash memory decoding method and apparatus. Background Technology

[0002] Semiconductor memory devices can be volatile or non-volatile. While volatile semiconductor memory devices can perform read and write operations at high speeds, the data stored in them is lost when power is off. Conversely, non-volatile semiconductor memory devices retain their stored data regardless of whether power is applied. Flash memory is a typical example of a non-volatile semiconductor memory device, and it is widely used as a data storage medium.

[0003] Non-volatile memory (NVRAM) consists of multiple storage cells arranged in an array for storing data. Each storage cell is divided into several blocks, and each block is further divided into several pages. Reading, writing, verifying, and clearing operations on NVRAM can all be performed on a page-by-page basis. When storing information, NVRAM requires encoding the data and writing the encoded data into the storage cells of the memory array. Decoding is required when reading the data.

[0004] In NAND Flash memory devices, there are mainly SLC (Single-Level Cell), MLC (Multi-Level Cell), and TLC (Trinary-Level Cell) types. nLC NAND Flash can inject different numbers of electrons into the floating gate or charge trapping layer of the NAND Flash memory device to obtain different threshold voltages, thereby representing different logic states. Taking Multi-Level Cell (MLC) NAND Flash as an example, when reading data, three different read voltages are applied to the gate to distinguish four logic states.

[0005] With the emergence of multilayer cell NAND Flash such as TLC, the distributed state is further compressed. TLC has a distribution along the threshold voltage of 2 3=8 distribution states, which overlap with each other, leading to increasingly serious bit error problems when reading data. Therefore, major manufacturers are researching various auxiliary decoding operations to enhance decoding performance. Among them, LLR (loglikelihood ratio) correction technology is a method that can significantly improve decoding capabilities with the advent of nLC NAND Flash. Traditional LLR correction technology usually corrects the LLR value by using data information from other logical pages in the same physical page. This requires that the read operation must be continuous and that the data of other logical pages in the same physical page must be kept as correct as possible. This is difficult to implement, has low efficiency, and results in a poor user experience. Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a TLC NAND flash memory decoding method, apparatus, system and medium that can easily and quickly correct LLR values, thereby improving the user experience while achieving correct decoding of TLC NAND flash memory.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] In a first aspect, embodiments of this application provide a TLC NAND flash memory decoding method, including:

[0009] Multiple read operations are performed on the first logic page of the TLC NAND flash memory using the read voltage to obtain multiple read results;

[0010] The initial decoding result is obtained by performing a bitwise OR operation on the read results;

[0011] The initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND are obtained based on the initial decoding results.

[0012] The initial LLR value is corrected based on the results of the multiple reads to obtain a corrected LLR value;

[0013] The TLC NAND flash memory is decoded according to the modified LLR value.

[0014] In one possible implementation, the step of correcting the initial LLR value based on the results of the multiple reads to obtain a corrected LLR value includes:

[0015] Obtain the position information of each distribution state corresponding to the multiple reading results;

[0016] The first LLR value is corrected based on the location information to obtain a corrected LLR value.

[0017] In one possible implementation, a physical page in the TLC NAND flash memory includes three logical pages: a lower page, a middle page, and a upper page; the TLC NAND flash memory includes eight distributed states: E, P1-P7.

[0018] When the first logical page is the next page; the step of performing multiple read operations on the first logical page of the TLC NAND flash memory using the read voltage to obtain multiple read results includes:

[0019] A first read result is obtained by performing a read operation using a first read voltage between the E state and the P1 state; a fifth read result is obtained by performing a read operation using a fifth read voltage between the P4 state and the P5 state.

[0020] In one possible implementation, the initial LLR value is corrected based on the multiple read results to obtain a corrected LLR value, and multiple read operations are performed on the second logic page of the TLC NAND flash memory using a read voltage to obtain multiple read results, which are performed in parallel.

[0021] Secondly, embodiments of this application provide a TLC NAND flash memory decoding device, comprising:

[0022] The first logic page read unit is used to perform multiple read operations on the first logic page of the TLC NAND flash memory using a read voltage to obtain multiple read results;

[0023] The XOR unit is used to perform an XOR operation on the read results to obtain the initial decoding result;

[0024] An initial LLR value acquisition unit is used to obtain the initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND based on the initial decoding result.

[0025] The modified LLR value acquisition unit is used to modify the initial LLR value based on the results of the multiple reads to obtain a modified LLR value;

[0026] The decoding unit is used to decode the TLC NAND flash memory according to the modified LLR value.

[0027] In one possible implementation, the modified LLR value acquisition unit includes:

[0028] A location information acquisition unit is used to acquire the location information of each distribution state corresponding to the multiple reading results;

[0029] The LLR value acquisition subunit is used to modify the first LLR value according to the location information to obtain a modified LLR value.

[0030] In one possible implementation, a physical page in the TLC NAND flash memory includes three logical pages: a lower page, a middle page, and a upper page; the TLC NAND flash memory includes eight distributed states: E, P1-P7.

[0031] When the first logical page is the next page; the first logical page read unit includes:

[0032] The first reading unit is used to perform a reading operation between the E state and the P1 state using a first reading voltage to obtain a first reading result;

[0033] The fifth read unit is used to perform a read operation between the P4 state and the P5 state using a fifth read voltage to obtain a fifth read result.

[0034] In one possible implementation, the device further includes:

[0035] The second logic page read unit is used to perform multiple read operations on the second logic page of the TLC NAND flash memory using a read voltage to obtain multiple read results.

[0036] A parallel operation unit is used to enable the modified LLR value acquisition unit and the second logical page read unit to run in parallel.

[0037] Thirdly, embodiments of this application provide a TLC NAND flash memory decoding system, including:

[0038] Memory, used to store computer programs;

[0039] A processor, used to implement the steps of the TLC NAND flash memory decoding method as described above when executing the computer program.

[0040] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when processed and executed, implements the steps of the TLC NAND flash memory decoding method described above.

[0041] Compared with the prior art, this application has at least the following advantages:

[0042] This application provides a TLC NAND flash memory decoding method, apparatus, system, and medium. The method includes: performing multiple read operations on a first logical page of the TLC NAND flash memory using a read voltage to obtain multiple read results; performing an XOR operation on the read results to obtain an initial decoding result; obtaining initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND flash memory based on the initial decoding result; correcting the initial LLR values ​​based on the multiple read results to obtain corrected LLR values; and decoding the TLC NAND flash memory based on the corrected LLR values. In other words, it uses data from the same logical page within the same physical page to correct the LLR values, eliminating the need to use data from other logical pages to correct the LLR values, thus completing the correct decoding of the TLC NAND flash memory. This method is simple to implement and improves efficiency and user experience. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart of a conventional TLC NAND flash memory decoding method is shown;

[0045] Figure 2 This illustration shows a Gray code diagram of a TLC NAND after performing a read operation on each logical page of the same physical page, according to an embodiment of this application.

[0046] Figure 3 A flowchart of another traditional TLC NAND flash memory decoding method is shown;

[0047] Figure 4 A flowchart of a TLC NAND flash memory decoding method provided in an embodiment of this application is shown;

[0048] Figure 5 This illustration shows a schematic diagram of repair decoding of the next page in a TLC NAND flash memory according to an embodiment of this application;

[0049] Figure 6 A schematic diagram of a TLC NAND flash memory decoding device provided in an embodiment of this application is shown. Detailed Implementation

[0050] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0052] As described in the background section, semiconductor memory devices can be volatile or non-volatile. While volatile semiconductor memory devices can perform read and write operations at high speeds, the content stored in them is lost when power is off. Conversely, non-volatile semiconductor memory devices retain their stored content regardless of whether power is applied. Flash memory is a typical example of a non-volatile semiconductor memory device, and it is widely used as a data storage medium.

[0053] Non-volatile memory (NVRAM) consists of multiple storage cells arranged in an array for storing data. Each storage cell is divided into several blocks, and each block is further divided into several pages. Reading, writing, verifying, and clearing operations on NVRAM can all be performed on a page-by-page basis. When storing information, NVRAM requires encoding the data and writing the encoded data into the storage cells of the memory array. Decoding is required when reading the data.

[0054] In NAND Flash memory devices, there are mainly SLC (Single-Level Cell), MLC (Multi-Level Cell), and TLC (Trinary-Level Cell) types. nLC NAND Flash can inject different numbers of electrons into the floating gate or charge trapping layer of the NAND Flash memory device to obtain different threshold voltages, thereby representing different logic states. Taking Multi-Level Cell (MLC) NAND Flash as an example, when reading data, three different read voltages are applied to the gate to distinguish four logic states.

[0055] With the emergence of multilayer cell NAND Flash such as TLC, the distributed state is further compressed. TLC has a distribution along the threshold voltage of 2 3=8 distribution states, which overlap with each other, leading to increasingly serious bit error problems when reading data. Therefore, major manufacturers are researching various auxiliary decoding operations to enhance decoding performance. Among them, LLR (loglikelihood ratio) correction technology is a method that can significantly improve decoding capabilities with the advent of nLC NAND Flash. Traditional LLR correction technology usually corrects the LLR value by using data information from other logical pages in the same physical page. This requires that the read operation must be continuous and that the data of other logical pages in the same physical page must be kept as correct as possible. This is difficult to implement, has low efficiency, and results in a poor user experience.

[0056] Specifically, traditional LLR correction algorithms can be broadly divided into two categories: one is to obtain more accurate information through more read operations, and the other is to use data information from other pages in the same physical page to correct LLR, as mentioned above.

[0057] See Figure 1 The diagram shows a flowchart of a traditional TLC NAND flash memory decoding method. More accurate information is obtained through multiple read operations. Specifically, a TLC NAND storage cell can store 3 bits, which belong to different logical pages: Upper Page, Middle Page, and Lower Page. That is, one physical page corresponds to three virtual logical pages.

[0058] The 3-bit Gray code has multiple distribution states (E to P7) as shown in Table 1 below.

[0059]

[0060]

[0061] Table 1

[0062] See Figure 1 As shown, the next page is first decoded. This can be done by performing a read operation between the E and P1 states using the first read voltage to obtain the first read result. See [link / reference]. Figure 2 As shown in the figure, the next page corresponding to the least significant bit (LSB) is read after the first read voltage (i.e., 1). st sensing, corresponding Figure 1 The correct Gray code obtained after LP read V1 should be 10000000, and then the fifth read voltage should be used for the read operation (i.e., 2). nd sensing, corresponding Figure 1The correct Gray code obtained after LP read V5 should be 11111000. However, due to the further compression and overlap of the TLC NAND distribution state along the threshold voltage, the decoding may fail (i.e., LPdecode failed).

[0063] At this point, soft decoding is performed by increasing the number of reads (i.e., Start Soft decode). First, the voltage value Vt increased by the number of reads (i.e., Cal read Vt) is calculated. Then, the number of reads is increased, with the aim of obtaining more accurate read information through more read operations. See, for example... Figure 1 As shown, the Lower Page decoding is successful by adding three read operations. Specifically, a second read voltage is used between P1 and P2 states to obtain the second read result (LP read V2), a third read voltage is used between P2 and P3 states to obtain the third read result (LP read V3), and a fourth read voltage is used between P3 and P4 states to obtain the fourth read result (LP read V4). This results in the correct decoding result for the Lower Page (get LP date).

[0064] Then you can continue decoding other logical pages, such as middle pages, see [link to documentation]. Figure 2 As shown in the figure, the middle page corresponding to the central significant bit (CSB) is read after the second read voltage (i.e., 1). st sensing, corresponding Figure 1 The correct Gray code obtained after MP read V2 should be 11000000. Then, the fourth read voltage is used for the read operation (i.e., 2). nd sensing, corresponding Figure 1 The correct Gray code obtained after MP read V4 should be 11110000. The sixth read voltage should be used for the read operation (i.e., 3). rd sensing, corresponding Figure 1 The correct Gray code obtained after MP read V6 should be 11111100, in order to successfully decode the middle page.

[0065] The above method of obtaining more accurate information through more read operations to correct the LLR value requires more reads and also greatly increases read latency, which has an adverse effect on NAND, resulting in a series of problems such as slower decoding process and lower efficiency.

[0066] See Figure 3 The diagram shows a flowchart of another traditional TLC NAND flash memory decoding method. The LLR value is corrected using data information from other logical pages within the same physical page. Decoding the lower page can begin by performing a read operation between the E and P1 states using a first read voltage to obtain the first read result. (See [link to relevant documentation]). Figure 2 As shown in the figure, the next page corresponding to the least significant bit (LSB) is read after the first read voltage (i.e., 1). st sensing, corresponding Figure 1 The correct Gray code obtained after LP read V1 should be 10000000, and then the fifth read voltage should be used for the read operation (i.e., 2). nd sensing, corresponding Figure 1 The correct Gray code obtained after LP read V5 should be 11111000. However, due to the further compression and overlap of the TLC NAND distribution state along the threshold voltage, the decoding may fail (i.e., LP decode failed).

[0067] At this point, the system waits to use data from another logical page (Middlepage) that is in the same physical page as the Lower Page for repair (i.e., Wait MP data). A second read voltage is used for reading (i.e., MP read V2), followed by a fourth read voltage (i.e., MP read V4), and a sixth read voltage (i.e., MP read V6), hoping to successfully repair the data using the Middle Page data, enabling successful decoding of the Lower Page (i.e., LP decode success). Then, the Middle Page is decoded again (i.e., start MP decode), resulting in the correct decoding result for the Lower Page (get LP data).

[0068] Optionally, the two methods described above can be used in combination. If the method of using data information from other logical pages in the same physical page to correct the LLR value still fails to decode, the method of increasing the number of reads can be used to correct it until the decoding is successful.

[0069] The above method of correcting the LLR value by utilizing data information from other logical pages within the same physical page requires ensuring continuous read operations and that the data information from other logical pages within the same physical page is correct. This method is difficult to implement, inefficient, and results in a poor user experience.

[0070] To address the aforementioned technical problems, this application provides a TLC NAND flash memory decoding method, apparatus, system, and medium. The method includes: performing multiple read operations on a first logical page of the TLC NAND flash memory using a read voltage to obtain multiple read results; performing an XOR operation on the read results to obtain an initial decoding result; obtaining initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND flash memory based on the initial decoding result; correcting the initial LLR values ​​based on the multiple read results to obtain corrected LLR values; and decoding the TLC NAND flash memory based on the corrected LLR values. In other words, it uses data from the same logical page within the same physical page to correct the LLR values, eliminating the need to use data from other logical pages to correct the LLR values, thus achieving correct decoding of the TLC NAND flash memory. This method is simple to implement and improves efficiency and user experience.

[0071] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0072] Exemplary methods

[0073] See Figure 4 As shown, this figure is a flowchart of a TLC NAND flash memory decoding method provided in an embodiment of this application, including:

[0074] S101: The first logic page of the TLC NAND flash memory is read multiple times using the read voltage to obtain multiple read results.

[0075] In this embodiment, we can take advantage of the fact that the transfer probabilities in different pages of NAND flash memory are significantly different, and we can use flash memory read information to correct the value of LLR.

[0076] When the first logical page is the lower page, a first read operation can be performed between the E state and the P1 state to obtain the first read result. See [link to relevant documentation]. Figure 2 As shown in the figure, the correct Gray code obtained after the first reading operation (i.e., 1st sensing) of the lower page corresponding to the least significant bit (LSB) should be 10000000. After the fifth reading operation (i.e., 2nd sensing) is performed, the correct Gray code obtained should be 11111000.

[0077] When the first logical page is a middle page, a second read operation can be performed between the P1 and P2 states to obtain the second read result. See [link to relevant documentation]. Figure 2As shown in the figure, the middle page corresponding to the central significant bit (CSB) is read after the second read voltage (i.e., 1). st The correct Gray code obtained after sensing should be 11000000. Then, the fourth reading voltage is used to perform the reading operation to obtain the fourth reading result (i.e., 2). nd After sensing, the correct Gray code should be 11110000. The sixth reading voltage is used to perform the reading operation, resulting in the sixth reading result (i.e., 3). rd sensing, corresponding Figure 1 The correct Gray code obtained after MP read V6 should be 11111100.

[0078] When the first logical page is the upper page, a third read operation can be performed between the P2 and P3 states to obtain the third read result. See [link to relevant documentation]. Figure 2 As shown in the figure, the upper page corresponding to the most significant bit (MSB) is read after the third read voltage (i.e., 1). st The correct Gray code obtained after sensing should be 11100000. Then, the seventh reading voltage is used to perform the reading operation to obtain the seventh reading result (i.e., 2). nd The correct Gray code obtained after sensing should be 11111110.

[0079] Then, the results of multiple read operations can be placed into the page buffer so that they can be quickly accessed later.

[0080] S102: Perform an XOR operation on the read results to obtain the initial decoding result;

[0081] In this embodiment of the application, in order to perform decoding correctly, the Gray code in each logical page needs to be as shown in Table 1. Therefore, the initial decoding result can be obtained by performing an XOR operation between the read results.

[0082] When the first logical page is the next page, the first read result 10000000 and the fifth read result 11111000 are XORed to obtain 10000111.

[0083] When the first logical page is a middle page, the second read result 11000000 and the fourth read result 11110000 are first XORed to get 11001111, and then 11001111 and the sixth read result 11111100 are XORed to get 11001100.

[0084] When the first logical page is the upper page, the third read result 11100000 and the seventh read result are XORed to obtain 11111110.

[0085] Then, the initial decoding result obtained by performing the above XOR operation can be placed into the page buffer so that it can be quickly accessed later.

[0086] S103: Obtain the initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND based on the initial decoding results.

[0087] S104: Decode the TLC NAND flash memory according to the modified LLR value.

[0088] In the embodiments of this application, the size of the LLR value represents the order in which repairs are performed. The smaller the absolute value of the LLR value, the more likely its corresponding distribution state is to be wrong, so it needs to be flipped first. Conversely, the larger the absolute value of the LLR value, the lower the probability of its corresponding distribution state being wrong, so it can be flipped later.

[0089] In this embodiment of the application, since the initial decoding result is obtained by performing an XOR operation, some position information is lost. Taking the first logical page as the lower page as an example, the XOR operation of the data results in 10000111, that is, E state, P5, P6, and P7 are all 1, and it is impossible to determine which one to flip first.

[0090] However, the probability of error in state E is higher in the early stages of data retention. As the data retention time increases, the threshold voltage gradually shifts to the right, so the probability of error in P5, P6, and P7 is higher.

[0091] Therefore, the position information of each distribution state corresponding to multiple read results can be obtained. The first LLR value is corrected according to the position information to obtain the corrected LLR value, so that the correction can be made accurately, thereby improving the decoding performance. Then, the TLC NAND flash memory is decoded according to the corrected LLR value to achieve successful decoding.

[0092] See Figure 5The diagram illustrates a method for repairing and decoding the next page in a TLC NAND flash memory according to an embodiment of this application. When decoding the next page fails, the location information of each distributed state corresponding to multiple read results can be retransmitted. The first LLR value is corrected based on the location information to obtain a corrected LLR value, thus enabling successful decoding of the next page. Simultaneously, to improve decoding efficiency, the initial LLR value can be corrected based on multiple read results to obtain a corrected LLR value, and the TLC NAND flash memory can be decoded based on the corrected LLR value. Furthermore, multiple read operations are performed on the second logic page of the TLC NAND flash memory using a read voltage to obtain multiple read results, all performed in parallel.

[0093] For example, if the location information indicates that the E state needs to be repaired, the first read voltage is used to flip the E state (Trans LP read V1); the read voltage is used to read the page in the TLC NAND flash memory. First, the second read voltage can be used to perform the read operation (MP read V2) to obtain the second read result. That is, the two are performed in parallel, which improves the decoding efficiency.

[0094] It should be noted that the above-mentioned XOR technical feature can also be implemented by XOR in actual operation, and the embodiments of this application are not specifically limited here.

[0095] This application provides a TLC NAND flash memory decoding method. The method includes: performing multiple read operations on a first logical page of the TLC NAND flash memory using a read voltage to obtain multiple read results; performing an XOR operation on the read results to obtain an initial decoding result; obtaining initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND flash memory based on the initial decoding result; correcting the initial LLR values ​​based on the multiple read results to obtain corrected LLR values; and decoding the TLC NAND flash memory based on the corrected LLR values. In other words, it uses data from the same logical page within the same physical page to correct the LLR values, eliminating the need to use data from other logical pages to correct the LLR values, thus completing the correct decoding of the TLC NAND flash memory. This method is simple to implement and improves efficiency and user experience.

[0096] Exemplary device

[0097] See Figure 6 The diagram shown is a schematic of a TLC NAND flash memory decoding device provided in an embodiment of this application, comprising:

[0098] The first logic page read unit 601 is used to perform multiple read operations on the first logic page of the TLC NAND flash memory using a read voltage to obtain multiple read results.

[0099] The XOR unit 602 is used to perform an XOR operation on the read results to obtain an initial decoding result;

[0100] The initial LLR value acquisition unit 603 is used to obtain the initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND according to the initial decoding result.

[0101] The modified LLR value acquisition unit 604 is used to modify the initial LLR value based on the results of the multiple reads to obtain a modified LLR value;

[0102] Decoding unit 605 is used to decode the TLC NAND flash memory according to the modified LLR value.

[0103] In one possible implementation, the modified LLR value acquisition unit includes:

[0104] A location information acquisition unit is used to acquire the location information of each distribution state corresponding to the multiple reading results;

[0105] The LLR value acquisition subunit is used to modify the first LLR value according to the location information to obtain a modified LLR value.

[0106] In one possible implementation, a physical page in the TLC NAND flash memory includes three logical pages: a lower page, a middle page, and a upper page; the TLC NAND flash memory includes eight distributed states: E, P1-P7.

[0107] When the first logical page is the next page; the first logical page read unit includes:

[0108] The first reading unit is used to perform a reading operation between the E state and the P1 state using a first reading voltage to obtain a first reading result;

[0109] The fifth read unit is used to perform a read operation between the P4 state and the P5 state using a fifth read voltage to obtain a fifth read result.

[0110] In one possible implementation, the device further includes:

[0111] The second logic page read unit is used to perform multiple read operations on the second logic page of the TLC NAND flash memory using a read voltage to obtain multiple read results.

[0112] A parallel operation unit is used to enable the modified LLR value acquisition unit and the second logical page read unit to run in parallel.

[0113] This application provides a TLC NAND flash memory decoding device. The method applied to this device includes: performing multiple read operations on a first logical page of the TLC NAND flash memory using a read voltage to obtain multiple read results; performing an XOR operation on the read results to obtain an initial decoding result; obtaining initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND flash memory based on the initial decoding result; correcting the initial LLR values ​​based on the multiple read results to obtain corrected LLR values; and decoding the TLC NAND flash memory based on the corrected LLR values. That is, it uses data from the same logical page within the same physical page to correct the LLR values, eliminating the need to use data from other logical pages to correct the LLR values, thus completing the correct decoding of the TLC NAND flash memory. This simplifies implementation and improves efficiency and user experience.

[0114] Based on the above embodiments, this application also provides a TLC NAND flash memory decoding system, including:

[0115] Memory, used to store computer programs;

[0116] A processor is used to implement the steps of the TLC NAND flash memory decoding method described above when executing the computer program.

[0117] Based on the above embodiments, this application also provides a computer-readable storage medium storing a computer program, which, when processed and executed, implements the steps of the TLC NAND flash memory decoding method described above.

[0118] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so they are described more simply; relevant parts can be referred to the descriptions in the method embodiments.

[0120] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A TLC NAND flash memory decoding method, characterized in that, include: Multiple read operations are performed on the first logical page of a TLC NAND flash memory using a read voltage to obtain multiple read results. A physical page in the TLC NAND flash memory includes three logical pages: the next page, the middle page, and the previous page. The TLC NAND flash memory includes eight distributed states: E, P1-P7. When the first logical page is the next page, the multiple read operations on the first logical page of the TLC NAND flash memory using a read voltage to obtain multiple read results include: performing a read operation using a first read voltage between the E state and the P1 state to obtain a first read result; and performing a read operation using a fifth read voltage between the P4 state and the P5 state to obtain a fifth read result. The initial decoding result is obtained by performing a bitwise OR operation on the read results; The initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND are obtained based on the initial decoding results. The initial LLR value is corrected based on the multiple reading results to obtain a corrected LLR value; the step of correcting the initial LLR value based on the multiple reading results to obtain a corrected LLR value includes: obtaining the location information of each distribution state corresponding to the multiple reading results; and correcting the first LLR value based on the location information to obtain a corrected LLR value. The TLC NAND flash memory is decoded according to the modified LLR value.

2. The method according to claim 1, characterized in that, The initial LLR value is corrected based on the multiple read results to obtain a corrected LLR value, and multiple read operations are performed on the second logic page of the TLC NAND flash memory using the read voltage to obtain multiple read results, which are performed in parallel.

3. A TLC NAND flash memory decoding device, characterized in that, include: The first logical page read unit is used to perform multiple read operations on the first logical page of the TLC NAND flash memory using a read voltage to obtain multiple read results; a physical page in the TLC NAND flash memory includes three logical pages: the next page, the middle page, and the previous page; the TLC NAND flash memory includes eight distributed states: E, P1-P7; when the first logical page is the next page; the first logical page read unit includes: a first read unit, used to perform a read operation between the E state and the P1 state using a first read voltage to obtain a first read result; and a fifth read unit, used to perform a read operation between the P4 state and the P5 state using a fifth read voltage to obtain a fifth read result; The XOR unit is used to perform an XOR operation on the read results to obtain the initial decoding result; An initial LLR value acquisition unit is used to obtain the initial LLR values ​​corresponding to each distribution state of the first logical page of the TLC NAND based on the initial decoding result. A modified LLR value acquisition unit is used to modify the initial LLR value based on the multiple reading results to obtain a modified LLR value; the modified LLR value acquisition unit includes: a location information acquisition unit, used to acquire the location information of each distribution state corresponding to the multiple reading results; and a modified LLR value acquisition subunit, used to modify the first LLR value based on the location information to obtain a modified LLR value. The decoding unit is used to decode the TLC NAND flash memory according to the modified LLR value.

4. The apparatus according to claim 3, characterized in that, The device further includes: The second logic page read unit is used to perform multiple read operations on the second logic page of the TLC NAND flash memory using a read voltage to obtain multiple read results; A parallel operation unit is used to enable the modified LLR value acquisition unit and the second logical page read unit to run in parallel.

5. A TLC NAND flash memory decoding system, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the TLC NAND flash memory decoding method as described in any one of claims 1-2 when executing the computer program.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when processed and executed, implements the steps of the TLC NAND flash memory decoding method as described in any one of claims 1-2.

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