A method and apparatus for model development of a multi-core heterogeneous processor

Abstract

The present invention discloses a method and apparatus for developing a model of a multi-core heterogeneous processor. In this method, abstract models of various types of processor cores are generated according to model configuration scripts and code generation rules of various types of processor cores; driver modules, inter-core communication modules, and external communication modules corresponding to various types of processor cores are encapsulated to generate module libraries corresponding to various types of processor cores; an abstract model of the multi-core heterogeneous processor is generated according to the information in the read configuration file, the abstract models of each processor core, and the model reference method; the generated code is obtained by calling the abstract models of each processor core and the module libraries corresponding to the categories to which each processor core belongs, and a multi-core project corresponding to the multi-core heterogeneous processor is obtained according to the generated code and the basic engineering framework of the multi-core heterogeneous processor. By using the method of the present invention, manual coding is not required, the workload of developers is reduced, and the efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of processors, and in particular, to a method and device for developing a model of a multi-core heterogeneous processor. Background Art

[0002] A multi-core heterogeneous processor refers to a hardware platform that includes multiple processor cores of different types. Generally, the development method of traditional multi-core heterogeneous processors is as follows: Embedded developers manually write code to generate embedded algorithms, such as inter-core communication algorithms and external communication algorithms. Algorithm developers manually write code to generate algorithms with certain functions of each processor core. Then, embedded developers and algorithm developers collaborate to manually write code to integrate the embedded algorithms and the algorithms with certain functions of each processor core to generate a project of a multi-core heterogeneous processor.

[0003] In the above development method, whether it is embedded developers or algorithm developers, they both implement algorithms by directly coding manually, resulting in a large workload and low efficiency for developers. Summary of the Invention

[0004] The present invention provides a method and device for developing a model of a multi-core heterogeneous processor, which does not require manual coding, reduces the workload of developers, and improves efficiency. The specific technical solutions are as follows.

[0005] In a first aspect, the present invention provides a method for developing a model of a multi-core heterogeneous processor, including:

[0006] Receiving the basic models, model configuration scripts, and code generation rules of various types of processor cores in the multi-core heterogeneous processor written by developers according to the configuration file of the multi-core heterogeneous processor to be developed, and optimizing the basic models of various types of processor cores according to the model configuration scripts and code generation rules of various types of processor cores to generate abstract models of various types of processor cores;

[0007] Receiving the driver modules, inter-core communication modules, and external communication modules corresponding to various types of processor cores written by developers, and encapsulating the driver modules, inter-core communication modules, and external communication modules corresponding to various types of processor cores to generate a module library corresponding to various types of processor cores;

[0008] Receiving the model development tools and tool usage sequences selected by developers for various types of processor cores, and generating a development tool chain corresponding to various types of processor cores according to the model development tools and tool usage sequences;

[0009] Receive the basic engineering frameworks of each processor core created by developers based on the development toolchains corresponding to various processor cores, and generate the basic engineering framework of the multi-core heterogeneous processor based on the basic engineering frameworks of each processor core;

[0010] Read the information in the configuration file, and generate the abstract model of the multi-core heterogeneous processor according to the read information, the abstract models of each processor core, and the model reference method;

[0011] Call the code generated by the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs, and obtain the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor.

[0012] Optionally, the step of optimizing the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate the abstract models of various processor cores includes:

[0013] For each type of processor core, generate target code based on the code generation rule of this type of processor core, and optimize the basic model of this type of processor core according to the target code and the configuration items in the model configuration script of this type of processor core to generate the abstract model of this type of processor core.

[0014] Optionally, when the type of the processor core is a digital signal processor DSP C66x processor core, the inter-core communication module corresponding to this type of processor core includes: an inter-core message queue module, and the external communication module corresponding to this type of processor core includes at least one of the following: a serial port module, an external memory interface EMIF module, an Ethernet communication module, and a serial high-speed SRIO module;

[0015] When the type of the processor core is a Xilinx ARM A53 processor core or a Xilinx ARM R5 processor core, the inter-core communication module corresponding to this type of processor core includes: a video direct memory access VDMA module, and the external communication module corresponding to this type of processor core includes at least one of the following: a video direct memory access VDMA module, an external memory interface EMIF module, and an Ethernet communication module.

[0016] Optionally, the step of obtaining the code generated by the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs, and obtaining the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor includes:

[0017] For the abstract model of each processor core in the abstract model of the multi-core heterogeneous processor, build an algorithm model of a preset type in the abstract model, and integrate the algorithm model of the preset type with the module library corresponding to the category to which the processor core belongs to obtain an integrated model;

[0018] Call a preset code generation toolbox to parse each integrated model to obtain the code generated by each integrated model;

[0019] Integrate the code generated by each integrated model into the basic engineering frameworks of each processor core included in the basic engineering framework of the multi-core heterogeneous processor to obtain the multi-core project corresponding to the multi-core heterogeneous processor.

[0020] Optionally, after the step of obtaining the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor, the above-mentioned model development method of the multi-core heterogeneous processor further includes:

[0021] Call the development toolchain corresponding to the category to which each processor core belongs to compile each processor core in the multi-core project to obtain each executable file corresponding to each processor core, and deploy each executable file to the corresponding processor core and run to generate a running result.

[0022] In a second aspect, the present invention provides a model development device for a multi-core heterogeneous processor, including:

[0023] An abstract model generation module for various processor cores, configured to receive the basic models, model configuration scripts, and code generation rules of various processor cores in the multi-core heterogeneous processor written by a developer according to the configuration file of the multi-core heterogeneous processor to be developed, and optimize the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores;

[0024] A module library generation module, configured to receive the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores written by a developer, and package the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate module libraries corresponding to various processor cores;

[0025] A development toolchain generation module, configured to receive model development tools for various processor cores selected by a developer and the tool usage order, and generate development toolchains corresponding to various processor cores according to the model development tools and the tool usage order;

[0026] A basic engineering framework generation module, configured to receive basic engineering frameworks of each processor core created by the developer based on the development toolchains corresponding to various processor cores, and generate the basic engineering framework of the heterogeneous multi-core processor based on the basic engineering frameworks of each processor core;

[0027] An abstract model generation module of the heterogeneous multi-core processor, configured to read information in the configuration file, and generate an abstract model of the heterogeneous multi-core processor according to the read information, the abstract models of each processor core, and the model reference method;

[0028] A multi-core project generation module, configured to call the code generated by the abstract models of each processor core in the abstract model of the heterogeneous multi-core processor and the module library corresponding to the category to which each processor core belongs, and obtain the multi-core project corresponding to the heterogeneous multi-core processor according to the generated code and the basic engineering framework of the heterogeneous multi-core processor.

[0029] Optionally, the abstract model generation module for each type of processor core is specifically configured to:

[0030] For each type of processor core, generate target code based on the code generation rules of this type of processor core, and optimize the basic model of this type of processor core according to the configuration items in the model configuration script of this type of processor core and the target code to generate the abstract model of this type of processor core.

[0031] Optionally, when the type of the processor core is a digital signal processor DSP C66x processor core, the inter-core communication module corresponding to this type of processor core includes: an inter-core message queue module, and the external communication module corresponding to this type of processor core includes at least one of the following: a serial port module, an external memory interface EMIF module, an Ethernet communication module, and a serial high-speed SRIO module;

[0032] When the type of the processor core is a Xilinx ARM A53 processor core or a Xilinx ARM R5 processor core, the inter-core communication module corresponding to this type of processor core includes: a video direct memory access VDMA module, and the external communication module corresponding to this type of processor core includes at least one of the following: a video direct memory access VDMA module, an external memory interface EMIF module, and an Ethernet communication module.

[0033] Optionally, the multi-core project generation module includes:

[0034] An integrated model generation sub-module, which is configured to build an algorithm model of a preset type in the abstract model for each processor core's abstract model in the abstract model of the multi-core heterogeneous processor, and integrate the algorithm model of the preset type with the module library corresponding to the category to which the processor core belongs to obtain an integrated model;

[0035] A code generation sub-module, which is configured to call a preset code generation toolbox to parse each integrated model to obtain the code generated by each integrated model;

[0036] A multi-core project generation sub-module, which is configured to integrate the code generated by each integrated model into the basic project frameworks of the respective processor cores included in the basic project framework of the multi-core heterogeneous processor to obtain the multi-core project corresponding to the multi-core heterogeneous processor.

[0037] Optionally, the above-mentioned model development device for a multi-core heterogeneous processor further includes:

[0038] A deployment module, which is configured to, after obtaining the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the abstract model of the multi-core heterogeneous processor, call the development toolchain corresponding to the category to which each processor core belongs to compile each processor core in the multi-core project to obtain respective executable files corresponding to each processor core, and deploy each executable file to the corresponding processor core and run to generate a running result.

[0039] As can be seen from the above, a method for developing a model of a multi-core heterogeneous processor provided by an embodiment of the present invention can receive the basic models of various processor cores, model configuration scripts, and code generation rules in the multi-core heterogeneous processor written by a developer according to the configuration file of the multi-core heterogeneous processor to be developed. Optimize the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores; receive the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores written by the developer, and encapsulate the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate module libraries corresponding to various processor cores; receive the model development tools selected by the developer for various processor cores and the order of tool use, and generate a development tool chain corresponding to various processor cores according to the model development tools and the order of tool use; receive the basic engineering frameworks of each processor core created by the developer based on the development tool chain corresponding to various processor cores, and generate a basic engineering framework of the multi-core heterogeneous processor based on the basic engineering frameworks of each processor core; read the information in the configuration file, and generate an abstract model of the multi-core heterogeneous processor according to the information read, the abstract models of each processor core, and the model reference method; call the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs to obtain the code generated by the abstract models of each processor core, and obtain the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor. In the embodiment of the present invention, by having the developer pre-write the basic models of various processor cores, model configuration scripts, and code generation rules in the multi-core heterogeneous processor, and modularize the complex embedded underlying drivers, inter-core communication, and external communication mechanisms, when developing the multi-core heterogeneous processor, directly call the model configuration scripts and code generation rules of various processor cores to optimize the basic models of various processor cores to generate abstract models of various processor cores, and then call the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs to obtain the code generated by the abstract models of each processor core, and obtain the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor, without manual coding, reducing the workload of developers and improving efficiency. Of course, implementing any product or method of the present invention does not necessarily require all of the above advantages to be achieved at the same time.

[0040] The innovation points of the embodiment of the present invention include:

[0041] 1. By pre-writing the basic models of various processor cores in a multi-core heterogeneous processor, model configuration scripts, and code generation rules by developers, and modularizing complex embedded underlying drivers, inter-core communication, and external communication mechanisms, when developing a multi-core heterogeneous processor, directly call the model configuration scripts and code generation rules of various processor cores to optimize the basic models of various processor cores to generate abstract models of various processor cores, and then call the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs to obtain the code generated by the abstract models of each processor core. According to the generated code and the basic engineering framework of the multi-core heterogeneous processor, the multi-core project corresponding to the multi-core heterogeneous processor is obtained, eliminating the need for manual coding, reducing the workload of developers, and improving efficiency.

[0042] 2. Since complex embedded underlying drivers, inter-core communication, and external communication mechanisms have been modularized before developing a multi-core heterogeneous processor, during development, developers do not need to concern themselves with underlying development and can directly call the modules, improving efficiency. Moreover, it avoids the occurrence of coding errors introduced during manual coding due to limitations in developers' experience or skills.

[0043] 3. Since the complex embedded underlying drivers, inter-core communication, and external communication mechanisms are modularized in the embodiments of the present invention, during debugging, they can be debugged separately without the need to debug the entire multi-core heterogeneous processor, improving efficiency.

[0044] 4. When using MATLAB software / Simulink software for development, since MATLAB software / Simulink software is a graphical visualization environment, developers can continuously view the entire development process, making debugging convenient.

[0045] 5. Each executable file can be deployed to the corresponding processor core simultaneously and run to generate a running result, avoiding the need to deploy each executable file to the corresponding processor core one by one through manual coding in the related art, improving efficiency.

[0046] 6. By calling a preset code generation toolbox to parse each integrated model, the code generated by each integrated model is obtained, eliminating the need for manual code writing and reducing the workload of developers. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0048] Figure 1 It is a schematic flowchart of a method for developing a model of a multi-core heterogeneous processor provided by an embodiment of the present invention;

[0049] Figure 2 It is a schematic diagram of a module library corresponding to 3 types of processor cores;

[0050] Figure 3 It is another schematic flowchart of a method for developing a model of a multi-core heterogeneous processor provided by an embodiment of the present invention;

[0051] Figure 4 It is a schematic structural diagram of a device for developing a model of a multi-core heterogeneous processor provided by an embodiment of the present invention. Detailed implementation manners

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0053] It should be noted that the terms "include" and "have" and any variations thereof in the embodiments of the present invention and the accompanying drawings are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include unlisted steps or units, or may optionally further include other steps or units inherent to these processes, methods, products or devices.

[0054] The embodiments of the present invention disclose a method and a device for developing a model of a multi-core heterogeneous processor, which do not require manual coding, reduce the workload of developers, and improve efficiency. The following will elaborate on the embodiments of the present invention.

[0055] Figure 1 It is a schematic flowchart of a method for developing a model of a multi-core heterogeneous processor provided by an embodiment of the present invention. This method is applied to an electronic device, and the electronic device can be a computer. The method specifically includes the following steps.

[0056] S110: Receive the basic models, model configuration scripts, and code generation rules of various processor cores in the multi-core heterogeneous processor written by developers according to the configuration file of the multi-core heterogeneous processor to be developed. Optimize the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores.

[0057] To develop a multi-core heterogeneous processor, it is necessary to define the configuration file of the multi-core heterogeneous processor to be developed. There are various ways to define the configuration file, including but not limited to the following two: manually write the configuration file or manually configure the multi-core heterogeneous processor to be developed in the visualization interface of the electronic device, and the electronic device automatically generates the configuration file according to the configuration result.

[0058] Among them, the configuration file of the multi-core heterogeneous processor to be developed is a file used to describe the specific configuration of the multi-core heterogeneous processor to be developed. Exemplarily, the information in the configuration file may include the target name of the multi-core heterogeneous processor to be developed, the target types and target numbers of various processor cores included, and the format of the configuration file may be XML (Extensible Markup Language) format.

[0059] In the embodiment of the present invention, to improve efficiency, after obtaining the configuration file, developers need to write the basic models, model configuration scripts, and code generation rules of various processor cores in the multi-core heterogeneous processor according to the configuration file of the multi-core heterogeneous processor to be developed.

[0060] Among them, the basic model is a model used to describe the basic code of the processor core. Developers can write the basic models of various processor cores in the multi-core heterogeneous processor based on the configuration file and the preset simulation software. For example: assuming that the information in the configuration file includes 2 type-A processor cores and 1 type-B processor core, then developers can write the basic models of the type-A processor core and the type-B processor core in the multi-core heterogeneous processor based on the configuration file and the preset simulation software. Exemplarily, the preset simulation software can be MATLAB software / Simulink software.

[0061] Since each type of processor core is different, the requirements for the code generated by the abstract model of various processor cores are also different. Therefore, different code generation rules need to be customized for different types of processor cores. Specifically, developers write the code generation rules of various processor cores in the multi-core heterogeneous processor based on the configuration file and the target language compiler, so that the code generated based on this code generation rule is specific to the multi-core heterogeneous processor.

[0062] Exemplarily, the target language compiler can be the TLC (Target Language Compiler) in the Simulink software code generation mechanism. TLC is an interpreted programming language that enables users to customize code generation.

[0063] Since the establishment of each model needs to support the modeling specifications, developers also need to write model configuration scripts for various processor cores in the multi-core heterogeneous processor according to the configuration file, so that the established models comply with the modeling specifications. Exemplarily, developers can program the model configuration scripts for various processor cores using the MATLAB language.

[0064] After developers write the basic models, model configuration scripts, and code generation rules for various processor cores in the multi-core heterogeneous processor according to the configuration file of the to-be-developed multi-core heterogeneous processor, they send them to the electronic device.

[0065] The electronic device receives the basic models, model configuration scripts, and code generation rules for various processor cores in the multi-core heterogeneous processor written by the developer according to the configuration file of the to-be-developed multi-core heterogeneous processor, and then optimizes the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores.

[0066] Among them, the step of optimizing the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores may include:

[0067] For each type of processor core, generate target code based on the code generation rule of this type of processor core, and optimize the basic model of this type of processor core according to the target code and the configuration items in the model configuration script of this type of processor core to generate the abstract model of this type of processor core.

[0068] For each type of processor core, generate target code based on the code generation rule of this type of processor core. Among them, the code generation rule may include the chip type and the structure of the generated code, and the code generation rules for each type of processor core are different.

[0069] For each type of processor core, the model configuration script may include one or more configuration items, and each configuration item is used to configure the basic model. Exemplarily, the configuration item may be: do not generate exception handling code. After generating the target code, the basic model of this type of processor core can be optimized according to the target code and the configuration items in the model configuration script of this type of processor core to generate the abstract model of this type of processor core, where the abstract model is generated by an abstract description method.

[0070] S120: Receive the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores written by developers, and encapsulate the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate module libraries corresponding to various processor cores.

[0071] Since algorithm development is carried out by manual coding in related technologies, the efficiency is low. In the embodiments of the present invention, in order to improve the efficiency, complex embedded underlying drivers, inter-core communication, and external communication mechanisms are modularized. When development is required, the modules can be directly called, which improves the efficiency.

[0072] Specifically, developers can write the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores based on Simulink software. Among them, the driver module is a module for implementing a specific function. Since there may be multiple functions to be implemented, there can also be multiple driver modules; the inter-core communication module is a module for implementing communication between multiple processor cores in the same multi-core heterogeneous processor; the external communication module is a module for implementing communication between the processor core in the multi-core heterogeneous processor and other platforms or processor cores in other platforms.

[0073] After developers write the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores, they are sent to the electronic device. The electronic device receives the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores written by developers, and then encapsulates the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate module libraries corresponding to various processor cores.

[0074] Specifically, encapsulating the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate module libraries corresponding to various processor cores may include:

[0075] For each type of processor core, call the module encapsulation mechanism of Simulink software to encapsulate the driver module, inter-core communication module, and external communication module corresponding to this type of processor core to generate the module library corresponding to this type of processor core.

[0076] Figure 2 For a schematic diagram of the module libraries corresponding to 3 types of processor cores, see Figure 2When the type of the processor core is a DSP (Digital Signal Processing) C66x processor core, the inter-core communication module corresponding to this type of processor core may include: an inter-core message queue module, and the external communication module corresponding to this type of processor core includes at least one of the following: a serial port module, an EMIF (External Memory Interface) module, an Ethernet communication module, and an SRIO (Serial RapidIO) module.

[0077] Among them, the inter-core message queue module is used to communicate between multiple processor cores in the same heterogeneous multi-core processor in the form of a message queue; the serial port module is used for communication of information with a relatively small amount of data; the external memory interface EMIF module is used to communicate with external storage components; the Ethernet communication module is used to communicate with external hardware; and the serial high-speed SRIO module is used to communicate with external digital signal processors.

[0078] Continue to refer to Figure 2 When the type of the processor core is a Xilinx ARM A53 processor core or a Xilinx ARM R5 processor core, the inter-core communication module corresponding to this type of processor core may include: a Video Direct Memory Access (VDMA) module, and the external communication module corresponding to this type of processor core includes at least one of the following: a Video Direct Memory Access (VDMA) module, an external memory interface EMIF module, and an Ethernet communication module.

[0079] Among them, the Video Direct Memory Access (VDMA) module can be used both to communicate with external storage components and to communicate with storage components in the same heterogeneous multi-core processor.

[0080] S130: Receive the model development tools and the tool usage order selected by the developer, and generate the development tool chain corresponding to each type of processor core according to the model development tools and the tool usage order.

[0081] For the development of the heterogeneous multi-core processor, in the embodiment of the present invention, manual coding is no longer performed, but the development tools are formed into a development tool chain, and when needed, it can be directly called, which improves the efficiency.

[0082] Specifically, since development tools are generally provided by chip manufacturers, for various processor cores, developers manually select the model development tools for various processor cores and the tool usage order, and send them to the electronic device. The electronic device receives the model development tools for various processor cores and the tool usage order selected by the developer, and then generates a development toolchain corresponding to each processor core according to the model development tools and the tool usage order.

[0083] Exemplarily, the model development tools may include a compiler and a linker.

[0084] Among them, generating a development toolchain corresponding to each processor core according to the model development tools and the tool usage order may include:

[0085] For each type of processor core, arrange the model development tools in the tool usage order and integrate them into MATLAB software / Simulink software to generate a development toolchain corresponding to this type of processor core.

[0086] For example: Assume that the model development tools for the Z type of processor core include a compiler and a linker, and the tool usage order is that the compiler is the first and the linker is the second. Then the development toolchain corresponding to the Z type of processor core is: compiler, linker.

[0087] S140: Receive the basic engineering frameworks of each processor core created by the developer based on the development toolchains corresponding to each type of processor core, and generate a basic engineering framework of the multi-core heterogeneous processor based on the basic engineering frameworks of each processor core.

[0088] To develop a multi-core heterogeneous processor, it is necessary to establish the basic engineering frameworks of each processor core. Specifically, the developer creates the basic engineering frameworks of each processor core based on the development toolchains corresponding to each type of processor core and sends them to the electronic device. The electronic device receives the basic engineering frameworks of each processor core created by the developer based on the development toolchains corresponding to each type of processor core, and then generates a basic engineering framework of the multi-core heterogeneous processor based on the basic engineering frameworks of each processor core. Among them, the basic engineering framework of each processor core is an engineering that only contains the basic code that the processor core can run. Exemplarily, the basic engineering framework may include: an application code execution entry, memory allocation, and a bottom-layer driver.

[0089] At this time, the generated basic engineering framework of the multi-core heterogeneous processor is only an engineering that contains the basic engineering frameworks of each processor core, and it still cannot really run to implement various functions, and it is not yet a complete multi-core project of the multi-core heterogeneous processor.

[0090] In summary, we have obtained the abstract models of various processor cores and the corresponding module libraries and development tool chains required for the model development method of multi-core heterogeneous processors, as well as the basic engineering framework of each processor core and the basic engineering framework of multi-core heterogeneous processors. This allows each processor core to support development based on the model development method, and further allows multi-core heterogeneous processors to be developed based on the model development method. Among them, the model-based development method is a method of software development through modeling and then with the help of code generation. Now let's start developing multi-core heterogeneous processors.

[0091] S150: Read information in the configuration file, and generate an abstract model of the multi-core heterogeneous processor according to the read information, the abstract models of each processor core, and the model reference method.

[0092] In order to develop a multi-core heterogeneous processor, the electronic device reads information in a configuration file, and then generates an abstract model of the multi-core heterogeneous processor based on the read information, abstract models of each processor core, and a model reference method.

[0093] The process of reading the information in the configuration file and generating the abstract model of the multi-core heterogeneous processor according to the read information, the abstract models of each processor core, and the model reference method may include:

[0094] The target name of the multi-core heterogeneous processor to be developed, the target types of various types of processor cores included, and the target number are obtained by reading the information in the configuration file through MATLAB software / Simulink software. An abstract model of the multi-core heterogeneous processor whose name is the target name and includes an abstract model of processor cores of the target number and target type is generated through a model reference method.

[0095] S160: Call the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs to obtain the code generated by the abstract model of each processor core, and obtain the multi-core project corresponding to the multi-core heterogeneous processor based on the generated code and the basic engineering framework of the multi-core heterogeneous processor.

[0096] After generating the abstract model of the multi-core heterogeneous processor, in order to make the multi-core heterogeneous processor actually run, it is also necessary to call the abstract model of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs to obtain the code generated by the abstract model of each processor core, and obtain the multi-core project corresponding to the multi-core heterogeneous processor based on the generated code and the basic engineering framework of the multi-core heterogeneous processor.

[0097] Specifically, the above step S160 may include:

[0098] For the abstract model of each processor core in the abstract model of a multi-core heterogeneous processor, build an algorithm model of a preset type in the abstract model, and integrate the algorithm model of the preset type with the module library corresponding to the category to which the processor core belongs to obtain an integrated model;

[0099] Call a preset code generation toolbox to parse each integrated model to obtain the code generated by each integrated model;

[0100] Integrate the code generated by each integrated model into the basic engineering frameworks of the respective processor cores included in the basic engineering framework of the multi-core heterogeneous processor to obtain a multi-core project corresponding to the multi-core heterogeneous processor.

[0101] For the abstract model of each processor core in the abstract model of a multi-core heterogeneous processor, build an algorithm model of a preset type in the abstract model. Among them, building an algorithm model of a preset type in the abstract model can be to build an algorithm model of a preset type in the abstract model through Simulink software, and the algorithm model of the preset type is an algorithm model for implementing a preset type of function.

[0102] In order to implement the function of the algorithm model of the preset type, it is also necessary to integrate the algorithm model of the preset type with the module library corresponding to the category to which the processor core belongs to obtain an integrated model.

[0103] After obtaining the integrated model, call a preset code generation toolbox to parse each integrated model to obtain the code generated by each integrated model. Since the code generation rules of the abstract models of various processor cores are written by developers, that is, pre-customized, therefore, the code generated by each integrated model obtained by parsing each integrated model can include the code of the algorithm model and the code of each communication module. Exemplarily, the preset code generation toolbox can be an EmbeddedCoder code generation toolbox.

[0104] Since in the embodiment of the present invention, by calling a preset code generation toolbox to parse each integrated model, the code generated by each integrated model is obtained, and there is no need to manually write code, which reduces the workload of developers.

[0105] After obtaining the code generated by each integrated model, MATLAB software can be used to integrate the code generated by each integrated model into the basic engineering frameworks of the respective processor cores included in the basic engineering framework of the multi-core heterogeneous processor to obtain a multi-core project corresponding to the multi-core heterogeneous processor. Among them, the multi-core project is a project that includes the basic engineering frameworks of multiple processor cores and the code generated by the integrated models corresponding to the abstract models of the respective processor cores.

[0106] At this time, the multi-core project corresponding to the generated multi-core heterogeneous processor is not only the basic project framework containing each processor core, but also the code generated from the integrated model corresponding to the abstract model of each processor core, which can truly run to implement various functions, and is the multi-core project of a complete multi-core heterogeneous processor.

[0107] As can be seen from the above, this embodiment can receive the basic models, model configuration scripts, and code generation rules of various processor cores in the multi-core heterogeneous processor written by developers according to the configuration file of the multi-core heterogeneous processor to be developed, and optimize the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores; receive the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores written by developers, and encapsulate the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate module libraries corresponding to various processor cores; receive the model development tools of various processor cores selected by developers and the tool usage order, and generate development toolchains corresponding to various processor cores according to the model development tools and tool usage order; receive the basic project frameworks of each processor core created by developers based on the development toolchains corresponding to various processor cores, and generate the basic project framework of the multi-core heterogeneous processor based on the basic project frameworks of each processor core; read the information in the configuration file, and generate the abstract model of the multi-core heterogeneous processor according to the information read, the abstract models of each processor core, and the model reference method; call the code generated from the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs to obtain the multi-core project corresponding to the multi-core heterogeneous processor. In the embodiment of the present invention, by having developers pre-write the basic models, model configuration scripts, and code generation rules of various processor cores in the multi-core heterogeneous processor, and modularizing complex embedded underlying drivers, inter-core communication, and external communication mechanisms, when developing a multi-core heterogeneous processor, directly call the model configuration scripts and code generation rules of various processor cores to optimize the basic models of various processor cores to generate abstract models of various processor cores, and then call the code generated from the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module library corresponding to the category to which each processor core belongs to obtain the multi-core project corresponding to the multi-core heterogeneous processor, without manual coding, reducing the workload of developers and improving efficiency.

[0108] Moreover, before developing the multi-core heterogeneous processor, complex embedded underlying drivers, inter-core communication, and external communication mechanisms have been modularized. During development, developers do not need to concern themselves with underlying development and can directly call the modules, which improves efficiency. Additionally, it avoids the occurrence of coding errors introduced during manual coding due to limitations in developers' experience or skills.

[0109] Furthermore, when using MATLAB software / Simulink software for development, since MATLAB software / Simulink software provides a graphical visualization environment, developers can continuously view the entire development process, making debugging convenient.

[0110] In addition, because the complex embedded underlying drivers, inter-core communication, and external communication mechanisms are modularized in the embodiments of the present invention, they can be debugged individually during debugging without the need to debug the entire multi-core heterogeneous processor, which improves efficiency.

[0111] In one implementation, after the above step S160, the above method for developing a model of a multi-core heterogeneous processor may further include:

[0112] Call the development toolchains corresponding to the categories to which each processor core belongs to compile each processor core in the multi-core project to obtain respective executable files corresponding to each processor core, and deploy the respective executable files to the corresponding processor cores and run them to generate operation results.

[0113] To ensure that the developed multi-core heterogeneous processor can truly operate and the operation results are accurate, it is also necessary to call the development toolchains corresponding to the categories to which each processor core belongs to compile each processor core in the multi-core project to obtain respective executable files corresponding to each processor core.

[0114] For example: Suppose the development toolchain corresponding to the category to which a certain processor core belongs is: compiler, linker. Then, calling the development toolchain corresponding to the category to which this processor core belongs to compile this processor core in the multi-core project to obtain the executable file corresponding to this processor core can be:

[0115] Compile the source code of this processor core through the compiler in the development toolchain corresponding to the category to which this processor core belongs to obtain an object file, and link the object file through the linker in the development toolchain corresponding to the category to which this processor core belongs to obtain the executable file corresponding to this processor core.

[0116] After obtaining the executable files corresponding to each processor core, deploy each executable file to the corresponding processor core and run it to generate a running result. After obtaining the running result, the developer compares the running result with the model simulation result. If the difference is small, it indicates that the running result of the heterogeneous multi-core processor developed by the model development method of the heterogeneous multi-core processor provided by the embodiments of the present invention is accurate.

[0117] Thus, each executable file can be deployed to the corresponding processor core simultaneously and run to generate a running result, avoiding deploying each executable file to the corresponding processor core one by one through manual coding in the related art, and improving the efficiency.

[0118] For the convenience of viewing, a specific embodiment is used below to introduce in detail a model development method for a heterogeneous multi-core processor provided by the present invention:

[0119] Figure 3 Another flow diagram of a model development method for a heterogeneous multi-core processor provided by the embodiments of the present invention is shown in Figure 3 :

[0120] 1. Module library, which is step S120 above.

[0121] 2. Basic engineering framework, which is step S140 above.

[0122] 3. Toolchain, which is step S130 above.

[0123] 4. Heterogeneous multi-core processor configuration file, which is to read the information in the configuration file in step S150 above.

[0124] 5. Abstract model of the heterogeneous multi-core processor, which is to generate the abstract model of the heterogeneous multi-core processor according to the information read, the abstract models of each processor core, and the model reference method in step S150 above.

[0125] 6. Integrated model, which is the abstract models of each processor core in the abstract model of the heterogeneous multi-core processor in steps S110 and S160 above. Build an algorithm model of a preset type in this abstract model, and integrate the algorithm model of the preset type with the module library corresponding to the category to which this processor core belongs to obtain the integrated model.

[0126] 7. Automatic code generation, which is to call a preset code generation toolbox to parse each integrated model in step S160 above to obtain the code generated by each integrated model.

[0127] 8. Multicore project, that is, in step S160 above, the code generated by each integrated model is integrated into the basic engineering frameworks of each processor core included in the basic engineering framework of the heterogeneous multi-core processor, so as to obtain the multi-core project corresponding to the heterogeneous multi-core processor.

[0128] 9. Executable files, that is, in the above, the development toolchains corresponding to the categories to which each processor core belongs are called to compile each processor core in the multi-core project, so as to obtain the executable files corresponding to each processor core.

[0129] 10. Deployment and operation, that is, in the above, each executable file is deployed to the corresponding processor core and run to generate a running result.

[0130] Corresponding to the above method embodiments, an embodiment of the present invention provides a model development device for a heterogeneous multi-core processor, as Figure 4 shown. The device may include:

[0131] An abstract model generation module 410 for various types of processor cores, configured to receive the basic models, model configuration scripts, and code generation rules of various types of processor cores in the heterogeneous multi-core processor written by a developer according to the configuration file of the heterogeneous multi-core processor to be developed, and optimize the basic models of various types of processor cores according to the model configuration scripts and code generation rules of various types of processor cores to generate abstract models of various types of processor cores;

[0132] A module library generation module 420, configured to receive the driver modules, inter-core communication modules, and external communication modules corresponding to various types of processor cores written by a developer, and encapsulate the driver modules, inter-core communication modules, and external communication modules corresponding to various types of processor cores to generate module libraries corresponding to various types of processor cores;

[0133] A development toolchain generation module 430, configured to receive the model development tools and tool usage sequences of various types of processor cores selected by a developer, and generate development toolchains corresponding to various types of processor cores according to the model development tools and tool usage sequences;

[0134] A basic engineering framework generation module 440, configured to receive the basic engineering frameworks of each processor core created by a developer based on the development toolchains corresponding to various types of processor cores, and generate the basic engineering framework of the heterogeneous multi-core processor based on the basic engineering frameworks of each processor core;

[0135] An abstract model generation module 450 for the heterogeneous multi-core processor, configured to read the information in the configuration file, and generate the abstract model of the heterogeneous multi-core processor according to the read information, the abstract models of each processor core, and the model reference method;

[0136] The multi-core engineering generation module 460 is configured to call the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module libraries corresponding to the categories to which each processor core belongs to obtain the code generated by the abstract models of each processor core, and obtain the multi-core engineering corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor.

[0137] The device in this embodiment can receive the basic models of various processor cores in the multi-core heterogeneous processor, model configuration scripts, and code generation rules written by developers according to the configuration file of the multi-core heterogeneous processor to be developed, and optimize the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores; receive the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores written by developers, and encapsulate the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate module libraries corresponding to various processor cores; receive the model development tools of various processor cores selected by developers and the tool usage order, and generate development toolchains corresponding to various processor cores according to the model development tools and tool usage order; receive the basic engineering frameworks of each processor core created by developers based on the development toolchains corresponding to various processor cores, and generate the basic engineering framework of the multi-core heterogeneous processor based on the basic engineering frameworks of each processor core; read the information in the configuration file, and generate the abstract model of the multi-core heterogeneous processor according to the read information, the abstract models of each processor core, and the model reference method; call the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module libraries corresponding to the categories to which each processor core belongs to obtain the code generated by the abstract models of each processor core, and obtain the multi-core engineering corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor. In the embodiment of the present invention, by having developers pre-write the basic models of various processor cores in the multi-core heterogeneous processor, model configuration scripts, and code generation rules, and modularize complex embedded underlying drivers, inter-core communication, and external communication mechanisms, when developing a multi-core heterogeneous processor, directly call the model configuration scripts and code generation rules of various processor cores to optimize the basic models of various processor cores to generate abstract models of various processor cores, and then call the abstract models of each processor core in the abstract model of the multi-core heterogeneous processor and the module libraries corresponding to the categories to which each processor core belongs to obtain the code generated by the abstract models of each processor core, and obtain the multi-core engineering corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor, eliminating the need for manual coding, reducing the workload of developers, and improving efficiency.

[0138] In another embodiment of the present invention, the abstract model generation module 410 for various types of processor cores may specifically be used for:

[0139] For each type of processor core, generate target code based on the code generation rules of this type of processor core, and optimize the basic model of this type of processor core according to the configuration items in the model configuration script of this type of processor core and the target code to generate the abstract model of this type of processor core.

[0140] In another embodiment of the present invention, when the type of the processor core is a digital signal processor DSP C66x processor core, the inter-core communication module corresponding to this type of processor core includes: an inter-core message queue module, and the external communication module corresponding to this type of processor core includes at least one of the following: a serial port module, an external memory interface EMIF module, an Ethernet communication module, and a serial high-speed SRIO module;

[0141] When the type of the processor core is a Xilinx ARM A53 processor core or a Xilinx ARM R5 processor core, the inter-core communication module corresponding to this type of processor core includes: a video direct memory access VDMA module, and the external communication module corresponding to this type of processor core includes at least one of the following: a video direct memory access VDMA module, an external memory interface EMIF module, and an Ethernet communication module.

[0142] In another embodiment of the present invention, the multi-core project generation module 460 may include:

[0143] An integrated model generation sub-module, which is used to build an algorithm model of a preset type in the abstract model for each processor core's abstract model in the abstract model of the multi-core heterogeneous processor, and integrate the algorithm model of the preset type with the module library corresponding to the category to which this processor core belongs to obtain an integrated model;

[0144] A code generation sub-module, which is used to call a preset code generation toolbox to parse each integrated model to obtain the code generated by each integrated model;

[0145] A multi-core project generation sub-module, which is used to integrate the code generated by each integrated model into the basic project frameworks of the respective processor cores included in the basic project framework of the multi-core heterogeneous processor to obtain the multi-core project corresponding to the multi-core heterogeneous processor.

[0146] In another embodiment of the present invention, the above-mentioned model development device for a multi-core heterogeneous processor further includes:

[0147] A deployment module, after obtaining the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the abstract model of the multi-core heterogeneous processor, calls the development toolchains corresponding to the categories to which each processor core belongs to compile each processor core in the multi-core project, obtains each executable file corresponding to each processor core, deploys each executable file to the corresponding processor core and runs to generate a running result.

[0148] The above device embodiment corresponds to the method embodiment and has the same technical effect as the method embodiment. For specific descriptions, please refer to the method embodiment. The device embodiment is obtained based on the method embodiment. For specific descriptions, please refer to the method embodiment section and will not be elaborated here.

[0149] Those of ordinary skill in the art can understand that the drawings are only schematic diagrams of one embodiment, and the modules or processes in the drawings are not necessarily essential for implementing the present invention.

[0150] Those of ordinary skill in the art can understand that the modules in the device in the embodiment can be distributed in the device of the embodiment according to the description of the embodiment, or can be correspondingly changed to be located in one or more devices different from this embodiment. The modules of the above embodiment can be combined into one module, or can be further split into multiple sub-modules.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for developing a model of a multi-core heterogeneous processor, characterized in that Including: Receiving the basic models of various processor cores in the heterogeneous multi-core processor, model configuration scripts, and code generation rules written by developers according to the configuration file of the heterogeneous multi-core processor to be developed, and optimizing the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores; Receiving the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores written by developers, and encapsulating the driver modules, inter-core communication modules, and external communication modules corresponding to various processor cores to generate a module library corresponding to various processor cores; Receiving the model development tools selected by developers and the tool usage order, and generating a development tool chain corresponding to various processor cores according to the model development tools and the tool usage order; Receiving the basic engineering frameworks of each processor core created by developers based on the development tool chain corresponding to various processor cores, and generating the basic engineering framework of the heterogeneous multi-core processor based on the basic engineering frameworks of each processor core; Reading the information in the configuration file, and generating the abstract model of the heterogeneous multi-core processor according to the read information, the abstract models of each processor core, and the model reference method; Invoking the abstract models of each processor core in the abstract model of the heterogeneous multi-core processor and the module library corresponding to the category to which each processor core belongs to obtain the code generated by the abstract models of each processor core, and obtaining the multi-core project corresponding to the heterogeneous multi-core processor according to the generated code and the basic engineering framework of the heterogeneous multi-core processor; The step of invoking the abstract models of each processor core in the abstract model of the heterogeneous multi-core processor and the module library corresponding to the category to which each processor core belongs to obtain the code generated by the abstract models of each processor core, and obtaining the multi-core project corresponding to the heterogeneous multi-core processor according to the generated code and the basic engineering framework of the heterogeneous multi-core processor includes: For the abstract model of each processor core in the abstract model of the heterogeneous multi-core processor, building a preset type of algorithm model in the abstract model, and integrating the preset type of algorithm model with the module library corresponding to the category to which the processor core belongs to obtain an integrated model; Invoking a preset code generation toolbox to parse each integrated model to obtain the code generated by each integrated model; Integrating the code generated by each integrated model into the basic engineering frameworks of each processor core included in the basic engineering framework of the heterogeneous multi-core processor to obtain the multi-core project corresponding to the heterogeneous multi-core processor.

2. The method according to claim 1, wherein, The step of optimizing the basic models of various processor cores according to the model configuration scripts and code generation rules of various processor cores to generate abstract models of various processor cores includes: For each type of processor core, target code is generated based on the code generation rules for that type of processor core, and the basic model of that type of processor core is optimized according to the configuration items in the model configuration script of that type of processor core and the target code to generate the abstract model of that type of processor core.

3. The method according to claim 1 or 2, characterized in that, When the type of the processor core is a digital signal processor DSP C66x processor core, the inter-core communication module corresponding to this type of processor core includes: an inter-core message queue module, and the external communication module corresponding to this type of processor core includes at least one of the following: a serial port module, an external memory interface EMIF module, an Ethernet communication module, and a serial high-speed SRIO module; When the type of the processor core is a Xilinx ARM A53 processor core or a Xilinx ARM R5 processor core, the inter-core communication module corresponding to this type of processor core includes: a video direct memory access VDMA module, and the external communication module corresponding to this type of processor core includes at least one of the following: a video direct memory access VDMA module, an external memory interface EMIF module, and an Ethernet communication module.

4. The method according to claim 1, characterized in that After the step of obtaining the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the basic engineering framework of the multi-core heterogeneous processor, the method further includes: Invoking the development toolchains corresponding to the categories to which each processor core belongs to compile each processor core in the multi-core project to obtain the executable files corresponding to each processor core, and deploying the executable files to the corresponding processor cores and running them to generate a running result.

5. A model development device for a multi-core heterogeneous processor, characterized in that, Including: An abstract model generation module for each type of processor core, which is configured to receive the basic models, model configuration scripts, and code generation rules of each type of processor core in the multi-core heterogeneous processor written by a developer according to the configuration file of the multi-core heterogeneous processor to be developed, and optimize the basic models of each type of processor core according to the model configuration scripts and code generation rules of each type of processor core to generate the abstract models of each type of processor core; A module library generation module, which is configured to receive the driver modules, inter-core communication modules, and external communication modules corresponding to each type of processor core written by a developer, and encapsulate the driver modules, inter-core communication modules, and external communication modules corresponding to each type of processor core to generate the module libraries corresponding to each type of processor core; A development toolchain generation module, which is configured to receive the model development tools and tool usage sequences selected by a developer for each type of processor core, and generate the development toolchains corresponding to each type of processor core according to the model development tools and tool usage sequences; A basic engineering framework generation module, which is configured to receive the basic engineering frameworks of each processor core created by a developer based on the development toolchains corresponding to each type of processor core, and generate the basic engineering framework of the multi-core heterogeneous processor based on the basic engineering frameworks of each processor core; The abstract model generation module of the heterogeneous multi-core processor is used to read the information in the configuration file and generate the abstract model of the heterogeneous multi-core processor according to the read information, the abstract models of the respective processor cores, and the model reference method; The multi-core project generation module is used to call the abstract models of the respective processor cores in the abstract model of the heterogeneous multi-core processor and the module libraries corresponding to the categories to which the respective processor cores belong to obtain the code generated by the abstract models of the respective processor cores, and obtain the multi-core project corresponding to the heterogeneous multi-core processor according to the generated code and the basic project framework of the heterogeneous multi-core processor; The multi-core project generation module includes: The integrated model generation sub-module is used to build an algorithm model of a preset type in the abstract model of each processor core in the abstract model of the heterogeneous multi-core processor, and integrate the algorithm model of the preset type with the module library corresponding to the category to which the processor core belongs to obtain an integrated model; The code generation sub-module is used to call a preset code generation toolbox to parse each integrated model to obtain the code generated by each integrated model; The multi-core project generation sub-module is used to integrate the code generated by each integrated model into the basic project frameworks of the respective processor cores included in the basic project framework of the heterogeneous multi-core processor to obtain the multi-core project corresponding to the heterogeneous multi-core processor.

6. The device according to claim 5, characterized in that, The abstract model generation module of each type of processor core is specifically used for: For each type of processor core, generate target code based on the code generation rule of the type of processor core, and optimize the basic model of the type of processor core according to the configuration items in the model configuration script of the type of processor core and the target code to generate the abstract model of the type of processor core.

7. The device according to claim 5 or 6, characterized in that, When the type of the processor core is the digital signal processor DSP C66x processor core, the inter-core communication module corresponding to this type of processor core includes: an inter-core message queue module, and the external communication module corresponding to this type of processor core includes at least one of the following: a serial port module, an external memory interface EMIF module, an Ethernet communication module, and a serial high-speed SRIO module; When the type of the processor core is the Xilinx ARM A53 processor core or the Xilinx ARM R5 processor core, the inter-core communication module corresponding to this type of processor core includes: a video direct memory access VDMA module, and the external communication module corresponding to this type of processor core includes at least one of the following: a video direct memory access VDMA module, an external memory interface EMIF module, and an Ethernet communication module.

8. The device according to claim 5, characterized in that, The device further includes: A deployment module, which is used to, after obtaining the multi-core project corresponding to the multi-core heterogeneous processor according to the generated code and the abstract model of the multi-core heterogeneous processor, call the development toolchains corresponding to the categories to which each processor core belongs to compile each processor core in the multi-core project to obtain respective executable files corresponding to each processor core, deploy the respective executable files to the corresponding processor cores and run to generate a running result.

Images