A cache-based data verification method, device and medium

Abstract

A cache-based data checking method, comprising: establishing, in the cache, second predetermined bytes of checking data for every first predetermined bytes of data; in response to data interaction with the cache, performing data checking according to the data involved in the data interaction and the corresponding checking data; through the cache-based data checking method, when data is stored in the cache, checking data is creatively established for data of a certain size, when data is input or output from the cache, data is checked according to the checking data, a checking bit field is added in the system bus, when data is transmitted to other terminals through the system bus, data is also checked according to the corresponding checking data, if data is abnormal, the way and reason of the abnormal data can be accurately located. In some cases, the abnormal data can be compensated through data reloading. The stability of system operation is improved.

Description

Technical Field

[0001] This invention belongs to the field of computer science, and specifically relates to a data verification method, device, and medium based on caching. Background Technology

[0002] In the high-end embedded field, with continuous advancements in manufacturing processes, the CPU clock speed of System-on-a-Chip (SoC) is constantly increasing. However, main memory, limited by cost and capacity, cannot keep up with the CPU's speed. Therefore, adding a cache between the CPU and main memory is a fundamental method for existing processors. However, in traditional implementations, when data errors occur, it's impossible to determine which specific addresses are problematic, or whether the error is in the cache or the memory itself, making it difficult to locate chip data errors. This can even lead to the same program running differently on different devices with different results. When tracing the problem, it's difficult to determine whether the issue stems from data anomalies stored in memory during program execution, data anomalies after being sent to the cache via the system bus, or even a failure during system bus transmission. Even when using other memory testing tools or other diagnostic tools to test the memory and cache, it's difficult to recreate the scenario where the problem occurred. In other words, facing randomly generated anomalies, subsequent testing methods cannot promptly and accurately determine which storage devices or terminal devices are responsible for the data errors or anomalies.

[0003] Therefore, an effective solution is urgently needed to address the above problems. Summary of the Invention

[0004] To address the above problems, this invention proposes a cache-based data verification method, comprising:

[0005] In the cache, a second predetermined byte of check data is created for every first predetermined byte of data;

[0006] In response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data.

[0007] In some embodiments of the present invention, the method further includes:

[0008] A parity bit field is added to the system bus, and the parity data is transmitted through the parity bit field.

[0009] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, including:

[0010] In response to writing data to the cache, the written data is validated based on the validation data of the written data;

[0011] In response to successful verification, the data is written to the cache;

[0012] In response to the verification failure, a data source error report is sent to the system based on the source of the data.

[0013] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, further comprising:

[0014] In response to reading data from the cache, the data is validated according to the validation data corresponding to the data in the cache, and the result of the validation is determined.

[0015] In response to a pass result from the verification, the data is read and sent to the corresponding data reading terminal via the system bus;

[0016] If the verification fails, a cache error report is sent to the system.

[0017] In some embodiments of the present invention, the method further includes

[0018] In response to the CPU writing data to the cache, the CPU calculates a second predetermined byte size corresponding to the first predetermined byte of data for each first predetermined byte of data, and sends the written data and its corresponding verification data to the cache via the system bus.

[0019] In some embodiments of the present invention, the method further includes:

[0020] In response to writing data from memory to the cache, a check is performed based on the data in memory and the check data corresponding to the data.

[0021] In response to the verification result, the data and its corresponding verification data are sent to the cache via the system bus;

[0022] If the verification result fails, a memory data error report is sent to the system.

[0023] In some embodiments of the present invention, the method further includes:

[0024] In response to the CPU reading data from the cache, the CPU verifies the read data and its corresponding check data.

[0025] If the verification result fails, a system bus error report is sent to the operating system.

[0026] In some embodiments of the present invention, the method further includes:

[0027] In response to the memory reading data from the cache, the memory controller of the memory verifies the data read from the memory and its corresponding verification data.

[0028] If the verification result fails, a system bus error report is sent to the operating system.

[0029] Another aspect of the present invention provides a computer device comprising:

[0030] At least one processor; and

[0031] A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of any of the methods described in the above embodiments.

[0032] Another aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the methods described in the above embodiments.

[0033] This invention proposes a cache-based data verification method. When storing data in the cache, it innovatively establishes verification data for a certain size of data. Data is verified against this verification data when entering or leaving the cache. Simultaneously, a verification bit field is added to the system bus. When data is transmitted to other terminals via the system bus, it is similarly verified against the corresponding verification data. If data anomalies are found, the method and cause of the anomaly can be accurately located. In some cases, data reloading can even compensate for the anomaly, thus improving system stability. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A flowchart illustrating an embodiment of a cache-based data verification method provided by this invention;

[0036] Figure 2A schematic diagram of the structure of a computer device provided in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the structure of a computer storage medium provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0039] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0040] like Figure 1 As shown, this invention proposes a cache-based data verification method, including:

[0041] Step S1: Create a second predetermined byte of check data in the cache for each first predetermined byte of data;

[0042] Step S2: In response to data interaction with the cache, perform data verification based on the data involved in the data interaction and its corresponding verification data.

[0043] In step S1, the data storage method is specified in the cache. The data stored in the cache is grouped into groups of 64 bytes each. At the same time, a corresponding 8-bit (1-byte) check data is established for each group of data. The check data and the corresponding group of data are calculated through a corresponding check algorithm to ensure unique correlation.

[0044] In step S2, when the CPU or memory reads or writes data from the cache, the data is written to the cache according to the format used to store the data in step S1 (i.e., an additional 1 byte of checksum data is added for every 64 bytes of data). The written data is then checked using the 1-byte checksum data. If the checksum is successful, the data is written to the cache. Similarly, when reading data from the cache, the read data is also checked using the corresponding checksum data. Reading from the cache is only allowed if the checksum passes.

[0045] It should be noted that the writing or reading of data into the cache disclosed in this embodiment of the invention refers to writing or reading data in groups of 64 bytes, along with the corresponding 1 byte (8 bits) of check data. This means that data is grouped into 64-byte groups to form 1 byte of check data before transmission and storage (in the cache). This means that data grouping and supplementation are possible; when the transmission task is relatively normal, data is transmitted and stored in groups of 64 bytes (rarely in cases of small data volumes). In cases of extremely small data volumes, where the data is less than 64 bytes, it is padded to 64 bytes using predetermined content, and then the 1 byte of check data is calculated from the padded 64 bytes.

[0046] In some embodiments of the present invention, the method further includes:

[0047] A parity bit field is added to the system bus, and the parity data is transmitted through the parity bit field.

[0048] In this embodiment, to facilitate data storage according to the predetermined format, a check bit field is added to the system bus, meaning that the transmitter checks the data simultaneously during transmission. Since check data must be transmitted along with the data on the system bus, the completion of each data transmission does not necessarily signify the completion of a transmission request. Specifically, when transmitting data on the system bus, if a transmission request involves a data address in the cache or memory, the address of the corresponding check data must be included. Furthermore, data transmission is considered complete only when the data at the data address and the check data at the check data address have been transmitted.

[0049] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, including:

[0050] In response to writing data to the cache, the written data is validated based on the validation data of the written data;

[0051] In response to successful verification, the data is written to the cache;

[0052] In response to the verification failure, a data source error report is sent to the system based on the source of the data.

[0053] In this embodiment, when writing data to the cache, the data to be written is obtained through the system bus. Before being stored in the cache, the obtained data to be written and its corresponding verification data are verified. If the verification passes, the data is written to the cache. If the verification fails, a data error report is reported to the system (operating system), and the address information on the system bus is also reported to the system. This is to indicate that the data error did not occur in the cache.

[0054] Specifically, data is retrieved from the system bus in 64-byte units, along with the corresponding checksum. Following the checksum generation algorithm, new checksum data is generated from these 64 bytes. The system then compares the newly generated checksum data with the received checksum data. If they match, the checksum passes and the data can be written to the cache. If they differ, the system reports a data verification failure to the operating system, along with traceable information such as the data's address on the bus.

[0055] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, further comprising:

[0056] In response to reading data from the cache, the data is validated according to the validation data corresponding to the data in the cache, and the result of the validation is determined.

[0057] In response to a pass result from the verification, the data is read and sent to the corresponding data reading terminal via the system bus;

[0058] If the verification fails, a cache error report is sent to the system.

[0059] In this embodiment, similar to the embodiments described above, if data is read from the cache, the data is verified according to the corresponding verification data before being sent to the bus. Similarly, a new verification data is calculated based on the verification data generation algorithm and compared with the verification data read from the cache. If they are the same, the verification passes; otherwise, the verification fails, and an error in the data read from the cache is promptly reported to the system.

[0060] In some embodiments of the present invention, the operating system is reported the address of the cache containing the error along with the error in the cache. The operating system can then mask the cache space where the error occurred as needed.

[0061] In some embodiments of the present invention, the operating system sends the blocked cache address to the cache controller to send the address space that needs to be blocked. When writing data to the corresponding address space, the corresponding data is simultaneously written to other cache space addresses in the form of a backup.

[0062] In some embodiments of the present invention, the method further includes

[0063] In response to the CPU writing data to the cache, the CPU calculates a second predetermined byte size corresponding to the first predetermined byte of data for each first predetermined byte of data, and sends the written data and its corresponding verification data to the cache via the system bus.

[0064] In this embodiment, if data is written from the CPU to the cache, the CPU generates 1 byte of checksum data in groups of 64 bytes, and then sends the 64 bytes of data along with the corresponding checksum data to the system bus. Specifically, according to the above-described invention, 1 byte of checksum data is always transmitted in the checksum field established in the system bus.

[0065] In some embodiments of the present invention, the method further includes:

[0066] In response to writing data from memory to the cache, a check is performed based on the data in memory and the check data corresponding to the data.

[0067] In response to the verification result, the data and its corresponding verification data are sent to the cache via the system bus;

[0068] If the verification result fails, a memory data error report is sent to the system.

[0069] In this embodiment, if data is written from memory to the cache, the data is validated when it is read from memory. If the validation is successful, the data and the corresponding validation data are sent to the cache via the system bus. If the validation fails, a report indicating an error in the data in memory is sent to the system.

[0070] In some embodiments of the present invention, if the memory type is memory with built-in verification, the reading of the corresponding data in the memory can be directly verified using the existing verification method of the memory controller. For example, with ECC memory, when reading data from memory, verification can be performed according to the ECC memory verification method.

[0071] In some embodiments of the present invention, the CRC checksum algorithm is used to verify the 64-byte data corresponding to the 1-byte checksum. If the memory is ECC memory, after verification in the ECC memory according to the ECC memory verification method, a new CRC checksum (according to the method of 1-byte checksum for 64-byte data) is generated by the memory controller and sent to the system bus.

[0072] In some embodiments of the present invention, if the memory also uses the CRC check algorithm, then before sending data to the cache on the system bus, the memory controller directly performs CRC check on the corresponding data in the memory. After the check passes, the 64 bytes of data and the 1 byte of check data are sent to the cache simultaneously through the system bus.

[0073] In some embodiments of the present invention, the method further includes:

[0074] In response to the CPU reading data from the cache, the CPU verifies the read data and its corresponding check data.

[0075] If the verification result fails, a system bus error report is sent to the operating system.

[0076] In this embodiment, if the CPU simply reads data from the cache, after reading the corresponding data, the CPU performs a checksum verification based on the received data and the corresponding checksum. If the verification fails, an error report is sent to the operating system to transmit the system bus. Since no error occurred when the data left the cache, the data error can be considered to have occurred during transmission.

[0077] In some embodiments of the present invention, the method further includes:

[0078] In response to the memory reading data from the cache, the memory controller of the memory verifies the data read from the memory and its corresponding verification data.

[0079] If the verification result fails, a system bus error report is sent to the operating system.

[0080] In this embodiment, if data is read from memory and the data read from memory is sent to the cache side via the system bus, the cache verifies the received data according to the data's verification data. If the verification fails, it sends a report to the operating system that the system bus data transmission has failed.

[0081] In addition, if the verification is successful, the data and the corresponding verification data can be directly stored in the cache.

[0082] This invention proposes a cache-based data verification method. While storing data in the cache, it innovatively establishes verification data for a certain size of data. Data is verified against this verification data when entering or leaving the cache. Furthermore, a verification bit field is added to the system bus. When data is transmitted to other terminals via the system bus, it is similarly verified against the corresponding verification data. If data anomalies are detected, the method and cause of the anomaly can be accurately identified. In some cases, data reloading can even compensate for the anomaly, thus improving system stability.

[0083] like Figure 2 As shown, another aspect of the present invention provides a computer device comprising:

[0084] At least one processor 21; and

[0085] Memory 22 stores computer instructions 23 that can be executed by the processor.

[0086] A cache-based data validation method includes:

[0087] In the cache, a second predetermined byte of check data is created for every first predetermined byte of data;

[0088] In response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data.

[0089] In some embodiments of the present invention, the method further includes:

[0090] A parity bit field is added to the system bus, and the parity data is transmitted through the parity bit field.

[0091] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, including:

[0092] In response to writing data to the cache, the written data is validated based on the validation data of the written data;

[0093] In response to successful verification, the data is written to the cache;

[0094] In response to the verification failure, a data source error report is sent to the system based on the source of the data.

[0095] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, further comprising:

[0096] In response to reading data from the cache, the data is validated according to the validation data corresponding to the data in the cache, and the result of the validation is determined.

[0097] In response to a pass result from the verification, the data is read and sent to the corresponding data reading terminal via the system bus;

[0098] If the verification fails, a cache error report is sent to the system.

[0099] In some embodiments of the present invention, the method further includes

[0100] In response to the CPU writing data to the cache, the CPU calculates a second predetermined byte size corresponding to the first predetermined byte of data for each first predetermined byte of data, and sends the written data and its corresponding verification data to the cache via the system bus.

[0101] In some embodiments of the present invention, the method further includes:

[0102] In response to writing data from memory to the cache, a check is performed based on the data in memory and the check data corresponding to the data.

[0103] In response to the verification result, the data and its corresponding verification data are sent to the cache via the system bus;

[0104] If the verification result fails, a memory data error report is sent to the system.

[0105] In some embodiments of the present invention, the method further includes:

[0106] In response to the CPU reading data from the cache, the CPU verifies the read data and its corresponding check data.

[0107] If the verification result fails, a system bus error report is sent to the operating system.

[0108] In some embodiments of the present invention, the method further includes:

[0109] In response to the memory reading data from the cache, the memory controller of the memory verifies the data read from the memory and its corresponding verification data.

[0110] If the verification result fails, a system bus error report is sent to the operating system.

[0111] like Figure 3As shown, another aspect of the present invention provides a computer-readable storage medium 401, which stores a computer program 402. When executed by a processor, the computer program implements a cache-based data verification method, comprising:

[0112] In the cache, a second predetermined byte of check data is created for every first predetermined byte of data;

[0113] In response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data.

[0114] In some embodiments of the present invention, the method further includes:

[0115] A parity bit field is added to the system bus, and the parity data is transmitted through the parity bit field.

[0116] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, including:

[0117] In response to writing data to the cache, the written data is validated based on the validation data of the written data;

[0118] In response to successful verification, the data is written to the cache;

[0119] In response to the verification failure, a data source error report is sent to the system based on the source of the data.

[0120] In some embodiments of the present invention, in response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data, further comprising:

[0121] In response to reading data from the cache, the data is validated according to the validation data corresponding to the data in the cache, and the result of the validation is determined.

[0122] In response to a pass result from the verification, the data is read and sent to the corresponding data reading terminal via the system bus;

[0123] If the verification fails, a cache error report is sent to the system.

[0124] In some embodiments of the present invention, the method further includes

[0125] In response to the CPU writing data to the cache, the CPU calculates a second predetermined byte size corresponding to the first predetermined byte of data for each first predetermined byte of data, and sends the written data and its corresponding verification data to the cache via the system bus.

[0126] In some embodiments of the present invention, the method further includes:

[0127] In response to writing data from memory to the cache, a check is performed based on the data in memory and the check data corresponding to the data.

[0128] In response to the verification result, the data and its corresponding verification data are sent to the cache via the system bus;

[0129] If the verification result fails, a memory data error report is sent to the system.

[0130] In some embodiments of the present invention, the method further includes:

[0131] In response to the CPU reading data from the cache, the CPU verifies the read data and its corresponding check data.

[0132] If the verification result fails, a system bus error report is sent to the operating system.

[0133] In some embodiments of the present invention, the method further includes:

[0134] In response to the memory reading data from the cache, the memory controller of the memory verifies the data read from the memory and its corresponding verification data.

[0135] If the verification result fails, a system bus error report is sent to the operating system.

[0136] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The embodiments of the computer program can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0137] Furthermore, typically, the devices and equipment disclosed in the embodiments of this invention can be various electronic terminal devices, such as mobile phones, personal digital assistants (PDAs), tablet computers (PADs), smart TVs, etc., or they can be large terminal devices, such as servers. Therefore, the scope of protection disclosed in the embodiments of this invention should not be limited to a specific type of device or equipment. The client disclosed in the embodiments of this invention can be applied to any of the above-mentioned electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.

[0138] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0139] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0140] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM may be available in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0141] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of the various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0142] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0143] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

Claims

1. A data verification method based on caching, characterized in that, include: In the cache, a second predetermined byte of check data is created for every first predetermined byte of data; In response to data interaction with the cache, data verification is performed based on the data involved in the data interaction and its corresponding verification data; The step of responding to data interaction with the cache and performing data verification based on the data involved in the data interaction and its corresponding verification data includes: In response to writing data to the cache, the written data is validated based on the validation data of the written data; In response to successful verification, the data is written to the cache; In response to the verification failure, a data source error report is sent to the system based on the source of the data; In response to reading data from the cache, the data is validated according to the validation data corresponding to the data in the cache, and the result of the validation is determined. In response to a pass result from the verification, the data is read and sent to the corresponding data reading terminal via the system bus; If the verification result is a failure, a cache error report is sent to the system; In response to the memory reading data from the cache, the memory controller of the memory verifies the data read from the memory and its corresponding verification data. If the verification result fails, a system bus error report is sent to the operating system.

2. The method according to claim 1, characterized in that, Also includes: A parity bit field is added to the system bus, and the parity data is transmitted through the parity bit field.

3. The method according to claim 1, characterized in that, Also includes In response to the CPU writing data to the cache, the CPU calculates a second predetermined byte size corresponding to the first predetermined byte of data for each first predetermined byte of data, and sends the written data and its corresponding verification data to the cache via the system bus.

4. The method according to claim 1, characterized in that, Also includes: In response to writing data from memory to the cache, a check is performed based on the data in memory and the check data corresponding to the data. In response to the verification result, the data and its corresponding verification data are sent to the cache via the system bus; If the verification result fails, a memory data error report is sent to the system.

5. The method according to claim 1, characterized in that, Also includes: In response to the CPU reading data from the cache, the CPU verifies the read data and its corresponding check data. If the verification result fails, a system bus error report is sent to the operating system.

6. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-5.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-5.

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