Circuit schematic detection method, device, terminal equipment and storage medium

Abstract

The present invention discloses a detection method of a circuit schematic diagram, comprising: obtaining a circuit schematic diagram to be detected, the circuit schematic diagram to be detected includes a plurality of network pins and a plurality of pin identifiers corresponding to the network pins; determining a target network pin from the plurality of network pins; obtaining a first pin identifier of the target network pin and a second pin identifier of the target network pin; and obtaining a detection result of the circuit schematic diagram to be detected according to the first pin identifier and the second pin identifier. The present invention also discloses a detection device, a terminal device, and a storage medium for a circuit schematic diagram. Using the method of the present invention, it is not necessary for a technician to perform detection manually, which greatly reduces the detection time and improves the detection efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit detection, and in particular to a detection method, device, terminal equipment and storage medium for a circuit schematic. Background Art

[0002] Currently, circuit schematics are drawn through auxiliary software, and then technicians manually check whether the network pins in the circuit schematics are connected normally.

[0003] However, the existing circuit schematics include many differential networks and communication transceiver networks. When technicians manually detect each network pin in the circuit schematic, the detection speed of the network pins is slow, resulting in low detection efficiency of the circuit schematic. Summary of the invention

[0004] The main purpose of the present invention is to provide a circuit schematic detection method, device, terminal equipment and storage medium, aiming to solve the technical problem in the prior art that the detection speed of network pins is slow, resulting in low detection efficiency of circuit schematics.

[0005] To achieve the above object, the present invention provides a circuit schematic detection method for terminal equipment, the method comprising the following steps:

[0006] Acquire a schematic diagram of a circuit to be detected, wherein the schematic diagram to be detected includes a plurality of network pins and a plurality of pin identifiers corresponding to the network pins;

[0007] Determining a target network pin from among the plurality of network pins;

[0008] Obtain a first pin identifier of a target network pin and a second pin identifier of the target network pin;

[0009] A detection result of the circuit schematic to be detected is obtained according to the first pin identifier and the second pin identifier.

[0010] Optionally, an initial circuit schematic diagram is drawn according to the target circuit, wherein the initial circuit schematic diagram includes a plurality of the network pins and pin identifiers corresponding to the plurality of the network pins;

[0011] Determine the target network connection in the initial circuit schematic diagram;

[0012] Generate a first pin identifier and a second pin identifier according to the target network connection and a preset naming rule;

[0013] The target network pins of the target network connection are marked by using the first pin identifier and the second pin identifier to obtain the schematic diagram of the circuit to be detected.

[0014] Optionally, the step of obtaining a detection result of the circuit schematic to be detected according to the first pin identifier and the second pin identifier includes:

[0015] According to the first pin identifier, obtaining a detection pin identifier corresponding to the second pin identifier;

[0016] A detection result of the circuit schematic to be detected is obtained according to the detection pin identifier and the second pin identifier.

[0017] Optionally, the step of obtaining a detection pin identifier corresponding to the second pin identifier according to the first pin identifier includes:

[0018] According to the first pin identifier and the preset naming rule, a detection pin identifier corresponding to the second pin identifier is obtained.

[0019] Optionally, the detection pin identifier includes multiple ones; the step of obtaining the detection result of the circuit schematic to be detected according to the detection pin identifier and the second pin identifier:

[0020] Determining whether the second pin identifier matches a plurality of the detection pin identifiers;

[0021] If yes, then a normal detection result of the circuit schematic to be detected is obtained, or,

[0022] If not, a detection result indicating that the circuit schematic to be detected is abnormal is obtained.

[0023] Optionally, the first pin identifier includes one of a differential network positive terminal identifier, a differential network negative terminal identifier, a communication network sending terminal identifier, and a communication network receiving terminal identifier.

[0024] Optionally, the differential network positive terminal identifier includes at least one of DP, P, +, TXP and RXP, the differential network negative terminal identifier includes at least one of DN, N, -, TXN and RXN, the communication network transmitting end identifier includes at least one of _TX, TX and TXD, and the communication network receiving end identifier includes at least one of _RX, RX and RXD.

[0025] In addition, to achieve the above-mentioned purpose, the present invention also proposes a circuit schematic detection device for terminal equipment, the device comprising:

[0026] A diagram acquisition module, used to acquire a schematic diagram of a circuit to be detected, wherein the schematic diagram to be detected includes a plurality of network pins and a plurality of pin identifiers corresponding to the network pins;

[0027] A determination module, used to determine a target network pin from the plurality of network pins;

[0028] An identification acquisition module, used to acquire a first pin identification of a target network pin and a second pin identification of the target network pin;

[0029] The obtaining module is used to obtain the detection result of the circuit schematic to be detected according to the first pin identifier and the second pin identifier.

[0030] In addition, to achieve the above-mentioned purpose, the present invention also proposes a terminal device, which includes: a memory, a processor, and a circuit schematic detection program stored in the memory and running on the processor, and when the detection program of the circuit schematic to be detected is executed by the processor, the steps of the circuit schematic detection method described in any one of the above items are implemented.

[0031] In addition, to achieve the above-mentioned purpose, the present invention also proposes a storage medium, on which a circuit schematic detection program is stored. When the detection program of the circuit schematic to be detected is executed by a processor, the steps of the circuit schematic detection method described in any of the above items are implemented.

[0032] The technical solution of the present invention proposes a method for detecting a circuit schematic diagram, including: obtaining a circuit schematic diagram to be detected, the schematic diagram to be detected includes multiple network pins and multiple pin identifiers corresponding to the network pins; determining a target network pin from the multiple network pins; obtaining a first pin identifier of the target network pin and a second pin identifier of the target network pin; and obtaining a detection result of the circuit schematic diagram to be detected based on the first pin identifier and the second pin identifier.

[0033] In the existing method, the technician manually determines the network pins that need to be detected, and manually checks whether the network pins are connected normally. The manual detection of the network pins is slow, resulting in low detection efficiency of the circuit schematic. Using the method of the present invention, the terminal device determines the target network pins that need to be detected in the circuit schematic to be detected, and automatically obtains the detection result of the circuit schematic to be detected based on the first pin identifier and the second pin identifier of the target network pin, without the need for the technician to manually perform the detection, which greatly reduces the detection time and improves the detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0035] Figure 1A schematic diagram of the structure of a terminal device in a hardware operating environment involved in an embodiment of the present invention;

[0036] Figure 2 It is a schematic flow chart of a first embodiment of a method for detecting a circuit schematic diagram of the present invention;

[0037] Figure 3 It is a structural block diagram of the first embodiment of the detection device of the circuit principle diagram of the present invention.

[0038] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Reference Figure 1 , Figure 1 A schematic diagram of the terminal device structure of the hardware operating environment involved in the embodiment of the present invention.

[0041] Typically, the terminal device includes: at least one processor 301, a memory 302, and a circuit schematic detection program stored in the memory and executable on the processor, wherein the circuit schematic detection program to be detected is configured to implement the steps of the circuit schematic detection method as described above.

[0042] The processor 301 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 301 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 301 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 301 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. The processor 301 may also include an AI (Artificial Intelligence) processor, which is used to process the detection method operation related to the circuit schematic diagram, so that the detection method model of the circuit schematic diagram can be trained and learned autonomously to improve efficiency and accuracy.

[0043] The memory 302 may include one or more storage media, which may be non-transitory. The memory 302 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory storage medium in the memory 302 is used to store at least one instruction, which is used to be executed by the processor 301 to implement the detection method of the circuit schematic diagram provided in the method embodiment of the present application.

[0044] In some embodiments, the terminal may further optionally include: a communication interface 303 and at least one peripheral device. The processor 301, the memory 302 and the communication interface 303 may be connected via a bus or a signal line. Each peripheral device may be connected to the communication interface 303 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit 304, a display screen 305 and a power supply 306.

[0045] The communication interface 303 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 301 and the memory 302. In some embodiments, the processor 301, the memory 302, and the communication interface 303 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 301, the memory 302, and the communication interface 303 may be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0046] The radio frequency circuit 304 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuit 304 communicates with the communication network and other communication devices through electromagnetic signals. The radio frequency circuit 304 converts the electrical signal into an electromagnetic signal for transmission, or converts the received electromagnetic signal into an electrical signal. Optionally, the radio frequency circuit 304 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The radio frequency circuit 304 can communicate with other terminals through at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: a metropolitan area network, various generations of mobile communication networks (2G, 3G, 4G and 5G), a wireless local area network and / or a WiFi (Wireless Fidelity) network. In some embodiments, the radio frequency circuit 304 may also include circuits related to NFC (Near Field Communication), which is not limited in this application.

[0047] The display screen 305 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen 305 is a touch display screen, the display screen 305 also has the ability to collect touch signals on the surface or above the surface of the display screen 305. The touch signal can be input to the processor 301 as a control signal for processing. At this time, the display screen 305 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 305 can be one, the front panel of the electronic device; in other embodiments, the display screen 305 can be at least two, respectively arranged on different surfaces of the electronic device or in a folding design; in some further embodiments, the display screen 305 can be a flexible display screen, arranged on a curved surface or a folding surface of the electronic device. Even, the display screen 305 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 305 can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode).

[0048] The power supply 306 is used to power various components in the electronic device. The power supply 306 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 306 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0049] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the terminal device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0050] In addition, an embodiment of the present invention further proposes a storage medium, on which a detection program of a circuit schematic is stored, and when the detection program of the circuit schematic to be detected is executed by a processor, the steps of the detection method of the circuit schematic described above are implemented. Therefore, it will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the storage medium embodiment involved in this application, please refer to the description of the method embodiment of this application. As an example, the program instructions can be deployed to be executed on a terminal device, or on multiple terminal devices located at one location, or on multiple terminal devices distributed at multiple locations and interconnected by a communication network.

[0051] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the above-mentioned program can be stored in a storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the above-mentioned storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0052] Based on the above hardware structure, an embodiment of the circuit schematic detection method of the present invention is proposed.

[0053] Reference Figure 2 , Figure 2 The present invention is a schematic flow chart of a first embodiment of a method for detecting a circuit schematic diagram of the present invention, wherein the method comprises the following steps:

[0054] Step S11: obtaining a schematic diagram of a circuit to be detected, wherein the schematic diagram to be detected includes a plurality of network pins and a plurality of pin identifiers corresponding to the network pins.

[0055] Step S12: determining a target network pin from the plurality of network pins.

[0056] Step S13: Acquire a first pin identifier of a target network pin and a second pin identifier of the target network pin.

[0057] It should be noted that the executor of the present invention is a terminal device, which is installed with a circuit schematic detection program. When the terminal device executes the circuit schematic detection program, the steps of the circuit schematic detection method of the present invention are implemented.

[0058] The schematic diagram of the circuit to be tested is the schematic diagram of the circuit to be tested. The circuit schematic diagram may correspond to a target circuit, which is an actual circuit. According to the target circuit, the schematic diagram of the circuit to be tested is drawn using software such as EDA.

[0059] Specifically, before the step of obtaining the schematic diagram of the circuit to be detected, the method also includes: drawing an initial circuit schematic diagram according to the target circuit, the initial circuit schematic diagram including multiple network pins and pin identifiers corresponding to the multiple network pins; determining the target network connection in the initial circuit schematic diagram; generating a first pin identifier and a second pin identifier according to the target network connection and a preset naming rule; and marking the target network pins of the target network connection using the first pin identifier and the second pin identifier to obtain the schematic diagram of the circuit to be detected.

[0060] Directly use drawing software (such as EDA) to draw the circuit schematic of the target circuit to obtain an initial circuit schematic, which includes multiple network connections, one network connection corresponds to two network pins, multiple network connections correspond to multiple network pins, multiple network pins correspond to multiple pin identifiers, and one network pin corresponds to one pin identifier.

[0061] The target network connection is a part of multiple network connections in the initial circuit schematic diagram. The target network connection may include multiple target network connections. Each target network connection has two target network pins: a first network pin and a second network pin. The pin identifier of the first network pin is a first pin identifier, and the pin identifier of the second network pin is a second pin identifier.

[0062] For example, the target network connection is the network connection corresponding to the communication network sending end and the communication network receiving end. When the first pin identifier is the pin identifier of the communication network sending end, the second pin identifier is the pin identifier of the communication network receiving end. When the second pin identifier is the pin identifier of the communication network sending end, the first pin identifier is the pin identifier of the communication network receiving end. The target network connection is the network connection corresponding to the differential network positive end and the differential network negative end. When the first pin identifier is the pin identifier of the differential network positive end, the second pin identifier is the pin identifier of the differential network negative end. When the first pin identifier is the pin identifier of the differential network negative end, the second pin identifier is the pin identifier of the differential network positive end.

[0063] It is necessary to determine the target network connection in the initial circuit schematic. In the present invention, the target network connection usually includes a differential network and a communication network, that is, the network connections corresponding to the four network pins of the differential network positive terminal, the differential network negative terminal, the communication network transmitting terminal and the communication network receiving terminal are all target network connections, that is, for the initial circuit schematic, when the differential network is included, the network connections corresponding to the differential network positive terminal and the differential network negative terminal need to be determined as the target network connections, and when the initial circuit schematic also includes the communication network, the network connections corresponding to the communication network transmitting terminal and the communication network receiving terminal need to be determined as the target network connections.

[0064] The first pin identifier may be generated by drawing software according to the target network connection and a preset naming rule, wherein the preset naming rule is as follows:

[0065] Add at least one of the keywords "DP, P, +, TXP and RXP" to the positive end of the differential network to obtain the corresponding first pin identification; add at least one of the keywords "DN, N, -, TXN and RXN" to the negative end of the differential network to obtain the corresponding first pin identification; add at least one of the keywords "_TX, TX and TXD" to the transmitting end of the communication network to obtain the corresponding first pin identification; add at least one of the keywords "_RX, RX and RXD" to the receiving end of the communication network to obtain the corresponding first pin identification.

[0066] The steps for obtaining the second pin identifier refer to the steps for obtaining the first pin identifier, and will not be repeated. It is understandable that the above preset naming rules are only examples, and users can add other legal keywords based on needs and in accordance with industry standards to obtain the corresponding target network connection identifier, and the present invention does not limit this.

[0067] After determining the target network connection, the first pin identifier and the second pin identifier, the first pin identifier and the second pin identifier are added to the corresponding network pins in the initial circuit schematic diagram to obtain the circuit schematic diagram to be detected.

[0068] Step S14: obtaining a detection result of the circuit schematic to be detected according to the first pin identifier and the second pin identifier.

[0069] After determining the first pin identifier and the second pin identifier, the detection result of the target network connection is obtained using the first pin identifier and the second pin identifier, and the detection result of the circuit schematic to be detected is obtained according to the detection result of the target network connection.

[0070] The detection result of the target network connection includes a target network connection error or a target network connection correct connection. When the target network connection is incorrectly connected, the detection result of the circuit schematic to be detected is that there is an incorrect network connection in the circuit schematic to be detected. When the target network connection is correctly connected, the detection result of the circuit schematic to be detected is that there is no incorrect network connection in the circuit schematic to be detected.

[0071] When there are multiple target network connections, none of the multiple target network connections have connection errors, and the detection result of the circuit schematic to be detected is that there are no network connections with connection errors in the circuit schematic to be detected; when there are one or more target network connections with connection errors among the multiple target network connections, the detection result of the circuit schematic to be detected is that there are network connections with connection errors in the circuit schematic to be detected.

[0072] Further, the step of obtaining the detection result of the circuit schematic diagram to be detected according to the first pin identifier and the second pin identifier includes: obtaining the detection pin identifier corresponding to the second pin identifier according to the first pin identifier; obtaining the detection result of the circuit schematic diagram to be detected according to the detection pin identifier and the second pin identifier. Wherein, the step of obtaining the detection pin identifier corresponding to the second pin identifier according to the first pin identifier includes: obtaining the detection pin identifier corresponding to the second pin identifier according to the first pin identifier and the preset naming rule.

[0073] Specifically, the detection pin identifier includes multiple ones; the step of obtaining the detection result of the circuit schematic to be detected based on the detection pin identifier and the second pin identifier is: judging whether the second pin identifier matches the multiple detection pin identifiers; if so, obtaining the normal detection result of the circuit schematic to be detected, or, if not, obtaining the abnormal detection result of the circuit schematic to be detected.

[0074] For any target network connection, the corresponding network pins include two combinations: a combination of a differential network positive terminal and a differential network negative terminal, and a combination of a communication network sending terminal and a communication network receiving terminal.

[0075] Based on the above description, the pin identifier of the first network pin of the target network connection is the first pin identifier. According to the first pin identifier, it can be known whether the target network connection is a differential network or a communication network; then according to the known target network connection and the above-mentioned preset naming rules, the correct pin identifier of the second network pin of the target network connection can be determined-the detection pin identifier, and then the detection result of the circuit schematic to be detected is obtained according to the second pin identifier of the second network pin obtained in the circuit schematic to be detected and the above-mentioned detection pin identifier.

[0076] The second pin identifier matches the plurality of detection pin identifiers, which may mean that the plurality of detection pin identifiers include the second pin identifier.

[0077] For example, the first pin is identified as TXP, the second pin is identified as DN, and the target network connection is determined to be a differential network. At the same time, the corresponding detection pin identification of the second network pin is DN, N, -, TXN and RXN, and then it is determined that the second pin identification matches the detection pin identification, thereby determining that the target network connection is correctly connected.

[0078] For example, when the first pin identifier includes the positive terminal identifier of the differential network, the obtained detection pin identifier includes DN, N, -, TXN and RXNP, and then it is determined whether the second pin identifier is included in DN, N, -, TXN and RXN. If not, the second pin identifier does not match multiple detection pin identifiers; if so, the second pin identifier matches multiple detection pin identifiers.

[0079] Similarly, when the first pin identifier includes the negative terminal identifier of the differential network, the obtained detection pin identifier includes DP, P, +, TXP and RXP, and then it is determined whether the second pin identifier is included in DP, P, +, TXP and RXP. If not, the second pin identifier does not match multiple detection pin identifiers; if so, the second pin identifier matches multiple detection pin identifiers.

[0080] When the first pin identifier includes the communication network transmitting end identifier, the obtained detection pin identifier includes _RX, RX and RXD, and then it is determined whether the second pin identifier is included in _RX, RX and RXD. If not, the second pin identifier does not match multiple detection pin identifiers; if so, the second pin identifier matches multiple detection pin identifiers.

[0081] When the first pin identifier includes the communication network receiving end identifier, the obtained detection pin identifier includes _TX, TX and TXD, and then it is determined whether the second pin identifier is included in _TX, TX and TXD. If not, the second pin identifier does not match multiple detection pin identifiers; if so, the second pin identifier matches multiple detection pin identifiers.

[0082] When the detection result is that the schematic diagram of the circuit to be detected is abnormal, it means that the target network connection is incorrectly connected. The detection result may also include the first pin identifier and the second pin identifier of the specific target network connection, and output the detection result so that the user can quickly find the incorrectly connected target network connection in the schematic diagram of the circuit to be detected.

[0083] The technical solution of the present invention proposes a method for detecting a circuit schematic diagram, including: obtaining a circuit schematic diagram to be detected, the schematic diagram to be detected includes multiple network pins and multiple pin identifiers corresponding to the network pins; determining a target network pin from the multiple network pins; obtaining a first pin identifier of the target network pin and a second pin identifier of the target network pin; and obtaining a detection result of the circuit schematic diagram to be detected based on the first pin identifier and the second pin identifier.

[0084] In the existing method, the technician manually determines the network pins that need to be detected, and manually checks whether the network pins are connected normally. The manual detection of the network pins is slow, resulting in low detection efficiency of the circuit schematic. Using the method of the present invention, the terminal device determines the target network pins that need to be detected in the circuit schematic to be detected, and automatically obtains the detection result of the circuit schematic to be detected based on the first pin identifier and the second pin identifier of the target network pin, without the need for the technician to manually perform the detection, which greatly reduces the detection time and improves the detection efficiency.

[0085] Reference Figure 3 , Figure 3 This is a structural block diagram of a first embodiment of a detection device for a circuit schematic diagram of the present invention, the device is used in a terminal device, based on the same inventive concept as the above embodiment, the device comprises:

[0086] A diagram acquisition module 10, used to acquire a schematic diagram of a circuit to be detected, wherein the schematic diagram to be detected includes a plurality of network pins and a plurality of pin identifiers corresponding to the network pins;

[0087] A determination module 20, configured to determine a target network pin from among the plurality of network pins;

[0088] An identification acquisition module 30, used to acquire a first pin identification of a target network pin and a second pin identification of the target network pin;

[0089] The obtaining module 40 is used to obtain the detection result of the circuit schematic to be detected according to the first pin identifier and the second pin identifier.

[0090] It should be noted that, since the steps executed by the device of this embodiment are the same as the steps of the aforementioned method embodiment, its specific implementation method and the technical effects that can be achieved can refer to the aforementioned embodiment and will not be repeated here.

[0091] The above descriptions are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A method for detecting a circuit schematic diagram, characterized in that: For a terminal device, the method comprises the following steps: Obtaining a schematic diagram of a circuit to be detected, wherein the schematic diagram of the circuit to be detected includes a plurality of network pins and a plurality of pin identifiers corresponding to the network pins; Determine a target network pin from the plurality of network pins, the target network pin being one of two network pins of a network connection in the schematic diagram of the circuit to be detected, the network connection being a network connection corresponding to a differential network positive terminal and a differential network negative terminal, and / or a network connection corresponding to a communication network transmitting end and a communication network receiving end; Obtain a first pin identifier of a target network pin and a second pin identifier of the target network pin; Obtaining a detection result of the circuit schematic to be detected according to the first pin identifier and the second pin identifier; The step of obtaining the detection result of the circuit schematic to be detected according to the first pin identifier and the second pin identifier comprises: According to the first pin identifier and a preset naming rule, obtaining a detection pin identifier corresponding to the second pin identifier; Obtaining a detection result of the circuit schematic to be detected according to a match between the detection pin identifier and the second pin identifier; The detection pin identifier is a correct pin identifier of the second pin identifier, and the detection pin identifier includes a plurality of pin identifiers; the step of obtaining the detection result of the circuit schematic to be detected according to the matching of the detection pin identifier and the second pin identifier includes: Determining whether the plurality of detection pin identifiers include the second pin identifier; If yes, then obtaining a test result that the circuit schematic diagram to be tested is normal; If not, a detection result indicating that the circuit schematic to be detected is abnormal is obtained.

2. The method according to claim 1, characterized in that Before the step of obtaining the schematic diagram of the circuit to be detected, the method further includes: According to the target circuit, an initial circuit schematic diagram is drawn, wherein the initial circuit schematic diagram includes a plurality of the network pins and pin identifiers corresponding to the plurality of the network pins; Determine the target network connection in the initial circuit schematic diagram; Generate a first pin identifier and a second pin identifier according to the target network connection and a preset naming rule; The target network pins of the target network connection are marked by using the first pin identifier and the second pin identifier to obtain the schematic diagram of the circuit to be detected.

3. The method according to claim 2, characterized in that The first pin identifier includes one of a differential network positive terminal identifier, a differential network negative terminal identifier, a communication network sending terminal identifier, and a communication network receiving terminal identifier.

4. The method according to claim 3, characterized in that The differential network positive terminal identifier includes at least one of DP, P, +, TXP and RXP, the differential network negative terminal identifier includes at least one of DN, N, -, TXN and RXN, the communication network transmitting end identifier includes at least one of _TX, TX and TXD, and the communication network receiving end identifier includes at least one of _RX, RX and RXD.

5. A circuit schematic detection device, characterized in that: For terminal equipment, the device comprises: A diagram acquisition module, used to acquire a schematic diagram of a circuit to be detected, wherein the schematic diagram of the circuit to be detected includes a plurality of network pins and a plurality of pin identifiers corresponding to the network pins; A determination module, used to determine a target network pin from the plurality of network pins, wherein the target network pin is one of two network pins of a network connection in the schematic diagram of the circuit to be detected, wherein the network connection is a network connection corresponding to a positive terminal of a differential network and a negative terminal of a differential network, and / or a network connection corresponding to a transmitting end of a communication network and a receiving end of a communication network; An identification acquisition module, used to acquire a first pin identification of a target network pin and a second pin identification of the target network pin; An obtaining module, used for obtaining a detection result of the circuit schematic to be detected according to the first pin identifier and the second pin identifier; The obtaining module is further used to obtain a detection pin identifier corresponding to the second pin identifier according to the first pin identifier and a preset naming rule; and obtain a detection result of the circuit schematic to be detected according to a match between the detection pin identifier and the second pin identifier; The detection pin identifier is the correct pin identifier of the second pin identifier, and the detection pin identifiers include multiple ones; the acquisition module is also used to determine whether the second pin identifier is included in the multiple detection pin identifiers; if so, the normal detection result of the schematic diagram of the circuit to be detected is obtained; if not, the abnormal detection result of the schematic diagram of the circuit to be detected is obtained.

6. A terminal device, characterized in that: The terminal device includes: a memory, a processor, and a circuit schematic detection program stored in the memory and running on the processor. When the circuit schematic detection program is executed by the processor, the steps of the circuit schematic detection method as described in any one of claims 1 to 4 are implemented.

7. A storage medium, characterized in that: The storage medium stores a circuit schematic detection program, and when the circuit schematic detection program is executed by a processor, the steps of the circuit schematic detection method according to any one of claims 1 to 4 are implemented.

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