Backlight system, display device, and method of transmitting data in a backlight system

Abstract

A backlight system, a display device, and a method of transmitting data in a backlight system are provided. The backlight system includes a backlight member and a main driving circuit. The backlight member includes a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns such that first through m-th slave driving circuits are arranged in each of the driving rows, where m is a positive integer greater than 1, and the first through m-th slave driving circuits are connected in a daisy chain structure. The main driving circuit is configured to generate a plurality of input data signals, wherein each of the plurality of input data signals corresponds to each of the driving rows, and each of the input data signals includes first through m-th groups including luminance data corresponding to the first through m-th slave driving circuits.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0130199, filed on October 8, 2020, and Korean Patent Application No. 10-2020-0154074, filed on November 17, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to semiconductor integrated circuits, and more particularly to a backlight system, a display device including the backlight system, and a method for transmitting data in the backlight system. Background Technology

[0004] Display devices, such as liquid crystal displays (LCDs), represent image grayscale levels by adjusting the amount of transmitted light from a backlight. Displays can include various types of backlights, such as cold cathode fluorescent lamps (CCFLs), directional light-emitting diodes (LEDs), edge-lit LEDs, and local dimming schemes. Recently, full array local dimming (FALD) schemes, which arrange LEDs in a two-dimensional array, have gained attention due to their high image quality. FALD schemes are widely used in display products requiring high image quality, such as high-end TVs; however, it is difficult to drive a large number of backlights (e.g., LEDs) using FALD schemes. Noise may increase due to the increased number of driver integrated circuits (ICs), the non-uniformity of the driver ICs, and the increased number of connectors to the printed circuit board (PCB), and it is difficult to ensure the brightness quality of the backlight. Summary of the Invention

[0005] A backlight system capable of effectively performing local dimming and a display device including the backlight system are provided.

[0006] A method for transmitting data in a backlight system that can effectively load brightness data is provided.

[0007] According to one aspect of this disclosure, a backlight system includes: a backlight element comprising a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns such that first to m-th slave driving circuits are arranged in each driving row of the driving rows, wherein m is a positive integer greater than 1, and the first to m-th slave driving circuits are connected in a daisy-chain structure; and a main driving circuit configured to generate a plurality of input data signals, wherein each of the plurality of input data signals corresponds to each driving row, and each input data signal includes first to m-th groups, the first to m-th groups including brightness data corresponding to the first to m-th slave driving circuits.

[0008] According to one aspect of this disclosure, a display device includes: a display panel including a plurality of pixels configured to display an image corresponding to input image data; a display panel driver configured to drive the display panel based on the input image data; a backlight member including a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns such that first to m-th slave driving circuits are arranged in each driving row, where m is a positive integer greater than 1, and the first to m-th slave driving circuits are connected in a daisy-chain structure; and a main driving circuit configured to generate a plurality of input data signals, wherein each of the plurality of input data signals corresponds to each driving row, and each input data signal includes first to m-th groups, the first to m-th groups including brightness data corresponding to the first to m-th slave driving circuits.

[0009] According to one aspect of this disclosure, a method for transmitting data in a backlight system is provided, the backlight system including a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, the plurality of slave driving circuits being arranged in a matrix of driving rows and driving columns such that first to m-th slave driving circuits arranged in each driving row are connected in a daisy-chain structure, where m is a positive integer greater than 1, the method comprising: generating an input data signal including a first to m-th group having a virtual identifier and brightness data corresponding to the first to m-th slave driving circuits, such that the value of the virtual identifier sequentially increases or sequentially decreases; and transmitting the input data... A signal is applied to the m-th slave drive circuit among the first to m-th slave drive circuits, and the input data signal is sequentially transmitted from the m-th slave drive circuit to the first slave drive circuit among the first to m-th slave drive circuits; in each of the first to m-th slave drive circuits, the value of the virtual identifier of the received packet transmitted from the next-level slave drive circuit is increased or decreased, so as to transmit the transmitted packet including the virtual identifier with the increased or decreased value to the previous-level slave drive circuit; and in each of the first to m-th slave drive circuits, based on the result of comparing the value of the virtual identifier of the received packet with a fixed address, the brightness data included in the received packet is stored.

[0010] The backlight system according to the example embodiment can reduce the number of backlight components and enhance noise tolerance by connecting the drive circuit in a daisy-chain structure and transmitting brightness data via a digital scheme.

[0011] Furthermore, the backlight system and method for transmitting brightness data according to the example embodiment can omit the configuration and operation of applying identifiers to the slave drive circuits by using virtual identifiers to load brightness data into the corresponding slave drive circuits among a plurality of slave drive circuits connected in a daisy chain structure, thereby reducing the size of the backlight device and increasing the speed of local dimming operation. Attached Figure Description

[0012] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a block diagram illustrating a backlight system according to an example embodiment.

[0014] Figure 2 This is a diagram illustrating data signals and packets transmitted in a backlight system according to an example embodiment.

[0015] Figure 3 This is a flowchart illustrating a method for transmitting data in a backlight system according to an example embodiment.

[0016] Figure 4 and Figure 5This is a diagram used to describe virtual identifiers included in data signals transmitted in a backlight system according to an example embodiment.

[0017] Figure 6 This is a block diagram illustrating a display system according to an example embodiment.

[0018] Figure 7 This is a perspective view of a display device according to an example embodiment.

[0019] Figure 8 This is a diagram illustrating a local dimming block included in a backlight element according to an example embodiment.

[0020] Figure 9 This is a diagram illustrating the relationship between the drive circuitry and the local dimming block included in the backlight according to an example embodiment.

[0021] Figure 10 and Figure 11 This is a block diagram illustrating a backlight system according to an example embodiment.

[0022] Figure 12 This is a diagram illustrating an example embodiment of providing a clock signal to a slave driving circuit included in a backlight element, according to an example embodiment.

[0023] Figure 13 This is a block diagram illustrating an example embodiment of a drive circuit included in a backlight element according to an example embodiment.

[0024] Figure 14 and Figure 15 This is a timing diagram illustrating an example embodiment of transmitting data signals in a backlight according to an example embodiment.

[0025] Figure 16 This is a block diagram illustrating an example embodiment of a data driver included in a display device according to an example embodiment.

[0026] Figure 17 This illustrates an example embodiment. Figure 16 The timing diagram of the operation of the data driver.

[0027] Figure 18 This is a diagram illustrating an exemplary embodiment of a driver included in a slave drive circuit of a backlight element according to an example embodiment.

[0028] Figure 19 This illustrates the inclusion of examples according to the embodiment. Figure 18 Timing diagram of the operation of the analog driver in the driver.

[0029] Figure 20 It is shown that it includes Figure 18A circuit diagram of an example embodiment of the sample-and-hold circuit in a driver.

[0030] Figure 21 This illustrates the example embodiment by Figure 18 A diagram illustrating the brightness achieved by the driver.

[0031] Figure 22 This is a block diagram illustrating a backlight system according to an example embodiment.

[0032] Figure 23 It is shown that it includes Figure 22 A block diagram of an example embodiment of the drive circuit in the backlight device.

[0033] Figure 24 This illustrates the inclusion of examples according to the embodiment. Figure 23 The circuit diagram of the monitoring circuit in the drive circuit.

[0034] Figure 25 This illustrates an example embodiment. Figure 24 The timing diagram of the operation of the monitoring circuit.

[0035] Figure 26A and Figure 26B This is a diagram illustrating an example embodiment of dimming operation in a backlight system according to an example embodiment.

[0036] Figure 27 This is a block diagram illustrating a computing system according to an example embodiment. Detailed Implementation

[0037] Various exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. In the drawings, the same reference numerals consistently denote the same elements. Repeated descriptions of various elements may be omitted.

[0038] As is customary in the art, embodiments can be described and illustrated in blocks that perform one or more of the described functions. These blocks may be referred to herein as units or modules, or by names such as drivers, controllers, devices, etc., and may be physically implemented by analog or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and may be driven by firmware and software. For example, the circuitry may be implemented in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuitry included in a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Each block of an embodiment may be physically divided into two or more interacting and discrete blocks. Similarly, the blocks of an embodiment may be physically combined into more complex blocks.

[0039] Figure 1 This is a block diagram illustrating a backlight system according to an example embodiment.

[0040] Reference Figure 1 The backlight system 10 may include a main drive circuit MDR 600 and a backlight element 700, which may be, for example, a backlight unit.

[0041] The backlight unit 700 may include multiple drive circuits PDR1,1 to PDRn,m and multiple light sources driven by the multiple drive circuits PDR1,1 to PDRn,m. For ease of illustration, in Figure 1 Multiple light sources are omitted, and the reference is... Figures 6 to 9 Further examples of light sources included in the backlight element 700 are described.

[0042] Multiple drive circuits PDR1,1 to PDRn,m can be arranged into a matrix of drive rows DR1 to DRn and drive columns DC1 to DCm, where each of n and m is a positive integer greater than 1. For example... Figure 1 As shown, the first to m-th slave drive circuits PDRi,1 to PDRi,m (i = 1 to n) arranged in each drive row DRi can be connected in a daisy-chain structure. For clarity, throughout the disclosure, the character "~" can be used to indicate "to" or "to". For example, the expression PDR1,1 to PDRn,m can mean PDR1,1 to PDRn,m.

[0043] The main drive circuit MDR 600 can generate multiple input data signals SDT1,m to SDTn,m, respectively, corresponding to multiple drive lines DR1 to DRn. Each input data signal SDT1,m corresponding to each drive line DRi can include first to m groups, which include brightness data to be loaded into the first to m slave drive circuits PDRi,1 to PDRi,m respectively. (Refer to the following...) Figure 2 Examples of data signals and packets transmitted in the backlight system 10 are further described.

[0044] The master drive circuit MDR 600 can apply each input data signal SDTi,m to the m-th slave drive circuit PDRi,m, which is the last slave drive circuit in the daisy chain. The first to m-th slave drive circuits PDRi,1 to PDRi,m arranged in each drive row DRi can sequentially transmit each input data signal SDTi,m from the m-th slave drive circuit PDRi,m to the first slave drive circuit PDRi,1. In other words, each slave drive circuit PDRi,j (i = 1 to n, j = 1 to m) arranged in each drive row DRi can receive the data signal SDTi,j transmitted from the next slave drive circuit PDRi,j+1, which may be, for example, a slave drive circuit one stage later than the slave drive circuit PDRi,j, and can transmit the data signal SDTi,j-1 to the previous slave drive circuit PDRi,j-1, which may be a slave drive circuit one stage earlier than the slave drive circuit PDRi,j.

[0045] Multiple slave drive circuits PDR1,1 to PDRn,m can respectively receive clock signals SCLK1,1 to SCLKn,m and operate based on the received clock signals. The following will refer to... Figures 10 to 12 This describes an example embodiment that provides clock signals SCLK1,1 to SCLKn,m.

[0046] Traditional backlight systems employ either a direct-drive scheme or a peer-to-peer drive scheme. In the peer-to-peer scheme, multiple slave drive circuits are connected to the master drive circuit via corresponding wiring, and the master drive circuit directly controls each of the multiple slave drive circuits. In this case, the number of wiring increases with the number of slave drive circuits, and the complex wiring reduces design margins and limits the expansion of the display device.

[0047] To simplify wiring, the backlight panel can be divided into multiple sub-panels, each controlled by a different main drive circuit. However, the problem of complex wiring may still exist, and uneven local dimming may occur due to the characteristic deviations of the multiple main drive circuits.

[0048] The backlight system according to the example embodiment can reduce the number of backlight components and enhance noise tolerance by connecting the drive circuit in a daisy-chain structure and transmitting brightness data via a digital scheme.

[0049] Figure 2 This is a diagram illustrating data signals and packets transmitted in a backlight system according to an example embodiment.

[0050] Reference Figure 1 and Figure 2 Each input data signal SDTi,m generated from the main drive circuit MDR 600 may include multiple groups, namely, the first to the m-th groups PKTi,1 to PKTi,m corresponding to the first to the m-th slave drive circuits PDRi,1 to PDRi,m arranged in each drive row DRi. As described above, each input data signal SDTi,m can be applied to the m-th slave drive circuit PDRi,m in the last stage. In this case, the first group PKTi,1 corresponding to the first slave drive circuit PDRi,1 can be arranged at the beginning of each input data signal SDTi,m, such that the first group PKTi,1 can be output from the main drive circuit MDR 600 first.

[0051] Figure 2 An example embodiment of the format of a block PKT is shown. A block PKT may include a start identifier STT, a virtual identifier VID, a lock identifier LCK, a type identifier TP, luminance data DMD1 to DMDk, and a parity bit PRT.

[0052] The start identifier STT can indicate the beginning position of a packet PKT. For example, the start identifier STT can be a single data bit, and when the value of the start identifier STT is 0, each slave driver circuit can detect the start of a packet PKT. The size or total number of bits of the packet PKT can be predetermined, and each slave driver circuit can identify a packet PKT as the data bits corresponding to the total number of bits received after the start identifier STT.

[0053] The Virtual Identifier (VID) can indicate the slave driver circuit corresponding to the group PKT. See below for reference. Figures 3 to 5 As described, when passing through a daisy-chain of slave drive circuits, the value of the virtual identifier VID can sequentially increase or decrease. Using the virtual identifier VID, the corresponding brightness data can be efficiently transmitted to the target slave drive circuit.

[0054] The lock identifier LCK can indicate whether the virtual identifier VID is fixed. For example, the lock identifier LCK can be a single bit. When the lock identifier LCK has a value of 0, the virtual identifier VID can change when passing through the slave driver circuit, and when the lock identifier LCK has a value of 1, the virtual identifier VID can be fixed to the value output from the master driver circuit MDR 600 without changing.

[0055] The type identifier TP indicates the type of the grouped PKT. Based on the value of TP, it can indicate whether the grouped PKT includes luminance data, whether it includes control data other than luminance data, the row address of the local dimming block corresponding to the luminance data, the operating mode, etc.

[0056] The luminance data DMD1 to DMDk can correspond to multiple local dimming blocks. The luminance data DMD1 to DMDk can be replaced by other data depending on the type of group PKT.

[0057] The parity check bit (PRT) can be used to check for errors in the luminance data DMD1 to DMDk. Each slave drive circuit may include a decoder (DEC), as will be referred to below. Figure 13 The decoder DEC can detect errors in the luminance data DMD1–DMDk based on the parity check bit PRT. When it is determined that the luminance data DMD1–DMDk includes errors, each slave driver circuit can discard the received luminance data DMD1–DMDk and maintain the luminance level corresponding to the previously received luminance data. When using luminance data including errors, image quality may be degraded, and the parity check bit PRT can be used to verify the validity of the luminance data DMD1–DMDk. In some example embodiments, a cyclic redundancy check (CRC) bit can be used instead of the parity check bit PRT to enforce the validity of the luminance data DMD1–DMDk.

[0058] Figure 3 This is a flowchart illustrating a method for transmitting data in a backlight system according to an example embodiment.

[0059] Figure 3 A method for transmitting data in a backlight system as described above is illustrated. The backlight system includes multiple slave drive circuits and multiple light sources driven by the multiple slave drive circuits. The multiple slave drive circuits are arranged in a matrix of drive rows and drive columns, such that the first to m-th slave drive circuits arranged in each drive row are connected in a daisy-chain structure.

[0060] Reference Figure 3In operation S100, an input data signal can be generated including a first to m-th group of brightness data to be loaded into the first to m-th drive circuits, such that the value of the virtual identifier increases or decreases sequentially.

[0061] In operation S200, by applying the input data signal to the m-th slave drive circuit, the input data signal can be sequentially transmitted from the m-th slave drive circuit to the first slave drive circuit.

[0062] In operation S300, in each of the first to m slave drive circuits, the value of the virtual identifier of the received packet transmitted from the slave drive circuit in the next stage can be increased or decreased to transmit the transmitted packet including the virtual identifier with the increased or decreased value to the slave drive circuit in the previous stage.

[0063] In operation S400, in each of the first to m-th drive circuits, brightness data included in the received packet can be stored based on the result of comparing the value of the virtual identifier of the received packet with a fixed address.

[0064] Figure 4 and Figure 5 This is a diagram used to describe virtual identifiers included in data signals transmitted in a backlight system according to an example embodiment.

[0065] exist Figure 4 and Figure 5 In this context, VID indicates that, as referenced... Figure 2 The virtual identifier described, and ETC represents the portion of the packet other than the virtual identifier VID. Figure 4 The diagram shows each input data signal SDTi,m output from the main drive circuit MDR 600 and applied to the m-th slave drive circuit PDRi,m of each drive line DRi.

[0066] Reference Figures 1 to 4 The main drive circuit MDR 600 can generate each input data signal SDTi,m corresponding to each drive line DRi, such that the values ​​of the virtual identifiers included in the first to m groups PKTi,1 to PKTi,m increase or decrease sequentially.

[0067] In some example embodiments, as the first case CS1, the main drive circuit MDR 600 can generate each input data signal SDTi,m by sequentially decreasing the value of the virtual identifier VID included in the first to m-th groups PKTi,1 to PKTi,m. For ease of illustration, Figure 4The diagram shows three groups PKTi,j-1, PKTi,j and PKTi,j+1 sequentially output from the main drive circuit MDR 600, and the value of the virtual identifier VID can be sequentially decreased to Q+1, Q and Q-1.

[0068] In some example embodiments, as a second case CS2, the main drive circuit MDR 600 can generate each input data signal SDTi,m by sequentially increasing the value of the virtual identifier VID included in the first to m-th groups PKTi,1 to PKTi,m. For example... Figure 4 As shown, the value of the virtual identifier VID included in the three groups PKTi,j-1, PKTi,j and PKTi,j+1 can be sequentially increased to R-1, R and R+1.

[0069] Reference Figure 1 and Figure 5 In each drive line DRi, each of the first to m slave drive circuits PDRi,1 to PDRi,m can increment or decrement the value of the virtual identifier VID of the received packet transmitted from the slave drive circuit in the next stage, so as to transmit the transmitted packet including the incremented or decremented virtual identifier to the slave drive circuit in the previous stage. Figure 4 In the first case CS1, when the group PKTi,j passes through the drive circuits PDRi,m,PDRi,m-1, and PDRi,m-2, the value of the group PKTi,j can be decreased by 1, such as Q, Q-1, and Q-2. Figure 4 In the second case CS2, when the group PKTi,j passes through the drive circuits PDRi,m,PDRi,m-1 and PDRi,m-2, the value of the group PKTi,j can be incremented by 1, such as R, R+1 and R+2.

[0070] The following will refer to Figure 14 and Figure 15 Further examples of data transfer methods using virtual identifiers (VIDs) are described.

[0071] Figure 6 This is a block diagram illustrating a display system according to an example embodiment.

[0072] Reference Figure 6The display system 50 may include a host device (host) 60 and a display device 70. The display device 70 may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200 (which may be, for example, a timing controller (TCON)), a gate driver (GDRV) 300, a gamma reference voltage generator (GGEN) 400, and a data driver DDRV 500 (which may be, for example, a source driver). The display device 70 may also include a backlight element (BLU) for providing light to the display panel 100 and a main drive circuit (MDR) 600 for driving the backlight element (BLU). In an embodiment, the backlight element (BLU) may be, for example, a backlight unit. The host device 60 may provide input image data (IMG) to the drive controller 200 and provide dimming information (DIMM) corresponding to the input image data (IMG) to the main drive circuit (MDR) 600. The dimming information (DIMM) may include dimming data.

[0073] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction, while the data lines DL may extend in a second direction intersecting the first direction.

[0074] The display panel 100 may be a liquid crystal display panel. The display panel 100 may include a first substrate, a second substrate, and a liquid crystal layer. The first substrate includes gate lines GL, data lines DL, pixels, and switching elements. The second substrate faces the first substrate and includes a common electrode. The liquid crystal layer is disposed between the first substrate and the second substrate.

[0075] The drive controller 200 can receive input image data IMG and input control signal CONT from the host device 60. For example, the input image data IMG may include red image data, green image data, and blue image data. In some embodiments, the input image data IMG may include white image data. In some embodiments, the input image data IMG may include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0076] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0077] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver GDRV 300, and outputs the first control signal CONT1 to the gate driver GDRV 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0078] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver DDRV 500, and outputs the second control signal CONT2 to the data driver DDRV 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0079] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver DDRV 500.

[0080] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator GGEN400, and outputs the third control signal CONT3 to the gamma reference voltage generator GGEN400.

[0081] In some example embodiments, the drive controller 200 can generate dimming information DIMM based on the input image data IMG, and the drive controller 200, instead of the host device 60, can provide the dimming information DIMM to the main drive circuit MDR 600. In some example embodiments, such as Figure 6 As shown, the dimming information DIMM can be provided from the host device 60 to the main drive circuit MDR 600.

[0082] The gate driver GDRV 300 generates a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver GDRV 300 can output the gate signal to the gate line GL.

[0083] The gamma reference voltage generator GGEN 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator GGEN 400 provides the gamma reference voltage VGREF to the data driver DDRV 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA. The gamma reference voltage generator GGEN 400 can be located in the drive controller 200 or in the data driver DDRV 500.

[0084] The data driver DDRV 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and a gamma reference voltage VGREF from the gamma reference voltage generator GGEN 400. The data driver DDRV 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver DDRV 500 outputs the data voltage to the data line DL.

[0085] Figure 7 This is a perspective view of a display device according to an example embodiment.

[0086] Reference Figure 7 The display device 70 includes a display panel 100, a gate driver GDRV 300 which may be, for example, a gate driving unit, a data driver DDRV 500 which may be, for example, a data driver, a printed circuit board 80, and a backlight unit BLU.

[0087] Each of the display panel 100 and the backlight unit BLU has a rectangular shape, which has a short side in a first direction D1 and a long side in a second direction D2 intersecting the first direction D1. However, the shape of each of the display panel 100 and the backlight unit BLU is not limited to this and may be different in other embodiments.

[0088] A backlight unit (BLU) generates light and provides the generated light to the display panel 100. The backlight unit (BLU) may include multiple slave drive circuits, such that the slave drive circuits arranged in each drive row are connected in a daisy-chain structure, as described above. The display panel 100 uses the light received from the backlight unit (BLU) to generate an image. The generated image is displayed to the user through the upper part of the display panel 100.

[0089] The display panel 100 includes a first substrate 101, a second substrate 102 facing the first substrate 101, and a liquid crystal layer LC disposed between the first substrate 101 and the second substrate 102. Each of the first substrate 101 and the second substrate 102 has a rectangular shape, which has a short side in a first direction D1 and a long side in a second direction D2.

[0090] A plurality of pixels PX, a plurality of gate lines GL1 to GLm, and a plurality of data lines DL1 to DLn are disposed on the first substrate 101. Here, m and n are natural numbers. Although for ease of description, Figure 7 Only one pixel PX is shown, but multiple pixels PX are disposed on the first substrate 101.

[0091] Gate lines GL1 to GLm and data lines DL1 to DLn are insulated from each other and cross each other. Gate lines GL1 to GLm extend in the second direction D2 and are connected to gate driver GDRV 300. Data lines DL1 to DLn extend in the first direction D1 and are connected to data driver DDRV 500. Pixels PX are connected to gate lines GL1 to GLm and data lines DL1 to DLn, respectively.

[0092] A gate driver GDRV 300 is disposed on a predetermined portion of a first substrate 101, the predetermined portion being adjacent to one of the short sides of the first substrate 101. The gate driver GDRV 300 is formed in the same process as the transistors of the pixel PX and then mounted on the first substrate 101 as an amorphous silicon TFT gate driver circuit (ASG) or an oxide semiconductor TFT gate driver circuit (OSG). However, the embodiments are not limited to this. For example, the gate driver GDRV 300 may be provided as multiple driver chips and mounted on a flexible circuit board, then connected to the first substrate 101 as a tape package (TCP). In an embodiment, the driver chips of the gate driver GDRV 300 may be mounted on the first substrate 101 as a chip-on-glass (COG).

[0093] The data driver DDRV 500 includes a source driver chip 501 mounted on a flexible circuit board 502. For example, although Figure 7 The illustration shows four source driver chips 501 and four flexible circuit boards 502, but the embodiment is not limited to this. In other embodiments, the number of source driver chips 501 and the number of flexible circuit boards 502 may vary depending on the size of the display panel 100.

[0094] One side of each flexible circuit board 502 is connected to one side of the first substrate 101. One side of the first substrate 101 is one of the long sides of the first substrate 101. The other side of each flexible circuit board 502, opposite to one side of each flexible circuit board 502, is connected to the printed circuit board 80. The source driver chip 501 is connected to the first substrate 101 and the printed circuit board 80 through the flexible circuit board 502.

[0095] The timing controller described above is mounted on printed circuit board 80. The timing controller is mounted on printed circuit board 80 as an integrated circuit chip. The timing controller is connected to gate driver GDRV 300 and data driver DDRV 500 via flexible circuit board 502. The timing controller outputs gate control signals, data control signals, and image data.

[0096] The gate driver GDRV 300 receives a gate control signal from the timing controller and generates multiple gate signals in response to the gate control signal. The gate driver GDRV 300 outputs the gate signals sequentially. The gate signals are provided to the pixel PX row by row through gate lines GL1 to GLm. As a result, the pixel PX is driven row by row.

[0097] The data driver DDRV 500 receives image data and data control signals from the timing controller. In response to the data control signals, the data driver DDRV 500 generates and outputs an analog data voltage corresponding to the image data. This data voltage is transmitted to the pixel PX via data lines DL1 to DLn.

[0098] Pixel PX receives data voltage via data lines DL1 to DLn in response to gate signals received via gate lines GL1 to GLm. Pixel PX displays gray levels corresponding to the data voltage. As a result, an image can be displayed.

[0099] Figure 8 This is a diagram illustrating a local dimming block included in a backlight element according to an example embodiment, and Figure 9 This is a diagram illustrating the relationship between the drive circuitry and the local dimming block included in the backlight according to an example embodiment. Figure 8 This illustrates the concept of a local dimming block for the backlight unit BLU.

[0100] Reference Figures 6 to 8 The backlight unit (BLU) may include multiple local dimming blocks LDB1,1 to LDBN,M for local dimming operations. The local dimming blocks LDB1,1 to LDBN,M may be arranged in a matrix of dimming block rows BR1 to BRN and dimming block columns BC1 to BCM. Additionally, the display panel 100 may be divided into display blocks for local dimming operations. In some example embodiments, the local dimming blocks LDB1,1 to LDBN,M in the backlight unit (BLU) may correspond one-to-one with the display blocks in the display panel 100. In embodiments, multiple local dimming blocks may correspond to a single display block, or multiple display blocks may correspond to a single local dimming block.

[0101] In local dimming methods, when the grayscale data of the image displayed on the display block is high, the dimming level of the local dimming block corresponding to the display block can be increased. Conversely, when the grayscale data of the image displayed on the display block is low, the dimming level of the local dimming block corresponding to the display block can be decreased.

[0102] Reference Figure 9 One drive circuit PDR1,1 can control multiple local dimming blocks LDB1,1 to LDB1,4 and LDB2,1 to LDB2,4. Figure 9An exemplary connection between a slave driver circuit PDR1,1 and a corresponding local dimming block is shown, and it should be understood that other slave driver circuits have the same or similar connections.

[0103] As an example, Figure 9 A 2×4 structure is shown, in which eight local dimming blocks LDB1,1 to LDB1,4 and LDB2,1 to LDB2,4 from two dimming block rows BR1 and BR2 and four dimming block columns BC1 to BC4 are connected to a slave driver circuit PDR1,1 from drive row DR1 and drive column DC1. However, the exemplary embodiment is not limited thereto. A slave driver circuit PDR1,1 can control the luminous intensity of light sources, such as LEDs, included in the eight local dimming blocks LDB1,1 to LDB1,4 and LDB2,1 to LDB2,4 based on eight luminance data points.

[0104] Figure 10 and Figure 11 This is a block diagram illustrating a backlight system according to an exemplary embodiment.

[0105] Reference Figure 10 The backlight system 11 may include a main driving circuit 601 and a backlight element 701. In an embodiment, the backlight element 701 may be, for example, a backlight unit. Figure 10 As shown, the master drive circuit 601 can provide clock signals SCLKi,1 to SCLKi,m to the first to m-th slave drive circuits PDRi,1 to PDRi,m arranged in each drive row DRi using a daisy-chain scheme. In other words, each slave drive circuit PDRi,j (i = 1 to 3, j = 1 to 4) can receive clock signals SCLKi,j from the next-level slave drive circuit PDRi,j+1 in the same drive row DRi and transmit clock signals SCLKi,j-1 to the previous-level slave drive circuit PDRi,j-1 in the same drive row DRi. In an embodiment, each slave drive circuit PDRi,j may include a retiming circuit to output data signals SDTi,j-1 synchronously with the clock signal SCLKi,j-1.

[0106] Reference Figure 11 The backlight system 12 may include a main driving circuit 602 and a backlight element 702. In an embodiment, the backlight element 702 may be, for example, a backlight unit. Figure 11 As shown, the main drive circuit 602 can provide clock signals SCLKi,1 to SCLKi,m to the first to m slave drive circuits PDRi,1 to PDRi,m arranged in each drive row DRi through a multi-point scheme.

[0107] Figure 10Each slave drive circuit PDRi,j may include a data input terminal DI, a data output terminal DO, a clock input terminal CKI, and a clock output terminal CKO. Conversely, Figure 11 Each slave driver circuit PDRi,j in the drive line can include a data input terminal DI, a data output terminal DO, and a clock input terminal CKI, but may not include a clock output terminal CKO. The multi-point scheme has the advantage of reducing the number of input-output pins in the slave driver circuits compared to the daisy-chain scheme. In the multi-point scheme, if the clock signal delay along the clock path is ignored, the first to m-th slave driver circuits PDRi,1 to PDRi,m in each drive line DRi can operate simultaneously. The clock frequency may be limited as the number of slave driver circuits in the same drive line increases and therefore the clock signal delay increases.

[0108] Figure 10 The daisy-chain clock supply structure maintains the load between two adjacent slave drivers in the same drive row, regardless of the clock supply path length. Each slave driver PDRi,j operates only considering the operations of the subsequent slave driver PDRi,j+1 and the preceding slave driver PDRi,j-1. Therefore, high-speed operation can be achieved, and clock frequency limitations can be mitigated. Figure 11 Compared to the drive circuit in the middle, Figure 10 Each slave driver circuit requires one or more pins or clock output terminals (CKO) to transmit clock signals to the previous slave driver circuit.

[0109] Figure 12 This is a diagram illustrating an example embodiment of providing a clock signal to a slave driving circuit included in a backlight element, according to an example embodiment.

[0110] Reference Figure 12 The first type of slave drive circuit PDRA can receive clock signal SCLK for shift register SREG, which is configured to transmit data DIN and DOUT, and clock signal GCLK for driver DRU, which can be, for example, a drive unit configured to drive a light source.

[0111] In the second type of slave drive circuit PDRb, the shift register SREG can operate based on the received clock signal SCLK, and the driver DRU can operate based on the oscillation signal generated by the oscillator OSC.

[0112] In the third type of slave driver circuit PDRc, both the shift register SREG and the driver DRU can operate based on the received clock signal SCLK. In some example embodiments, the slave driver circuit PDRc may also include a clock divider CDV, which is configured to divide the frequency of the clock signal SCLK to provide a divided clock signal to the driver DRU.

[0113] The slave driver circuitry included in the backlight device according to the example embodiment can be implemented as a third type of slave driver circuit, PDRc. In other words, the shift register SREG and driver DRU included in each slave driver circuit can operate based on the same clock signal SCLK. In this example, the clock pin for receiving the additional clock signal GCLK can be removed, eliminating the need for oscillator OSC fine-tuning, reducing the size of the slave driver circuitry, and facilitating system-wide synchronization using the same clock signal SCLK.

[0114] Figure 13 This is a block diagram illustrating an example embodiment of a drive circuit included in a backlight element according to an example embodiment.

[0115] Reference Figure 13 Each slave drive circuit PDRi,j 800 may include a shift register SREG 810, control circuitry CLG 820 (e.g., control logic), a data register DREG 830, and a driver DRU 840 (e.g., a drive unit). According to an example embodiment, the slave drive circuit PDRi,j 800 may also include an address selector AMX 811.

[0116] The shift register SREG 810 stores the received packets from the slave driver circuit SDTi,j transmitted from the subsequent stage by shifting the received packets bit by bit, and outputs the stored received packets. The control circuit CLG 820 generates a latch signal LATj based on the value of the virtual identifier included in the received packets. The data register DREG 830 latches and stores the brightness data included in the received packets based on the latch signal LATj. The driver DRU 840 drives the light sources LED1 to LEDk connected to the slave driver circuit PDRi,j 800 based on the brightness data stored in the data register DREG 830.

[0117] The control circuit CLG 820 may include an address updater AUP, a decoder DEC, and an address comparator ACMP.

[0118] The address comparator ACMP compares the value of the virtual identifier (ADD) of the received packet included in the data signal SDTi,j with the fixed address AFX, and activates the latch signal LATj when the virtual identifier value ADD of the received packet is the same as the fixed address AFX. The data register DREG 830 latches and stores the luminance data included in the received packet in response to the activation of the latch signal LATj. The decoder DEC can be based on, as referenced... Figure 2 The parity check bit PRT is used to check for errors in the luminance data DMD.

[0119] In some example embodiments, the address updater AUP in the control circuit CLG 820 can generate an updated value ADD' by incrementing or decrementing the value ADD of the virtual identifier of the received packet, and generate an address selection signal ASEL that is activated when the virtual identifier of the received packet is output from the shift register SREG 810. The address selector AMX 811 can select the updated value ADD' in response to the activation of the address selection signal ASEL and select the output ROUT of the shift register SREG 810 in response to the deactivation of the address selection signal ASEL. As a result, the drive circuit PDRi,j 800 can transmit a transmit packet including the virtual identifier of the updated value ADD' instead of the received value ADD to the slave drive circuit in the preceding stage.

[0120] In the following text, refer to Figure 14 and Figure 15 An example embodiment is described, in which the address comparator ACMP uses a virtual identifier to generate a latch signal and the luminance data is stored in the data register DREG 830 based on the latch signal.

[0121] Figure 14 and Figure 15 This is a timing diagram illustrating an example embodiment of transmitting data signals in a backlight according to an example embodiment.

[0122] Figure 14 and Figure 15 As shown Figure 10 and Figure 11 The diagram illustrates the operation of the slave drive circuits PDRi,1 to PDRi,4 in each drive row DRi. During each shift cycle PD1 to PD4 between time points T0 and T4, each slave drive circuit can store the received packet transmitted from the next slave drive circuit and output the transmitted packet corresponding to the received packet received during the previous shift cycle. Figure 14 and Figure 15In this context, SDTi,4 represents the input data signal applied to the fourth slave drive circuit PDRi,4 in the last stage; SDTi,3 represents the data signal transmitted from the fourth slave drive circuit PDRi,4 to the third slave drive circuit PDRi,3; SDTi,2 represents the data signal transmitted from the third slave drive circuit PDRi,3 to the second slave drive circuit PDRi,2; and SDTi,1 represents the data signal transmitted from the second slave drive circuit PDRi,2 to the first slave drive circuit PDRi,1.

[0123] Reference Figure 14 The aforementioned fixed address AFX can be set to zero. The fixed address AFX can be set to the same value (e.g., zero) for all slave drive circuits PDRi,1 to PDRi,4 from the first to the fourth slave drive circuits. As described above, the master drive circuit can generate an input data signal SDTi,4 such that the value of the virtual identifier VID in the first to fourth packets PKTi,1 to PKTi,4 can be sequentially decreased by 1, such as 3, 2, 1, and 0. Each of the first to fourth slave drive circuits PDRi,1 to PDRi,4 can decrease the value of the virtual identifier VID in the received packet transmitted from the slave drive circuit in the next stage by 1, so as to output a transmitted packet including the decreased value of the virtual identifier VID to the slave drive circuit in the previous stage.

[0124] For example, in the case of the first group PKTi,1, the fourth slave drive circuit PDRi,4 can receive the first group PKTi,1 including the virtual identifier VID with a value of 3 during the first shift period PD1, the third slave drive circuit PDRi,3 can receive the first group PKTi,1 including the virtual identifier VID with a value of 2 during the second shift period PD2, the second slave drive circuit PDRi,2 can receive the first group PKTi,1 including the virtual identifier VID with a value of 1 during the third shift period PD3, and the first slave drive circuit PDRi,1 can receive the first group PKTi,1 including the virtual identifier VID with a value of 0 during the fourth shift period PD4.

[0125] Thus, the value of the virtual identifier VID can be decremented by 1 when passing through each slave driver circuit, and during the fourth shift period PD4, the values ​​of the virtual identifier VID can be zero for the fourth packet PKTi,4 received by the fourth slave driver circuit PDRi,4, the third packet PKTi,3 received by the third slave driver circuit PDRi,3, the second packet PKTi,2 received by the second slave driver circuit PDRi,2, and the first packet PKTi,1 received by the first slave driver circuit PDRi,1.

[0126] As described above, the address comparator ACMP in the control circuit CLG 820 can compare the value of the virtual identifier VID of the received packet included in the data signal with the fixed address AFX (e.g., zero), and activate the latch signal when the value of the virtual identifier VID of the received packet is the same as the fixed address AFX.

[0127] As a result, the address comparator ACMP in the first to fourth slave drive circuits PDRi,1 to PDRi,4 can simultaneously activate latch signals LAT1 to LAT4 at time point Ta, and the data registers DREG 830 in the first to fourth slave drive circuits PDRi,1 to PDRi,4 can simultaneously latch and store the corresponding brightness data in the first to fourth groups PKTi,1 to PKTi,4 based on latch signals LAT1 to LAT4.

[0128] Reference Figure 15 The aforementioned fixed address AFX can be set to 3. The fixed address AFX can be set to the same value (e.g., value 3) for all slave driver circuits PDRi,1 to PDRi,4 from the first to the fourth slave driver circuits. As described above, the master driver circuit can generate an input data signal SDTi,4 such that the value of the virtual identifier VID in the first to fourth packets PKTi,1 to PKTi,4 can be sequentially incremented by 1, such as 0, 1, 2, and 3. Each of the first to fourth slave driver circuits PDRi,1 to PDRi,4 can increment the value of the virtual identifier VID in the received packet transmitted from the slave driver circuit in the next stage by 1, so as to output a transmitted packet including the incremented value of the virtual identifier VID to the slave driver circuit in the previous stage.

[0129] For example, in the case of the first group PKTi,1, the fourth slave driver circuit PDRi,4 can receive the first group PKTi,1 including the virtual identifier VID with a value of 0 during the first shift period PD1, the third slave driver circuit PDRi,3 can receive the first group PKTi,1 including the virtual identifier VID with a value of 1 during the second shift period PD2, the second slave driver circuit PDRi,2 can receive the first group PKTi,1 including the virtual identifier VID with a value of 2 during the third shift period PD3, and the first slave driver circuit PDRi,1 can receive the first group PKTi,1 including the virtual identifier VID with a value of 3 during the fourth shift period PD4.

[0130] Thus, the value of the virtual identifier VID can be incremented by 1 when passing through each slave driver circuit, and during the fourth shift cycle PD4, the value of the virtual identifier VID can be 3 for the fourth packet PKTi,4 received by the fourth slave driver circuit PDRi,4, the third packet PKTi,3 received by the third slave driver circuit PDRi,3, the second packet PKTi,2 received by the second slave driver circuit PDRi,2, and the first packet PKTi,1 received by the first slave driver circuit PDRi,1.

[0131] As described above, the address comparator ACMP in the control circuit CLG 820 can compare the value of the virtual identifier VID of the received packet included in the data signal with the fixed address AFX (e.g., 3), and activate the latch signal when the value of the virtual identifier VID of the received packet is the same as the fixed address AFX.

[0132] As a result, the address comparator ACMP in the first to fourth slave drive circuits PDRi,1 to PDRi,4 can simultaneously activate latch signals LAT1 to LAT4 at time point Ta, and the data registers DREG 830 in the first to fourth slave drive circuits PDRi,1 to PDRi,4 can simultaneously latch and store the corresponding brightness data in the first to fourth groups PKTi,1 to PKTi,4 based on latch signals LAT1 to LAT4.

[0133] An identifier for each slave driver circuit can be applied via an additional terminal for providing the identifier or through an initialization operation to transmit a signal, such as a command signal for providing the identifier, before the dimming operation. In these cases, the configuration of the slave driver circuits may become more complex or the efficiency of the dimming operation may decrease because the initialization operation time is increased.

[0134] Conversely, the drive circuit may not require additional terminals to receive identifiers and perform initialization processing for applying identifiers.

[0135] Thus, the backlight system and method for transmitting brightness data according to the example embodiment can omit the configuration and operation of applying identifiers to the slave drive circuits by using virtual identifiers to load brightness data into the corresponding slave drive circuits among a plurality of slave drive circuits connected in a daisy chain structure, thereby reducing the size of the backlight device and increasing the speed of local dimming operation.

[0136] Figure 16 This is a block diagram illustrating an example embodiment of a data driver included in a display device according to an example embodiment, and Figure 17 This illustrates an example embodiment. Figure 16 The timing diagram of the operation of the data driver.

[0137] Reference Figure 16 The data driver DDRV 500 (which may be, for example, a source driver) may include a shift register 510, a data latch 530, a digital-to-analog converter (DAC) 550, and an output buffer block 570.

[0138] The shift register 510 can receive a clock signal CLK and an input / output control signal DIO, and can generate multiple latch clock signals LCLK0 to LCLKn-1 based on the clock signal CLK. Each of the latch clock signals LCLK0 to LCLKn-1 can determine the latching time of the data latch 530 as a clock signal of a specific period.

[0139] Data latch 530 can store data DDT in response to latch clock signals LCLK0 to LCLKn-1 provided by shift register 510. Data latch 530 can output the stored data to DAC 550 in response to load signal TP. Data latch 530 can provide output signals D0 to Dn-1 in response to load signal TP. DAC 550 can use grayscale voltage GMA to generate input voltage signals VIN0 to VINn-1, which are analog signals corresponding to the output signals D0 to Dn-1 of data latch 530.

[0140] Output buffer block 570 buffers input voltage signals VIN0 to VINn-1 and generates source drive signals, i.e., pad output voltage signals VPO0 to VPOn-1. Output buffer block 570 may include multiple output buffer circuits OBF that drive the source lines (or data lines) of the display panel respectively.

[0141] Reference Figure 17 Based on the transitions in voltage levels Vi1, Vi2, and Vi3 of the input voltage signal VIN, the voltage levels Vo1, Vo2, and Vo3 of the pad output voltage signal VPO can sequentially transition within each unit period 1H. When the output buffer circuit is a source amplifier circuit included in the source driver of the display device, the unit period 1H can correspond to the line scan period used to apply the source voltage or the pad output voltage signal VPO to each pixel of the selected line.

[0142] The output enable signal SOEN can be deactivated during the pre-latch period tPL corresponding to the second part of the unit period 1H, and can be activated during the output period corresponding to the first part of the unit period 1H. Figure 17 An example is shown of activating the output enable signal SOEN and the inverted signal SOENB at a logic high level, but the activation logic level is not limited to this.

[0143] The transmission of brightness data as described above can be performed during the pre-latch period tPL. The latching operation of the data driver DDRV500 (which may be, for example, a source driver) and the transmission of brightness data of the backlight system can be performed during the pre-latch period tPL, and the data driver DDRV500 and the backlight device can share the output enable signal SOEN, and can easily achieve synchronization between the display image of the pixels and the local dimming operation of the light source.

[0144] Figure 18 This is a diagram illustrating an example embodiment of a driver included in the drive circuit of a backlight element according to an example embodiment, and Figure 19 It is shown that it includes Figure 18 Timing diagram of the operation of the analog driver in the driver.

[0145] Reference Figure 18 The driver DRU 840 may include an analog driver 841 and a digital driver 842, which may be, for example, drive units. Figure 18 The diagram also shows multiple light sources LED1 to LEDk connected to the light source voltage VLed and driven by a drive circuit.

[0146] Each group as described above may include brightness data corresponding to each light source LED1 to LEDk, and each brightness data may include a first digital data DMDa for analog driving and a second digital data DMDd for digital driving. For example, each brightness data corresponding to each light source may be 20 bits of data, such that the first digital data DMDa is eight bits and the second digital data DMDd is twelve bits.

[0147] The analog driver 841 may include a digital-to-analog converter (DAC) and sample-and-hold circuits SH1 to SHk. The DAC converts the value of a first digital data DMDa of the brightness data stored in a data register to sequentially output voltages V1 to Vk corresponding to the value of the first digital data DMDa. The sample-and-hold circuits SH1 to SHk store the voltages V1 to Vk and provide drive currents ILed1 to ILedk to the light sources LED1 to LEDk connected to the respective slave driver circuits based on the voltages V1 to Vk.

[0148] The digital driver 842 may include a modulator MOD and dimming switches SWD1 to SWDk. The modulator MOD may generate pulse signals PL1 to PLk based on the value of a second digital data DMDd of the luminance data. In some exemplary embodiments, the modulator MOD may perform pulse width modulation (MOD) to convert the value of the second digital data DMDd into the pulse width of the pulse signals PL1 to PLk. Figure 18An example of a digital drive 842 is shown, and the example embodiment is not limited to a specific configuration of the digital drive 842.

[0149] Reference Figure 18 and Figure 19 It can be based on from Figure 13 The control circuit CLG 820 provides switch control signals SC1 to SCk to turn on switches SW1 to SWk included in the analog driver 841. Switch control signals SC1 to SCk can be activated sequentially at time points T1 to Tk+1 when the values ​​DA1 to DAk of ​​the first digital data DMDa are provided to the digital-to-analog converter DAC, and switches SW1 to SWk can be turned on sequentially. Therefore, voltages V1 to Vk corresponding to values ​​DA1 to DAk can be stored in sample-and-hold circuits SH1 to SHk at each time point.

[0150] Figure 20 It is shown that it includes Figure 18 A circuit diagram of an example embodiment of the sample-and-hold circuit in a driver.

[0151] Reference Figure 20 Each sample-and-hold circuit SHk may include a capacitor CST, a current source CS, and a current mirror CM. The capacitor CST may store a voltage Vk applied by a switch SWk, which is turned on in response to activation of a switch control signal SCk. As described above, the voltage Vk has a level corresponding to the value DAk of ​​the first digital data DMDa. The current source CS, connected to the power supply voltage VDD, generates a drive current ILDk corresponding to the voltage Vk and provides the drive current ILDk to the current mirror CM. The current mirror CM, connected to the ground voltage VSS, replicates the drive current ILDk and provides the replicated drive current ILDk to... Figure 18 The light source LEDk is used. Example embodiments are not limited to... Figure 20 The specific configuration can be implemented, and the sampling and holding circuit can be configured in various ways.

[0152] Traditional drivers include multiple digital-to-analog converters corresponding to the number of light sources LED1 to LEDk, each generating drive currents ILed1 to ILedk. In this case, the size and power consumption can increase with the increase in the number of light sources LED1 to LEDk.

[0153] For reference Figures 18 to 20 As described, the driver DRU 840 may include a common digital-to-analog converter (DAC) regardless of the number of light sources LED1 to LEDk. Therefore, compared to conventional drivers, the driver DRU840 according to the example embodiment can have a reduced size and power consumption.

[0154] Figure 21 It is shown by Figure 18 The brightness diagram implemented by the driver.

[0155] Reference Figure 21 The brightness of the light source can be represented by the product of the pulse width and the current ILED. The pulse width corresponds to... Figure 18 The pulse width of each of the pulse signals PL1 to PLk in the pulse signal is determined, and this pulse width can be determined based on each value of the second digital data DMDd used for digital drive. The current ILD corresponds to Figure 18 The driving current ILed1 to ILedk is each of the driving currents, and the current ILed can be determined based on each value of the first digital data DMDa used for analog driving.

[0156] Figure 22 This is a block diagram illustrating a backlight system according to an example embodiment, and Figure 23 It is shown that it includes Figure 22 A block diagram of an example embodiment of the drive circuit in a backlight device.

[0157] Figure 22 and Figure 23 The backlight system 13 and the drive circuit 801 with Figure 10 and Figure 13 The backlight system 11 and the drive circuit 800 are basically similar, so repeated descriptions are omitted.

[0158] Reference Figure 22 and Figure 23 Each slave drive circuit PDRi,j may also include a monitoring circuit MNC 900 configured to generate a current IMONi,j. The first to fourth slave drive circuits PDRi,1 to PDRi,4 in each drive row DRi can generate a monitoring current IMONi (which will be referred to below). Figure 24 and Figure 25 (Description to be provided), and the monitoring current IMONi is provided to the monitoring terminal TMIi of the main drive circuit 603.

[0159] Figure 24 It is shown that it includes Figure 23 The circuit diagram of the monitoring circuit in the drive circuit, and Figure 25 It is shown Figure 24 The timing diagram of the operation of the monitoring circuit.

[0160] Reference Figure 24 The monitoring circuit MNC 900 may include a bandgap reference circuit BGR, an amplifier AMP, multiple transistors PM1, PM2 and PM3, a resistor Rtune and a path selector PMX.

[0161] The bandgap reference circuit BGR generates a reference voltage with a uniform voltage level regardless of operating conditions. The amplifier AMP and transistor PM1 form a negative feedback loop, and the output voltage of the amplifier AMP tracks the reference voltage from the bandgap reference circuit BGR. As a result, the reference current IR flowing through the resistor Rtune from the supply voltage VDD to the ground voltage VSS can have a uniform amplitude corresponding to the reference voltage.

[0162] The output voltage of amplifier AMP can be applied together to the gate electrodes of transistors PM1, PM2, and PM3. In some example embodiments, the size nX of transistor PM3 can be n times the size 1X of transistors PM1 and PM2. In this case, a reference current IR can be generated through the drain of transistor PM2, and an amplified current nIR, which is n times the reference current IR, can be generated through the drain of transistor PM3.

[0163] The path selector PMX can be based on... Figure 13 The path control signal PSEL provided by the control circuit CLG 820 generates the monitoring current IMON. For example, as... Figure 25 As shown, the path control signal PSEL can sequentially have a first value VL1 and a second value VL2. When the path control signal PSEL has the first value VL1, the path selector PMX can be connected to the drain of transistor PM2 to provide a reference current IR as the monitoring current IMON. When the path control signal PSEL has the second value VL2, the path selector PMX can be connected to the drain of transistor PM3 to provide an amplified current nIR as the monitoring current IMON, which is n times the reference current IR. The terminating resistor RMON can be connected between the ground voltage VSS and the monitoring terminal of the main drive circuit 603.

[0164] Thus, each slave drive circuit can perform correlated double sampling to sample the reference current IR and the amplified current nIR.

[0165] Figure 22 The main drive circuit 603 may include a calibration circuit CAL to compensate for operational deviations of the multiple slave drive circuits based on monitoring currents from monitoring circuits in each of the multiple slave drive circuits. The calibration circuit CAL may include an analog-to-digital converter (ADC) configured to convert the multiple monitoring currents into multiple digital values, wherein each monitoring current is provided from a monitoring circuit included in each of the multiple slave drive circuits. Each monitoring current IMONi (i = 1, 2, 3) may sequentially include currents sampled by the first to fourth slave drive circuits PDRi,1 to PDRi,4 in each drive row DRi, respectively.

[0166] The calibration circuit CAL in the main drive circuit 603 can compensate for operational deviations through correlated double sampling based on the difference (nIR-IR) between the reference current IR and the amplified current nIR. Correlated double sampling reduces the influence of external noise and accurately compensates for operational deviations from the drive circuit.

[0167] Figure 26A and Figure 26B This is a diagram illustrating an example embodiment of dimming operation in a backlight system according to an example embodiment.

[0168] For reference Figure 8 The backlight unit (BLU) may include multiple local dimming blocks LDB1,1 to LDBN,M. The local dimming blocks LDB1,1 to LDBN,M may be arranged in a matrix of dimming block rows BR1 to BRN and dimming block columns BC1 to BCM.

[0169] Reference Figure 26A The dimming operation can be performed on a per-row basis for multiple dimming blocks BR1 to BRN. For example, LED emission from the first dimming block row BR1 can be performed during a frame period 1F starting from the first time point T1, LED emission from the second dimming block row BR2 can be performed during a frame period 1F starting from the second time point T2, and so on. In this way, LED emission from the nth dimming block row BRN can be performed during a frame period 1F starting from the nth time point TN.

[0170] Brightness data can be transmitted to the drive circuit at the frame rate of the display device (e.g., 60Hz or 120Hz), and the transmitted brightness data can be used for a frame period 1F corresponding to the reciprocal of the frame rate.

[0171] Figure 26B The black subframe insertion (BSFI) operation corresponding to the dimming operation of each dimming block line BRi during a frame period 1F is shown.

[0172] Reference Figure 26B A frame period 1F can be divided into multiple subframes SF1 to SFp. For example, a frame period 1F can be divided into twelve subframes SF1 to SF12.

[0173] The slave drive circuit in each dimming block row BRi can drive the corresponding light source based on the corresponding luminance data DMDi during the first part of subframes SF1 to SFp, and based on the corresponding black data BLD during the second part of subframes SF1 to SFp. Black data BLD represents data where the luminance of the light from the light source is zero.

[0174] For example, such as Figure 26BAs shown, the drive circuit can drive the light source based on luminance data DMDi during odd-numbered subframes SF1, SF3, and SFp-1, and based on black data BLD during even-numbered subframes SF2, SF4, and SFp. In other words, actual dimming and black dimming can be performed alternately.

[0175] In this way, by applying black dimming to a portion of the subframe, the effect of inserting a black frame can be achieved, and the afterimage phenomenon in the display device can be reduced.

[0176] Figure 27 This is a block diagram illustrating a computing system according to an example embodiment.

[0177] Reference Figure 27 The computing system 1100 may employ or support a MIPI interface and may include an application processor 1110, an image sensor 1140, and a display device (display) 1150. The CSI host 1112 of the application processor 1110 may perform serial communication with the CSI device 1141 of the image sensor 1140 using a Camera Serial Interface (CSI). In some example embodiments, the CSI host 1112 may include a deserializer (DES), and the CSI device 1141 may include a serializer (SER). The DSI host 1111 of the application processor 1110 may perform serial communication with the DSI device 1151 of the display device 1150 using a Display Serial Interface (DSI). In some example embodiments, the DSI host 1111 may include a serializer (SER), and the DSI device 1151 may include a deserializer (DES).

[0178] The computing system 1100 may also include a radio frequency (RF) chip 1160, which may include a physical layer PHY 1161 and a slave DigRF 1162. The physical layer PHY 1113 of the application processor 1110 may perform data transmission with the physical layer PHY 1161 of the RF chip 1160 using a MIPI DigRF. The physical layer PHY 1113 of the application processor 1110 may interface (or communicate, for example, with a master DigRF 1114) for controlling data transmission with the physical layer PHY 1161 of the RF chip 1160.

[0179] The computing system 1100 may also include a Global Positioning System (GPS) 1120, a storage device 1170, a microphone (MIC) 1180, DRAM 1185, and / or a speaker 1190. The computing system 1100 may communicate with external devices using an Ultra-Wideband (UWB) communication interface 1210, a Wireless Local Area Network (WLAN) communication interface 1220, a WiMAX communication interface 1230, etc. However, the embodiments are not limited to this. Figure 27The configuration or interface of the computing system 1100 shown.

[0180] According to an example embodiment, the display device 1150 includes a backlight system (BLS) comprising a main driving circuit and a backlight element as described above. The backlight element may include a plurality of slave driving circuits and a plurality of light sources driven by the slave driving circuits. The plurality of slave driving circuits may be arranged in a matrix of driving rows and driving columns, such that the first to m-th slave driving circuits arranged in each driving row are connected in a daisy-chain configuration. The main driving circuit may generate a plurality of input data signals. Each input data signal corresponding to each driving row may include a first to m-th group, each of the first to m-th groups including brightness data to be loaded into the first to m-th slave driving circuits, respectively.

[0181] As described above, the backlight system according to the example embodiment can reduce the number of backlight components and enhance noise margin by connecting the slave driver circuits in a daisy-chain structure and transmitting brightness data using a digital scheme. Furthermore, the backlight system and method for transmitting brightness data according to the example embodiment can reduce the size of the backlight component and increase the speed of local dimming operations by using virtual identifiers to load brightness data into the corresponding slave driver circuits among the multiple slave driver circuits connected in a daisy-chain structure, thereby omitting the configuration and operation for applying identifiers to the slave driver circuits.

[0182] The embodiments can be applied to display devices and any electronic devices and systems that include display devices. For example, the embodiments can be applied to systems such as mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, vehicle navigation systems, video phones, monitoring systems, autofocus systems, tracking systems, motion monitoring systems, and the like.

[0183] The above is a description of exemplary embodiments, and these contents should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the scope of this disclosure.

Claims

1. A backlight system, comprising: A backlight device includes a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns, such that first to m-th slave driving circuits are arranged in each of the driving rows, where m is a positive integer greater than 1, and the first to m-th slave driving circuits are connected in a daisy-chain structure; and A main drive circuit is configured to generate a plurality of input data signals, wherein each of the plurality of input data signals corresponds to each drive row, and each input data signal includes first to m-th groups, the first to m-th groups including brightness data corresponding to the first to m-th slave drive circuits. Wherein, each of the first to m-th groups includes a virtual identifier, and As each group passes through the daisy chain structure, the value of the virtual identifier decreases or increases sequentially.

2. The backlight system according to claim 1, wherein, The main drive circuit is further configured to apply each input data signal to the m-th slave drive circuit among the first to m-th slave drive circuits, and The first to m-th slave drive circuits are configured to sequentially transmit each input data signal from the m-th slave drive circuit to the first slave drive circuit among the first to m-th slave drive circuits.

3. The backlight system according to claim 1, wherein, Each of the first to m-th slave drive circuits is configured to increase or decrease the value of the virtual identifier of the received packet transmitted from the subsequent slave drive circuit, so as to transmit the transmitted packet including the virtual identifier with the increased or decreased value to the previous slave drive circuit.

4. The backlight system according to claim 3, wherein, Each of the slave drive circuits is further configured to compare the value of the virtual identifier of the received packet with a fixed address, and when the value of the virtual identifier of the received packet is the same as the fixed address, to store the brightness data included in the received packet.

5. The backlight system according to claim 4, wherein, The fixed address is set to the same value for each of the first to m-th slave drive circuits.

6. The backlight system according to claim 3, wherein, Each of the first to m slave drive circuits is further configured to simultaneously latch and store brightness data corresponding to each slave drive circuit.

7. The backlight system according to claim 1, wherein, The main drive circuit is further configured to generate each of the input data signals such that the first to m groups respectively include the first to m virtual identifiers, and the values ​​of the first to m virtual identifiers are sequentially decremented by 1. Each of the first to m slave drive circuits is configured to decrease the value of the virtual identifier of the received packet transmitted from the next slave drive circuit by 1, so as to transmit the transmitted packet including the virtual identifier with the decreased value to the previous slave drive circuit.

8. The backlight system according to claim 7, wherein, Each of the first to m slave drive circuits is further configured to compare the value of the virtual identifier of the received packet with a fixed address set to zero, and when the value of the virtual identifier of the received packet is the same as the fixed address, to store the brightness data included in the received packet.

9. The backlight system according to claim 1, wherein, Each of the plurality of slave drive circuits includes: A shift register configured to store the received packets by shifting the received packets transmitted from the next stage drive circuit bit by bit, and to output the received packets. A control circuit configured to generate a latch signal based on the value of a virtual identifier included in the received packet; A data register, configured to latch and store luminance data included in the received packet based on the latch signal; and A driver is configured to drive the light sources among the plurality of light sources connected to each of the slave driver circuits based on brightness data stored in the data register.

10. The backlight system according to claim 9, wherein, The control circuit is further configured to compare the value of the virtual identifier of the received packet with a fixed address, and to activate the latch signal when the value of the virtual identifier of the received packet is the same as the fixed address. The data register is further configured to latch and store luminance data included in the received packet in response to activation of the latch signal.

11. The backlight system according to claim 9, wherein, The control circuit is also configured to generate an update value by increasing or decreasing the value of the virtual identifier of the received packet, and to generate an address selection signal activated when the virtual identifier of the received packet is output from the shift register. Each of the plurality of slave driver circuits includes an address selector configured to select the updated value in response to activation of the address select signal and to select the output of the shift register in response to deactivation of the address select signal, so as to transmit a transmit packet including a virtual identifier having the updated value to the preceding slave driver circuit.

12. The backlight system according to claim 9, wherein, The driver includes: A digital-to-analog converter configured to convert digital values ​​of luminance data stored in the data register to sequentially output voltages corresponding to the digital values; and A sample and hold circuit is configured to store the voltage and provide a drive current to the light source connected to each of the slave drive circuits based on the voltage.

13. The backlight system according to claim 9, wherein, Each of the slave drive circuits further includes: A monitoring circuit is configured to generate a monitoring current that indicates the circuit characteristics of the driver.

14. The backlight system according to claim 13, wherein, The main drive circuit includes an analog-to-digital converter configured to convert a plurality of monitored currents into a plurality of digital values, wherein each of the plurality of monitored currents is provided from a monitoring circuit included in each of the plurality of slave drive circuits. The main drive circuit is further configured to compensate for operational deviations of the multiple slave drive circuits based on the multiple digital values.

15. The backlight system according to claim 9, wherein, The shift register and the driver are also configured to operate based on the same clock signal provided from the main drive circuit.

16. The backlight system according to claim 1, wherein, The main drive circuit is also configured to provide clock signals to the first to m slave drive circuits arranged in each drive row via a daisy-chain scheme.

17. The backlight system according to claim 1, wherein, The main drive circuit is also configured to provide clock signals to the first to m slave drive circuits arranged in each drive row via a multi-point scheme.

18. The backlight system according to claim 1, wherein, The plurality of light sources include light-emitting diodes.

19. A display device, comprising: The display panel includes a plurality of pixels configured to display an image corresponding to input image data; A display panel driver is configured to drive the display panel based on the input image data; A backlight device includes a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, wherein the plurality of slave driving circuits are arranged in a matrix of driving rows and driving columns, such that first to m-th slave driving circuits are arranged in each of the driving rows, where m is a positive integer greater than 1, and the first to m-th slave driving circuits are connected in a daisy-chain structure; and A main drive circuit is configured to generate a plurality of input data signals, wherein each of the plurality of input data signals corresponds to each drive row, and each input data signal includes first to m-th groups, the first to m-th groups including brightness data corresponding to the first to m-th slave drive circuits. Wherein, each of the first to m-th groups includes a virtual identifier, and As each group passes through the daisy chain structure, the value of the virtual identifier decreases or increases sequentially.

20. A method for transmitting data in a backlight system, the backlight system comprising a plurality of slave driving circuits and a plurality of light sources driven by the plurality of slave driving circuits, the plurality of slave driving circuits being arranged in a matrix of driving rows and driving columns such that first to m-th slave driving circuits arranged in each driving row are connected in a daisy-chain structure, where m is a positive integer greater than 1, the method comprising: An input data signal is generated comprising a first to m-th group of luminance data having a virtual identifier and corresponding to the first to m-th slave driving circuits, such that the value of the virtual identifier increases or decreases sequentially. By applying the input data signal to the m-th slave drive circuit among the first to m-th slave drive circuits, the input data signal is sequentially transmitted from the m-th slave drive circuit to the first slave drive circuit among the first to m-th slave drive circuits; In each of the first to m-th slave drive circuits, the value of the virtual identifier of the received packet transmitted from the next-level slave drive circuit is increased or decreased, so as to transmit the transmitted packet including the virtual identifier with the increased or decreased value to the previous-level slave drive circuit. as well as In each of the first to m-th slave drive circuits, brightness data included in the received packet is stored based on the result of comparing the value of the virtual identifier of the received packet with a fixed address.

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