Array substrate and manufacturing method thereof, display panel and display device

Abstract

Embodiments of the present invention disclose an array substrate, a method for manufacturing the same, a display panel, and a display device. The array substrate manufacturing method includes: providing a substrate; forming a first electrode on one side of the substrate; forming an insulating layer on a side of the first electrode facing away from the substrate, the insulating layer comprising at least two sub-insulating layers, with particles from any two adjacent sub-insulating layers prepared in different environments; and forming a second electrode on a side of the insulating layer facing away from the substrate, the first electrode and the second electrode being electrically connected to different signal transmission terminals, respectively. The array substrate manufacturing method provided by the embodiments of the present invention can reduce the probability of cracking the insulating layer, reduce the probability of dark spots forming on the screen, and improve the display quality and reliability of the display panel.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, a display panel, and a display device. Background Art

[0002] With the development of display technology, display panels have been widely used in people's production and life, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] However, the display panels in the prior art still have some problems that need to be solved, such as the dark spot problem of the display panels. Summary of the Invention

[0004] An embodiment of the present invention provides an array substrate and a preparation method thereof, a display panel and a display device. By setting different particle preparation environments for two adjacent sub-insulating layers in an insulating layer, the probability of forming dark spots on the screen is reduced, and the display effect and reliability of the display panel are improved.

[0005] In a first aspect, an embodiment of the present invention provides a method for preparing an array substrate, the method comprising:

[0006] providing a substrate;

[0007] preparing a first electrode on one side of the substrate;

[0008] preparing an insulating layer on a side of the first electrode away from the substrate, wherein the insulating layer includes at least two sub-insulating layers, and particles of any two adjacent sub-insulating layers are prepared in different environments;

[0009] A second electrode is formed on a side of the insulating layer away from the substrate, and the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively.

[0010] In a second aspect, an embodiment of the present invention provides an array substrate, comprising:

[0011] substrate;

[0012] a first electrode located on one side of the substrate;

[0013] an insulating layer located on a side of the first electrode away from the substrate, the insulating layer comprising at least two sub-insulating layers, wherein any two adjacent sub-insulating layers have different particle compositions and / or particle contents;

[0014] The second electrode is located on a side of the insulating layer away from the substrate, and the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively.

[0015] In a third aspect, an embodiment of the present invention provides a display panel, which includes the array substrate described in the second aspect.

[0016] In a fourth aspect, an embodiment of the present invention provides a display device, which includes the display panel described in the third aspect.

[0017] The array substrate preparation method provided in an embodiment of the present invention forms an insulating layer having at least two sub-insulating layers between a first electrode and a second electrode by preparing any two adjacent sub-insulating layers in different preparation environments. This reduces the probability of impurity particles being deposited at the same location in the different sub-insulating layers formed in different preparation environments. Even if impurity particles are deposited in each sub-insulating layer, the insulating layer having multiple sub-insulating layers is not easily punctured by impurity particles, and the probability of forming dark spots on the screen decreases dramatically. Furthermore, by providing at least two sub-insulating layers, the upper sub-insulating layer can flatten impurity particles in the lower sub-insulating layer during film formation, further reducing the probability of the insulating layer rupturing. This prevents short circuits between the first and second electrodes on either side of the insulating layer, reduces the probability of forming dark spots on the screen, and improves the display quality and reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, although the drawings described below are some specific embodiments of the present invention, for those skilled in the art, the basic concepts of the device structure, driving method and manufacturing method disclosed and suggested by the various embodiments of the present invention can be expanded and extended to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0019] Figure 1 This is a schematic diagram of a top view of an array substrate in the prior art;

[0020] Figure 2 yes Figure 1 The schematic cross-sectional structure diagram of the array substrate along the section line aa' is shown;

[0021] Figure 3 yes Figure 2 A partial enlarged schematic diagram of area A in the middle;

[0022] Figure 4 yes Figure 2 Another partial enlarged schematic diagram of area A in the middle;

[0023] Figure 5 yes Figure 2 Another partial enlarged schematic diagram of area A in the middle;

[0024] Figure 6 This is a structural diagram of an array substrate provided by an embodiment of the present invention;

[0025] Figure 7 yes Figure 6 A partial enlarged schematic diagram of the middle B area;

[0026] Figure 8 yes Figure 6 Another partial enlarged schematic diagram of area B in the middle;

[0027] Figure 9 is a flow chart of a method for preparing an array substrate provided by an embodiment of the present invention;

[0028] Figure 10 is a flow chart of another method for preparing an array substrate provided by an embodiment of the present invention;

[0029] Figure 11 is a flow chart of another method for preparing an array substrate provided by an embodiment of the present invention;

[0030] Figure 12 is a structural schematic diagram of another array substrate provided by an embodiment of the present invention;

[0031] Figure 13 This is a structural diagram of another array substrate provided by an embodiment of the present invention;

[0032] Figure 14 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0033] Figure 15 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the present invention more clear, the following will refer to the accompanying drawings of the embodiments of the present invention to clearly and completely describe the technical solutions of the present invention through implementation methods. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the basic concepts disclosed and suggested by the embodiments of the present invention, all other embodiments obtained by those skilled in the art are within the scope of protection of the present invention.

[0035] Figure 1 This is a schematic diagram of a top view structure of an array substrate in the prior art, such as Figure 1As shown, the array substrate includes a pixel circuit 11', a first electrode 12' and a second electrode 13', wherein the pixel circuit 11' is electrically connected to the first electrode 12' for providing a display signal to the first electrode 12', and the second electrode 13' is electrically connected to a common voltage signal line (not shown in the figure) for receiving a common voltage signal. The first electrode 12' and the second electrode 13' work together to control the liquid crystal to deflect within the plane, so that the display device including the array substrate structure can display normally. The pixel circuit 11' may include at least one thin film transistor, which may include an active layer, a gate, a source and a drain. The source and drain are respectively in contact with the source region and the drain in the active layer, and the gate corresponds to the channel region in the active layer. The array substrate may also include a scan line 14' and a data line 15'. The scan line 14' is electrically connected to the gate, and the data line 15' is electrically connected to the source. The scan signal output by the scan line 14' controls the transistor to turn on and writes the data signal in the data line 15' into the first electrode 12'.

[0036] Further, Figure 2 yes Figure 1 The cross-sectional structure diagram of the array substrate along the section line aa' is shown in FIG. Figure 3 yes Figure 2 A partial enlarged schematic diagram of area A in the middle. Figure 4 yes Figure 2 Another partial enlarged schematic diagram of the A area, for example, refer to Figures 2 to 4 , the array substrate also includes an insulating layer 16' located between the first electrode layer 12' and the second electrode layer 13', and the insulating layer 16' is used to prevent a short circuit between the first electrode 12' and the second electrode 13'. The inventors of the present application have found that in the actual process, impurity particles and other film-forming foreign matter 17' in the film-forming environment of the insulating layer 16' will enter the insulating layer 16', and the film-forming foreign matter 17' can easily puncture the insulating layer 16', causing a short circuit between the first electrode 12' and the second electrode 13'. After the short circuit, the first electrode 12' and the second electrode 13' have the same potential, and no electric field can be formed between them, and the liquid crystal cannot be driven to deflect, thereby causing dark spots on the display. Furthermore, the film-forming foreign matter 17' may have two sizes of different sizes. The larger size of the film-forming foreign matter 17' can be referred to Figure 3 and Figure 4 As shown, the smaller film-forming foreign matter 17' can be referred to Figure 5 For details, refer to Figure 2 If the film-forming foreign matter 17' is conductive, the first electrode layer 12' and the second electrode layer 13' can be connected to form a short circuit; Figure 4If the film-forming foreign matter 17' is non-conductive, but it punctures the insulating layer 16' during the coating process, the second electrode layer 13' will enter the gap of the insulating layer 16' and contact the first electrode layer 12' to form a short circuit when the second electrode layer 13' is coated. After the first electrode layer 12' and the second electrode layer 13' are short-circuited, the screen cannot display images and dark spots will appear on the screen, affecting the display effect of the display panel. Figure 5 When the size of the film-forming foreign matter 17 ′ is small, there may be a situation where a plurality of film-forming foreign matter 17 ′ is stacked and causes a short circuit between the first electrode layer 12 ′ and the second electrode layer 13 ′.

[0037] To solve the above problems, an embodiment of the present invention provides a method for preparing an array substrate, the method comprising:

[0038] providing a substrate;

[0039] Prepare a first electrode on one side of the substrate;

[0040] An insulating layer is formed on a side of the first electrode away from the substrate, wherein the insulating layer includes at least two sub-insulating layers, and particles of any two adjacent sub-insulating layers are prepared in different environments;

[0041] A second electrode is prepared on a side of the insulating layer away from the substrate, and the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively.

[0042] The array substrate preparation method provided in an embodiment of the present invention forms an insulating layer having at least two sub-insulating layers between a first electrode and a second electrode by preparing any two adjacent sub-insulating layers in different preparation environments. This reduces the probability of impurity particles being deposited at the same location in the different sub-insulating layers formed in different preparation environments. Even if impurity particles are deposited in each sub-insulating layer, the insulating layer having multiple sub-insulating layers is not easily punctured by impurity particles, and the probability of forming dark spots on the screen decreases dramatically. Furthermore, by providing at least two sub-insulating layers, the upper sub-insulating layer can flatten impurity particles in the lower sub-insulating layer during film formation, further reducing the probability of the insulating layer rupturing. This prevents short circuits between the first and second electrodes on either side of the insulating layer, reduces the probability of forming dark spots on the screen, and improves the display quality and reliability of the display panel.

[0043] The above is the core idea of ​​the present invention. The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0044] Figure 6 is a structural diagram of an array substrate provided by an embodiment of the present invention. Figure 7 yes Figure 6 A partial enlarged schematic diagram of area B in the middle. Figure 8 yes Figure 4 Another partial enlarged schematic diagram of area B in the middle, Figure 9 is a flow chart of a method for preparing an array substrate provided by an embodiment of the present invention. For example, referring to Figures 6 to 9 , the preparation method comprises:

[0045] S110 , providing a substrate.

[0046] S120, preparing a first electrode on one side of the substrate.

[0047] The material and preparation method of the first electrode 300 are not limited. For example, the first electrode 300 may be made of a conductive material such as indium tin oxide, and may be prepared by methods such as evaporation.

[0048] S130 , preparing an insulating layer on a side of the first electrode away from the substrate, wherein the insulating layer includes at least two sub-insulating layers, and particles of any two adjacent sub-insulating layers are prepared in different environments.

[0049] Optionally, a chemical vapor deposition method is used to prepare an insulating layer on a side of the first electrode away from the substrate.

[0050] The insulating layer includes two or more sub-insulating layers, and each sub-insulating layer can be prepared by chemical vapor deposition, and the materials of any two sub-insulating layers can be the same or different, as long as the particle preparation environments of any two adjacent sub-insulating layers are different. It should be noted that the different particle preparation environments of any two adjacent sub-insulating layers mean that when preparing any two adjacent sub-insulating layers, the environments in which different sub-insulating layers are located are different. Due to the different preparation environments, the types, sizes and distributions of impurity particles in different preparation environments may be different, and the deposition positions of impurity particles in the corresponding sub-insulating layers in the different sub-insulating layers finally formed are also different. Among them, different deposition positions can be understood as that the orthographic projections of impurity particles in different sub-insulating layers on the plane where the substrate is located do not overlap.

[0051] Specifically, chemical vapor deposition (CVD) involves introducing vapors of gaseous or liquid reactants containing the elements that make up the thin film, along with other gases required for the reaction, into a reaction chamber. A chemical reaction occurs on the film surface, and solid products are deposited onto the surface to form a thin film. CVD can employ a variety of different CVD processes, including metal-organic, plasma CVD, laser CVD, low-pressure CVD, and ultra-vacuum CVD. These processes allow for precise control of film thickness and structure, resulting in high-quality films.

[0052] For the convenience of explanation, the following example is taken as follows: the insulating layer includes three sub-insulating layers, the number of impurity particles in each sub-insulating layer is 1, and the preparation environments of any two sub-insulating layers are different. Figures 6 to 8 The insulating layer 400 includes a first sub-insulating layer 410, a second sub-insulating layer 420, and a third sub-insulating layer 430 stacked in sequence. The particles of the first sub-insulating layer 410, the second sub-insulating layer 420, and the third sub-insulating layer 430 are prepared in different environments. That is, the impurity particles in the preparation environment of the first sub-insulating layer 410 are first particles 11, the impurity particles in the preparation environment of the second sub-insulating layer 420 are second particles 12, and the impurity particles in the preparation environment of the third sub-insulating layer 430 are third particles 13. Among them, if any one or more of the types, sizes, and distributions of the first particles 11, the second particles 12, and the third particles 13 are different, then the deposition positions of the first particles 11 in the first sub-insulating layer 410, the second particles 12 in the second sub-insulating layer 420, and the third particles 13 in the third sub-insulating layer 430 are all different. In other words, the orthographic projection of the first particle 11 on the plane where the substrate 100 is located does not overlap with the orthographic projection of the second particle 12 on the plane where the substrate 100 is located, the orthographic projection of the first particle 11 on the plane where the substrate 100 is located does not overlap with the orthographic projection of the third particle 13 on the plane where the substrate 100 is located, and the orthographic projection of the second particle 12 on the plane where the substrate 100 is located does not overlap with the orthographic projection of the third particle 13 on the plane where the substrate 100 is located. The first particle 11 may be located on the surface of the first sub-insulating layer 410 or may penetrate at least a portion of the first sub-insulating layer 410, the second particle 12 may be located on the surface of the second sub-insulating layer 420 or may penetrate at least a portion of the second sub-insulating layer 420, and similarly, the third particle 13 may be located on the surface of the third sub-insulating layer 430 or may penetrate at least a portion of the third sub-insulating layer 430. Since the orthographic projections of the first particle 11, the second particle 12 and the third particle 13 on the plane where the substrate 100 is located do not overlap, even if the first particle 11, the second particle 12 and the third particle 13 all penetrate the corresponding sub-insulating layer, the finally formed insulating layer 400 will not be punctured by impurity particles, and the probability of forming dark spots on the screen will drop sharply.

[0053] Table 1 below shows the changes in product defect rates before and after improvements for different product sizes and different film layer structures.

[0054] Table 1

[0055]

[0056] It can be seen from Table 1 above that by setting different particle preparation environments for any two adjacent sub-insulating layers, the product defect rate can be significantly reduced, that is, the probability of dark spots on the screen can be reduced.

[0057] Further, refer to Figure 8If the first particles 11 are relatively large, they not only penetrate the first sub-insulating layer 410 but also extend beyond the first sub-insulating layer 410 to contact the second sub-insulating layer 420 located above the first sub-insulating layer 410. While the second particles 12 do not penetrate the second sub-insulating layer 420, they extend beyond the second sub-insulating layer 420 to contact the third sub-insulating layer 430 located above the second sub-insulating layer 420. During the fabrication process, the second sub-insulating layer 420 can be planarized by covering the first particles 11, and similarly, the third sub-insulating layer 430 can be planarized by covering the second particles 12, further reducing the probability of cracking in the insulating layer 400.

[0058] It should be noted that Figures 6 to 8 Taking the example that the insulating layer 400 includes three sub-insulating layers and the preparation environments of any two sub-insulating layers are different, this is not limiting. Those skilled in the art can set the number of sub-insulating layers according to actual needs, as long as the particle preparation environments of any two adjacent sub-insulating layers in the insulating layer 400 are different.

[0059] It should also be noted that the first electrode and the second electrode in the embodiment of the present invention can be a pixel electrode and a common electrode, and the pixel electrode and the common electrode respectively receive different voltage signals. An electric field is formed between the pixel electrode and the common electrode to control the deflection of the liquid crystal molecules in the plane, thereby achieving different light-emitting effects. It is understandable that the first electrode and the second electrode in the embodiment of the present invention can also be other structures, as long as the first electrode and the second electrode receive different voltage signals, they are all within the protection scope of the embodiment of the present invention. For example, the first electrode can be the active layer of a thin film transistor, the second electrode can be the gate of the thin film transistor, and the insulating layer can be the insulating layer between the active layer and the gate, that is, the gate insulating layer. The active layer can, for example, receive a data signal, and the gate can, for example, receive a scan signal. Under the common control of the scan signal and the data signal, the thin film transistor is controlled to turn on and transmit the data signal to the first electrode or the second electrode.

[0060] In summary, due to the different preparation environments of different sub-insulating layers, the types, sizes, and distributions of impurity particles in different preparation environments may be different. Compared to forming multiple sub-insulating layers in the same preparation environment, the probability of impurity particles being deposited at different locations in different sub-insulating layers formed in different preparation environments is higher, or the probability of impurity particles being deposited at the same location is lower. Since the insulating layer has multiple sub-insulating layers, impurity particles are required to be present at the same location in the multiple sub-insulating layers, and the impurity particles in each layer must penetrate the sub-insulating layer in which they are located before they can penetrate the entire insulating layer, thereby allowing the first and second electrodes on both sides of the insulating layer to conduct. Therefore, even if impurity particles are deposited in each sub-insulating layer, due to the different preparation environments of the two adjacent sub-insulating layers, the types, sizes, and deposition locations of the impurity particles in the two adjacent sub-insulating layers are different. The insulating layer finally formed with multiple sub-insulating layers is not easily penetrated by impurity particles, and the probability of forming dark spots on the screen will drop sharply. In addition, at least two sub-insulating layers are provided so that the sub-insulating layer located on the upper layer can flatten the impurity particles in the sub-insulating layer located on the lower layer during film formation, thereby further reducing the probability of cracking of the insulating layer, thereby avoiding short circuit between the first electrode and the second electrode located on both sides of the insulating layer, reducing the probability of forming dark spots on the screen, and improving the display effect and reliability of the display panel.

[0061] S140 , preparing a second electrode on a side of the insulating layer away from the substrate, and the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively.

[0062] The first electrode 300 and the second electrode 500 are electrically connected to different signal transmission terminals, respectively, to transmit different electrical signals, thereby jointly controlling the display panel to display images. The material and preparation method of the second electrode 500 are also not limited. For example, the second electrode 500 can be a conductive material such as indium tin oxide, and can be prepared by methods such as evaporation.

[0063] The array substrate preparation method provided in an embodiment of the present invention forms an insulating layer having at least two sub-insulating layers between a first electrode and a second electrode by preparing any two adjacent sub-insulating layers in different preparation environments. This reduces the probability of impurity particles being deposited at the same location in the different sub-insulating layers formed in different preparation environments. Even if impurity particles are deposited in each sub-insulating layer, the insulating layer having multiple sub-insulating layers is not easily punctured by impurity particles, and the probability of forming dark spots on the screen decreases dramatically. Furthermore, by providing at least two sub-insulating layers, the upper sub-insulating layer can flatten impurity particles in the lower sub-insulating layer during film formation, further reducing the probability of the insulating layer rupturing. This prevents short circuits between the first and second electrodes on either side of the insulating layer, reduces the probability of forming dark spots on the screen, and improves the display quality and reliability of the display panel.

[0064] Figure 10 is a flow chart of another method for preparing an array substrate provided by an embodiment of the present invention, such as Figure 10 As shown, the preparation method comprises:

[0065] S210 , providing a substrate.

[0066] S220 , preparing a first electrode on one side of the substrate.

[0067] S230 , using different sub-insulating layer preparation gases and / or different gas flow rates in different preparation chambers to prepare two adjacent sub-insulating layers on a side of the first electrode away from the substrate.

[0068] In accordance with actual processes, to achieve different particle preparation environments for any two adjacent sub-insulating layers, the two adjacent sub-insulating layers can be prepared in different preparation chambers. The differences in preparation chambers are reflected in the use of different sub-insulating layer preparation gases and / or gas flow rates when preparing the sub-insulating layers in different preparation chambers.

[0069] For example, refer to Figures 6 to 8 The adjacent first sub-insulating layer 410 and second sub-insulating layer 420 are prepared in different preparation chambers, and the preparation environments of the first sub-insulating layer 410 and the second sub-insulating layer 420 are different. Specifically, the first sub-insulating layer 410 is prepared in a first preparation chamber, and the second sub-insulating layer 420 is prepared in a second preparation chamber.

[0070] For example, the gases used in the first preparation chamber and the second preparation chamber for preparing the sub-insulating layer are different. The gases used in the first preparation chamber for preparing the sub-insulating layer may be SiH4, NH3 and N2, and the gases used in the second preparation chamber for preparing the sub-insulating layer may be SiH4 and NO2. Then, the first sub-insulating layer 410 formed correspondingly is SiN x The second sub-insulating layer 420 is SiO x , that is, the materials of the first sub-insulating layer 410 and the second sub-insulating layer 420 are different, and the insulation effects are also different.

[0071] Taking the different gas flow rates used in the first preparation chamber and the second preparation chamber as an example, if the sub-insulating layer preparation gases used in the first preparation chamber and the second preparation chamber are both SiH4, NH3 and N2, the corresponding first sub-insulating layer 410 and the second sub-insulating layer 420 are both SiN x, wherein the gas flow rate used in the first preparation chamber can be as follows: SiH4 is 600sccm~800sccm, NH3 is 3100sccm~3400sccm, and N2 is 6000sccm~8000sccm; the gas flow rate used in the second preparation chamber can be as follows: SiH4 is 220sccm~230sccm, NH3 is 2100sccm~2300sccm, and N2 is 11000sccm~13000sccm, that is, when the first preparation chamber and the second preparation chamber use the same sub-insulating layer preparation gas, the gas flow rates of the same seed insulating layer preparation gas in different preparation chambers can be different, then the corresponding first sub-insulating layer 410 and the second sub-insulating layer 420 formed are the same material, but have different densities and different insulating effects.

[0072] For example, the gas and gas flow rate used in the first preparation chamber and the second preparation chamber for preparing the sub-insulating layer are different. The gas used in the first preparation chamber for preparing the sub-insulating layer may be SiH4, NH3 and N2, and the gas used in the second preparation chamber for preparing the sub-insulating layer may be SiH4 and NO2. Then, the first sub-insulating layer 410 formed correspondingly is SiN x The second sub-insulating layer 420 is SiO x At the same time, the gas flow rates used in the first preparation chamber can be as follows: SiH4 is 600sccm~800sccm, NH3 is 3100sccm~3400sccm, and N2 is 6000sccm~8000sccm. The gas flow rates used in the second preparation chamber can be as follows: SiH4 is 600sccm~800sccm, and NO2 is 6000sccm~8000sccm.

[0073] S240 , preparing a second electrode on a side of the insulating layer away from the substrate, and the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively.

[0074] The array substrate preparation method provided by an embodiment of the present invention forms an insulating layer having at least two sub-insulating layers between a first electrode and a second electrode by preparing any two adjacent sub-insulating layers in different preparation chambers using different sub-insulating layer preparation gases and / or different gas flow rates. Due to the different preparation environments in different preparation chambers, the types, sizes, and distributions of impurity particles in these environments may vary. This reduces the probability of impurity particles being deposited at the same location in different sub-insulating layers prepared in different preparation chambers. Even if impurity particles are deposited in each sub-insulating layer, the insulating layer having multiple sub-insulating layers is less likely to be punctured by impurity particles, significantly reducing the probability of screen dark spots. Furthermore, by providing at least two sub-insulating layers, the upper sub-insulating layer can flatten impurity particles in the lower sub-insulating layer during film formation, further reducing the probability of insulation layer cracking. This prevents short circuits between the first and second electrodes on either side of the insulation layer, reduces the probability of screen dark spots, and improves the display quality and reliability of the display panel.

[0075] refer to Figure 6 On the basis of the above embodiment, optionally, the insulating layer 400 includes a first sub-insulating layer 410, a second sub-insulating layer 420 and a third sub-insulating layer 430 that are stacked; the preparation chamber of the third sub-insulating layer 430 is the same preparation chamber as the preparation chamber of the first sub-insulating layer 410; the sub-insulating layer preparation gas of the third sub-insulating layer 430 is the same as the sub-insulating layer preparation gas of the first sub-insulating layer 410, and the gas flow rate of the third sub-insulating layer 430 is the same as the gas flow rate of the first sub-insulating layer 410.

[0076] For example, refer to Figure 6 , the first sub-insulating layer 410 in the insulating layer 400 contacts the first electrode 300, and the third sub-insulating layer 430 in the insulating layer 400 contacts the second electrode 500. By arranging the first sub-insulating layer 410 and the third sub-insulating layer 430 in the same preparation chamber and using the same sub-insulating layer preparation gas and gas flow rate, the first sub-insulating layer 410 and the third sub-insulating layer 430 have the same material and density. As a result, the contact resistance between the first sub-insulating layer 410 and the first electrode 300 is the same as the contact resistance between the third sub-insulating layer 430 and the second electrode 500, which can improve the display effect.

[0077] It can be understood that when the insulating layer includes more than three sub-insulating layers, the two sub-insulating layers in the insulating layer that are in contact with the first electrode and the second electrode respectively can also be arranged in the same preparation chamber, and the same sub-insulating layer preparation gas and gas flow rate can be used for preparation, so that the contact resistance between the two sub-insulating layers and the first electrode and the second electrode respectively is the same, thereby improving the display effect.

[0078] refer to Figures 6 to 8Optionally, the insulating layer 400 includes a first sub-insulating layer 410, a second sub-insulating layer 420 and a third sub-insulating layer 430 that are stacked; the preparation chamber of the third sub-insulating layer 430 is different from the preparation chamber of the first sub-insulating layer 410 and the preparation chamber of the second sub-insulating layer 420; the sub-insulating layer preparation gas of the third sub-insulating layer 430 is different from the sub-insulating layer preparation gas of the first sub-insulating layer 410 and the sub-insulating layer preparation gas of the second sub-insulating layer 420, and / or the gas flow rate of the third sub-insulating layer 430 is different from the gas flow rate of the first sub-insulating layer 410 and the gas flow rate of the second sub-insulating layer 420.

[0079] In this embodiment, the first sub-insulating layer 410, the second sub-insulating layer 420 and the third sub-insulating layer 430 are respectively prepared in different preparation chambers using different sub-insulating layer preparation gases and / or gas flow rates, so that the preparation environments of the first sub-insulating layer 410, the second sub-insulating layer 420 and the third sub-insulating layer 430 are all different. The first particles 11 in the prepared first sub-insulating layer 410, the second particles 12 in the second sub-insulating layer 420 and the third particles 13 in the third sub-insulating layer 430 are all deposited at different positions in the corresponding sub-insulating layers, which can greatly reduce the probability of the insulating layer 400 breaking, thereby avoiding short circuit between the first electrode 300 and the second electrode 500 located on both sides of the insulating layer 400, and reducing the probability of forming dark spots on the screen.

[0080] It can be understood that when the insulating layer includes more than three sub-insulating layers, any two sub-insulating layers can be prepared in different preparation chambers using different sub-insulating layer preparation gases and / or gas flow rates, so that the probability of impurity particles in different sub-insulating layers being deposited at the same position is smaller, thereby reducing the probability of the insulating layer breaking, thereby avoiding a short circuit between the first electrode and the second electrode located on both sides of the insulating layer, reducing the probability of forming dark spots on the screen, and improving the display effect and reliability of the display panel.

[0081] Figure 11 is a flow chart of another method for preparing an array substrate provided by an embodiment of the present invention, such as Figure 11 As shown, the preparation method comprises:

[0082] S310 , providing a substrate.

[0083] S320 , preparing a first electrode on one side of the substrate.

[0084] S330 , depositing a first sub-insulating layer material on a side of the first electrode away from the substrate using a first deposition rate to prepare a first sub-insulating layer.

[0085] S340 , depositing a second sub-insulating layer material on a side of the first sub-insulating layer away from the substrate using a second deposition rate to prepare a second sub-insulating layer; the first deposition rate is greater than the second deposition rate.

[0086] Figure 12 FIG. 1 is a structural diagram of another array substrate provided by an embodiment of the present invention. Figure 12 As shown, the insulating layer 400 in this embodiment includes a first sub-insulating layer 410 and a second sub-insulating layer 420, which are stacked. The second sub-insulating layer 420 is located on the side of the first sub-insulating layer 410 close to the second electrode 500, that is, the second sub-insulating layer 420 is located above the first sub-insulating layer 410. The first sub-insulating layer 410, located at the bottom layer, is formed using a higher deposition rate, namely a first deposition rate, to ensure production efficiency and increase production capacity. The second sub-insulating layer 420, located at the top layer, is formed using a lower deposition rate, namely a second deposition rate, so that the second sub-insulating layer 420 has better density and ensures insulation effect.

[0087] It should be noted that, in other embodiments, the deposition rates of the first sub-insulating layer 410 and the second sub-insulating layer 420 may be the same, and those skilled in the art may also design the deposition rates of the first sub-insulating layer 410 and the second sub-insulating layer 420 according to actual needs. For example, if a better film quality of the insulating layer 400 is required, the first sub-insulating layer 410 and the second sub-insulating layer 420 may both be formed using a lower deposition rate. If a faster deposition process is required, the first sub-insulating layer 410 and the second sub-insulating layer 420 may both be formed using a higher deposition rate.

[0088] S350 , preparing a second electrode on a side of the insulating layer away from the substrate, and the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively.

[0089] The array substrate fabrication method provided in an embodiment of the present invention, by fabricating adjacent first and second sub-insulating layers in different fabrication environments, reduces the probability of impurity particles in the first and second sub-insulating layers being deposited at the same location. This reduces the probability of cracking the insulating layer, thereby preventing short circuits between the first and second electrodes on either side of the insulating layer, reducing the probability of dark spots on the screen, and improving the display quality and reliability of the display panel. Furthermore, by setting a higher first deposition rate for the lower first sub-insulating layer and a lower second deposition rate for the upper second sub-insulating layer, fabrication efficiency is guaranteed, production capacity is increased, and the insulating layer is given greater density, ensuring insulation quality and further improving the reliability of the display panel.

[0090] Based on the same inventive concept, an embodiment of the present invention further provides an array substrate, exemplarily, referring to Figure 12The array substrate 10 includes: a substrate 100; a first electrode 300 located on one side of the substrate 100; an insulating layer 400 located on a side of the first electrode 300 away from the substrate 100, the insulating layer 400 including at least two sub-insulating layers (a first sub-insulating layer 410 and a second sub-insulating layer 420), and the particle composition and / or particle content of any two adjacent sub-insulating layers are different; a second electrode 500 located on a side of the insulating layer 400 away from the substrate 100, the first electrode 300 and the second electrode 500 being electrically connected to different signal transmission terminals, respectively.

[0091] It should be noted that because the particle preparation environments of any two adjacent sub-insulating layers are different, the types, sizes, and distributions of impurity particles in these different preparation environments may vary. Consequently, the types of impurity particles in the resulting different sub-insulating layers and the locations at which they are deposited in the corresponding sub-insulating layers will also vary. In other words, the particle composition and / or particle content of any two adjacent sub-insulating layers will differ. The term "different deposition locations" can be understood as meaning that the orthographic projections of the impurity particles in the different sub-insulating layers on the substrate plane do not overlap.

[0092] The array substrate provided by an embodiment of the present invention utilizes an insulating layer comprising at least two sub-insulating layers, wherein the particle composition and / or particle content of any two adjacent sub-insulating layers differ. This reduces the types of impurity particles in any two adjacent sub-insulating layers and the probability of impurity particles being deposited at the same location. Even if impurity particles are deposited in each sub-insulating layer, the insulating layer comprising multiple sub-insulating layers is less susceptible to being punctured by impurity particles, significantly reducing the probability of screen dark spots. Furthermore, by providing at least two sub-insulating layers, the upper sub-insulating layer can flatten impurity particles in the lower sub-insulating layer during film formation, further reducing the probability of insulation layer cracking. This prevents short circuits between the first and second electrodes on either side of the insulating layer, reduces the probability of screen dark spots, and improves the display quality and reliability of the display panel.

[0093] refer to Figure 12 Taking into account the actual process and the insulation effect of the insulating layer 400, the thickness d of the insulating layer 400 can optionally meet the requirement of 2700μm≤d≤3300μm. This ensures a good insulation effect of the insulating layer 400 on the one hand, and ensures that the preparation process of the insulating layer 400 matches the existing process on the other hand, thereby reducing the difficulty of preparing the insulating layer 400 and improving the preparation efficiency. It should be noted that if the thickness of the insulating layer 400 is too small, the thickness of the single insulating layer (the first sub-insulating layer 410 or the second sub-insulating layer 420) will be even smaller, and the time required to form the film layer will be even shorter. This will pose a great challenge to the production operation speed and the setting control accuracy.

[0094] refer to Figure 12Optionally, the insulating layer 400 includes at least two stacked sub-insulating layers; the materials of the two adjacent sub-insulating layers are different.

[0095] Since the materials of any two adjacent sub-insulating layers are different, the particle preparation environment of any two adjacent sub-insulating layers is also different. Combined with the actual process, the two adjacent sub-insulating layers can be prepared separately in different preparation chambers, and the sub-insulating layer preparation gases used in different chambers are different, so that two sub-insulating layers of different materials can be prepared in different preparation chambers, and the particle composition and / or particle content of the two adjacent sub-insulating layers are different, so that the types of impurity particles in any two adjacent sub-insulating layers and the probability of impurity particles being deposited at the same position are small, which can reduce the probability of the insulating layer breaking, avoid the first electrode and the second electrode located on both sides of the insulating layer from being short-circuited, and reduce the probability of forming dark spots on the screen.

[0096] It should be noted that the embodiment of the present invention does not limit the material of each sub-insulating layer. The material of the sub-insulating layer can be any insulating material such as silicon nitride or silicon oxide, as long as the materials of any two adjacent sub-insulating layers are different.

[0097] refer to Figure 12 Optionally, the insulating layer 400 includes at least two stacked sub-insulating layers; the compactness of two adjacent sub-insulating layers is different.

[0098] The density of the film layer is related to the gas flow rate used during film formation. Different gas flow rates result in different film densities. Since the density of any two adjacent sub-insulating layers is different, the particle preparation environment of any two adjacent sub-insulating layers is also different. In combination with the actual process, two adjacent sub-insulating layers can be prepared separately in different preparation chambers, and the gas flow rates used in different chambers are different. In this way, two sub-insulating layers with different densities can be prepared in different preparation chambers, and the particle composition and / or particle content of the two adjacent sub-insulating layers are different. This reduces the types of impurity particles in any two adjacent sub-insulating layers and the probability of impurity particles being deposited at the same location. This can reduce the probability of the insulating layer rupturing, avoid short circuiting between the first electrode and the second electrode on both sides of the insulating layer, and reduce the probability of forming dark spots on the screen.

[0099] refer to Figure 12 Optionally, the sub-insulating layer in contact with the first electrode 300 and the sub-insulating layer in contact with the second electrode 500 are made of the same material.

[0100] By setting the materials of the two sub-insulating layers in the insulating layer that are in contact with the first electrode and the second electrode respectively to be the same, the contact resistance between the two sub-insulating layers and the first electrode and the second electrode respectively is made the same, which can improve the display effect.

[0101] refer to Figure 6Optionally, the insulating layer 400 includes a first sub-insulating layer 410, a second sub-insulating layer 420 and a third sub-insulating layer 430 that are stacked, and the material of the second sub-insulating layer 420 includes silicon oxide.

[0102] Since silicon oxide has a high hardness, the second sub-insulating layer 420 located between the first sub-insulating layer 410 and the third sub-insulating layer 430 is made of silicon oxide with a relatively high hardness, which can ensure that impurity particles have difficulty in puncturing the insulating layer 400, further reducing the probability of dark spots on the screen.

[0103] Optionally, the first electrode 300 includes a pixel electrode, and the second electrode 500 includes a common electrode; or, the first electrode 300 includes a common electrode, and the second electrode 500 includes a pixel electrode; the array substrate 10 also includes a pixel circuit, a scanning signal line, a data signal line and a common voltage line; the pixel circuit is electrically connected to the scanning signal line, the data signal line and the pixel electrode, respectively; and the common voltage line is electrically connected to the common electrode.

[0104] The following description will be made by taking the first electrode 300 as a pixel electrode and the second electrode 500 as a common electrode as an example. Figure 13 is a structural diagram of another array substrate provided by an embodiment of the present invention, such as Figure 13 As shown, the array substrate 10 includes a stacked substrate 100, an active layer 201, an interlayer insulating layer 202, a gate insulating layer 203, a planarizing layer 204, an insulating layer 400, and other film layers, as well as a pixel circuit 205, a pixel electrode 206, and a common electrode 207. The pixel circuit 205 is generally composed of a thin film transistor. Figure 13 Only one thin film transistor in the pixel circuit 205 is shown, and the thin film transistor includes a gate G, a source S, and a drain D.

[0105] The pixel circuit 205 is electrically connected to the scanning signal line, the data signal line and the pixel electrode 206 respectively. Specifically, the scanning signal line is electrically connected to the gate G in the pixel circuit 205, transmits the scanning signal to the pixel circuit 205, and controls the working state of the thin film transistor; the data signal line is electrically connected to the source S in the pixel circuit 205, and the data signal line transmits the data signal to the pixel circuit 205 when the thin film transistor is turned on; the pixel electrode 206 is electrically connected to the drain D in the pixel circuit 205, and the data signal line writes the data signal to the pixel electrode 206 through the pixel circuit 205; the common voltage line is electrically connected to the common electrode 207, and transmits the common signal to the common electrode 207, thereby forming an electric field between the pixel electrode 206 and the common electrode 207. By controlling the voltage of the electric field, the deflection of the liquid crystal molecules in the display panel can be adjusted to form different display images. The first sub-insulating layer 410 and the second sub-insulating layer 420 serve as insulating layers between the pixel electrode 206 and the common electrode 207, which can ensure insulation between the pixel electrode 206 and the common electrode 207, ensure that no short circuit occurs between the pixel electrode 206 and the common electrode 207, ensure that the pixel electrode 206 and the common electrode 207 can form a planar electric field, control the deflection of the liquid crystal molecules in the plane, and ensure normal light emission.

[0106] It should be noted that although Figure 13-14 In the structure shown, the thin film transistor in the pixel circuit 205 is a top-gate structure, but the embodiments of the present application are not limited to this. There is no restriction on the specific type of the thin film transistor in the embodiments of the present application. For example, it can also be a bottom-gate structure.

[0107] An embodiment of the present invention further provides a display panel, illustratively, Figure 14 is a structural diagram of a display panel provided by an embodiment of the present invention, such as Figure 14 As shown, the display panel 20 may be a liquid crystal display panel, comprising an array substrate 10 and a color filter substrate 700 disposed opposite to each other, and a liquid crystal layer 600 located between the array substrate 10 and the color filter substrate 700. The array substrate 10 may be any of the array substrates 10 provided in any embodiment of the present invention. Since the display panel 20 includes any of the aforementioned array substrates 10, the display panel 20 possesses the corresponding functions and benefits of the array substrate 10.

[0108] An embodiment of the present invention further provides a display device, illustratively, Figure 15 is a structural diagram of a display device provided by an embodiment of the present invention, such as Figure 15 As shown, the display device includes the display panel 20 provided by any embodiment of the present invention, and has the corresponding functions and beneficial effects of the display panel 20.

[0109] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0110] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing an array substrate, characterized in that: include: providing a substrate; preparing a first electrode on one side of the substrate; An insulating layer is formed on a side of the first electrode away from the substrate by chemical vapor deposition, wherein the insulating layer includes at least two sub-insulating layers, and particles of any two adjacent sub-insulating layers are prepared in different environments; A second electrode is formed on a side of the insulating layer away from the substrate, wherein the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively; The insulating layer comprises at least two sub-insulating layers stacked in layers; Preparing an insulating layer on a side of the first electrode away from the substrate, comprising: Two adjacent sub-insulating layers are prepared on a side of the first electrode away from the substrate using different sub-insulating layer preparation gases and / or different gas flow rates in different preparation chambers.

2. The preparation method according to claim 1, characterized in that The insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer which are stacked; The preparation chamber for the third sub-insulating layer and the preparation chamber for the first sub-insulating layer are the same preparation chamber; The gas used to prepare the third sub-insulating layer is the same as that used to prepare the first sub-insulating layer, and the gas flow rate of the third sub-insulating layer is the same as that of the first sub-insulating layer.

3. The preparation method according to claim 1, characterized in that The insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer which are stacked; The preparation chamber for the third sub-insulating layer is different from the preparation chamber for the first sub-insulating layer and the preparation chamber for the second sub-insulating layer; The sub-insulating layer preparation gas of the third sub-insulating layer is different from the sub-insulating layer preparation gas of the first sub-insulating layer and the sub-insulating layer preparation gas of the second sub-insulating layer, and / or the gas flow rate of the third sub-insulating layer is different from the gas flow rate of the first sub-insulating layer and the gas flow rate of the second sub-insulating layer.

4. The preparation method according to claim 1, characterized in that The insulating layer includes a first sub-insulating layer and a second sub-insulating layer that are stacked; Preparing an insulating layer on a side of the first electrode away from the substrate, comprising: Depositing a first sub-insulating layer material on a side of the first electrode away from the substrate using a first deposition rate to prepare a first sub-insulating layer; A second sub-insulating layer material is deposited on a side of the first sub-insulating layer away from the substrate using a second deposition rate to prepare a second sub-insulating layer; the first deposition rate is greater than the second deposition rate.

5. An array substrate, characterized in that: include: substrate; a first electrode located on one side of the substrate; an insulating layer located on a side of the first electrode away from the substrate, the insulating layer comprising at least two sub-insulating layers, wherein any two adjacent sub-insulating layers have different particle compositions and / or particle contents; the insulating layer is prepared by chemical vapor deposition, the two adjacent sub-insulating layers are prepared in different chambers, and the preparation gases and / or gas flow rates used to prepare the different sub-insulating layers are different; The second electrode is located on a side of the insulating layer away from the substrate, and the first electrode and the second electrode are electrically connected to different signal transmission terminals respectively.

6. The array substrate according to claim 5, wherein: The thickness d of the insulating layer satisfies 2700µm≤d≤3300µm.

7. The array substrate according to claim 5, wherein: The insulating layer comprises at least two sub-insulating layers stacked in layers; The materials of the two adjacent sub-insulating layers are different.

8. The array substrate according to claim 5, wherein: The insulating layer comprises at least two sub-insulating layers stacked in layers; The density of two adjacent sub-insulating layers is different.

9. The array substrate according to claim 5, wherein: The sub-insulating layer in contact with the first electrode and the sub-insulating layer in contact with the second electrode are made of the same material.

10. The array substrate according to claim 5, wherein: The insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer which are stacked, and the material of the second sub-insulating layer includes silicon oxide.

11. The array substrate according to claim 5, wherein: The first electrode comprises a pixel electrode, and the second electrode comprises a common electrode; Alternatively, the first electrode comprises a common electrode, and the second electrode comprises a pixel electrode; The array substrate further includes pixel circuits, scanning signal lines, data signal lines and common voltage lines; The pixel circuit is electrically connected to the scan signal line, the data signal line and the pixel electrode respectively; The common voltage line is electrically connected to the common electrode.

12. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 5 to 11.

13. A display device, characterized in that: The display panel comprises the display panel according to claim 12.

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