Display panel and display device

Abstract

The present invention discloses a display panel and a display device, belonging to the field of display technology. The display panel includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit includes a first transistor, the first pole of the first transistor is connected to a first reference voltage signal terminal, and the second pole of the first transistor is electrically connected to the anode of the light-emitting element; during the light-emission holding stage of the sub-pixel, a negative potential signal or a ground potential signal is applied to the first reference voltage signal terminal; the color of the first sub-pixel among the plurality of sub-pixels is different from the color of the second sub-pixel; the width-to-length ratio N1 of the channel region of the first transistor in the first sub-pixel is greater than the width-to-length ratio N2 of the channel region of the first transistor in the second sub-pixel. The display device includes the above display panel. The present invention can avoid the situation of light leakage in some color sub-pixels when other color sub-pixels emit light, and can also avoid the color deviation phenomenon of light-emitting elements of different colors at low gray levels, which is beneficial to improving the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and more specifically, to a display panel and a display device. Background Art

[0002] An Organic Light Emitting Diode (OLED) display is an active light-emitting display device, which has the advantages of simple manufacturing process, low cost, high contrast ratio, wide viewing angle, low power consumption, etc., and has been widely used in digital products, and is one of the main technologies in new display technologies. Different from the traditional LCD (Liquid Crystal Display) display method, the OLED display technology does not require a backlight, and uses a very thin organic material coating and a glass substrate. When an electric current passes through, these organic materials will emit light. The OLED mainly controls the magnitude of the output current through a TFT (Thinfilm Transistor), so as to display different brightness levels.

[0003] In the field of full-color OLED displays, the high efficiency of R / G / B three-primary color light-emitting materials is extremely important. At present, due to the nature of the materials themselves, there are significant differences in the luminous efficiency and lifespan of light-emitting materials of different colors, which easily leads to color deviation problems in low-gray-scale images when environmental fluctuations (such as changes in environmental temperature, humidity, electric field, etc.) occur. Moreover, the sub-pixels of OLEDs usually adopt an array arrangement for evaporation coating. Due to the influence of the evaporation coating process and the characteristics of the light-emitting materials, the turn-on voltages of red sub-pixels, blue sub-pixels, and green sub-pixels are different, resulting in the phenomenon that some sub-pixels steal light easily, greatly reducing the display effect.

[0004] Therefore, it is an urgent technical problem for those skilled in the art to provide a display panel and a display device that can improve the display effect without affecting the panel circuit structure and overall performance. Summary of the Invention

[0005] In view of this, the present invention provides a display panel and a display device to solve the display problems in the prior art that some sub-pixels are prone to stealing light and color deviation is likely to occur in low-gray-scale images.

[0006] The present invention discloses a display panel, comprising: a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting element connected electrically, the pixel circuit including a first transistor, a first pole of the first transistor being connected to a first reference voltage signal terminal, a second pole of the first transistor being electrically connected to an anode of the light-emitting element; wherein, in a light-emission holding stage of the sub-pixel, a negative potential signal or a ground potential signal is applied to the first reference voltage signal terminal; the plurality of sub-pixels includes at least a first sub-pixel and a second sub-pixel, the color of the first sub-pixel being different from that of the second sub-pixel; a width-to-length ratio of a channel region of the first transistor in the first sub-pixel being N1, and a width-to-length ratio of a channel region of the first transistor in the second sub-pixel being N2; wherein, N1 > N2.

[0007] Based on the same inventive concept, the present invention also discloses a display device, which includes the above display panel.

[0008] Compared with the prior art, the display panel and the display device provided by the present invention achieve at least the following beneficial effects:

[0009] In the display panel provided by the present invention, the width-to-length ratio of the channel region of the first transistor in the first sub-pixel is greater than that of the first transistor in the second sub-pixel, which can make the leakage current of the first transistor in the first sub-pixel greater than that of the first transistor in the second sub-pixel. As a result, when the light-emitting element in the first sub-pixel emits light at a low gray level, compared with the second sub-pixel, a larger current leaks out from the first transistor in the first sub-pixel, reducing the light-emitting efficiency of the light-emitting element in the first sub-pixel, which is beneficial to enhancing its brightness stability. If the light-emitting efficiency of the light-emitting element in the first sub-pixel is originally greater than that of the light-emitting element in the second sub-pixel, then by setting the width-to-length ratio of the channel region of the first transistor in the first sub-pixel to be greater than that of the first transistor in the second sub-pixel, the light-emitting efficiency of the light-emitting element in the first sub-pixel can be reduced to be as consistent as possible or basically consistent with that of the light-emitting element in the second sub-pixel. That is, the brightness fluctuation of the light-emitting element in the first sub-pixel at a low gray level is reduced, so that the brightness increase amplitude of the light-emitting element in the first sub-pixel is reduced, and it is tried to reach the same brightness increase amplitude as that of the light-emitting element in the second sub-pixel. Finally, the brightness fluctuations of light-emitting elements of different colors under environmental changes are balanced as much as possible, so that the light-emitting elements of different colors emit light normally at a low gray level, avoiding color deviation phenomena, and further enabling the white picture at a low gray level to be displayed normally, which is beneficial to improving the display effect of the display panel at a low gray level. And the present invention sets the width-to-length ratio of the channel region of the first transistor in the first sub-pixel with a small turn-on voltage to be greater than that of the first transistor in the second sub-pixel with a large turn-on voltage. Since the larger the width-to-length ratio of the channel region of a transistor, the larger the leakage current of the transistor. When the light-emitting element in the second sub-pixel is turned on and carriers migrate to the light-emitting element in the first sub-pixel, the strong leakage current performance of the first transistor in the first sub-pixel can be used to export the leakage current in the state where the first transistor in the first sub-pixel is turned off, so as to avoid the light-emitting element in the first sub-pixel from stealing light, which is beneficial to improving the display effect. The present invention balances the display effects of different color sub-pixels by setting different width-to-length ratios of the channel regions of the first transistors connected to the anodes of light-emitting elements of different colors in the display panel, avoiding the situation that some color sub-pixels steal light when other color sub-pixels emit light, and can also avoid color deviation phenomena of light-emitting elements of different colors at a low gray level. Furthermore, without affecting the panel circuit structure and overall performance, it is beneficial to improve the display effect of the display panel at a low gray level.

[0010] Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned technical effects simultaneously.

[0011] Other features and advantages of the present invention will become clear through the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings incorporated in and forming a part of the specification illustrate embodiments of the present invention and, together with the description thereof, are used to explain the principles of the present invention.

[0013] Figure 1 It is a schematic plan view of a display panel provided by an embodiment of the present invention;

[0014] Figure 2 is Figure 1 A schematic connection structure diagram of a pixel circuit and a light-emitting element included in a sub-pixel in the Q region in

[0015] Figure 3 It is a graph of the efficiency of corresponding light-emitting elements of different colors at different values of low gray levels;

[0016] Figure 4 It is a schematic diagram of the film layer structure of a first transistor in a display panel provided by an embodiment of the present invention;

[0017] Figure 5 is Figure 1 Another schematic connection structure diagram of a pixel circuit and a light-emitting element included in a sub-pixel in the Q region in

[0018] Figure 6 is Figure 1 Another schematic connection structure diagram of a pixel circuit and a light-emitting element included in a sub-pixel in the Q region in

[0019] Figure 7 is Figure 1 Another schematic connection structure diagram of a pixel circuit and a light-emitting element included in a sub-pixel in the Q region in

[0020] Figure 8 is Figure 1 A schematic connection structure diagram of a pixel circuit and a light-emitting element in a sub-pixel of

[0021] Figure 9 is Figure 1 Another schematic connection structure diagram of a pixel circuit and a light-emitting element in a sub-pixel of

[0022] Figure 10 is Figure 1 Another schematic connection structure diagram of a pixel circuit and a light-emitting element in a sub-pixel of

[0023] Figure 11 is Figure 9 The specific circuit connection structure diagram in

[0024] Figure 12 is Figure 10 The specific circuit connection structure diagram in

[0025] Figure 13 is the graph of drain current data measured at low gray levels after changing the width-to-length ratio of the channel regions of different first transistors in the pixel circuit of Figure 11 ;

[0026] Figure 14 is Figure 1 another schematic diagram of the circuit connection structure of the pixel circuit and the light-emitting element in the sub-pixel of

[0027] Figure 15 is Figure 11 a circuit layout when the circuit structure in

[0028] Figure 16 is made on the display panel; Figure 11 is another circuit layout when the circuit structure in

[0029] Figure 17 is Figure 11 another circuit layout when the circuit structure in

[0030] Figure 18 is Figure 15 a comparison graph of the first transistors in the first sub-pixel and the second sub-pixel in

[0031] Figure 19 is Figure 15 another comparison graph of the first transistors in the first sub-pixel and the second sub-pixel in

[0032] Figure 20 is Figure 15 another comparison graph of the first transistors in the first sub-pixel and the second sub-pixel in

[0033] Figure 21 is Figure 15 another comparison graph of the first transistors in the first sub-pixel and the second sub-pixel in

[0034] Figure 22 is Figure 15 another comparison graph of the first transistors in the first sub-pixel and the second sub-pixel in

[0035] Figure 23 is Figure 15 another comparison graph of the first transistors in the first sub-pixel and the second sub-pixel in

[0036] Figure 24 is Figure 11 another circuit layout when the circuit structure in

[0037] Figure 25 is Figure 11Another circuit layout when the circuit structure in

[0038] Figure 26 is a schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0039] Now, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0040] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way serves as a limitation to the present invention or its application or use.

[0041] Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification.

[0042] In all the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as a limitation. Thus, other examples of the exemplary embodiments may have different values.

[0043] It should be noted that: like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0044] Please refer to Figure 1 and Figure 2 , Figure 1 is a schematic plan view of a display panel provided by an embodiment of the present invention. Figure 2 is Figure 1 a schematic connection structure diagram of a pixel circuit and a light-emitting element included in a sub-pixel in the Q region in Figure 1 (it can be understood that, for clearly showing the structure of this embodiment,

[0045] The width-to-length ratio of the channel region of the first transistor T1 in the first sub-pixel 00A is N1, and the width-to-length ratio of the channel region of the first transistor T1 in the second sub-pixel 00B is N2; where N1 > N2.

[0046] Specifically, the display panel 000 provided in this embodiment may be an Organic Light Emitting Diode (OLED) display panel. The display panel 000 may include a plurality of sub-pixels 00. Optionally, the plurality of sub-pixels 00 may include multiple different colors ( Figure 1 represented by different filling patterns), such as at least including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and may also include a white sub-pixel, etc.; the plurality of sub-pixels 00 may be arranged in an array on the display panel 000, or may also be in other arrangement manners. In this embodiment Figure 1 only takes the case where the plurality of sub-pixels 00 are arranged in an array as an example for illustration. It can be understood that in this embodiment Figure 1 takes the shape of the orthographic projection of one sub-pixel 00 onto the light-emitting surface of the display panel 000 as a strip as an example for illustration. In actual implementation, the shape of the sub-pixel 00 includes but is not limited to this shape and can be designed according to actual requirements.

[0047] Such as Figure 2 As shown, the sub-pixel 00 of this embodiment includes a pixel circuit 10 and a light-emitting element 20 that are electrically connected. Optionally, the light-emitting element 20 may be an organic light-emitting diode. The pixel circuit 10 is configured to transmit a light-emitting drive current to the light-emitting element 20 under the action of signals of drive signal lines (such as scan lines, data lines, voltage signal lines, etc., not shown in the figure) on the display panel 000, and provide a drive current for the light-emitting element 20 to make it emit light.

[0048] The pixel circuit 10 of this embodiment includes a first transistor T1. It can be understood that in this embodiment Figure 2 only uses a block diagram to represent the structure of the pixel circuit 10 other than the first transistor T1. The specific structures of other parts in the pixel circuit 10 are not limited in this embodiment. In actual implementation, the pixel circuit 10 includes but is not limited to the structure of this embodiment. The pixel circuit 10 may also include other structures that can enable the light-emitting element 20 to emit light, such as a reset module, a data signal writing module, etc. This embodiment will not elaborate here, and specific understanding can be referred to the structure of the pixel circuit 10 in related technologies.

[0049] The pixel circuit 10 of this embodiment includes a first transistor T1. The first pole of the first transistor T1 is connected to a first reference voltage signal terminal RV1, and the second pole of the first transistor T1 is connected to the anode of the light-emitting element 20. Optionally, the first reference voltage signal terminal RV1 can be connected to a first reference voltage signal line (not shown in the figure) in the display panel 000, so that in the light-emitting holding stage of the sub-pixel 00, a negative potential signal or a ground potential signal is applied to the first reference voltage signal terminal RV1 through the first reference voltage signal line. It can be understood that the light-emitting holding stage of the sub-pixel 00 in this embodiment can be understood as the stage in which the light-emitting element 20 in the sub-pixel 00 is in a light-emitting state and lasts for a period of time. At this time, optionally, the first transistor T1 is in a cut-off state. In some alternative embodiments, when the pixel circuit 10 drives the sub-pixel 00 to emit light, the working period of the sub-pixel may include multiple light-emitting holding stages. The multiple sub-pixels 00 of this embodiment at least include a first sub-pixel 00A and a second sub-pixel 00B. The color of the first sub-pixel 00A is different from that of the second sub-pixel 00B, that is, the light-emitting materials of the light-emitting element 20A in the first sub-pixel 00A and the light-emitting element 20B in the second sub-pixel 00B are different, and different colors of light can be emitted under the drive of the pixel circuit 10. This embodiment does not specifically limit whether the signal applied to the first reference voltage signal terminal RV1 is a negative potential signal or a ground potential signal, nor does it limit the specific value of the negative potential signal, as long as it can be ensured that through the first transistor T1, a negative potential signal or a ground potential signal can be transmitted to the anode of the light-emitting element 20 when the first transistor T1 is in a conducting state. The function of the first transistor T1 can be understood as a transistor for pulling down the anode potential of the light-emitting element 20 and resetting the anode potential.

[0050] In the prior art, generally, the sizes of the transistors with the same function in each sub-pixel on the display panel are designed to be the same without any differentiated design. However, due to the different light-emitting materials of the light-emitting elements in different color sub-pixels, the light-emitting efficiencies of different color light-emitting elements are also different, which further leads to inconsistent performances of different color light-emitting elements at low gray levels. For example, when the environment changes (changes in environmental temperature, humidity, and electric field), the low-gray-level light emission performance of the light-emitting element is mainly affected by the anode charging of the light-emitting element, that is, the low-gray-level light emission of the light-emitting element is mainly affected by the current of the first transistor connected to the anode of the light-emitting element. Under low-gray-level conditions, the current change of the first transistor is in the stage where the efficiency of the light-emitting element gradually increases, and the efficiency increase trends of different color light-emitting elements are different, that is, the efficiencies of different color light-emitting elements are different, which easily leads to chromaticity differences in the display panel during low-gray-level display, and the higher the refresh rate, the more serious the chromaticity differences.

[0051] Specifically, as Figure 3 shown, Figure 3It is an efficiency curve graph corresponding to light-emitting elements of different colors at different values of low gray levels. The abscissa is the gray level value, and the ordinate is the luminous efficiency of the light-emitting element. Optionally, the luminous efficiencies of the red and green light-emitting materials already meet commercial requirements, while the development of the efficiency and lifespan of the blue light-emitting material lags behind relatively. Figure 3 In [0000222], curve M1 represents the red light-emitting element, curve M2 represents the green light-emitting element, and curve M3 represents the blue light-emitting element. It can be seen from Figure 3 that within a certain range of low gray level values, the efficiencies of both the red light-emitting element and the green light-emitting element are greater than that of the blue light-emitting element, and the efficiency of the red light-emitting element is greater than that of the green light-emitting element. Moreover, since the efficiencies of the red light-emitting element and the green light-emitting element increase significantly within this gray level value range, and when the display panel is at a low gray level, the current of the light-emitting element with a higher efficiency is usually smaller. Therefore, when the ambient temperature changes, a slight change in current has a greater impact on the brightness of the light-emitting element at low gray levels, easily resulting in a large brightness fluctuation. While the efficiency of the blue light-emitting element increases less within this gray level value range and the current is larger, so when the ambient temperature changes, it is likely to result in a smaller brightness fluctuation. As a result, the current increase rate of the red light-emitting element and the green light-emitting element is greater than that of the blue light-emitting element, and further, the brightness increase rate of the red light-emitting element and the green light-emitting element is greater than that of the blue light-emitting element. Eventually, when the ambient temperature rises, the red light-emitting element and the green light-emitting element are prone to emit light with a cyan-yellowish color, thereby generating a color shift phenomenon at low gray levels.

[0052] It can be understood that in this embodiment, Figure 3 only one material system is used as an example to explain the relationship between the luminous efficiency of light-emitting elements of different colors prepared by this material system and the gray level. Specifically in implementation, it includes but is not limited to this. In the display panels of some other material systems, the corresponding relationship between curve M1, curve M2, and curve M3 and the colors is not restricted by Figure 3 any limitations and may also include other corresponding relationships, which are not elaborated in this embodiment.

[0053] And since the color of the first sub-pixel 00A is different from that of the second sub-pixel 00B, that is, the light-emitting materials of the light-emitting element 20A in the first sub-pixel 00A and the light-emitting element 20B in the second sub-pixel 00B are different, the luminous performances of the light-emitting element 20A in the first sub-pixel 00A and the light-emitting element 20B in the second sub-pixel 00B will also be different. For example, due to the different light-emitting materials of the light-emitting element 20A in the first sub-pixel 00A and the light-emitting element 20B in the second sub-pixel 00B, it may make the turn-on voltage V A of the light-emitting element 20A in the first sub-pixel 00A less than the turn-on voltage V B。Then when it is necessary to make the light-emitting element 20B in the second sub-pixel 00B emit light, the anode voltage of the light-emitting element 20B reaches the turn-on voltage V B , at this time the light-emitting element 20B emits light, and carriers will migrate horizontally (along the direction parallel to the light-emitting surface of the display panel 000) through the common film layer of the light-emitting elements 20 in the display panel to sub-pixels of other colors adjacent to the second sub-pixel 00B. It can be understood that when the light-emitting element 20 is an organic light-emitting diode, it may include an anode, a hole transport layer, a light-emitting layer, an electron transport layer, and a cathode stacked in sequence, where the anodes in different light-emitting elements 20 are independently arranged, and the light-emitting layers in different light-emitting elements 20 are also independently arranged because of different materials and are not connected to each other, while the hole transport layer, the electron transport layer, and the cathode are generally arranged as a whole layer, that is, the hole transport layers in different light-emitting elements 20 are connected to each other, the electron transport layers in different light-emitting elements 20 are also connected to each other, and the cathodes in different light-emitting elements 20 are also connected to each other. Therefore, the cathode layer, the hole transport layer, and the electron transport layer can be called the common layers of the light-emitting element 20. For example, when the light-emitting element 20B in the second sub-pixel 00B is turned on, carriers are likely to migrate to the light-emitting element 20A in the first sub-pixel 00A adjacent to it. Since the turn-on voltage V A of the light-emitting element 20A in the first sub-pixel 00A is less than the turn-on voltage V B of the light-emitting element 20B in the second sub-pixel 00B, that is, the turn-on voltage V A of the light-emitting element 20A in the first sub-pixel 00A is relatively low, then the relatively small number of carriers that migrate over may very likely cause the light-emitting element 20A in the first sub-pixel 00A to emit weak light, resulting in the problem that when the light-emitting element 20B in the second sub-pixel 00B emits light, the light-emitting element 20A in the first sub-pixel 00A emits light secretly, affecting the display effect.

[0054] Therefore, to solve the above problems, in this embodiment, the aspect ratio N1 of the channel region of the first transistor T1 in the first sub-pixel 00A is set to be greater than the aspect ratio N2 of the channel region of the first transistor T1 in the second sub-pixel 00B, which can make the leakage current of the first transistor T1 in the first sub-pixel 00A greater than the leakage current of the first transistor T1 in the second sub-pixel 00B (wherein, the leakage current of the transistor refers to the current between the source and drain electrodes of the transistor under a certain source-drain voltage when the gate voltage is the cut-off voltage of the transistor). As a result, when the light-emitting element 20A in the first sub-pixel 00A emits light at a low gray level, compared with the second sub-pixel 00B, a larger current leaks from the first transistor T1 in the first sub-pixel 00A, reducing the light-emitting efficiency of the light-emitting element 20A in the first sub-pixel 00A, which is beneficial to enhancing its brightness stability. If the light-emitting efficiency of the light-emitting element 20A in the first sub-pixel 00A is originally greater than that of the light-emitting element 20B in the second sub-pixel 00B, then by setting the aspect ratio N1 of the channel region of the first transistor T1 in the first sub-pixel 00A to be greater than the aspect ratio N2 of the channel region of the first transistor T1 in the second sub-pixel 00B, the light-emitting efficiency of the light-emitting element 20A in the first sub-pixel 00A can be reduced to be as consistent or substantially consistent as possible with the light-emitting efficiency of the light-emitting element 20B in the second sub-pixel 00B. That is, the brightness fluctuation of the light-emitting element 20A in the first sub-pixel 00A with respect to the change in ambient temperature is reduced, so that the brightness increase amplitude of the light-emitting element 20A in the first sub-pixel 00A is reduced, and as much as possible, the same brightness increase amplitude as that of the light-emitting element 20B in the second sub-pixel 00B is achieved. Finally, the brightness fluctuations of the light-emitting elements 20 of different colors under environmental changes are balanced as much as possible, enabling the light-emitting elements 20 of different colors to emit light normally at low gray levels, avoiding color deviation phenomena, and further enabling the white screen display at low gray levels to be normal, which is beneficial to improving the display effect of the display panel 000 at low gray levels.

[0055] Moreover, in this embodiment, the width-to-length ratio of the channel region of the first transistor T1 in the first sub-pixel 00A with a low turn-on voltage is set to N1, and the width-to-length ratio of the channel region of the first transistor T1 in the second sub-pixel 00B with a high turn-on voltage is set to N2, such that N1 > N2. That is, the width-to-length ratio N1 of the channel region of the first transistor T1 in the first sub-pixel 00A with a low turn-on voltage is greater than the width-to-length ratio N2 of the channel region of the first transistor T1 in the second sub-pixel 00B with a high turn-on voltage. Since the larger the width-to-length ratio of the channel region of a transistor, the greater the leakage current of the transistor, in this embodiment, the width-to-length ratio of the channel region of the first transistor T1 in the first sub-pixel 00A with a low turn-on voltage is set to be relatively large, that is, the leakage current performance of the first transistor T1 in the first sub-pixel 00A is relatively strong. When the light-emitting element 20B in the second sub-pixel 00B is turned on and has a relatively high brightness, when carriers migrate to the light-emitting element 20A in the first sub-pixel 00A, the relatively strong leakage current performance of the first transistor T1 in the first sub-pixel 00A can be used to conduct the leakage current in the state where the first transistor T1 in the first sub-pixel 00A is turned off, so as to avoid the light-emitting element 20A in the first sub-pixel 00A from stealing light when the first sub-pixel 00A is not required to emit light, thereby being beneficial to improving the display effect.

[0056] In this embodiment, by setting different width-to-length ratios of the channel regions of the first transistors T1 connected to the light-emitting elements 20 of different colors in the display panel 000, the display effects of different color sub-pixels are balanced, the situation where some color sub-pixels steal light when other color sub-pixels emit light is avoided, and the color deviation phenomenon of the light-emitting elements 20 of different colors at low gray levels can also be avoided. Furthermore, without affecting the panel circuit structure and overall performance, it is beneficial to improve the display effect of the display panel 000 at low gray levels.

[0057] It can be understood that in the display panel 000 of this embodiment, by only adjusting the aspect ratio of the channel region of the first transistor T1 connected to the light-emitting elements 20 of different colors to be different, the overall size of the first transistor T1 connected to the light-emitting elements 20 of different colors can be made different, without making the overall size of the first transistor T1 connected to the light-emitting elements 20 of one color smaller or larger, so that the overall sizes of the first transistors T1 connected to the light-emitting elements 20 of different colors are different. This embodiment makes less modification to the overall structure of the pixel circuit 10, that is, in this embodiment, only the off-state leakage current of the first transistor T1 at the anode port position of the light-emitting element 20 needs to be adjusted to achieve the purpose of adjusting the low gray-scale color shift, without changing other structures, and has less impact on other performances of the first transistor T1. The channel length value or width value of the first transistor has a certain influence on different characteristics of the transistor. When there is a requirement for the channel length value or width value of the first transistor T1 in the display panel, only the corresponding channel width value or channel length value needs to be adjusted to improve the display effect of the display panel at low gray scales. Under the condition of ensuring the display effect, it has less impact on the spatial arrangement of the display panel.

[0058] It can be understood that, as Figure 1 , Figure 2 and Figure 4 shown, Figure 4 is a schematic diagram of the film layer structure of the first transistor in the display panel provided by the embodiment of the present invention (it can be understood that, for the sake of clearly showing the structure of this embodiment, Figure 4 transparency filling is performed). The display panel 000 in this embodiment may include a substrate 01 (not filled in the figure), and the light-emitting element 20 and the pixel circuit 10 are both disposed on the substrate 01. The first transistor T1 includes a first gate T1G, a first source T1S, a first drain T1D, and a first active part T1P. In the direction perpendicular to the plane where the substrate 01 is located, the region where the first gate T1G overlaps with the first active part T1P is the channel region T1C of the first transistor T1. In this embodiment, there is no specific limitation on the width and length of the channel region of the first transistor T1 in the first sub-pixel 00A, and there is no specific limitation on the width and length of the channel region of the first transistor T1 in the second sub-pixel 00B, as long as the aspect ratio N1 of the channel region of the first transistor T1 in the first sub-pixels 00A of different colors is different from the aspect ratio N2 of the channel region of the first transistor T1 in the second sub-pixels 00B.

[0059] Optionally, please continue to refer to Figure 1 and Figure 4, in this embodiment, the first transistor T1 further includes a first gate T1G, a first source T1S, and a first drain T1D; along the first direction X, the length of the channel region T1C of the first transistor T1 is L, and along the second direction Y, the width of the channel region T1C of the first transistor T1 is W. The width-to-length ratio of the channel region T1C of the first transistor T1 is W / L; wherein, in the direction parallel to the light-emitting surface of the display panel 000, the direction from the first source T1S to the first drain T1D is the first direction X, and the second direction Y intersects the first direction X. Optionally, in the figure, the example is illustrated with the first direction X and the second direction Y being perpendicular to each other in the direction parallel to the light-emitting surface of the display panel 000.

[0060] Optionally, the first transistor T1 of this embodiment may be a P-type transistor. The first transistor T1 includes a first active portion T1P, and the first active portion T1P includes silicon semiconductor. That is, the first transistor T1 in this embodiment may be a P-type transistor of semiconductor silicon. Compared with IGZO (indium gallium zinc oxide) transistors and N-type transistors, IGZO and N-type transistors have better anti-leakage current performance. Therefore, for the first transistor T1 with slightly worse anti-leakage current performance, by setting different width-to-length ratios of the channel regions of the first transistors T1 corresponding to the light-emitting elements 20 of different colors in this embodiment, the effect of improving color shift can be better achieved by changing its own leakage current.

[0061] It should be noted that in this embodiment, when the display panel 000 is at a high gray level (when the light-emitting element 20 emits light in the bright state), although the leakage current of the first transistor T1 of the first sub-pixel 00A is greater than the leakage current of the first transistor T1 of the second sub-pixel 00B, at a high gray level, the order of magnitude of the light-emitting current of the light-emitting element 20 is much larger than the order of magnitude of the leakage current. Therefore, in this embodiment, setting different width-to-length ratios of the channel regions of the first transistors T1 connected to the light-emitting elements 20 of different colors has a negligible impact on the light-emitting current at a high gray level.

[0062] It should be further noted that the structure of the display panel 000 in this embodiment includes but is not limited to the above structure. Specifically, when implemented, the display panel 000 may further include other structures capable of realizing the display function, which will not be elaborated in this embodiment. Specifically, reference may be made to the structure of an organic light-emitting diode display panel in related technologies for understanding.

[0063] In some alternative embodiments, please continue to refer to Figures 1 - 4 , in this embodiment, at the first gray level, the luminous efficiency of the light-emitting element 20A in the first sub-pixel 00A is greater than the luminous efficiency of the light-emitting element 20B in the second sub-pixel 00B; wherein, the gray level value of the first gray level is Gray, and 5 ≤ Gray ≤ 65. ByFigure 3 It can be seen that the light-emitting element 20A in the first sub-pixel 00A in this embodiment can be either a red light-emitting element or a green light-emitting element, and the light-emitting element 20B in the second sub-pixel 00B can be a blue light-emitting element, satisfying that at the first gray level, the luminous efficiency of the light-emitting element 20A in the first sub-pixel 00A is greater than that of the light-emitting element 20B in the second sub-pixel 00B. Or the light-emitting element 20A in the first sub-pixel 00A is a red light-emitting element, and the light-emitting element 20B in the second sub-pixel 00B is a green light-emitting element, satisfying that at the first gray level, the luminous efficiency of the light-emitting element 20A in the first sub-pixel 00A is greater than that of the light-emitting element 20B in the second sub-pixel 00B. During specific implementation, it is set according to actual requirements, and this embodiment does not make specific limitations.

[0064] This embodiment explains that among the efficiencies corresponding to light-emitting elements of different colors, as Figure 3 shown, at low gray-level values represented within the first gray-level range, the efficiency values of the three light-emitting elements 20 of different colors differ significantly, while outside the first gray-level range, the efficiencies of the three light-emitting elements 20 of different colors basically tend to be the same. Therefore, the problem of low-gray-level color deviation solved by this embodiment refers to that at the first gray level, among at least two sub-pixels 00 of different colors, the luminous efficiency of the light-emitting element 20A in the first sub-pixel 00A is greater than that of the light-emitting element 20B in the second sub-pixel 00B; wherein, the gray-level value of the first gray level is Gray, and 5 ≤ Gray ≤ 65. As Figure 3Among them, when the gray scale value of the first gray scale is greater than or equal to 5 and less than or equal to 65, the luminous efficiency of the red light-emitting element indicated by curve M1 is greater than that of the green light-emitting element indicated by curve M2, and the luminous efficiency of the green light-emitting element indicated by curve M2 is greater than that of the blue light-emitting element indicated by curve M3. When the gray scale value G of the first gray scale is less than 5, the efficiencies of the three light-emitting elements 20 of different colors are all close to 0. When the gray scale value G of the first gray scale is greater than 65, the efficiencies of the three light-emitting elements 20 of different colors are basically all around 100. Therefore, in this embodiment, after setting the aspect ratio N1 of the channel region of the first transistor T1 in the first sub-pixel 00A with a larger original luminous efficiency to be greater than the aspect ratio N2 of the channel region of the first transistor T1 in the second sub-pixel 00B with a smaller original luminous efficiency, the leakage current of the first transistor T1 in the first sub-pixel 00A can be made greater than the leakage current of the first transistor T1 in the second sub-pixel 00B. As a result, when the light-emitting element 20A in the first sub-pixel 00A emits light at the first gray scale, compared with the second sub-pixel 00B, a larger current leaks from the first transistor T1 in the first sub-pixel 00A, reducing the luminous efficiency of the light-emitting element 20A in the first sub-pixel 00A, and making it as consistent or basically consistent as possible with the luminous efficiency of the light-emitting element 20B in the second sub-pixel 00B, which is beneficial to enhancing its brightness stability. That is, after the efficiency of the light-emitting element 20A in the first sub-pixel 00A with a larger original luminous efficiency is reduced, the brightness fluctuation with the change of the ambient temperature is reduced, so that the brightness increase amplitude of the light-emitting element 20A in the first sub-pixel 00A is reduced, and it is made to reach the same brightness increase amplitude as the light-emitting element 20B in the second sub-pixel 00B as much as possible. Finally, the brightness fluctuations of the light-emitting elements 20 of different colors under environmental changes can be balanced as much as possible, avoiding color deviation phenomena, and thus improving the display effect of the display panel at the first gray scale.

[0065] In some alternative embodiments, please refer to Figure 1 and Figure 5 , Figure 5 is Figure 1 Another schematic diagram of the connection structure of the pixel circuit and the light-emitting element included in the sub-pixels in the Q region in

[0066] This embodiment explains that the first transistor T1 can be used as a leakage current transistor, that is, the first transistor T1 is electrically connected to the anode of the light-emitting element 20, and by designing a larger width-to-length ratio of the channel region of the first transistor T1 of the first sub-pixel 00A with a small turn-on voltage and high luminous efficiency, the leakage current of the first transistor T1 is increased to solve the problems of sub-pixel light stealing and color shift of the display panel at low gray levels. The pixel circuit 10 in the display panel 000 itself can also include a reset transistor T0, that is, the first transistor T1 in this embodiment and the transistor for resetting the anode of the light-emitting element 20 can be two different transistors. The first pole of the reset transistor T0 is connected to the anode of the light-emitting element 20, and the second pole of the reset transistor T0 is connected to the reset signal terminal REF1. A reset signal provided by the reset signal terminal REF1 can be used to reset the anode of the light-emitting element 20 during the initialization stage of the operation of the pixel circuit 10, so that the anode of the light-emitting element 20 is initialized, thereby improving the residual of the previous frame display signal and the afterimage phenomenon during the display process, and enhancing the display effect.

[0067] It can be understood that the pixel circuit 10 of this embodiment includes but is not limited to Figure 5 the structure shown. During specific implementation, the pixel circuit 10 can also include other electrically connected module structures for realizing the light emission of the light-emitting element 20 ( Figure 5 only represented by a block diagram), and specific understanding can be referred to the circuit structure of the pixel circuit in the related art. This embodiment does not make any limitations here.

[0068] Optionally, as Figure 6 shown, Figure 6 is Figure 1 another schematic diagram of the connection structure of the pixel circuit and the light-emitting element included in the sub-pixels in the Q region in

[0069] This embodiment explains that in the pixel circuit 10, the second pole of the first transistor T1 is electrically connected to the anode of the light-emitting element 10, as Figure 6As shown, the second pole of the first transistor T1 is also connected to the drain of the driving transistor DT, while the first pole of the first transistor T1 is connected to the first reference voltage signal terminal RV1. The first transistor T1 can be a bias adjustment transistor for adjusting the performance of the driving transistor DT. Since in non-bias stages such as the light-emitting stage of the pixel circuit, there may be a situation where the potential of the gate of the driving transistor DT is greater than the potential of the drain of the driving transistor DT. Being in this situation for a long time is likely to cause internal ion polarization of the driving transistor DT, and then an internal built-in electric field is formed inside the driving transistor DT, resulting in a drift of the characteristic curve of the driving transistor DT and affecting the display effect of the light-emitting element 20. Therefore, in this embodiment, it is provided that the operation process of the pixel circuit 10 can include a voltage bias adjustment stage. In the voltage bias adjustment stage, the first transistor T1 (bias adjustment transistor) is turned on, and the signal provided by the first reference voltage signal terminal RV1 is transmitted to the drain of the driving transistor DT to relieve the threshold voltage offset of the driving transistor DT. It can be understood that at this time, the first reference voltage signal terminal RV1 provides a bias adjustment voltage. That is, the first transistor T1 can be multiplexed as a bias adjustment transistor. That is, in the voltage bias adjustment stage of the pixel circuit 10 in this embodiment, the first transistor T1 is turned on to transmit the bias adjustment voltage to the driving transistor DT to adjust the characteristic curve of the driving transistor DT; while in the display stage (i.e., the light-emitting stage of the light-emitting element 20), the first transistor T1 is turned off, and the first reference voltage signal terminal RV1 transmits a negative potential signal or a ground potential signal. By differentially designing the channel width-to-length ratio of the first transistor T1 in the sub-pixels 00 of different colors, the display effects of sub-pixels of different colors are balanced, the color deviation phenomenon of the light-emitting elements 20 of different colors at low gray levels is avoided, and thus the display effect of the display panel 000 at low gray levels can be improved.

[0070] It can be understood that the electrical connection between the second pole of the first transistor T1 and the anode of the light-emitting element 10 in this embodiment can be understood as various ways to achieve electrical connection between the two. For example, when there is no other structure between the second pole of the first transistor T1 and the anode of the light-emitting element 10, the electrical connection can be achieved by directly connecting the second pole of the first transistor T1 and the anode of the light-emitting element 10; if there are other structures between the second pole of the first transistor T1 and the anode of the light-emitting element 10, such as a light-emitting control transistor connected to the anode of the light-emitting element 20 may also be included in the pixel circuit 10. In this case, when the light-emitting control transistor is turned on, the electrical connection can also be achieved between the second pole of the first transistor T1 and the anode of the light-emitting element 10. This embodiment does not limit the specific structure of the electrical connection between the second pole of the first transistor T1 and the anode of the light-emitting element 10. During specific implementation, it can be understood according to the actual design structure of the pixel circuit. In this embodiment, the drain of the driving transistor DT is electrically connected to the anode of the light-emitting element 10, which can also be understood as, for example, a light-emitting control transistor connected to the anode of the light-emitting element 20 may also be included in the pixel circuit 10. In this case, when the light-emitting control transistor is turned on, the electrical connection can also be achieved between the drain of the driving transistor DT and the anode of the light-emitting element 10.

[0071] It should be noted that this embodiment only exemplarily shows the connection structure included in the pixel circuit 10. During specific implementation, the structure of the pixel circuit 10 includes but is not limited to this, and may also include other structures that are beneficial to realizing the effective light emission of the driving light-emitting element 20 and achieving the display effect. This embodiment will not elaborate here.

[0072] In some alternative embodiments, please refer to Figure 1 and Figure 7 , Figure 7 is Figure 1 Another schematic diagram of the connection structure of the pixel circuit and the light-emitting element included in the sub-pixels of the Q region in

[0073] This embodiment illustrates that since the first pole of the first transistor T1 is connected to the first reference voltage signal terminal RV1, the second pole of the first transistor T1 is connected to the anode of the light-emitting element 20, and the first reference voltage signal terminal RV1 is used to transmit a negative potential signal or a ground potential signal to the anode of the light-emitting element 20. Also, the first pole of the reset transistor T0 is connected to the anode of the light-emitting element 20, and the second pole of the reset transistor T0 is connected to the reset signal terminal REF1. Generally, the reset signal provided by the reset signal terminal REF1 to the anode of the light-emitting element 20 is also a low-potential signal. Therefore, the first transistor T1 in this embodiment can be multiplexed as the reset transistor T0, and the first reference voltage signal terminal RV1 can be multiplexed as the reset signal terminal REF1 for use. This is beneficial for resetting the anode of the light-emitting element 20 in the pixel circuit 10 through the reset transistor T0 (the first transistor T1). By setting different aspect ratios of the channel regions of the reset transistor T0 (the first transistor T1) in sub-pixels of different colors 00, while solving the problems of color shift and crosstalk, it is also beneficial to reduce the number of transistors included in the pixel circuit 10, thereby reducing the total number of transistors in the display panel 000 and improving the panel transmittance.

[0074] In some alternative embodiments, please refer to Figure 1 and Figure 8 , Figure 8 is Figure 1 a schematic diagram of the connection structure of the pixel circuit and the light-emitting element in the sub-pixel of

[0075] The light-emitting control module 102 is electrically connected to the first voltage signal terminal PVDD and the anode of the light-emitting element 20 respectively; the cathode of the light-emitting element 20 is electrically connected to the second power supply signal terminal PVEE.

[0076] The driving transistor DT is electrically connected to the light-emitting control module 102 and the data writing module 101 respectively.

[0077] This embodiment explains that the pixel circuit 10 includes a first transistor T1. It can be understood that this embodiment takes the multiplexing of the first transistor T1 as the reset transistor T0 as an example for illustration. The output terminal of the first transistor T1 is connected to the anode of the light-emitting element 20, which is used to reset the anode of the light-emitting element 20 during the reset stage. At the same time, by setting different aspect ratios of the channel regions of the first transistor T1 in sub-pixels of different colors 00, the problems of color shift and crosstalk are solved.

[0078] The pixel circuit 10 of this embodiment further includes a driving transistor DT, a data writing module 101, and a light-emitting control module 102. Among them, the driving transistor DT is used to provide a driving current during the light-emitting stage. The light-emitting control module 102 is connected in series between the first power supply signal terminal PVDD and the light-emitting element 20. The light-emitting control module 102 is electrically connected to the first power supply signal terminal PVDD and the anode of the light-emitting element 20 respectively. The cathode of the light-emitting element 20 is electrically connected to the second power supply signal terminal PVEE. The light-emitting control module 102 is used to provide a light-emitting signal for the light-emitting element 20 during the light-emitting stage. The light-emitting element 20 is connected in series between the driving transistor DT and the second power supply signal terminal PVEE and is used to emit light in response to the driving current.

[0079] Optionally, as Figure 8 shown, the light-emitting control module 102 of this embodiment may include a first light-emitting control module 1021 and a second light-emitting control module 1022. One end of the first light-emitting control module 1021 is connected to the first power supply signal terminal PVDD. The first power supply signal terminal PVDD inputs a first voltage signal to the first light-emitting control module 1021. The first power supply signal terminal PVDD may be connected to a first power supply signal line (not shown in the figure) in the display panel 000. The other end of the first light-emitting control module 1021 is connected to the source DT of the driving transistor DT S connected, and one end of the second light-emitting control module 1022 is connected to the drain DT of the driving transistor DT DThe other end of the second light-emitting control module 1022 is connected to the anode of the light-emitting element 20, which is used to realize the path among the first power signal terminal PVDD, the first light-emitting control module 102, the driving transistor DT, the second light-emitting control module 103, the light-emitting element 20, and the second power signal terminal PVEE. The first light-emitting control module 1021 and the second light-emitting control module 1022 may further include a first light-emitting signal terminal EM1 and a second light-emitting signal terminal EM2 respectively, and the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are used to input a light-emitting enable signal. Specifically, the first end of the first light-emitting control module 1021 may be electrically connected to the first power signal terminal PVDD to input a first voltage signal, the cathode of the light-emitting element 20 is electrically connected to the second power signal terminal PVEE to input a second voltage signal, and the second power signal terminal PVEE may be connected to a second power signal line (not shown in the figure) in the display panel 000. The levels of the first voltage signal and the second voltage signal are different, and the value of the first voltage signal may be set to be greater than the value of the second voltage signal. The first light-emitting signal terminal EM1 of the first light-emitting control module 1021 is used to receive the first light-emitting signal of the pixel circuit 10, and the second light-emitting signal terminal EM2 of the second light-emitting control module 1022 is used to receive the second light-emitting signal of the pixel circuit 10, so that the first light-emitting control module 1021 and the second light-emitting control module 1022 are turned on during the light-emitting stage to provide a current path for the light-emitting element 20, enabling the light-emitting element 20 to emit light, and during other stages (such as the reset stage or the data writing stage, etc.), controlling the first light-emitting control module 1021 and the second light-emitting control module 1022 to turn off to avoid the light-emitting element 20 emitting light erroneously during the non-light-emitting stage. Optionally, as Figure 8 shown, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 may be connected together to receive the same light-emitting signal EM, that is, the first light-emitting signal for turning on the first light-emitting control module 1021 and the second light-emitting signal for turning on the second light-emitting control module 1022 can be shared, which is beneficial to reducing the number of signal lines in the display panel, improving the transmittance of the display panel or increasing the wiring space of the display panel.

[0080] Optionally, as Figure 8 shown, when the first transistor T1 of this embodiment is used as the reset transistor T0, the input end of the first transistor T1 is connected to the first reference voltage signal terminal RV1 (reset signal terminal REF1), and the first reference voltage signal terminal RV1 receives the first reset signal, which is used to provide the first reset signal for the first transistor T1. The output end of the first transistor T1 is connected to the anode of the light-emitting element 20, and the anode of the light-emitting element 20 is reset by the first reset signal received by the first reference voltage signal terminal RV1. Optionally, the first transistor T1 may further include a first gate T1G, and the first gate T1G is used to receive the first reset enable signal, and the first reset enable signal may be the first scan signal (such asFigure 8 As shown in S1), when the first gate T1G of the first transistor T1 is turned on in response to the first scan signal, the first reset signal of the first reference voltage signal terminal RV1 is transmitted to the anode of the light-emitting element 20. The first reset signal can reset the anode of the light-emitting element 20 by using the potential of its low level.

[0081] Optionally, as Figure 8 shown, the input terminal of the data writing module 101 in this embodiment is connected to the data voltage signal terminal DATA, and the output terminal of the data writing module 101 is connected to the source DT of the driving transistor DT S The data voltage signal terminal DATA can be connected to a data line (not shown in the figure) in the display panel 000 to receive a data voltage signal on the data line. The control terminal S2 of the data writing module 101 can be used to receive a data writing enable signal, and the data writing enable signal can be a second scan signal. That is, the data writing enable signal received by the control terminal S2 of the data writing module 101 and the first reset enable signal received by the first gate T1G of the first transistor T1 can both be the second scan signal. When the control terminal S2 of the data writing module 101 responds to the second scan signal, the data writing module 101 is in a conducting state and is used to transmit the data voltage signal of the data voltage signal terminal DATA to the source DT of the driving transistor DT S to provide a data voltage signal for the driving transistor DT.

[0082] It can be understood that this embodiment is only an example to illustrate the module structure that the pixel circuit 10 can include. In specific implementation, the connection structure between the pixel circuit 10 and the light-emitting element 20 includes but is not limited to this, and can also include other connection structures. For understanding, reference can be made to the connection structure of the pixel circuit in the organic light-emitting display panel in the related art. This embodiment does not make specific limitations here.

[0083] In some alternative embodiments, please refer to Figure 1 and Figure 9 , Figure 9 is Figure 1 Another schematic diagram of the connection structure between the pixel circuit and the light-emitting element in the sub-pixel of. In this embodiment, the pixel circuit 10 further includes a second transistor T2. The first pole of the second transistor T2 is connected to the first reference voltage signal terminal RV1, and the second pole of the second transistor T2 is connected to the gate DT of the driving transistor DT G connected.

[0084] This embodiment explains that the pixel circuit 10 of the display panel 000 can further include a second transistor T2. The first pole, that is, the input terminal, of the second transistor T2 can be connected to the first reference voltage signal terminal RV1, and the second pole, that is, the output terminal, of the second transistor T2 can be connected to the gate DT of the driving transistor DTG Connected, the second transistor T2 can receive the first reset signal provided by the first reference voltage signal terminal RV1 for the gate DT of the driving transistor DT G for resetting. Optionally, the gate of the second transistor T2 can be the control terminal S1 for receiving the first reset enable signal, and the first reset enable signal can be the first scan signal. That is, the first transistor T1 and the second transistor T2 can share a first scan signal as the reset enable signal. When the gate of the second transistor T2 responds to the first scan signal and opens, the first reset signal provided by the first reference voltage signal terminal RV1 is transmitted to the gate DT of the driving transistor DT G , and the potential of its low level can be used to reset the gate DT of the driving transistor DT G for resetting, so that it is convenient for the driving transistor DT to conduct after completing the reset work.

[0085] It can be understood that this embodiment is only an example to illustrate the module structure that the pixel circuit 10 can include. In specific implementation, the connection structure between the pixel circuit 10 and the light-emitting element 20 includes but is not limited to this, and can also include other connection structures. For understanding, reference can be made to the connection structure of the pixel circuit in the organic light-emitting display panel in the related art, and this embodiment does not make specific limitations here.

[0086] It should be noted that when the first transistor T1 and the second transistor T2 in this embodiment play a reset role, the input ends of the first transistor T1 and the second transistor T2 can be commonly connected to the first reference voltage signal terminal RV1 to provide the same first reset signal to reset the gate DT of the driving transistor DT G and the anode of the light-emitting element 20. In specific implementation, the structure of the input end of the reset transistor is not limited to this, and the input ends of the first transistor T1 and the second transistor T2 can also be connected to different reset signals, and this embodiment does not make specific limitations here.

[0087] It should be further noted that the second transistor T2 and the driving transistor DT in this embodiment are exemplified by P-type transistors. In some other optional embodiments, the second transistor T2 and the driving transistor DT can also be N-type transistors. When the second transistor T2 and the driving transistor DT are P-type transistors, the P-type transistor conducts when its gate is at a low potential. That is to say, when the second transistor T2 and the driving transistor DT are N-type transistors, the N-type transistor conducts when its gate is at a high potential. To realize the conduction of the transistor, in specific implementation, the type of the transistor can be set according to actual needs, and this embodiment does not make limitations here.

[0088] In some optional embodiments, please refer to Figure 1 and Figure 10, Figure 10 is Figure 1 Another schematic diagram of the connection structure of the pixel circuit and the light-emitting element in the sub-pixel. In this embodiment, the pixel circuit 10 of the display panel 000 further includes a third transistor T3. The first pole of the third transistor T3 is connected to the second reference voltage signal terminal RV2, and the second pole of the third transistor T3 is connected to the gate DT of the driving transistor DT G connected;

[0089] The potential applied to the second reference voltage signal terminal RV2 is different from the potential applied to the first reference voltage signal terminal RV1. Optionally, the potential transmitted by the second reference voltage signal terminal RV2 is greater than the potential transmitted by the first reference voltage signal terminal RV1.

[0090] This embodiment explains that the pixel circuit 10 of the display panel 000 may further include a third transistor T3. The first pole, i.e., the input terminal, of the third transistor T3 may be connected to the second reference voltage signal terminal RV2, and the second pole, i.e., the output terminal, of the third transistor T3 may be connected to the gate DT of the driving transistor DT G connected. The third transistor T3 can receive the second reset signal provided by the second reference voltage signal terminal RV2 for resetting the gate DT of the driving transistor DT G For resetting. Optionally, the gate of the third transistor T3 may be a control terminal S1 for receiving a first reset enable signal. The first reset enable signal may be a first scan signal, that is, the first transistor T1 and the third transistor T3 may share a first scan signal as the reset enable signal. When the gate of the third transistor T3 responds to the first scan signal and opens, the second reset signal provided by the second reference voltage signal terminal RV2 is transmitted to the gate DT of the driving transistor DT G , and its low-level potential can be used to reset the gate DT of the driving transistor DT G For resetting, so as to facilitate the conduction of the driving transistor DT after completing the reset operation.

[0091] In this embodiment, the display panel 000 may include different first reference voltage signal lines and second reference voltage signal lines. The first reference voltage signal terminal RV1 may be connected to a first reference voltage signal line (not shown in the figure) in the display panel 000, so that a first reset signal of a negative potential signal or a ground potential signal is applied to the first reference voltage signal terminal RV1 through the first reference voltage signal line. The second reference voltage signal terminal RV2 may be connected to a second reference voltage signal line (not shown in the figure) in the display panel 000, so that a second reset signal is applied to the second reference voltage signal terminal RV2 through the second reference voltage signal line, so that the first transistor T1 and the third transistor T3 use different reset signals for the anode of the light-emitting element 20 and the gate DT of the driving transistor DT GReset is performed. Also, through the independent setting of the input signals of the first transistor T1 and the second transistor T2, when measuring the leakage current of the first transistor T1 to design the aspect ratio of the corresponding first transistor T1 in different pixel circuits for matching, it is easier to measure that the leakage current in the differential pixel circuit 10 is the leakage current of the first transistor T1, avoiding the situation where when both the first transistor T1 and the second transistor T2 are connected to the first reference voltage signal terminal RV1, it is impossible to distinguish which transistor's leakage current reaches the first reference voltage signal terminal RV1 when there is a leakage current.

[0092] The potential applied to the second reference voltage signal terminal RV2 in this embodiment is different from the potential applied to the first reference voltage signal terminal RV1. Optionally, the potential applied to the second reference voltage signal terminal RV2 is greater than the potential applied to the first reference voltage signal terminal RV1.

[0093] Since the potential applied to the second reference voltage signal terminal RV2 cannot be too low, if the potential applied to the second reference voltage signal terminal RV2 is too low, when the data writing module 101 writes a fixed data signal to the driving transistor DT during the data writing stage, because the potential applied to the second reference voltage signal terminal RV2 will pull the original potential of the gate DT of the driving transistor DT G very low, it is very likely that the charging of the gate DT of the driving transistor DT G will not be full. Especially when the display panel is driven to display at a high refresh rate, it has a greater impact on the display effect. And the potential applied to the first reference voltage signal terminal RV1 is expected to be lower, so as to more thoroughly reset the anode of the light-emitting element 20, thereby improving the residue of the previous frame of data signal during the display process, improving the ghosting phenomenon, enhancing the display effect, and at the same time reducing the phenomenon of sub-pixel crosstalk caused by the horizontal leakage current between the light-emitting elements 20 of adjacent sub-pixels.

[0094] In this embodiment, the first reference voltage signal terminal RV1 and the second reference voltage signal terminal RV2 are set independently, and the potential applied to the second reference voltage signal terminal RV2 is different from the potential applied to the first reference voltage signal terminal RV1. When it is necessary to lower the potential applied to the first reference voltage signal terminal RV1 to improve the problem of crosstalk of the light-emitting element 20, the potential applied to the second reference voltage signal terminal RV2 does not need to be lowered along with the lowering of the potential applied to the first reference voltage signal terminal RV1. Thus, after resetting the gate DT of the driving transistor DT G and writing the data signal to the gate DT of the driving transistor DT G a data signal can be written on the basis of a slightly higher potential applied to the second reference voltage signal terminal RV2, which is beneficial to reducing the gate DT of the driving transistor DT GThe voltage difference between the initial potential and the data signal to be written, so that the data signal can be written more fully during the data writing stage.

[0095] It can be understood that in this embodiment, the types of the potentials applied to the second reference voltage signal terminal RV2 and the first reference voltage signal terminal RV1 are not specifically limited. The potentials applied to the second reference voltage signal terminal RV2 and the first reference voltage signal terminal RV1 can both be DC signals, or the second reference voltage signal terminal RV2 can be a square wave AC signal, and the potential applied to the first reference voltage signal terminal RV1 can be a DC signal, or other types of signals can also be used, as long as the potential applied to the second reference voltage signal terminal RV2 is greater than the potential applied to the first reference voltage signal terminal RV1. This embodiment does not make specific limitations.

[0096] In some alternative embodiments, please refer to Figure 1 、 Figure 4 、 Figure 10 and Figures 11 - 12 , Figure 11 is Figure 9 the specific circuit connection structure diagram in Figure 12 is Figure 10 the specific circuit connection structure diagram in Figure 13 is for Figure 11 the leakage current data diagram measured at low gray levels after changing the width-to-length ratios of the channel regions of different first transistors in the pixel circuit of S ) connection; the first pole of the second data writing transistor T5 is connected to the gate DT of the driving transistor DT G connection, and the second pole of the second data writing transistor T5 is connected to the second pole of the driving transistor DT (which can be the drain DT of the driving transistor DT D ) connection; optionally, the gates of the first data writing transistor T4 and the second data writing transistor T5 can be commonly connected to the second scan signal, that is, when the gates of the first data writing transistor T4 and the second data writing transistor T5 commonly respond to the second scan signal, the first data writing transistor T4 and the second data writing transistor T5 are in the conducting state;

[0097] The first light-emitting control module 1021 of the light-emitting control module 102 includes a first light-emitting control transistor T6, and the second light-emitting control module 1022 of the light-emitting control module 102 includes a second light-emitting control transistor T7. The first pole of the first light-emitting control transistor T6 is connected to the first voltage signal terminal PVDD, and the second pole of the first light-emitting control transistor T6 is connected to the first pole of the driving transistor DT (which can be the source DT of the driving transistor DT S ) connection; the first pole of the second light-emitting control transistor T7 is connected to the second pole of the driving transistor DT (which can be the drain DT of the driving transistor DT D ) connection, and the second pole of the second light-emitting control transistor T7 is connected to the anode of the light-emitting element 20; optionally, the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T7 can be commonly connected to the same light-emitting signal, that is, when the gates of the first light-emitting control transistor T6 and the second light-emitting control transistor T7 respond to the light-emitting signal together, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are in the conducting state;

[0098] It further includes a storage capacitor Cst. One end of the storage capacitor Cst is connected to the first voltage signal terminal PVDD, and the other end of the storage capacitor Cst is connected to the gate DT of the driving transistor DT G connection. Optionally, the storage capacitor Cst is used to stabilize the potential of the gate DT of the driving transistor DT G which is beneficial for the driving transistor DT to maintain conduction.

[0099] This embodiment explains the circuit connection structure that the pixel circuit 10 in the display panel 000 can include. The pixel circuit 10 includes a plurality of transistors and a storage capacitor Cst. Among them, one transistor is the driving transistor DT, and the remaining transistors are switching transistors. Taking the Figure 11 schematic structure of the pixel circuit 10 electrically connected to the light-emitting element 20 as an example, taking the gate DT of the driving transistor DT G as the first node N01, the source DT of the driving transistor DT S as the second node N02, the drain DT of the driving transistor DT D as the third node N03, and the anode of the light-emitting element 20 as the fourth node N04, the working principle of the pixel circuit 10 is as follows:

[0100] In the initial reset stage, the first transistor T1 and the third transistor T3 are conducting, and the remaining transistors are cut off. The potential of the first node N01 is the second reset signal Vref2 provided by the second reference voltage signal terminal RV2, and the potential of the fourth node N04 is the first reset signal Vref1 provided by the first reference voltage signal terminal RV1. The gate DT of the driving transistor DT Gand the anode reset of the light-emitting element 20.

[0101] During the data writing and threshold capturing phases, the first data writing transistor T4, the second data writing transistor T5, and the driving transistor DT are turned on, and the rest of the transistors are turned off. The potential of the second node N02 is the data voltage signal Vdata provided by the data voltage signal terminal DATA. The potentials of the first node N01 and the third node N03 are Vdata - |Vth|, where Vth is the threshold voltage of the driving transistor DT.

[0102] During the light-emitting phase, the first light-emitting control transistor T6, the second light-emitting control transistor T7, and the driving transistor DT are turned on, and the rest of the transistors are turned off. The first voltage signal Vpvdd of the first voltage signal terminal PVDD is transmitted to the driving transistor DT. The driving transistor DT generates a driving current to drive the light-emitting element 20 to emit light. The potential of the second node N02 is the first voltage signal Vpvdd. The potential of the first node N01 is Vdata - |Vth|. The potential of the third node N03 is Vpvee + Voled, where Vpvee is the second voltage signal provided by the second power signal terminal PVEE and can be a negative potential, and Voled is the corresponding voltage on the light-emitting element 20. Then the light-emitting current Id = k(Vgs - |Vth|) 2 = k(Vpvdd - Vdata - |Vth|) 2 ; where the constant k is related to the performance of the driving transistor DT itself.

[0103] In the structure of the pixel circuit 10 provided in this embodiment connected to the light-emitting element 20, as Figure 11 shown, under low gray-scale conditions, the driving current I provided by the driving transistor DT DT a part of it supplies the leakage current of the first transistor T1, denoted as Ioff, and the other part supplies the light-emitting element 20, denoted as I EL , under low gray-scale, I DT = I EL + I off , in this embodiment, by adjusting the aspect ratio of the channel region of the first transistor T1 connected to the light-emitting element 20 of different colors, the leakage current Ioff of the first transistor T1 can be changed. According to the experimental data, as Figure 13 shown, the abscissa represents the low gray-scale value, and the ordinate represents the leakage current of the first transistor T1. Among them, the curve M4 represents the leakage current when the aspect ratio of the channel region of the first transistor T1 is N2, and the curve M5 represents the leakage current when the aspect ratio of the channel region of the first transistor T1 is N1. It is equivalent to that the aspect ratio N1 of the channel region of the first transistor T1 shown by the curve M5 is greater than the aspect ratio N2 of the channel region of the first transistor T1 shown by the curve M4. From Figure 13As can be seen from the data, after the aspect ratio of the channel region of the first transistor T1 increases, the leakage current Ioff under low gray levels increases significantly.

[0104] When the light-emitting element 20 is an organic light-emitting diode, the efficiency of the light-emitting element 20 under low gray levels where γ EL represents the efficiency of the light-emitting element 20 under low gray levels, L um represents the brightness of the display panel, S represents the display area of the display panel, L um ×S is a fixed value based on the same display panel. Therefore, in this embodiment, for the light-emitting element with a relatively high efficiency under low gray levels, such as the light-emitting element 20A corresponding to the first sub-pixel 00A, the aspect ratio of the channel region of the first transistor T1 of the first sub-pixel 00A is increased, and its leakage current Ioff increases. While the I EL of the light-emitting element 20A corresponding to the first sub-pixel 00A remains unchanged, the efficiency of the light-emitting element 20A corresponding to the first transistor T1 under the same brightness at low gray levels decreases, and the stability is enhanced. Thus, the brightness increase amplitude of the light-emitting element 20A in the first sub-pixel 00A can be reduced, and it can be made to reach approximately the same brightness increase amplitude as the light-emitting element 20B in the second sub-pixel 00B as much as possible. Finally, the brightness fluctuations of the light-emitting elements 20 of different colors under environmental changes can be balanced as much as possible, enabling the light-emitting elements 20 of different colors to emit light normally under low gray levels, avoiding color shift phenomena, and further enabling the white screen display under low gray levels to be normal, which is beneficial to improving the display effect of the display panel 000 under low gray levels.

[0105] It should be noted that the transistors included in the pixel circuit 10 in this embodiment are exemplified by P-type transistors. In some other alternative embodiments, N-type transistors can also be selected, or a structure where some of the transistors are N-type transistors and some are P-type transistors can be used. When the transistor is selected as a P-type transistor, the P-type transistor conducts when its gate is at a low potential. That is to say, when the transistor is selected as an N-type transistor, the N-type transistor conducts when its gate is at a high potential. To achieve the conduction of the transistor, in specific implementation, the type of the transistor can be set according to actual requirements, and this embodiment does not limit it here.

[0106] Optionally, as Figure 14 shown, Figure 14 is Figure 1Another schematic diagram of the circuit connection structure of the pixel circuit and the light-emitting element in the sub-pixel. In this embodiment, the pixel circuit 10 includes a reset transistor T0. The first pole of the reset transistor T0 is connected to the anode of the light-emitting element 20, and the second pole of the reset transistor T0 is connected to the reset signal terminal REF1. It further includes a third transistor T3. The first pole of the third transistor T3 is connected to the second reference voltage signal terminal RV2, and the second pole of the third transistor T3 is connected to the gate DT of the driving transistor DT G The potential applied to the second reference voltage signal terminal RV2 and the potential applied to the reset signal terminal REF1 can be different. At this time, the second pole of the first transistor T1 in the pixel circuit 10 is connected to the drain (the third node N03) of the driving transistor DT, and the second pole of the first transistor T1 is connected to the first pole of the second light-emitting control transistor T7. Optionally, at this time, the gates of the reset transistor T0 and the third transistor T3 can be connected to the same reset enable signal, such as Figure 14 The reset enable signal S1 shown in the figure. That is, when the gates of the reset transistor T0 and the third transistor T3 jointly respond to the reset enable signal S1, the reset transistor T0 and the third transistor T3 are in the conducting state; the gates of the first data writing transistor T4 and the second data writing transistor T5 can be jointly connected to the enable signal S2. That is, when the gates of the first data writing transistor T4 and the second data writing transistor T5 jointly respond to the enable signal S2, the first data writing transistor T4 and the second data writing transistor T5 are in the conducting state; the gate of the first transistor T1 can be connected to the enable signal S3. That is, when the gate of the first transistor T1 responds to the enable signal S3, the first transistor T1 is in the conducting state.

[0107] This embodiment explains that in the pixel circuit 10, the second pole of the first transistor T1 is electrically connected to the anode of the light-emitting element 10, the second pole of the first transistor T1 is connected to the first pole of the second light-emitting control transistor T7, and the second pole of the second light-emitting control transistor T7 is connected to the anode of the light-emitting element 20. Thus, the second pole of the first transistor T1 is electrically connected to the anode of the light-emitting element 10, as Figure 14As shown, the second pole of the first transistor T1 is also connected to the second pole of the driving transistor DT (i.e., the third node N03), while the first pole of the first transistor T1 is connected to the first reference voltage signal terminal RV1. The first transistor T1 can be an anti - bias transistor for adjusting the performance of the driving transistor DT. Since in non - bias stages such as the light - emitting stage of the pixel circuit, there may be a situation where the potential of the gate of the driving transistor DT is greater than the potential of the drain of the driving transistor DT. Being in this situation for a long time is likely to cause ion polarization inside the driving transistor DT, and then an internal built - in electric field is formed inside the driving transistor DT, resulting in the drift of the characteristic curve of the driving transistor DT and affecting the display effect of the light - emitting element 20. Therefore, this embodiment provides that the working process of the pixel circuit 10 can include a voltage bias adjustment stage. In the voltage bias adjustment stage, the first transistor T1 (bias adjustment transistor) is turned on, and the signal provided by the first reference voltage signal terminal RV1 is transmitted to the drain of the driving transistor DT (i.e., the third node N03) to relieve the threshold voltage shift of the driving transistor DT. It can be understood that at this time, the first reference voltage signal terminal RV1 provides a bias adjustment voltage. That is, the first transistor T1 can be multiplexed as a bias adjustment transistor. That is, in the voltage bias adjustment stage of the pixel circuit 10 in this embodiment, the first transistor T1 is turned on to transmit the bias adjustment voltage to the driving transistor DT to adjust the characteristic curve of the driving transistor DT; while in the display stage (i.e., the light - emitting stage of the light - emitting element 20), the first transistor T1 is turned off, and the first reference voltage signal terminal RV1 transmits a negative potential signal or a ground potential signal. By differentially designing the channel width - length ratio of the first transistor T1 in the sub - pixels 00 of different colors, the display effects of different - color sub - pixels are balanced, avoiding color deviation phenomena in the light - emitting elements 20 of different colors at low gray levels, and thus the display effect of the display panel 000 at low gray levels can be improved.

[0108] It can be understood that in this embodiment, the electrical connection between the second pole of the first transistor T1 and the anode of the light - emitting element 10 can be understood as various ways that can achieve electrical connection between the two. For example, when there is no other structure between the second pole of the first transistor T1 and the anode of the light - emitting element 10, the second pole of the first transistor T1 and the anode of the light - emitting element 10 can be directly connected to achieve electrical connection; if there are other structures between the second pole of the first transistor T1 and the anode of the light - emitting element 10, such as in this embodiment, when a second light - emitting control transistor T7 is connected to the anode of the light - emitting element 10, when the second light - emitting control transistor T7 is turned on, electrical connection can also be achieved between the second pole of the first transistor T1 and the anode of the light - emitting element 10. This embodiment does not limit the specific structure of the electrical connection between the second pole of the first transistor T1 and the anode of the light - emitting element 10. During specific implementation, it can be understood according to the actual design structure of the pixel circuit.

[0109] In some alternative embodiments, please refer to Figure 1 , Figure 4 , Figure 10 and Figures 11 - 13 , Figures 15 - 17 . Figure 15 is Figure 11 a circuit layout when the circuit structure in Figure 16 is fabricated on the display panel, Figure 11 is Figure 17 another circuit layout when the circuit structure in Figure 11 is fabricated on the display panel (it can be understood that this embodiment only schematically shows the layout of the circuit structure corresponding to Figure 11 . In specific implementation, Figure 12 the circuit layout can also be designed, and the difference is only that Figure 12 the first reference voltage signal terminal RV1 and the second reference voltage signal terminal RV2 in Figure 15 are separately arranged. As shown in Figure 15 , when the pixel circuit 10 in the display panel 000 is fabricated on the substrate 01 of the display panel 000, it can be schematically shown as the layout of Figure 15 . The film layer structure of the display panel 000 can at least include a first metal layer M1, a second metal layer M2, a third metal layer Mc, and an active layer POLY. The first metal layer M1 can be used to fabricate the first scan signal line in the display panel 000 (providing the first scan signal S1 for the first transistor T1 and the second transistor T2), the second scan signal line (providing the second scan signal S2 for the gates of the first data writing transistor T4 and the second data writing transistor T5), the light emitting signal line (providing the light emitting signal EM for the gates of the first light emitting control transistor T6 and the second light emitting control transistor T7), the gates of each transistor, etc.; the second metal layer M2 can be used to fabricate the data line in the display panel 000 (providing the data voltage signal Vdata for the data voltage signal terminal DATA), the first power supply signal line (providing the first voltage signal Vpvdd for the first power supply signal terminal PVDD), the second power supply signal line (providing the second voltage signal Vpvee for the second power supply signal terminal PVEE), the sources and drains of each transistor, etc.; the third metal layer Mc can be used to fabricate the first reference voltage signal line (providing the first reset signal for the first reference voltage signal terminal RV1), etc. The active layer POLY can be used to fabricate the active part or the source / drain of each transistor.

[0110] Optionally, the film layer structure of the display panel can also include a fourth metal layer ( Figure 15(not shown in the figure), at least one of the data line and the first power supply signal line or the first reference voltage signal line may also be located in the fourth metal layer, which can effectively reduce the signal line density in the single-layer metal film layer structure, is beneficial to reducing the projected area of the overall structure of the pixel circuit 10 on the substrate 01, and improves the pixel density of the display panel. Optionally, the data line can be arranged in the fourth metal layer. With such an arrangement, in the direction perpendicular to the substrate 01, the film layer where the data line is located can be farther away from the film layer where the driving transistor DT is located, which is beneficial to reducing the signal crosstalk between the data line (providing the data voltage signal Vdata for the data voltage signal terminal DATA) and the gate connection structure N101 of the driving transistor DT (the structure shown by the dashed box in Figure 15 ), improving the stability of the gate signal of the driving transistor DT, and being beneficial to improving the display effect. Optionally, when the data line is arranged in the fourth metal layer, the first power supply signal line (the signal line providing the first voltage signal Vpvdd for the first power supply signal terminal PVDD) can be located in the third metal layer Mc and between the film layer where the data line is located and the film layer where the gate connection structure N101 of the driving transistor DT is located, which can improve the signal crosstalk between the two. The gate connection structure N101 of the driving transistor DT refers to the structure connecting the gate of the second data writing transistor T5 and the driving transistor DT to realize the signal transmission between the two. Optionally, at least a part of the first power supply signal line can be arranged in the fourth metal layer and the data line is located in the third metal layer Mc. At this time, the part of the first power supply signal line located in the fourth metal layer can be set as a mesh to reduce the voltage drop of the first power supply signal line and improve the display uniformity of the display panel.

[0111] When the pixel circuit 10 in the display panel 000 is set to Figure 11 the connection structure shown, its corresponding circuit layout structure is as shown in Figure 15 (for clearly showing the channel region of the first transistor T1 in this embodiment, Figure 15 in Figure 15 the positions of each signal line and each transistor are shown. It can be understood that the Figure 15 in this embodiment only shows a Figure 11 corresponding circuit layout structure of the pixel circuit. In specific implementation, it includes but is not limited to this design. In the Figure 15 of this embodiment, only the circuit layout of two sub-pixels (the first sub-pixel 00A and the second sub-pixel 00B) corresponding in the display panel is taken as an example to illustrate the different aspect ratios of the channel region of the first transistor. Specifically as follows:

[0112] As shown in Figure 16As shown, the first sub-pixel 00A includes a first transistor T1A and a light-emitting element 20A, and the second sub-pixel 00B includes a first transistor T1B and a light-emitting element 20B. The width WA and length LA of the channel region of the first transistor T1A are as Figure 16 shown, and the width WB and length LB of the channel region of the first transistor T1B are as Figure 16 shown. N1 = WA / LA, and N2 = WB / LB. It is possible to set the width WA of the channel region of the first transistor T1A to be greater than the width WB of the channel region of the first transistor T1B, and the length LA of the channel region of the first transistor T1A to be equal to the length LB of the channel region of the first transistor T1B, such that the aspect ratio N1 of the width to the length of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the width to the length of the channel region of the first transistor T1B in the second sub-pixel 00B. As Figure 16 shown, by setting the width of the first active portion T1P at the position of the channel region of the first transistor T1A in the first sub-pixel 00A in the second direction Y to be greater than the width of the first active portion T1P at the position of the channel region of the first transistor T1B in the second sub-pixel 00B in the second direction Y, it is possible to make the width WA of the channel region of the first transistor T1A greater than the width WB of the channel region of the first transistor T1B, and achieve that the aspect ratio N1 of the width to the length of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the width to the length of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0113] Alternatively, as Figure 17 shown, the first sub-pixel 00A includes a first transistor T1A and a light-emitting element 20A, and the second sub-pixel 00B includes a first transistor T1B and a light-emitting element 20B. The width WA and length LA of the channel region of the first transistor T1A are as Figure 17 shown, and the width WB and length LB of the channel region of the first transistor T1B are as Figure 17 shown. N1 = WA / LA, and N2 = WB / LB. It is also possible to set the width WA of the channel region of the first transistor T1A to be equal to the width WB of the channel region of the first transistor T1B, and the length LA of the channel region of the first transistor T1A to be less than the length LB of the channel region of the first transistor T1B, such that the aspect ratio N1 of the width to the length of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the width to the length of the channel region of the first transistor T1B in the second sub-pixel 00B. As Figure 17As shown, the width of the gate at the position of the channel region of the first transistor T1A in the first sub-pixel 00A in the first direction X is smaller than the width of the gate at the position of the channel region of the first transistor T1B in the second sub-pixel 00B in the first direction X. Then, the length LA of the channel region of the first transistor T1A can be made smaller than the length LB of the channel region of the first transistor T1B, so that the aspect ratio N1 of the width to length of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the width to length of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0114] It can be understood that in this embodiment, Figure 16 and Figure 17 only exemplarily show the structure for changing the aspect ratio of the channel region of the first transistor T1, including but not limited to this. In specific implementation, the aspect ratio of the channel region of the first transistor T1 can also be changed by other means, and in specific implementation, it can be set according to actual requirements.

[0115] In some alternative embodiments, please refer to Figure 1 、 Figure 11 、 Figure 15 、 Figure 18 and Figure 19 ,

[0116] Figure 18 is Figure 15 a comparison diagram of the first transistors in the first sub-pixel and the second sub-pixel in

[0117] Figure 19 is Figure 15 another comparison diagram of the first transistors in the first sub-pixel and the second sub-pixel in. In this embodiment, the width of the channel region of the first transistor T1A in the first sub-pixel 00A is W1, and the width of the channel region of the first transistor T1B in the second sub-pixel 00B is W2;

[0118] The length of the channel region of the first transistor T1A in the first sub-pixel 00A is L1, and the length of the channel region of the first transistor T1B in the second sub-pixel 00B is L2;

[0119] If W1 = W2, then L1 < L2; or,

[0120] If L1 = L2, then W1 > W2.

[0121] This embodiment explains a structure for changing the aspect ratio of the channel region of the first transistor T1, such as Figure 18As shown, by setting the width W1 of the channel region of the first transistor T1A in the first sub-pixel 00A equal to the width W2 of the channel region of the first transistor T1B in the second sub-pixel 00B, i.e., W1 = W2, the length L1 of the channel region of the first transistor T1A in the first sub-pixel 00A can be made less than the length L2 of the channel region of the first transistor T1B in the second sub-pixel 00B, i.e., L1 < L2; or, as Figure 19 shown, it is also possible to make the length L1 of the channel region of the first transistor T1A in the first sub-pixel 00A equal to the length L2 of the channel region of the first transistor T1B in the second sub-pixel 00B, i.e., L1 = L2, such that the width W1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the width W2 of the channel region of the first transistor T1B in the second sub-pixel 00B, i.e., W1 > W2, thereby achieving that the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B, so that the aspect ratios of the channel regions of the first transistors T1 connected to the different-color light-emitting elements 20 in the display panel 000 are different, to balance the display effects of different-color sub-pixels, avoid color deviation of the different-color light-emitting elements 20 at low gray levels, and improve the display effect of the display panel 000.

[0122] In some alternative embodiments, please continue to refer to Figure 1 、 Figure 11 、 Figure 15 、 Figure 18 and Figure 19 . In this embodiment, along the first direction X, in the first sub-pixel 00A, the length of the first gate T1G of the first transistor T1A is A1; in the second sub-pixel 00B, the length of the first gate T1G of the first transistor T1B is A2;

[0123] Along the second direction Y, in the first sub-pixel 00A, the length of the first active part T1P of the first transistor T1A is B1; in the second sub-pixel 00B, the length of the first active part T1P of the first transistor T1B is B2;

[0124] If A1 = A2, then B1 > B2; or,

[0125] If B1 = B2, then A1 < A2.

[0126] This embodiment explains how to Figure 19As shown, a structure that can increase the width W of the channel region of the first transistor T1 can increase the length B1 of the first active portion T1P of the first transistor T1A in the first sub-pixel 00A in the second direction Y, that is, the length A1 of the first gate T1G of the first transistor T1A in the first sub-pixel 00A in the first direction X is equal to the length A2 of the first gate T1G of the first transistor T1B in the second sub-pixel 00B, so that the length B1 of the first active portion T1P of the first transistor T1A in the first sub-pixel 00A in the second direction Y is greater than the length B2 of the first active portion T1P of the first transistor T1B in the second sub-pixel 00B, thereby equivalently increasing the width W1 of the channel region of the first transistor T1A in the first sub-pixel 00A, and thus realizing that the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0127] As Figure 18 shown, a structure that can decrease the length L of the channel region of the first transistor T1 can decrease the length A1 of the first gate T1G of the first transistor T1A in the first sub-pixel 00A in the first direction X, that is, the length B1 of the first active portion T1P of the first transistor T1A in the second direction Y is equal to the length B2 of the first active portion T1P of the first transistor T1B in the second sub-pixel 00B, so that the length A1 of the first gate T1G of the first transistor T1A in the first sub-pixel 00A in the first direction X is less than the length A2 of the first gate T1G of the first transistor T1B in the second sub-pixel 00B, thereby equivalently decreasing the length L1 of the channel region of the first transistor T1A in the first sub-pixel 00A, and thus realizing that the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0128] In some alternative embodiments, please refer to Figure 1 、 Figure 11 、 Figure 15 and Figure 20 、 Figure 21 ., Figure 20 is Figure 15 another comparison diagram of the first transistors in the first sub-pixel and the second sub-pixel, Figure 21 is Figure 15Another comparison diagram of the first transistor in the first sub-pixel and the second sub-pixel. In this embodiment, the first gate T1G includes a first sub-part T1G1 and a second sub-part T1G2. In the direction perpendicular to the light-emitting surface of the display panel 000, the first sub-part T1G1 overlaps with the first active part T1P, and the second sub-part T1G2 does not overlap with the first active part T1P. That is, the channel region T1C of the first transistor T1 refers to the region where the first sub-part T1G1 overlaps with the first active part T1P;

[0129] Along the first direction X, in the first sub-pixel 00A, the length of the first sub-part T1G1 of the first gate T1G of the first transistor T1A is C1, and the length of the second sub-part T1G2 is C2; in the second sub-pixel 00B, the length of the first sub-part T1G1 of the first gate T1G of the first transistor T1B is C3, and the length of the second sub-part T1G2 is C4;

[0130] Along the second direction Y, in the first sub-pixel 00A, the length of the first active part T1P of the first transistor T1A is D1, and in the second sub-pixel 00B, the length of the first active part T1P of the first transistor T1B is D2;

[0131] D1 = D2, C2 = C4, then C1 < C3.

[0132] This embodiment explains that different channel width-to-length ratios of the first transistor T1 corresponding to different colors can be achieved by making some different shape designs for the first gates of the first transistors corresponding to two different color light-emitting elements 20. Specifically:

[0133] Such as Figure 20As shown, along the first direction X, in the first sub-pixel 00A, the length of the first sub-portion T1G1 of the first gate T1G of the first transistor T1A is C1, and the length of the second sub-portion T1G2 is C2, where C1 < C2. That is, the first gate T1G of the first transistor T1A includes two segments with different widths. The length C1 of the first sub-portion T1G1 overlapping with the first active portion T1P along the first direction X is smaller. In the second sub-pixel 00B, the length C3 of the first sub-portion T1G1 of the first gate T1G of the first transistor T1B may be equal to the length C4 of the second sub-portion T1G2. That is, the first gate T1G of the first transistor T1B has no special shape design and remains a strip structure. At this time, along the second direction Y, when the length D1 of the first active portion T1P of the first transistor T1A in the first sub-pixel 00A is equal to the length D2 of the first active portion T1P of the first transistor T1B in the second sub-pixel 00B, i.e., D1 = D2, and along the first direction X, when the length C2 of the second sub-portion T1G2 of the first gate T1G of the first transistor T1A is still equal to the length C4 of the second sub-portion T1G2 of the first gate T1G of the first transistor T1B, i.e., C2 = C4, the length C1 of the first sub-portion T1G1 of the first gate T1G of the first transistor T1A along the first direction X is less than the length C3 of the first sub-portion T1G1 of the first gate T1G of the first transistor T1B. This is equivalent to reducing the length L1 of the channel region of the first transistor T1A by making a different shape design for the first gate T1G of the first transistor T1A, thereby increasing the aspect ratio of the channel region of the first transistor T1A in the first sub-pixel 00A and achieving that the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0134] As Figure 21As shown, along the first direction X, in the second sub-pixel 00B, the length of the first sub-portion T1G1 of the first gate T1G of the first transistor T1B is C3, and the length of the second sub-portion T1G2 is C4, where C3 > C4. That is, the first gate T1G of the first transistor T1B includes two segments with different widths. The length C3 of the first sub-portion T1G1 overlapping with the first active portion T1P along the first direction X is larger. In the first sub-pixel 00A, the length C1 of the first sub-portion T1G1 of the first gate T1G of the first transistor T1A may be equal to the length C2 of the second sub-portion T1G2. That is, the first gate T1G of the first transistor T1A has no special shape design and remains a long strip structure. At this time, along the second direction Y, when the length D1 of the first active portion T1P of the first transistor T1A in the first sub-pixel 00A is equal to the length D2 of the first active portion T1P of the first transistor T1B in the second sub-pixel 00B, i.e., D1 = D2, and along the first direction X, when the length C2 of the second sub-portion T1G2 of the first gate T1G of the first transistor T1A is still equal to the length C4 of the second sub-portion T1G2 of the first gate T1G of the first transistor T1B, i.e., C2 = C4, the length C1 of the first sub-portion T1G1 of the first gate T1G of the first transistor T1A along the first direction X is less than the length C3 of the first sub-portion T1G1 of the first gate T1G of the first transistor T1B. This is equivalent to increasing the length L2 of the channel region of the first transistor T1B by making different shape designs for the first gate T1G of the first transistor T1B, thereby reducing the aspect ratio of the channel region of the first transistor T1B in the second sub-pixel 00B and achieving that the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0135] In some alternative embodiments, please refer to Figure 1 、 Figure 11 、 Figure 15 and Figure 22 、 Figure 23 , Figure 22 is Figure 15 Another comparison diagram of the first transistors in the first and second sub-pixels in Figure 23 is Figure 15 Another comparison diagram of the first transistors in the first and second sub-pixels in

[0136] Along the second direction Y, in the first sub-pixel 00A, the length of the third sub-portion T1P of the first active portion T1P of the first transistor T1A is E1, and the length of the fourth sub-portion T1P2 is E2; in the second sub-pixel 00B, the length of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1B is E3, and the length of the fourth sub-portion T1P2 is E4;

[0137] Along the first direction X, in the first sub-pixel 00A, the length of the first gate T1G of the first transistor T1A is F1, and in the second sub-pixel 00B, the length of the first gate T1G of the first transistor T1B is F2;

[0138] If F1 = F2 and E2 = E4, then E1 > E3.

[0139] This embodiment explains that different channel width-to-length ratios of the first transistor T1 corresponding to different colors can be achieved by making some different shape designs for the first active portions of the first transistors corresponding to two light-emitting elements 20 of different colors. Specifically:

[0140] As Figure 22As shown, along the second direction Y, in the first sub-pixel 00A, the length of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1A is E1, and the length of the fourth sub-portion T1P2 is E2. E1>E2, that is, the first active portion T1P of the first transistor T1A includes two segments with different widths. The length E1 of the third sub-portion T1P1 overlapping with the first gate T1G along the second direction Y is larger. In the second sub-pixel 00B, the length E3 of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1B may be equal to the length E4 of the fourth sub-portion T1P2, that is, the first active portion T1P of the first transistor T1B has no special shape design and is still a strip structure. At this time, when the length F1 of the first gate T1G of the first transistor T1A in the first sub-pixel 00A is equal to the length F2 of the first gate T1G of the first transistor T1B in the second sub-pixel 00B along the first direction X, that is, F1 = F2, and when the length E2 of the fourth sub-portion T1P2 of the first active portion T1P of the first transistor T1A is still equal to the length E4 of the fourth sub-portion T1P2 of the first active portion T1P of the first transistor T1B along the second direction Y, that is, E2 = E4, the length E1 of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1A is greater than the length E3 of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1B along the second direction X. It is equivalent to increasing the width W1 of the channel region of the first transistor T1A by making different shape designs for the first active portion T1P of the first transistor T1A, so as to increase the aspect ratio of the channel region of the first transistor T1A in the first sub-pixel 00A, and achieve that the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0141] As Figure 23 shown, along the second direction Y, in the second sub-pixel 00B, the length of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1B is E3, and the length of the fourth sub-portion T1P2 is E4. E3<E4, that is, the first active portion T1P of the first transistor T1B includes two segments with different widths. The length E3 of the third sub-portion T1P1 overlapping with the first gate T1G along the second direction Y is smaller. In the first sub-pixel 00A, the length E1 of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1A may be equal to the length E2 of the fourth sub-portion T1P2, that is, the first active portion T1P of the first transistor T1A has no special shape design and is still a strip structure.

[0142] At this time, when the length F1 of the first gate T1G of the first transistor T1A in the first sub-pixel 00A is equal to the length F2 of the first gate T1G of the first transistor T1B in the second sub-pixel 00B along the first direction X, that is, F1 = F2, and when the length E2 of the fourth sub-portion T1P2 of the first active portion T1P of the first transistor T1A is still equal to the length E4 of the fourth sub-portion T1P2 of the first active portion T1P of the first transistor T1B along the second direction Y, that is, E2 = E4, such that the length E1 of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1A is greater than the length E3 of the third sub-portion T1P1 of the first active portion T1P of the first transistor T1B along the second direction X. This is equivalent to reducing the width W2 of the channel region of the first transistor T1B by making different shape designs for the first active portion T1P of the first transistor T1B, thereby reducing the aspect ratio of the channel region of the first transistor T1B in the second sub-pixel 00B, and achieving that the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B.

[0143] It should be noted that in this embodiment, only the shape of the channel region of the first transistor T1 is taken as a rectangle for example to clearly explain the width and length of the channel region. In specific implementation, the shape of the channel region is not limited to this, and the shape of the channel region may also include others, which can be understood by referring to other shapes in the related art. This embodiment is not limited.

[0144] It can be understood that Figures 18 - 23 only several exemplary embodiments are drawn in which the aspect ratios of the channel regions of the first transistors T1 connecting different color light-emitting elements 20 in the display panel 000 are different. In specific implementation, it includes but is not limited to this structure, and it can also be other structures that can change the aspect ratio of the transistor channel region. This embodiment will not be elaborated here.

[0145] In some alternative embodiments, please continue to refer to Figures 1 - 4 、 Figure 15, in this embodiment, the length L of the channel region T1C of the first transistor T1 satisfies L ≤ 3.5 μm, and the width W of the channel region T1C of the first transistor T1 satisfies W ≤ 3 μm. Optionally, the width W of the channel region T1C of the first transistor T1 is 2 μm. This embodiment explains that, in order to consider the entire layout space of the display panel 000 and avoid excessive space occupation by transistors in the display panel affecting the transmittance, generally in the pixel circuit 10, the length L of the channel region T1C of the first transistor T1 satisfies L ≤ 3.5 μm, and the width W of the channel region T1C of the first transistor T1 satisfies W ≤ 3 μm. For example, if the width W of the channel region T1C of the first transistor T1 is 2 μm, then the length L of the channel region T1C of the first transistor T1A in the first sub-pixel 00A can be 2.7 μm, and the length L of the channel region T1C of the first transistor T1B in the second sub-pixel 00B can be 3 μm. Thus, while the aspect ratio N1 of the channel region of the first transistor T1A in the first sub-pixel 00A is greater than the aspect ratio N2 of the channel region of the first transistor T1B in the second sub-pixel 00B, it is also beneficial to ensure the transmittance of the display panel and improve the display effect.

[0146] In some alternative embodiments, please refer to Figure 1 、 Figure 4 、 Figure 11 、 Figure 15 、 Figure 24 、 Figure 25 , Figure 24 is Figure 11 another circuit layout when the circuit structure in Figure 25 is Figure 11 is made on the display panel. In this embodiment, the first sub-pixel 00A includes a first via R1A and at least one second via R2A. In the direction parallel to the light-emitting surface of the display panel 000, the distance K1 from the first via R1A to the channel region of the first transistor T1A is less than the distance K3 from the second via R2A to the channel region of the first transistor T1A;

[0147] The second sub-pixel 00B includes a third via R1B and at least one fourth via R2B. In the direction parallel to the light-emitting surface of the display panel 000, the distance K2 from the third via R1B to the channel region of the first transistor T1B is less than the distance K4 from the fourth via R2B to the channel region of the first transistor T1B;

[0148] K1 < K2.

[0149] This embodiment explains that when fabricating the pixel circuit structure using different conductive film layers in the display panel 000, it is often necessary to electrically connect structures located in mutually insulated and different conductive film layers to achieve signal transmission. For example, in combination with Figure 11 andFigure 15 As shown, the first source T1S of the first transistor T1 is connected to the first reference voltage signal terminal RV1. The first source T1S is located in the second metal layer M2, and the first reference voltage signal line where the first reference voltage signal terminal RV1 is located is in the third metal layer M C , and in order to achieve electrical connection between the two, a via R penetrating the insulating layer between the second metal layer M2 and the third metal layer M C needs to be provided. It can be understood that a plurality of vias R need to be included in the pixel circuit 10 of a sub-pixel 00.

[0150] During the manufacturing process, during the production of vias, hydrogen ions (hydrogen ions existing at the interface between the gate insulating layer and the active portion) are very likely to evaporate through the vias. Therefore, by adjusting the distance between the vias and the channel region of the first transistor T1 in different sub-pixels 00, the characteristics of the first transistor can be adjusted. The more hydrogen ions evaporate, the worse the on or off performance of the first transistor T1; the less hydrogen ions evaporate, the better the on or off performance of the first transistor T1.

[0151] In this embodiment, the first sub-pixel 00A includes a first via R1A and at least one second via R2A. In the direction parallel to the light-emitting surface of the display panel 000, the distance K1 from the first via R1A to the channel region of the first transistor T1A is less than the distance K3 from the second via R2A to the channel region of the first transistor T1A. That is, it can be understood that the first via R1A is the via closest to the channel region of the first transistor T1A, and the second via R2A can be one, or two or more. Compared with any other second via R2A in the first sub-pixel 00A, the distance from the first via R1A to the channel region of the first transistor T1A is the closest; similarly, the second sub-pixel 00B includes a third via R1B and at least one fourth via R2B. In the direction parallel to the light-emitting surface of the display panel 000, the distance K2 from the third via R1B to the channel region of the first transistor T1B is less than the distance K4 from the fourth via R2B to the channel region of the first transistor T1B. That is, it can be understood that the third via R1B is the via closest to the channel region of the first transistor T1B, and the fourth via R2B can be one, or two or more. Compared with any other fourth via R2B in the second sub-pixel 00B, the distance from the third via R1B to the channel region of the first transistor T1B is the closest. Optionally, as Figure 15 and Figure 24 shown, the first via R1A can be understood as the first source of the first transistor T1A in the second metal layer M2 of the first sub-pixel 00A and the third metal layer M CThe third via R1B can be understood as a via hole connected to the first reference voltage signal line of the second sub-pixel 00B and the first source of the first transistor T1B of the second metal layer M2 and the third metal layer M C The vias connected to the first reference voltage signal line, that is, the vias closest to the channel region of the first transistor T1 in different sub-pixels can be vias that realize the same function, or in some other embodiments, the vias closest to the channel region of the first transistor T1 in different sub-pixels can also be vias of different types, and it is only necessary to satisfy that the first via R1A is the via closest to the channel region of the first transistor T1A, and the third via R1B is the via closest to the channel region of the first transistor T1B. It can be understood that the distance from the channel region to the via in this embodiment can be the distance between the edge position of the channel region closest to the via and the edge position of the via closest to the channel region in a direction parallel to the light-emitting surface of the display panel 000, or when the channel region and the via are both geometric images, it can also be understood as the distance between the geometric center of the channel region and the geometric center of the via in a direction parallel to the light-emitting surface of the display panel 000 (such as Figure 24 shown).

[0152] It should be noted that this embodiment is only an example of drawing the first via R1A closest to the first transistor T1A and the third via R1B closest to the first transistor T1B in the circuit layout. Figure 15 and Figure 24 , Figure 25 As shown, the layout range of the design of the first sub-pixel 00A and the second sub-pixel 00B may also include the first transistor in the sub-pixel of the previous row. At this time, the transistor can also be designed with different distances between the via and its channel region, so that the performance of the first sub-pixel in the previous row is changed. The principle is similar to that of the present embodiment, and this embodiment will not be repeated here.

[0153] This embodiment is arranged in the direction parallel to the light-emitting surface of the display panel 000. The distance K1 from the first via R1A to the channel region of the first transistor T1A in the first sub-pixel 00A is less than the distance K2 from the third via R1B to the channel region of the first transistor T1B in the second sub-pixel 00B. This can make there be a via within a relatively short distance range of the channel region of the first transistor T1A, thereby accelerating the evaporation of hydrogen ions of the first transistor T1A in the first sub-pixel 00A, increasing the evaporation amount of hydrogen ions of the first transistor T1A in the first sub-pixel 00A, which is beneficial to reducing the on or off performance of the first transistor T1A in the first sub-pixel 00A. Thus, the brightness fluctuation of the light-emitting element 20A in the first sub-pixel 00A at low gray levels can be reduced, and as much as possible, it can reach the same brightness fluctuation level as the light-emitting element 20B in the second sub-pixel 00B. Finally, the brightness fluctuations of light-emitting elements 20 of different colors under environmental changes can be balanced as much as possible, enabling the light-emitting elements 20 of different colors to emit light normally at low gray levels, avoiding color deviation phenomena, and further enabling the white screen display at low gray levels to be normal, which is beneficial to improving the display effect of the display panel 000 at low gray levels.

[0154] Optionally, in this embodiment Figure 24 is only an example to illustrate that the characteristics of the transistor can be adjusted by changing the position of the via closest to the channel region of the first transistor T1 in the sub-pixel 00. In specific implementation, the methods for adjusting the characteristics of the transistor include but are not limited to this. It can also be achieved by increasing the number of vias around the first transistor T1A in the first sub-pixel 00A (not shown in the figure). It can also be achieved by increasing the aperture Q1 of the first via R1A, that is, making the aperture Q1 of the first via R1A larger than the aperture Q2 of the third via R1B, so that the edge of the first via R1A approaches the channel region of the first transistor T1A, thereby reducing the distance K1 from the first via R1A to the channel region of the first transistor T1A (as Figure 25 shown). It can also be achieved by adding virtual vias around the first transistor T1A in the first sub-pixel 00A to increase the evaporation amount of hydrogen ions, or it can be other implementation methods. In specific implementation, it can be selected and set according to actual requirements, and this embodiment will not elaborate here.

[0155] It should be further noted that this embodiment only takes Figure 15 the circuit layout as an example to illustrate the via closest to the first transistor T1 around it, including but not limited to this via. In specific implementation, it can be designed according to the actual circuit layout, and this embodiment will not elaborate here.

[0156] In some alternative embodiments, please refer to Figure 26 , Figure 26It is a schematic structural diagram of a display device provided by an embodiment of the present invention. The display device 111 provided in this embodiment includes the display panel 000 provided by the above-mentioned embodiment of the present invention. Figure 26 In this embodiment, only a mobile phone is taken as an example to illustrate the display device 111. It can be understood that the display device 111 provided by the embodiment of the present invention can be other display devices 111 with a display function, such as a computer, a television, a vehicle-mounted display device, etc. The present invention does not make specific limitations thereto. The display device 111 provided by the embodiment of the present invention has the beneficial effects of the display panel 000 provided by the embodiment of the present invention. For specific descriptions of the display panel 000, reference can be made to the above embodiments, and details are not repeated herein.

[0157] Through the above embodiments, it can be seen that the display panel and the display device provided by the present invention have at least achieved the following beneficial effects:

[0158] In the display panel provided by the present invention, the aspect ratio of the channel region of the first transistor in the first sub-pixel is greater than that of the channel region of the first transistor in the second sub-pixel, which can make the leakage current of the first transistor in the first sub-pixel greater than that of the first transistor in the second sub-pixel. As a result, when the light-emitting element in the first sub-pixel emits light at a low gray level, compared with the second sub-pixel, a larger current leaks from the first transistor in the first sub-pixel, reducing the luminous efficiency of the light-emitting element in the first sub-pixel, which is beneficial to enhancing its brightness stability. If the luminous efficiency of the light-emitting element in the first sub-pixel is originally greater than that of the light-emitting element in the second sub-pixel, then by setting the aspect ratio of the channel region of the first transistor in the first sub-pixel to be greater than that of the channel region of the first transistor in the second sub-pixel, the luminous efficiency of the light-emitting element in the first sub-pixel can be reduced to be as consistent or substantially consistent as possible with that of the light-emitting element in the second sub-pixel. That is, the brightness fluctuation of the light-emitting element in the first sub-pixel at a low gray level is reduced, so that the brightness increase amplitude of the light-emitting element in the first sub-pixel is reduced, and it is made to reach the same brightness increase amplitude as that of the light-emitting element in the second sub-pixel as much as possible. Finally, the brightness fluctuations of light-emitting elements of different colors under environmental changes are balanced as much as possible, enabling the light-emitting elements of different colors to emit light normally at a low gray level, avoiding color deviation phenomena, and further enabling the white screen display at a low gray level to be normal, which is beneficial to improving the display effect of the display panel at a low gray level. Moreover, in the present invention, the aspect ratio of the channel region of the first transistor in the first sub-pixel with a small turn-on voltage is set to be greater than that of the channel region of the first transistor in the second sub-pixel with a large turn-on voltage. Since the larger the aspect ratio of the channel region of a transistor, the greater the leakage current of the transistor, when the light-emitting element in the second sub-pixel is turned on and carriers migrate to the light-emitting element in the first sub-pixel, the strong leakage current performance of the first transistor in the first sub-pixel can be used to conduct the leakage current in the state where the first transistor in the first sub-pixel is turned off, so as to avoid the light-emitting element in the first sub-pixel from stealing light, which is beneficial to improving the display effect. The present invention balances the display effects of sub-pixels of different colors by setting different aspect ratios of the channel regions of the first transistors connected to the anodes of light-emitting elements of different colors in the display panel, avoiding the situation where some color sub-pixels steal light when other color sub-pixels emit light, and also avoiding color deviation phenomena of light-emitting elements of different colors at a low gray level. Furthermore, it is beneficial to improving the display effect of the display panel at a low gray level without affecting the panel circuit structure and overall performance.

[0159] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present invention. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, Comprising: A plurality of sub-pixels, the sub-pixels including a pixel circuit and a light-emitting element connected electrically, the pixel circuit including a first transistor, a first pole of the first transistor being connected to a first reference voltage signal terminal, a second pole of the first transistor being electrically connected to an anode of the light-emitting element; if the first transistor is a P-type transistor, the first pole of the first transistor is a drain, and the second pole of the first transistor is a source; if the first transistor is an N-type transistor, the first pole of the first transistor is a source, and the second pole of the first transistor is a drain; wherein, in a light-emitting holding stage of the sub-pixel, the first reference voltage signal terminal accesses a negative potential signal or a ground potential signal; the plurality of sub-pixels at least include a first sub-pixel and a second sub-pixel, a color of the first sub-pixel being different from a color of the second sub-pixel; a width-to-length ratio of a channel region of the first transistor in the first sub-pixel being N1, a width-to-length ratio of the channel region of the first transistor in the second sub-pixel being N2; wherein, N1 > N2.

2. The display panel according to claim 1, wherein At a first gray scale, a light-emitting efficiency of the light-emitting element in the first sub-pixel is greater than a light-emitting efficiency of the light-emitting element in the second sub-pixel; wherein, a gray scale value of the first gray scale is Gray, 5 ≤ Gray ≤ 65.

3. The display panel according to claim 1, wherein The pixel circuit further includes a reset transistor, a first pole of the reset transistor being connected to the anode of the light-emitting element, a second pole of the reset transistor being connected to a reset signal terminal.

4. The display panel according to claim 3, wherein The pixel circuit further includes a driving transistor, the second pole of the first transistor being connected to a drain of the driving transistor, the drain of the driving transistor being electrically connected to the anode of the light-emitting element.

5. The display panel according to claim 3, characterized in that, The first transistor is multiplexed as the reset transistor, and the first reference voltage signal terminal is multiplexed as the reset signal terminal.

6. The display panel according to claim 4, wherein, The pixel circuit further includes a data writing module and a light-emitting control module; The light-emitting control module is respectively electrically connected to a first voltage signal terminal and the anode of the light-emitting element; a cathode of the light-emitting element is electrically connected to a second power supply signal terminal; The driving transistor is respectively electrically connected to the light-emitting control module and the data writing module.

7. The display panel according to claim 6, wherein, it further includes a second transistor, a first pole of the second transistor being connected to the first reference voltage signal terminal, a second pole of the second transistor being connected to a gate of the driving transistor.

8. The display panel according to claim 6, wherein, It further includes a third transistor, a first pole of the third transistor being connected to a second reference voltage signal terminal, a second pole of the third transistor being connected to the gate of the driving transistor; a potential accessed by the second reference voltage signal terminal is different from a potential accessed by the first reference voltage signal terminal.

9. The display panel according to claim 8, wherein The potential accessed by the second reference voltage signal terminal is greater than the potential accessed by the first reference voltage signal terminal.

10. The display panel according to claim 6, wherein, The data writing module includes a first data writing transistor and a second data writing transistor. A first pole of the first data writing transistor is connected to a data voltage signal terminal, and a second pole of the first data writing transistor is connected to a first pole of the driving transistor. A first pole of the second data writing transistor is connected to a gate of the driving transistor, and a second pole of the second data writing transistor is connected to a second pole of the driving transistor. The light emission control module includes a first light emission control transistor and a second light emission control transistor. A first pole of the first light emission control transistor is connected to the first voltage signal terminal, and a second pole of the first light emission control transistor is connected to a first pole of the driving transistor. A first pole of the second light emission control transistor is connected to a second pole of the driving transistor, and a second pole of the second light emission control transistor is connected to an anode of the light emitting element. A storage capacitor is further included. One end of the storage capacitor is connected to the first voltage signal terminal, and the other end of the storage capacitor is connected to a gate of the driving transistor.

11. The display panel according to claim 10, wherein, A second pole of the first transistor is connected to a second pole of the driving transistor, and the second pole of the first transistor is connected to a first pole of the second light emission control transistor.

12. The display panel according to claim 1, wherein The first transistor is a P-type transistor, and the first transistor includes a first active portion, and the first active portion includes a silicon semiconductor.

13. The display panel according to claim 12, wherein the first transistor further includes a first gate, a first source, and a first drain; Along a first direction, a length of a channel region of the first transistor is L, along a second direction, a width of the channel region of the first transistor is W, and an aspect ratio of the channel region of the first transistor is W / L; Wherein, in a direction parallel to a light-emitting surface of the display panel, a direction from the first source to the first drain is the first direction, and the second direction intersects the first direction.

14. The display panel according to claim 13, wherein a width of the channel region of the first transistor in the first sub-pixel is W1, and a width of the channel region of the first transistor in the second sub-pixel is W2; a length of the channel region of the first transistor in the first sub-pixel is L1, and a length of the channel region of the first transistor in the second sub-pixel is L2; If W1 = W2, then L1 < L2; or If L1 = L2, then W1 > W2.

15. The display panel according to claim 13, wherein along the first direction, in the first sub-pixel, a length of the first gate of the first transistor is A1; in the second sub-pixel, a length of the first gate of the first transistor is A2; along the second direction, in the first sub-pixel, a length of the first active portion of the first transistor is B1; in the second sub-pixel, a length of the first active portion of the first transistor is B2; If A1 = A2, then B1 > B2; or If B1 = B2, then A1 < A2.

16. The display panel according to claim 13, wherein The first gate includes a first sub - part and a second sub - part. In a direction perpendicular to the light - emitting surface of the display panel, the first sub - part overlaps with the first active part, and the second sub - part does not overlap with the first active part; Along the first direction, in the first sub - pixel, the length of the first sub - part of the first gate of the first transistor is C1, and the length of the second sub - part is C2; in the second sub - pixel, the length of the first sub - part of the first gate of the first transistor is C3, and the length of the second sub - part is C4; Along the second direction, in the first sub - pixel, the length of the first active part of the first transistor is D1, and in the second sub - pixel, the length of the first active part of the first transistor is D2; D1 = D2, C2 = C4, then C1 < C3.

17. The display panel according to claim 13, wherein The first active part includes a third sub - part and a fourth sub - part. In a direction perpendicular to the light - emitting surface of the display panel, the third sub - part overlaps with the first gate, and the fourth sub - part does not overlap with the first gate; Along the second direction, in the first sub - pixel, the length of the third sub - part of the first active part of the first transistor is E1, and the length of the fourth sub - part is E2; in the second sub - pixel, the length of the third sub - part of the first active part of the first transistor is E3, and the length of the fourth sub - part is E4; Along the first direction, in the first sub - pixel, the length of the first gate of the first transistor is F1, and in the second sub - pixel, the length of the first gate of the first transistor is F2; F1 = F2, E2 = E4, then E1 > E3.

18. The display panel according to claim 13, wherein, The length L of the channel region of the first transistor satisfies L ≤ 3.5 μm, and the width W of the channel region of the first transistor ≤ is 3 μm.

19. The display panel according to claim 1, wherein The first sub - pixel includes a first via and at least one second via. In a direction parallel to the light - emitting surface of the display panel, the distance from the first via to the channel region of the first transistor is less than the distance from the second via to the channel region of the first transistor; wherein, the distance from the first via to the channel region of the first transistor in the first sub - pixel is K1; The second sub - pixel includes a third via and at least one fourth via. In a direction parallel to the light - emitting surface of the display panel, the distance from the third via to the channel region of the first transistor is less than the distance from the fourth via to the channel region of the first transistor; wherein, the distance from the third via to the channel region of the first transistor in the second sub - pixel is K2; K1 < K2.

20. The display panel according to claim 1, wherein The light - emitting element in the first sub - pixel is any one of a red light - emitting element or a green light - emitting element, and the light - emitting element in the second sub - pixel is a blue light - emitting element.

21. The display panel according to claim 1, wherein The light - emitting element in the first sub - pixel is a red light - emitting element, and the light - emitting element in the second sub - pixel is a green light - emitting element.

22. The display panel according to claim 1, wherein The light - emitting element includes an organic light - emitting diode.

23. The display panel according to claim 1, wherein The shape of the channel region of the first transistor is rectangular.

24. A display device, characterized in that, Including the display panel according to any one of claims 1 - 23.

Images