Charge pump and electronic device including the same

Abstract

The present invention discloses a charge pump and an electronic device including the same. The charge pump includes a voltage converter, a signal generator, and a control module. The signal generator has a first input connected to the positive voltage output of the voltage converter, a second input connected to a reference power supply, and an output connected to the gate of a fourth NMOS transistor. The present invention uses the charge pump's signal generator to control the fourth NMOS transistor to turn on or off based on the positive voltage output of the voltage converter and an input reference voltage. This controls the voltage converter's positive voltage output to output a voltage between 1 and 2 times the power supply voltage, and its negative voltage output to output a voltage between -1 and -2 times the power supply voltage. This increases the charge pump's voltage output variation range, reduces output ripple, and increases circuit load capacity.

Description

Technical Field

[0001] The present invention belongs to the technical field of converters, and in particular relates to a charge pump and an electronic device comprising the same. Background Art

[0002] Currently, charge pumps, also known as switched-capacitor voltage converters, are DC-DC converters that utilize so-called "flying" or "pumping" capacitors (rather than inductors or transformers) to store energy. These DC-DC converters utilize capacitors as energy storage elements and are typically used to generate output voltages greater than the input voltage, or to generate negative output voltages. While charge pump circuits offer high electrical efficiency, approximately 90-95%, and are relatively simple, current pumps currently offer a narrow output voltage range, low current load, and high output ripple, making them unsuitable for current market demands. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the defect in the prior art that the voltage variation range of the charge pump output is small, and to provide a charge pump and an electronic device including the same.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] The present invention provides a charge pump, which includes a voltage converter, a signal generator, and a control module;

[0006] The voltage converter includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first capacitor, and a second capacitor;

[0007] The gates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fifth PMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all connected to the control module;

[0008] The drain of the first PMOS transistor and the source of the third PMOS transistor are both connected to a power supply, and the source of the first PMOS transistor is respectively connected to the drain of the second PMOS transistor and one end of the first capacitor;

[0009] The source of the second PMOS transistor is connected to the drain of the fifth PMOS transistor to form a positive voltage output terminal of the voltage converter;

[0010] The drain of the third PMOS transistor is connected to the other end of the first capacitor and the drain of the fourth NMOS transistor respectively;

[0011] The source of the fifth PMOS transistor of the voltage converter is connected to one end of the second capacitor and the drain of the sixth NMOS transistor respectively;

[0012] The source of the fourth NMOS transistor, the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor are all grounded, the drain of the seventh NMOS transistor is connected to the other end of the second capacitor and the drain of the eighth NMOS transistor respectively, and the source of the eighth NMOS transistor forms a negative voltage output terminal of the voltage converter;

[0013] The first input terminal of the signal generator is connected to the positive voltage output terminal, the second input terminal is connected to the reference power supply, and the output terminal is connected to the gate of the fourth NMOS transistor.

[0014] Preferably, the signal generator includes a comparator and a transmission gate, wherein the transmission gate is used to change the period of the input signal and enhance the driving capability of the input signal;

[0015] The first input terminal of the comparator is connected to the positive voltage output terminal, the second input terminal is connected to the reference power supply, and the output terminal is connected to the input terminal of the transmission gate;

[0016] The output end of the transmission gate is connected to the gate of the fourth NMOS transistor.

[0017] Preferably, the comparator includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a first resistor, and a second resistor;

[0018] The source of the ninth PMOS tube and the source of the twenty-second PMOS tube, that is, the source of the twenty-first PMOS tube, are respectively connected to a power supply, and the drain of the ninth PMOS tube is respectively connected to the source of the tenth PMOS tube and the source of the eleventh PMOS tube;

[0019] The drain of the tenth PMOS transistor is connected to the drain of the thirteenth NMOS transistor and the drain of the twelfth NMOS transistor respectively;

[0020] The drain of the eleventh PMOS tube is connected to the drain of the twelfth NMOS tube and the source of the thirteenth NMOS tube respectively;

[0021] The source of the twelfth NMOS tube, the source of the thirteenth NMOS tube, the source of the eighteenth NMOS tube, and the source of the nineteenth NMOS tube are all grounded, and the drain of the twelfth NMOS tube is connected to the source of the fourteenth NMOS tube;

[0022] The drain of the thirteenth NMOS tube is connected to the source of the fifteenth NMOS tube;

[0023] The drain of the fourteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor and one end of the first resistor respectively;

[0024] The other end of the first resistor is connected to one end of the second resistor, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor respectively;

[0025] The other end of the second resistor is respectively connected to the drain of the seventeenth PMOS transistor, the drain of the fifteenth NMOS transistor, and the gate of the twentieth PMOS transistor;

[0026] The drain of the twenty-second PMOS transistor is connected to the gate of the twenty-second transistor, the source of the sixteenth PMOS transistor, and the source of the seventeenth PMOS transistor respectively;

[0027] The drain of the twenty-first PMOS transistor is connected to the source of the twentieth PMOS transistor;

[0028] The drain of the eighteenth NMOS transistor is respectively connected to the drain of the twentieth PMOS transistor, the gate of the twentieth PMOS transistor, and the gate of the nineteenth NMOS transistor;

[0029] The drain of the twenty-first PMOS transistor and the drain of the nineteenth NMOS transistor form the output end of the comparator;

[0030] The gates of the ninth PMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the twenty-first PMOS transistor all receive a driving signal of a fixed level;

[0031] The gate of the tenth PMOS tube receives the reference power supply;

[0032] The gate of the eleventh PMOS tube is connected to the positive voltage output terminal.

[0033] Preferably, the transmission gate includes a twenty-third PMOS transistor, a twenty-fourth NMOS transistor and a twenty-fifth PMOS transistor;

[0034] The drain of the twenty-third PMOS transistor, the drain of the twenty-fourth NMOS transistor, and the drain of the twenty-fifth PMOS transistor are all connected to the gate of the fourth NMOS transistor, and the source of the twenty-third PMOS transistor and the source of the twenty-fourth NMOS transistor are all connected to the output terminal of the comparator;

[0035] The gates of the twenty-third PMOS transistor, the twenty-fourth NMOS transistor, and the twenty-fifth PMOS transistor are all connected to the control module;

[0036] The source of the twenty-fifth PMOS tube is connected to a power source.

[0037] Preferably, the control module includes a first level flip unit, a second level flip unit, a third level flip unit, a first NOT gate, a first NAND gate and a second NAND gate;

[0038] The output end of the first level flip unit is connected to the first input end of the first NAND gate through the first NOT gate, the output end of the first NAND gate is connected to the input end of the second level flip unit, the output end of the second level flip unit is respectively connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the gate of the third PMOS transistor, the second input end of the first NAND gate is connected to the input end of the third level flip unit, and the first level flip unit receives a driving signal;

[0039] The output end of the first level flip unit is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the input end of the second level flip unit, the output end of the second NAND gate is connected to the input end of the third level flip unit, and the output end of the third level flip unit is respectively connected to the gate of the fifth PMOS tube, the gate of the sixth NMOS tube, the gate of the seventh NMOS tube, and the gate of the eighth NMOS tube.

[0040] Preferably, an even number of NOT gates are connected between the output end of the first NAND gate and the input end of the second level flip unit.

[0041] Preferably, an even number of NOT gates are connected between the second NAND gate and the input end of the third level flip unit.

[0042] Preferably, the control module further includes a signal generating unit;

[0043] The driving signal is generated by the signal generating unit.

[0044] Preferably, the driving signal is generated by an external signal generator.

[0045] The present invention provides an electronic device, comprising the charge pump described above.

[0046] The positive and progressive effect of the present invention is that the signal generator of the charge pump controls the opening or closing of the fourth NMOS tube according to the positive voltage output by the voltage converter and the reference voltage connected, thereby controlling the positive voltage output end of the voltage converter to output 1 times the power supply voltage to 2 times the power supply voltage, and the negative voltage output end to output -1 times the power supply voltage to -2 times the power supply voltage, so that the voltage output variation range of the charge pump is increased, the output ripple is small, and the circuit load capacity is large. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 This is a structural block diagram of a charge pump provided in Example 1 of the present invention.

[0048] Figure 2 This is a circuit diagram of a voltage converter of a charge pump according to embodiment 1 of the present invention.

[0049] Figure 3 Schematic diagram of the structure of the signal generator of the charge pump according to embodiment 1 of the present invention.

[0050] Figure 4 This is a circuit diagram of a comparator of a charge pump according to embodiment 1 of the present invention.

[0051] Figure 5 This is a circuit diagram of a transmission gate of a charge pump according to embodiment 1 of the present invention.

[0052] Figure 6 Schematic diagram of the structure of the control module of the charge pump according to embodiment 1 of the present invention.

[0053] Figure 7 FIG. 1 is a timing diagram of a driving signal of a charge pump according to the first embodiment of the present invention.

[0054] Figure 8 This is a structural block diagram of another charge pump provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0055] The present invention is further described below by way of examples, but the present invention is not limited to the scope of the examples.

[0056] Example 1

[0057] This embodiment provides a charge pump, such as Figure 1 As shown, the charge pump includes a voltage converter 1 , a signal generator 2 , and a control module 3 .

[0058] like Figure 2As shown, the voltage converter 1 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth NMOS transistor M4, a fifth PMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a first capacitor C1, and a second capacitor C2.

[0059] The gates of the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, the fifth PMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, and the eighth NMOS transistor M8 are all connected to the control module, the drain of the first PMOS transistor M1 and the source of the third PMOS transistor M3 are both connected to a power supply, the source of the first PMOS transistor M1 is respectively connected to the drain of the second PMOS transistor M2 and one end of the first capacitor C1, the source of the second PMOS transistor M2 is connected to the drain of the fifth PMOS transistor M5, forming a positive voltage output end of the voltage converter, and the drain of the third PMOS transistor M3 is respectively connected to the other end of the first capacitor C1 and the drain of the fourth NMOS transistor M4; The source of the fifth PMOS transistor M5 of the voltage converter is respectively connected to one end of the second capacitor C2 and the drain of the sixth NMOS transistor M6; the source of the fourth NMOS transistor M4, the source of the sixth NMOS transistor M6, and the source of the seventh NMOS transistor M7 are all grounded, the drain of the seventh NMOS transistor M7 is respectively connected to the other end of the second capacitor C2 and the drain of the eighth NMOS transistor M8, and the source of the eighth NMOS transistor M8 forms the negative voltage output end of the voltage converter.

[0060] like Figure 3 As shown, the first input terminal of the signal generator 2 is connected to the positive voltage output terminal, the second input terminal is connected to the reference power supply, and the output terminal is connected to the gate of the fourth NMOS transistor M4.

[0061] In this embodiment, the gate of the fourth NMOS transistor M4 can be independently controlled by the signal generator 2, thereby controlling the fourth NMOS transistor M4 to be half-on (not fully on) or half-off (not fully off). The output voltage of the positive voltage output terminal of the voltage converter is controlled to be between VCC and 2VCC, thereby increasing the voltage variation range of the charge pump output. The voltage output from the positive voltage output terminal of the voltage converter is fed back to the first input terminal of the signal generator 2 to form a feedback loop, so that the entire control loop is in a dynamic balance state, which is conducive to controlling the charge pump to output an ideal voltage.

[0062] Specifically, see Figure 8As shown, the signal generator 2 includes a comparator 21 and a transmission gate 22. The transmission gate is used to change the period of the input signal and enhance the driving capability of the input signal.

[0063] like Figure 3 As shown, the first input terminal of the comparator 21 is connected to the positive voltage output terminal, the second input terminal is connected to the reference power supply, and the output terminal is connected to the input terminal of the transmission gate; the output terminal of the transmission gate is connected to the gate of the fourth NMOS transistor M4.

[0064] Specifically, if Figure 4 FIG2 is a circuit diagram of a comparator, wherein the comparator 21 includes a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth NMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth NMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, a twentieth PMOS transistor M20, a twenty-first PMOS transistor M21, a twenty-second PMOS transistor M22, a first resistor R1, and a second resistor R2.

[0065] The source of the ninth PMOS transistor M9 and the source of the twenty-second PMOS transistor M22 (i.e., the source of the twenty-first transistor) are respectively connected to a power supply, and the drain of the ninth PMOS transistor M9 is respectively connected to the source of the tenth PMOS transistor M10 and the source of the eleventh PMOS transistor M11;

[0066] The drain of the tenth PMOS transistor M10 is connected to the drain of the thirteenth NMOS transistor M13 and the drain of the twelfth NMOS transistor M12 respectively; the drain of the eleventh PMOS transistor M11 is connected to the drain of the twelfth NMOS transistor M12 and the source of the thirteenth NMOS transistor M13 respectively; the source of the twelfth NMOS transistor M12, the source of the thirteenth NMOS transistor M13, the source of the eighteenth NMOS transistor M18 and the source of the nineteenth NMOS transistor M19 are all grounded, the drain of the twelfth NMOS transistor M12 is connected to the drain of the fourteenth NMOS transistor M14. The drain of the thirteenth NMOS transistor M13 is connected to the source of the fifteenth NMOS transistor M15; the drain of the fourteenth NMOS transistor M14 is respectively connected to the drain of the sixteenth PMOS transistor M16 and one end of the first resistor R1; the other end of the first resistor R1 is respectively connected to one end of the second resistor R2, the gate of the sixteenth PMOS transistor M16, and the gate of the seventeenth PMOS transistor M17; the other end of the second resistor R2 is respectively connected to the drain of the seventeenth PMOS transistor M17, the drain of the fifteenth NMOS transistor M15, and the gate of the twentieth PMOS transistor M20; the drain of the twenty-second PMOS transistor M22 is respectively connected to the gate of the twenty-second, the source of the sixteenth PMOS transistor M16, and the source of the seventeenth PMOS transistor M17; the drain of the twenty-first PMOS transistor M21 is respectively connected to the gate of the twentieth PMOS The comparator comprises a first transistor M20 connected to the source of the first transistor M20; a second transistor M21 connected to the drain of the eighth NMOS transistor M18; a third transistor M22 connected to the drain of the eighth PMOS transistor M20, the gate of the eighth PMOS transistor M20, and the gate of the ninth NMOS transistor M19; a fourth transistor M21 connected to the drain of the ninth PMOS transistor M21 and the drain of the ninth NMOS transistor M19 form the output terminal of the comparator; a fourth transistor M21 connected to the gate of the ninth PMOS transistor M9, the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13, the fourteenth NMOS transistor M14, the fifteenth NMOS transistor M15, and the twenty-first PMOS transistor M21 all receive a fixed-level drive signal, which may be generated by the control module 3 or received from an external input. The gate of the tenth PMOS transistor M10 receives the reference power supply; and the gate of the eleventh PMOS transistor M11 is connected to the positive voltage output terminal.

[0067] Comparator 21's M9-M17 form the front stage of comparator 21, a folded amplifier structure. Gate resistors M16 and M17 maintain a consistent VDS+ voltage across M16 and M17, maintaining consistent impedance. The back stage, M18-M21, forms the comparator's output stage, driving the gate of the charge pump's fourth NMOS transistor, M4. Due to loop circuitry, the output voltage of comparator 21 is not a digital high or low level, but rather an intermediate level between the two. This results in the CLK4 signal turning the fourth NMOS transistor M4 into a half-on state, ensuring that the charge pump's output voltage, VP (positive voltage output terminal), remains between VCC and 2VCC.

[0068] Specifically, if Figure 5 2 is a circuit diagram of a transmission gate. The transmission gate 22 includes a twenty-third PMOS transistor M23, a twenty-fourth NMOS transistor M24 and a twenty-fifth PMOS transistor M25.

[0069] The drain of the twenty-third PMOS transistor M23, the drain of the twenty-fourth NMOS transistor M24, and the drain of the twenty-fifth PMOS transistor M25 are all connected to the gate of the fourth NMOS transistor, and the source of the twenty-third PMOS transistor M23 and the source of the twenty-fourth NMOS transistor M24 are all connected to the output end of the comparator; the gates of the twenty-third PMOS transistor M23, the twenty-fourth NMOS transistor M24, and the twenty-fifth PMOS transistor M25 are all connected to the control module; and the source of the twenty-fifth PMOS transistor M25 is connected to the power supply.

[0070] The control module 3 outputs a CLK_VOP signal to the gate of the twenty-third PMOS transistor M23. The CLK_VOP signal can control the turning on or off of the twenty-third PMOS transistor M23. The control module 3 outputs a CLK6_VOP_n signal to the gate of the twenty-fourth NMOS transistor M24. The CLK6_VOP_n signal can control the turning on or off of the twenty-fourth NMOS transistor M24. The control module 3 outputs a CLK5_VOP signal to the gate of the twenty-fifth PMOS transistor M25. The CLK5_VOP signal can control the turning on or off of the twenty-fifth PMOS transistor M25.

[0071] CLK5 and CLK5_VOP are in phase, CLK6 and CLK6_VOP are in phase, and CLK6_VOP_n and CLK6_VOP are in opposite phases.

[0072] Specifically, the principle of the transmission gate is:

[0073] (1) (When CLK6_VOP is 0 and CLK6_VOP_n is VCC, the major premise) At the same time, when CLK_VOP5 is VCC, the signal is transmitted, such as Figure 3 As shown, at this time, the transmission gate outputs the fourth driving signal CLK4 for controlling the fourth NMOS transistor M4 to turn on or off; when CLK_VOP5 is 0, the output level is a driving signal of VCC.

[0074] (2) When CLK6_VOP is VCC and CLK6_VOP_n is 0, no drive signal is output.

[0075] Specifically, if Figure 8 As shown, the control module 3 includes a first level flip unit 31 , a second level flip unit 32 , a third level flip unit 33 , a first NOT gate 34 , a first NAND gate 35 , a second NAND gate 36 and a NOT gate 38 .

[0076] The output end of the first level flip unit 31 is connected to the first input end of the first NAND gate 35 through the first NOT gate 34. The output end of the first NAND gate 35 is connected to the input end of the second level flip unit 32. The output end of the second level flip unit 32 is respectively connected to the gate of the first PMOS transistor M1, the gate of the second PMOS transistor M2, and the gate of the third PMOS transistor M3. The second input end of the first NAND gate 35 is connected to the input end of the third level flip unit 33. The first level flip unit 31 receives a driving signal.

[0077] See also Figure 6 As shown, the first driving signal CLK1 can control the opening or closing of the first PMOS transistor M1; the second driving signal CLK2 can control the opening or closing of the second PMOS transistor M2; and the third driving signal CLK3 can control the opening or closing of the third PMOS transistor M3.

[0078] The output end of the first level flip unit 31 is connected to the first input end of the second NAND gate 36, the second input end of the second NAND gate 36 is connected to the input end of the second level flip unit 32, the output end of the second NAND gate 36 is connected to the input end of the third level flip unit 33, and the output end of the third level flip unit 33 is respectively connected to the gate of the fifth PMOS transistor M5, the gate of the sixth NMOS transistor M6, the gate of the seventh NMOS transistor M7, and the gate of the eighth NMOS transistor M8.

[0079] See also Figure 6As shown, the output end of the third level flip unit 33 outputs a fifth driving signal CLK5, a sixth driving signal CLK6, a seventh driving signal CLK7 and an eighth driving signal CLK8 that respectively control the gate of the fifth PMOS transistor M5, the gate of the sixth NMOS transistor M6, the gate of the seventh NMOS transistor M7 and the gate of the eighth NMOS transistor M8.

[0080] Specifically, the timing relationship diagram of the eight drive signals can be found in Figure 7 As shown, no further details will be given here.

[0081] Specifically, if Figure 6 As shown, an even number of NOT gates 38 are connected between the output end of the first NAND gate 35 and the input end of the second level flip unit 32; the number of NOT gates 38 can be set according to actual needs. Preferably, four NOT gates 38 are set in this embodiment. For the specific connection relationship of the four NOT gates 38, please refer to Figure 6 The content shown.

[0082] An even number of NOT gates 38 are connected between the second NAND gate 36 and the input end of the third level flip unit 33. The more the number of NOT gates 38 is, the greater the current driving capability is.

[0083] Specifically, see Figure 8 As shown, the control module 3 further includes a signal generating unit 37 , and the driving signal received by the first level flip unit can be generated by the signal generating unit 37 . The input end of the first level flip unit 31 is connected to the output end of the signal generating unit 37 .

[0084] Preferably, the driving signal received by the first level flip unit 31 may also be generated by an external signal generator.

[0085] Specifically, the working principle of the charge pump can be divided into the following four processes:

[0086] (1) The third PMOS transistor M3 and the second PMOS transistor M2 are turned off, the first PMOS transistor M1 and the fourth NMOS transistor M4 are turned on, and the first capacitor C1 is charged.

[0087] (2) The first PMOS transistor M1 and the fourth NMOS transistor are turned off, the third PMOS transistor M3 and the second PMOS transistor M2 are turned on, the first capacitor C1 is discharged, and the positive voltage output terminal VP of the voltage converter 1 outputs a voltage from VCC to 2VCC, achieving double voltage output.

[0088] (3) The sixth NMOS transistor M6 and the eighth NMOS transistor M8 are turned off, the fifth PMOS transistor M5 and the seventh NMOS transistor M7 are turned on, and the second capacitor C2 is charged.

[0089] (4) The fifth PMOS transistor M5 and the seventh NMOS transistor M7 are turned off, the sixth NMOS transistor M6 and the eighth NMOS transistor M8 are turned on, the second capacitor C2 is discharged, and the negative voltage output terminal VN of the voltage converter 1 outputs a voltage of -VCC to -2VCC, thereby achieving negative voltage output.

[0090] Specifically, the process of the signal generator 2 controlling the voltage change of the fourth NMOS transistor M4 and the VP (positive voltage terminal) of the voltage converter is as follows:

[0091] 1. The voltage at the VP (positive voltage output) terminal of the voltage converter is initially low. Vref is a fixed reference voltage. VP and Vref are compared by a comparator to generate a first-level signal, which is between 0 and half of VCC. This first-level signal is driven by the transmission gate, increasing its current and controlling the gate of the fourth NMOS transistor M4, turning it on. However, this is not fully on, and the VP voltage increases (charging the first capacitor C1).

[0092] 2. VP is fed back to the comparator and compared with the Vref voltage, outputting a second-level signal opposite to the first-level signal. The second-level signal passes through the transmission gate again to control the gate of the fourth NMOS transistor M4, reducing the current of the fourth NMOS transistor M4. However, the transistor M4 is not completely shut down, causing the VP voltage to decrease. Processes 1 and 2 form a feedback loop. Under this dynamic balance, CLK4 exhibits periodic changes in high and low voltage (which changes with the drive signal).

[0093] In this embodiment, the signal generator of the charge pump controls the on / off state of the fourth NMOS transistor M4 according to the positive voltage output by the voltage converter and the input reference voltage, thereby controlling the output voltage of the positive voltage output terminal of the voltage converter to be between VCC and 2VCC, and the output voltage of the negative voltage output terminal to be between -VCC and -2VCC. This increases the voltage output variation range of the charge pump. Furthermore, the feedback loop responds quickly, the control structure is relatively simple, and the output ripple of the charge pump is reduced. In addition, the load capacity of the charge pump circuit can be increased by adjusting the width-to-length ratio of the switching MOS transistor.

[0094] Example 2

[0095] The present invention provides an electronic device, comprising the charge pump described in Example 1, wherein the charge pump and the electronic device are electrically connected.

[0096] The electronic device of this embodiment has the circuit function of a charge pump and has the same technical effect as the charge pump.

[0097] Although specific embodiments of the present invention have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of the present invention is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, and such changes and modifications are intended to fall within the scope of the present invention.

Claims

1. A charge pump, characterized in that: The charge pump includes a voltage converter, a signal generator, and a control module; The voltage converter includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first capacitor, and a second capacitor; The gates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fifth PMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all connected to the control module; The drain of the first PMOS transistor and the source of the third PMOS transistor are both connected to a power supply, and the source of the first PMOS transistor is respectively connected to the drain of the second PMOS transistor and one end of the first capacitor; The source of the second PMOS transistor is connected to the drain of the fifth PMOS transistor to form a positive voltage output terminal of the voltage converter; The drain of the third PMOS transistor is connected to the other end of the first capacitor and the drain of the fourth NMOS transistor respectively; The source of the fifth PMOS transistor of the voltage converter is connected to one end of the second capacitor and the drain of the sixth NMOS transistor respectively; The source of the fourth NMOS transistor, the source of the sixth NMOS transistor, and the source of the seventh NMOS transistor are all grounded, the drain of the seventh NMOS transistor is connected to the other end of the second capacitor and the drain of the eighth NMOS transistor respectively, and the source of the eighth NMOS transistor forms a negative voltage output terminal of the voltage converter; The first input terminal of the signal generator is connected to the positive voltage output terminal, the second input terminal is connected to the reference power supply, and the output terminal is connected to the gate of the fourth NMOS transistor; the signal generator controls the on or off of the fourth NMOS transistor through the positive voltage output by the voltage converter and the input reference voltage, thereby increasing the voltage variation range of the charge pump.

2. The charge pump according to claim 1, wherein The signal generator includes a comparator and a transmission gate, wherein the transmission gate is used to change the period of the input signal and enhance the driving capability of the input signal; The first input terminal of the comparator is connected to the positive voltage output terminal, the second input terminal is connected to the reference power supply, and the output terminal is connected to the input terminal of the transmission gate; The output end of the transmission gate is connected to the gate of the fourth NMOS transistor.

3. The charge pump according to claim 2, wherein: The comparator includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a first resistor and a second resistor; The source of the ninth PMOS transistor, the source of the twenty-second PMOS transistor, and the source of the twenty-first PMOS transistor are respectively connected to a power supply, and the drain of the ninth PMOS transistor is respectively connected to the source of the tenth PMOS transistor and the source of the eleventh PMOS transistor; The drain of the tenth PMOS transistor is connected to the drain of the thirteenth NMOS transistor and the drain of the twelfth NMOS transistor respectively; The drain of the eleventh PMOS tube is connected to the drain of the twelfth NMOS tube and the source of the thirteenth NMOS tube respectively; The source of the twelfth NMOS transistor, the source of the thirteenth NMOS transistor, the source of the eighteenth NMOS transistor, and the source of the nineteenth NMOS transistor are all grounded, and the drain of the twelfth NMOS transistor is connected to the source of the fourteenth NMOS transistor; The drain of the thirteenth NMOS tube is connected to the source of the fifteenth NMOS tube; The drain of the fourteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor and one end of the first resistor respectively; The other end of the first resistor is connected to one end of the second resistor, the gate of the sixteenth PMOS transistor, and the gate of the seventeenth PMOS transistor respectively; The other end of the second resistor is respectively connected to the drain of the seventeenth PMOS transistor, the drain of the fifteenth NMOS transistor, and the gate of the twentieth PMOS transistor; The drain of the twenty-second PMOS transistor is respectively connected to the gate of the twenty-second PMOS transistor, the source of the sixteenth PMOS transistor, and the source of the seventeenth PMOS transistor; The drain of the twenty-first PMOS transistor is connected to the source of the twentieth PMOS transistor; The drain of the eighteenth NMOS transistor is respectively connected to the drain of the twentieth PMOS transistor, the gate of the twentieth PMOS transistor, and the gate of the nineteenth NMOS transistor; The drain of the twenty-first PMOS transistor and the drain of the nineteenth NMOS transistor form the output end of the comparator; The gates of the ninth PMOS transistor, the twelfth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the twenty-first PMOS transistor all receive a driving signal of a fixed level; The gate of the tenth PMOS tube is connected to the reference power supply; The gate of the eleventh PMOS tube is connected to the positive voltage output terminal.

4. The charge pump according to claim 2, wherein: The transmission gate includes a twenty-third PMOS transistor, a twenty-fourth NMOS transistor and a twenty-fifth PMOS transistor; The drain of the twenty-third PMOS transistor, the drain of the twenty-fourth NMOS transistor, and the drain of the twenty-fifth PMOS transistor are all connected to the gate of the fourth NMOS transistor, and the source of the twenty-third PMOS transistor and the source of the twenty-fourth NMOS transistor are all connected to the output terminal of the comparator; The gates of the twenty-third PMOS transistor, the twenty-fourth NMOS transistor, and the twenty-fifth PMOS transistor are all connected to the control module; The source of the twenty-fifth PMOS tube is connected to a power source.

5. The charge pump according to claim 1, wherein: The control module includes a first level flip unit, a second level flip unit, a third level flip unit, a first NOT gate, a first NAND gate, and a second NAND gate; The output end of the first level flip unit is connected to the first input end of the first NAND gate through the first NOT gate, the output end of the first NAND gate is connected to the input end of the second level flip unit, the output end of the second level flip unit is respectively connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, and the gate of the third PMOS transistor, the second input end of the first NAND gate is connected to the input end of the third level flip unit, and the first level flip unit receives a driving signal; The output end of the first level flip unit is connected to the first input end of the second NAND gate, the second input end of the second NAND gate is connected to the input end of the second level flip unit, the output end of the second NAND gate is connected to the input end of the third level flip unit, and the output end of the third level flip unit is respectively connected to the gate of the fifth PMOS tube, the gate of the sixth NMOS tube, the gate of the seventh NMOS tube, and the gate of the eighth NMOS tube.

6. The charge pump according to claim 5, wherein: An even number of NOT gates are connected between the output end of the first NAND gate and the input end of the second level flip unit.

7. The charge pump according to claim 5, wherein: An even number of NOT gates are connected between the second NAND gate and the input end of the third level flip unit.

8. The charge pump according to claim 5, wherein: The control module further includes a signal generating unit; The driving signal is generated by the signal generating unit.

9. The charge pump according to claim 5, wherein: The driving signal is generated by an external signal generator.

10. An electronic device, characterized in that: The electronic device comprises the charge pump according to any one of claims 1 to 9.

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