Generation of a set of raised quasi-cyclic LDPC codes

Abstract

This invention relates to the generation of a set of raised quasi-cyclic LDPC codes. Methods for generating codes, methods for encoding and decoding data, and encoders and decoders for performing encoding and decoding are disclosed. In an embodiment, the method for raising subcodes from a base code for encoding and decoding data includes determining a single combination of a cycle size, a raising function, and a label base matrix (PCM) based on information length and coding rate using data stored in a raising table. The raising table is defined during the code generation phase. The method also includes calculating multiple shifts for the subcodes. Each shift is calculated by applying the raising function to the label base matrix (PCM) using an index defined with the cycle size, and the resulting subPCM is used to encode or decode data.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefits of U.S. Nonprovisional Application No. 15 / 968,597, filed May 1, 2018, and U.S. Provisional Application No. 62 / 500,370, filed May 2, 2017, which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to systems and methods for communicating in wireless networks, and in particular embodiments to methods for raising subcodes from base codes for encoding and decoding data, methods for generating codes for encoding or decoding data, methods for operating devices on the transmitting side, methods for operating devices on the receiving side, and corresponding encoders and decoders. Background Technology

[0004] Parity check codes are used to facilitate the recovery of stored data and data transmitted over communication channels. One type of parity check code is called Low-Density Parity-Check (LDPC), which is characterized by a sparse parity check matrix (PCM)—that is, a PCM with a low percentage of 1s. An LDPC encoder at the transmitter is used to encode the source word to generate codewords. An LDPC decoder at the receiver is used to decode the received codewords. LDPC codes at various coding rates are widely used or considered for use in data storage and wireless communication technologies and standards (such as those related to IEEE 802.11 and 5G).

[0005] Almost all LDPC codes used in practice are QC LDPCs with a quasi-cyclic (QC) parity-check matrix, where the quasi-cyclic identity matrix can be combined with an array of shift information (i.e., a QC shifted PCM) to define an extended QC PCM (e.g., a QC LDPC PCM). QC LDPC encoding and recovery algorithms, as well as the storage of PCM information, can consume significant hardware resources, thus creating a need for methods, systems, and techniques to improve the efficiency of the hardware resources required for QC LDPC encoding systems and reduce the hardware resources required for QC LDPC encoding systems. Summary of the Invention

[0006] Implementations of this disclosure provide a method for lifting subcodes from a base code for encoding and decoding data. The method includes determining a single combination of a circumstant size, a lifting function, and a labeled base matrix (PCM) based on information length and coding rate using data stored in a lifting table. The lifting table is defined during the code generation phase. The method also includes calculating multiple shifts for the subcode. Each shift is calculated by applying the lifting function to the labeled base matrix (PCM) using an index defined with the circumstant size, and using the resulting subPCM to encode or decode data. The method further includes obtaining the subPCM based on a single combination of the circumstant size, the lifting function, and the labeled PCM, and based on one of the multiple shifts for the subcode. The method also includes using the resulting subPCM to encode or decode data.

[0007] Implementations of this disclosure provide a method for generating codes. The method includes determining a subset of permissible boost sizes Z for each coding rate R and each information length K. The method also includes determining at least one boost function f for each coding rate R and each permissible Z. i The method also includes determining a set of base PCMs describing a single prototype graph. The base PCMs are based on the coding rate R and the allowable Zs. The method also includes selecting the lifting size Z and the lifting function f. i and PCM t The method also includes storing, for each information length and each coding rate, a corresponding cycle size offset and / or cycle size index, lifting function index, and basecode index for each individual combination.

[0008] Embodiments of this disclosure provide a method for operating a device on the transmitting side. The method includes encoding information bits into codewords at an encoder. The method also includes transmitting a signal to a receiving side at a transmitter. The signal includes the codewords. The information bits are encoded using multiple tag-based PCMs. The tag-based PCMs are derived from a single base PCM describing a single prototype diagram.

[0009] Embodiments of this disclosure provide a method for operating a device on a receiving side. The method includes receiving a signal from a transmitting side at a receiver. The signal includes codewords. The method further includes decoding the codewords at a decoder by applying extracted information bits. The information bits are decoded using multiple tag-based PCMs. The tag-based PCMs are derived from a single base PCM describing a single prototype diagram.

[0010] Embodiments of this disclosure provide an encoder or decoder. The encoder or decoder includes a processor and a computer-readable storage medium storing a program for execution by the processor. The program includes instructions for determining a single combination of a cycle size, a boosting function, and a tag PCM based on an information length and a coding rate using data stored in a boosting table defined during a code generation phase. The program also includes instructions for calculating multiple shifts for a subcode, wherein each shift is calculated by applying the boosting function to the tag PCM using an index defined with the cycle size. The program further includes instructions for obtaining a subPCM based on the single combination of the cycle size, the boosting function, and the tag PCM, and based on one of the multiple shifts for the subcode. The program also includes instructions for encoding or decoding data using the obtained subPCM.

[0011] In one or more aspects of this disclosure, the shift of non-zero circulants at predefined locations remains unchanged.

[0012] In one or more aspects of this disclosure, the lifting function is selected from a single lifting function.

[0013] In one or more aspects of this disclosure, the lifting function is selected from a plurality of lifting functions.

[0014] In one or more aspects of this disclosure, the label base matrix PCM is obtained directly from the cycle size.

[0015] In one or more aspects of this disclosure, the loop size is Z, where Z = a * 2^s.

[0016] In one or more aspects of this disclosure, the lifting function provides a code shift value.

[0017] In one or more aspects of this disclosure, the information bits have different bit lengths and are encoded at different coding rates.

[0018] In one or more aspects of this disclosure, the tag base PCM is selected based on the coding rate.

[0019] In one or more aspects of this disclosure, encoding includes switching from a first-label PCM to a second-label PCM when the encoding rate changes from a first encoding rate to a second encoding rate.

[0020] In one or more aspects of this disclosure, the encoding includes switching from a first-mark PCM to a second-mark PCM when the boost size changes from a first boost size to a second boost size, wherein the first boost size and the second boost size depend on different information bit lengths.

[0021] In one or more aspects of this disclosure, decoding includes switching from a first-label PCM to a second-label PCM when the coding rate changes from a first coding rate to a second coding rate.

[0022] In one or more aspects of this disclosure, decoding includes switching from a first-mark PCM to a second-mark PCM when the boost size changes from a first boost size to a second boost size, wherein the first boost size and the second boost size depend on different information bit lengths.

[0023] In one or more embodiments, high performance is achieved by providing rate-adaptive codes (switching from one code rate to another), by providing message-length adaptive codes, or by providing a combination of rate-adaptive and message-length adaptive codes. Other embodiments provide simple hardware based on these. One or more disclosed embodiments rely on some coding scheme (PCM matrix) that is flexible with respect to code rate and message length. This has the advantage that the embodiments provide generally optimal performance under varying conditions while also saving storage space. Attached Figure Description

[0024] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0025] Figure 1 This is a diagram showing a 3×6 parity check matrix (PCM) H and its corresponding Tanner plot representation;

[0026] Figure 2 This is a diagram showing a 4×6 PCM H and its corresponding Tanner plot representation;

[0027] Figure 3 Flowchart 300 shows the process for constructing the lifting table T;

[0028] Figures 4A to 4C Examples of possible promotion tables T are shown;

[0029] Figure 5A , Figure 5B-1 and Figure 5B-2 An example of a first base diagram or prototype diagram is shown;

[0030] Figure 6A , Figures 6B-1 to 6B-4 , Figure 7A , Figures 7B-1 to 7B-4 , Figure 8A , Figures 8B-1 to 8B-4 Figure 9A Figures 9B-1 to 9B-4 , Figure 10A , Figures 10B-1 to 10B-4 , Figure 11A , Figures 11B-1 to 11B-4 Figure 12A Figures 12B-1 to 12B-2 , Figure 13A and Figures 13B-1 to 13B-4 The specific implementation shown in the first figure is illustrated;

[0031] Figure 14A-1 , Figure 14A-2 and Figures 14B-1 to 14B-3 An example of a second base diagram or prototype diagram is shown;

[0032] Figure 15A , Figures 15B-1 to 15B-3 , Figure 16A , Figures 16B-1 to 16B-3 , Figure 17A , Figure 17B-1 To Figure 17B-3, Figure 18A , Figures 18B-1 to 18B-3 , Figure 19A , Figures 19B-1 to 19B-3 , Figure 20A , Figure 20B-1 to Figure 20B-3 , Figure 21A , Figures 21B-1 to 21B-3 , Figure 22A , Figures 22B-1 to 22B-3 , Figure 23A and Figure 23B-1 to Figure 23B-3 An implementation of a single marker is shown in the second figure;

[0033] Figures 24A-1 to 24A-6 and Figures 24B-1 to 24B-3 An implementation of the lifting table T for the first figure is shown;

[0034] Figures 24C-1 to 24C-6 and Figures 24D-1 to 24D-6 An implementation of the lifting table T for the second figure is shown;

[0035] Figures 25A to 25D The performance improvements of the decoders in Tables T1 and T2 are shown when applied to different information lengths and different coding rates R.

[0036] Figure 26 This is a block diagram of an implementation of an LDPC encoder;

[0037] Figure 27 This is a block diagram of an implementation of an LDPC decoder;

[0038] Figure 28 This is a flowchart of an implementation method for encoding data using LDPC, an explanatory lifting table, and an explanatory lifting function;

[0039] Figure 29 This is a flowchart illustrating an implementation method for decoding data using LDPC, an illustrated lifting table, and an illustrated lifting function;

[0040] Figure 30 A block diagram of a processing system for performing the methods described herein is shown, which can be installed in a host device.

[0041] Figure 31 A block diagram of a transceiver suitable for sending and receiving signals over a remote communication network is shown.

[0042] Figure 32 A network of implementations for transmitting data in which the disclosed methods and systems can be implemented is shown. Detailed Implementation

[0043] The implementation and use of the currently preferred embodiments will be discussed in detail below. However, it should be understood that this disclosure provides many applicable inventive concepts that can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways to implement and use this disclosure and do not limit the scope of this disclosure.

[0044] This document discloses systems, methods, and apparatus for encoding / decoding data using LDPC. Various implementations include offset boosting processes for determining cyclic offsets to encode / decode data. Furthermore, various implementations include non-sequential cyclic offsets and larger cyclic offsets than those in the prior art. Various implementations also include multiple boosting functions. Having large cyclic offsets allows for faster determination of the optimal offset and consumes fewer system resources than prior art methods (e.g., less offline simulation during boosting table construction, less memory required to store the boosting table in the encoder / decoder, etc.). Moreover, different boosting functions can be better suited for encoding codewords of different lengths.

[0045] Implementations of this disclosure also provide flexible methods for allocating codes (or matrices) as the information length size K and coding rate R vary (over time). Various implementations provide coding methods capable of switching between permissible boost values ​​Z and different labeled PCMs for different choices of the same prototype. Various other implementations provide methods capable of switching between different PCMs based on the coding rate R and boost value Z. Further implementations provide boost tables for various ranges of coding rates R and information length K. The resulting codes are advantageous because they provide boost values ​​and labeled PCMs for a given information length size K and coding rate R.

[0046] High performance can be achieved by providing rate-adaptive codes (to switch from one coding rate to another), by providing message-length adaptive codes, or by providing a combination of rate-adaptive and message-length adaptive codes. Other implementations provide simple hardware based on these methods.

[0047] These implementations rely on some coding schemes (PCM matrices) that are flexible with respect to coding rate and information length. This has the advantage that the implementation provides optimal performance in each case while saving storage space.

[0048] Figure 1 Figure 100 shows a 3×6 parity check matrix (PCM) H 102 and its corresponding Tanner graph representation 104. LDPC codes are defined by a sparse parity check matrix (PCM), which is a matrix of (NK) rows multiplied by N columns, where N is the codeword size (the number of bits in a codeword) and K is the information block size of the source word (the number of message bits in each codeword). Tanner graph 104 is a graphical representation of the parity check matrix specifying the parity check equation. In the described example, Tanner graph 104 includes 3 check nodes (CNs) c1, c2, and c3 and 6 variable nodes (VNs) v1, v2, v3, v4, v5, and v6. The Tanner graph consists of N variable nodes (VNs) and M check nodes (CNs). In the described example, Tanner diagram 104 includes 3 CNs—c1, c2, and c3—and 6 VNs—v1, v2, v3, v4, v5, and v6. Figure 1 In the Tanner diagram 104 shown, if and only if the nth element h in the mth row of the parity check matrix H... mn When the value is 1, the m-th check node is connected to the n-th variable node.

[0049] Figure 2 This is diagram 200 showing a 4×6 PCM H 202 and its corresponding Tanner diagram representation 204. The receiving entity can decode the received codewords encoded according to PCM H by applying PCM H in conjunction with a message passing algorithm (MPA). For example... Figure 2 As shown in the example, LDPC decoding using MPA is an iterative decoding algorithm using the structure of Tanner Figure 204. In the LDPC decoder, the nth element h in the m-th row of PCM H is defined as follows: mn When the value is 1, each m-th check node (C1, C2, C3) is connected to the n-th variable node (V1, ..., V6).

[0050] In practical applications, PCMs are typically configured as more structured matrices rather than simple sets of binary 1s and 0s. For example, more structured matrices are used to support a class of LDPC codes known as quasi-cyclic (QC) LDPCs, which are generated by cyclic permutation matrices with column weights of 1. Specifically, such as... Figure 2 As shown, LDPC PCM H can be partitioned into a set of square submatrices P of size Z×Z. i This set of submatrices is either a cyclic permutation of the identity matrix P0 or an empty submatrix with all entries set to 0. The size Z of the QC submatrix is ​​called the cyclic size and also the lifting factor. The identity matrix P0 has elements "1" on the diagonal from the top left to the bottom right and elements "0" everywhere else. The index value i can be used to represent the cyclic permutation submatrix P obtained from the Z×Z identity matrix P0 by cyclically shifting the columns i elements to the right. i As an example, Figure 2 The diagram shows a 4×6 LDPC PCM H partitioned into a set of 2×2 square submatrices. Submatrix P0 is the identity matrix, and submatrix P1 is obtained by circularly shifting the columns of submatrix P0 one bit to the right. QC LDPC allows a large PCM to be represented as a smaller, structured PCM in which each Z×Z submatrix is ​​represented by its index value i in the corresponding cell position of the QC PCM. As an example, Figure 2 In this context, a 4×6 PCM H can be re-represented as a 2×3 QC PCM H. c (and therefore it can be obtained from 2×3 QC PCM H) c (Generated), where each unit includes a cyclic shift index value or a null value. As used in this paper, H can be referred to as the prototype diagram of the code (i.e., the prototype diagram matrix). From H to H c The transformation is often referred to as "edge labeling" or simply "labeling". Additionally, as used in this article, H... c It can be called a marker prototype diagram or a marker matrix.

[0051] QC LDPC codes are typically decoded by message-passing decoders such as BP, Min-Sum, and their variants (NMSA, OMSA, etc.). The performance of QC LDPC codes depends on various factors, such as the distribution of row and column weights (often optimized using density evolution methods), code distance, trap set, and the number of short cycles. However, existing encoding / decoding systems and algorithms, as well as the storage of PCM information, consume significant system resources.

[0052] Therefore, to support fine-grained information length and adaptive coding rate, nested code families can be used, where adaptive coding rate R and adaptive length K are performed by puncturing (removing) parity bits and shortening (padding) information bits. Thus, a simple and powerful method is needed to construct a sub-PCM based on each (tagged) base PCM.

[0053] Nesting means adapting the code to the coding rate R by punching (removing) parity bits. The PCM itself corresponds to the lower or lowest code. If one or more columns (or cyclic columns or bit columns) are removed from the right (punching) and the same number of rows are removed from the bottom of the PCM, the PCM can still be used for encoding / decoding, but the coding rate R has changed (increased). This procedure can be performed incrementally until the smallest possible PCM is identified (called the "core" PCM corresponding to the highest coding rate). Therefore, a PCM is actually a composite code containing a set of nested codes. These are called "nested" subcodes of the code, which correspond to nested subgraphs of the main (maximum) graph of the code.

[0054] Switching between coding rates is accomplished by switching from one subcode to another. If additional parity bits are required for retransmission (meaning switching from one nested subcode (equivalent to a "smaller" PCM) to another (nested) subcode (equivalent to a "larger" PCM) (meaning the code has a lower coding rate)), the lifting method may remain unchanged (or, in other implementations, may not be allowed to be changed). Therefore, a lifting table can be shared for these subcodes.

[0055] As mentioned above, the storage and use of QC PCM information can be resource-intensive. Therefore, embodiments of this disclosure provide QC PCM methods and systems that allow the same QC PCM information to be adaptively used to support a range of different information coding rates R and information block sizes K. Thus, this document discloses methods and systems relating to shortening, puncturing, and boosting QC LDPC codes. Shortening means padding information bits with 0s to exactly match the given coding rate (these bits are not transmitted but are used as 0s by the encoder and decoder). Shortened bits can be filled from somewhere on the left, right, or even in the middle of the information block. Punching means removing some unwanted parity bits to increase the coding rate of the code. This corresponds to cutting off the last few columns and the same number of rows from the PCM.

[0056] To support fine-grained information length adaptation and coding rate adaptation, nested code families can be used, where coding rate and length adaptation are performed by puncturing parity bits and shortening information bits. Therefore, this paper describes a simple and powerful boosting method to construct a sub-PCM based on several base PCMs.

[0057] Figure 3 A flowchart 300 for constructing a robust parity check code is shown. Specifically, the code is a rate-adaptive code. The basal PCM corresponds to the lowest possible code rate. The code rate is changed, i.e., increased, by removing or punching one or more columns from the right side and removing or punching the same number of rows from the bottom of the basal PCM. Based on this (e.g., a stepwise process), the smallest possible PCM for a high code rate (called the "core" PCM) can be identified. Therefore, the basal PCM represents a set of codes.

[0058] In the first step, at position 302, a subset Z of multiple permissible boost sizes Z is determined for each coding rate R and each information length K. i First, calculate the minimum lift size Z. orig =K / K b Where k is the number of information bits and K b K is the number of information columns in the prototype diagram. For a specific hardware device, such as a decoder or encoder, K... b It is usually fixed. K b It can be 10, 16, or 22. K b It can have other values ​​in the teens or twenties. For all base PCMs and all labeled PCMs, K... b They can be the same. Second, determine a set of permissible Z, i.e., Z0 allowed Among them, Z allowed ≥Z orig The allowable value of Z can be a predefined fixed value, a*2. sA set of permissible values ​​Z in the form of , where a is a positive integer and s is a non-negative integer. Furthermore, a range of values ​​for a and s, or (a, s) pairs, can be specified. For example, if a ∈ {1, 2, ..., 16}, s ∈ {0, 1, 2, ..., 256}, and Z = a * 2 s Then Z can be restricted to be no less than 8 and no greater than 384. allowed It could be:

[0059] Z allowed ={8:1:16}∪{16:2:32}∪{32:4:64}∪{64:8:128}∪{128:16:256}∪{256:32:384}.

[0060] Third, select the allowable boost size Z. allowed A subset m. In an implementation, subset m can be a set such that Z ≥ Z. orig Z allowed The minimum number of m. In the alternative implementation, the allowable boost size Z. allowed A subset m can be such that K b ≤K bmax And Z≥Z orig The lowest m options of Z. Here, K b The number of information QC columns and K in the unshortened PCM bmax This is the maximum number of information columns in the PCM for the given K and R.

[0061] In various other implementations, additional constraints may be imposed. For example, the minimum m options for Z could be Z ≥ max(Z min Z orig ), where Z∈Z allowed And among them, Z min This is the minimum possible lift size. In a specific example, m can be equal to 8. Therefore, there are m distinct Zs for each coding rate R and each message length K. However, for each coding rate R and each message length K, only one of these Zs is stored in memory (e.g., a lift table).

[0062] In the next step, at step 304, for each coding rate R and for each Z∈Z allowed Define at least one promotion function f i Promotion function f i It can be defined as follows:

[0063] Each lifting function f i Use formula h child j =f i (hbase Z) provides non-negative integer shift values ​​for the subcode PCM, where h base It is the non-negative 1 shift value of the base code PCM, and h child j Therefore, the shift value of the subcode is obtained.

[0064] For example, the lifting function f i It can have the following forms:

[0065] h child j =h base mod 2 [log2(Z)] , where [x] is the (integral) part of x.

[0066] h child j =h base mod Z

[0067] h child j =[h base *Z / Z max ], where Z max It is the increase in the base PCM.

[0068] h child j =h base >>]log2(Z max / Z)[, where >> is a right binary shift operation (i.e., a >> b = [a / 2)] b And x[ is the upper integer part of x.

[0069] In various implementations, the number of lifting functions n can be equal to 1, meaning that a single fixed lifting function is used to derive each sub-PCM from a set of base PCMs. However, in alternative implementations, the number of lifting functions n can be greater than 1, such as 2, 3, 4, 5, or larger.

[0070] In the next step, at step 306, a set of labeled base PCMs describing a prototype graph (base graph) is determined. This set of labeled base PCMs is for each coding rate R and each Z∈Z allowed The base PCM is determined as follows: Base(R,Z)={PCM1,PCM2,…,PCM…} t These marked base PCMs correspond to the lowest code (e.g., the code with the highest overhead).

[0071] For example, Base(R,Z) can be a set of all available labeled versions of a base graph or prototype graph. In another example, Base(R,Z) can contain or include a single PCM that is deterministically defined by a value K (using some function or table).

[0072] In another example, Base(R,Z) may contain or include a single PCM that is deterministically defined by the lifting size Z (using some function or table). An implementation for constructing such a function or table is provided as follows: if all lifting or loop sizes Z have a*2 s Given a form where a∈{8,9,…,15}, then PCM M a-7 The value Z can be assigned. For example, if t = 8, then PCM M1, M2, ... M8 are predefined labeled versions of the same base prototype. Alternatively, t can be any other positive integer, such as 2, 3, 4, 5, 6, 7, or 10.

[0073] In the implementation, Figure 5A The first base PCM 500 is shown in the figure. Figures 5B-1 to 5B-2 It is the representation of column 502 on the left side of the base PCM 500, excluding the columns of the long identity matrix 504. Figure 6A The label PCM 600 (PCM0) is shown for a = 8. Figures 6B-1 to 6B-4 It is the representation of column 602 to the left of PCM0600, excluding the columns of the long identity matrix 604. Figure 7A The label PCM 700 (PCM1) is shown for a = 9. Figure 7B-1 Figure 7B-4 shows the left column 702 of PCM1700, excluding the columns of the long identity matrix 704. Figure 8A The label PCM 800 (PCM2) is shown for a = 10. Figures 8B-1 to 8B-4 It is the representation of column 802 on the left side of PCM2800, excluding the columns of the long identity matrix 804. Figure 9A The label PCM 900 (PCM3) is shown for a=11. Figures 9B-1 to 9B-4 It is the representation of column 902 on the left side of PCM3900, excluding the columns of the long identity matrix 904. Figure 10A The label PCM 1000 (PCM4) is shown for a = 12. Figures 10B-1 to 10B-4 This is a representation of column 1002 on the left side of PCM41000, excluding the columns of the long identity matrix 1004. Figure 11A shows the notation PCM 1100 (PCM5) for a = 13. Figures 11B-1 to 11B-4 It is the representation of column 1102 to the left of PCM51100, excluding the columns of the long identity matrix 1104. Figure 12AThe label PCM 1200 (PCM6) is shown for a=14. Figures 12B-1 to 12B-2 It is the representation of column 1202 on the left side of PCM61200, excluding the columns of the long identity matrix 1204. Figure 13A The marking PCM 1300 (PCM7) is shown for a = 15. Figures 13B-1 to... Figure 13B-4 It is the representation of column 1302 on the left side of PCM71300, excluding the columns of the long identity matrix 1304. Figure 6A , Figures 6B-1 to 6B-4 , Figure 7A , Figures 7B-1 to 7B-4 , Figure 8A , Figure 8B-1 To Figure 8B-4, Figure 9A , Figures 9B-1 to 9B-4 , Figure 10A , Figures 10B-1 to 10B-4 , Figure 11A , Figure 11B-1 to Figure 11B-4 , Figure 12A , Figures 12B-1 to 12B-2 , Figure 13A and Figures 13B-1 to 13B-4 The first base PCM 500 is shown as PCM 600, 700, 800, 900, 1000, 1100, 1200, 1300.

[0074] In another embodiment, Figure 14A-1 and Figure 14A-2 The second base PCM 1400 is shown in the figure. Figures 14B-1 to 14B-3 It is the representation of column 1402 on the left side of the base PCM 1400, excluding the columns of the long identity matrix 1404. Figure 15A A single mark PCM 1500 is shown. Figures 15B-1 to 15B-3 It is a representation of column 1502 to the left of a single marker PCM1500, excluding the columns of the long identity matrix 1504.

[0075] Figure 16A The label PCM 1600 (PCM0) is shown for a = 8. Figures 16B-1 to 16B-3 It is the representation of column 1602 to the left of PCM01600, excluding the columns of the long identity matrix 1604. Figure 17A The label PCM1700 (PCM1) is shown for a = 9. Figures 17B-1 to 17B-3 It is the representation of column 1702 to the left of PCM11700, excluding the columns of the long identity matrix 1704. Figure 18A The label PCM 1800 (PCM2) is shown for a = 10. Figures 18B-1 to 18B-3 It is the representation of column 1802 on the left side of PCM21800, excluding the columns of the long identity matrix 1804. Figure 19A The label PCM 1900 (PCM3) is shown for a = 11. Figures 19B-1 to 19B-3 It is the representation of column 1902 to the left of PCM31900, excluding the columns of the long identity matrix 1904. Figure 20A The label PCM 2000 (PCM4) is shown for a = 12. Figures 20B-1 to 21B-3 It is the representation of column 2002 on the left side of PCM42000, excluding the columns of the long identity matrix 2004. Figure 21A The label PCM 2100 (PCM5) is shown for a=13. Figures 21B-1 to 21B-3 It is the representation of column 2102 to the left of PCM52100, excluding the columns of the long identity matrix 2104. Figure 22A The label PCM 2200 (PCM6) is shown for a=14. Figures 22B-1 to 22B-3 It is the representation of column 2202 on the left side of PCM62200, excluding the columns of the long identity matrix 2204. Figure 23A The marking PCM 2300 (PCM7) is shown for a=15. Figure 23B-1 , Figure 23B-2 and Figure 23B-3 It is the representation of column 2302 on the left side of PCM72300, excluding the columns of the long identity matrix 2304. Figure 16A Figure 16B-1 to Figure 16B-3 , Figure 17A , Figures 17B-1 to 17B-3 , Figure 18A , Figures 18B-1 to 18B-3 Figure 19A Figures 19B-1 to 19B-3 , Figure 20A , Figures 20B-1 to 20B-3 , Figure 21A , Figures 21B-1 to 21B-3 , Figure 22A , Figures 22B-1 to 22B-3 and Figures 23B-1 to 23B-3 The second base PCM 1400 is shown as PCM 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300.

[0076] In step 308, {Z,f} are selected for each coding rate R and each information length K. i A single combination of (R,Z) is defined. This combination can be identified via simulation by measuring the decoder's error-correcting capability for each possible combination and selecting the one with the best performance among all options. The results can be stored in a lifting table T, which defines the lifting size Z (or lifting size offset) of the PCM used for each (R,Z) pair, and the lifting function f. jAnd index. For each pair (R,Z), a set of selected boost sizes Z can be explored at a time. For example, the selected boost size Z could be 8.

[0077] Alternatively, m can be different for different (K,R) pairs. For example, explore m=8 options for K<=2048 and explore m=4 options for K>2048.

[0078] As mentioned above, a set of lifting functions f1, f2, ..., f n There can be only one entry, i.e., a single lifting function (i.e., n = 1). Alternatively, more than one function can be explored. In both cases, different functions can be used for different ranges of K, R, or (K, R) pairs.

[0079] The code rate and message length can vary for each data transmission. A low code rate provides good protection (reliability), while a high code rate does not provide such good protection. If a transmission at a certain code rate fails, the data needs to be retransmitted. In this case, retransmission means sending the data using a lower code rate than before, but with the same message length.

[0080] In step 310, combinations are stored in memory for each information length and each coding rate. These combinations can be stored in a table (e.g., a promotion table), a list, a linked list, a database, a tree, or any other type of storage device and format.

[0081] Therefore, although steps 302-310 provide a subPCM for each length K and each coding rate R, the dependency on coding rate R can be removed for subsequent retransmissions or for each subsequent retransmission.

[0082] For example, for each subsequent retransmission, only the additional parity bits are sent (the so-called IR HARQ). In this case, subPCMs should be nested for the start and for all lower code rates, meaning that the boosting methods and tables should not depend on the code rate R or should be independent of the code rate R.

[0083] At the same time, several different overlapping (or non-overlapping) ranges of coding rates [R] can be used. low1 …R up1 ],[R low2 …R up2 This allows for the design of different code rate-independent lifting tables T1, T2, ... for each range using steps 302-310. From this perspective, the lifting size, lifting function, and PCM indirectly depend on the code rate or the range of the code rate.

[0084] In various implementations, the same set of labeled PCMs can be shared for different ranges of coding rates. In various other implementations, different sets of PCMs, and even different prototype maps, can be used for different ranges of coding rates.

[0085] The lifting table T can have, for example Figure 4A As shown in the figure. Figure 4A The first column of the promotion table T 402 is for Z. orig The second column is for the specific increase size Z. i The third column of index i is for the specific promotion function f. j The index j and the fourth column are specific to the PCM tag, i.e., PCM. t The index t.

[0086] Figure 4B The promotion table T 404 is shown, where the index i of the promotion size Z in the second column is replaced by the promotion size Z so that the entry shows the actual promotion size.

[0087] Figure 4C The elevation table T 406 is shown for a single elevation function f such that the third column can be removed.

[0088] Figure 5A Figure 5B shows an example of the first multi-marker QC LDPC base code 500 and Figure 6A Figure 6B, Figure 7A, Figure 7B Figure 8A Figure 8B Figure 9A Figure 9B Figure 10A Figure 10B Figure 11A Figure 11B Figure 12A Figure 12B Figure 13A Figure 13B shows the first marker QC LDPC codes 600, 700, 800, 900, 1000, 1100, 1200, and 1300.

[0089] Figure 14A-1 , Figure 14A-2 and Figures 14B-1 to 14B-3 An example of the second multi-marker QC LDPC base code 1400 is shown in Figure 15A. Figures 15B-1 to 1 5-3 Figure 16A , Figures 16B-1 to 16B-3 , Figure 17A , Figures 17B-1 to 17B-3 , Figure 18A , Figures 18B-1 to 18B-3 , Figure 19A , Figures 19B-1 to 19B-3 , Figure 20A , Figures 20B-1 to 20B-3 , Figure 21A , Figures 21B-1 to 21B-3 , Figure 22A , Figures 22B-1 to 22B-3, Figure 23A and Figures 23B-1 to 23B-3 The second marker LDPC codes are shown as 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, and 2300.

[0090] Figures 24A-1 to 24A-6 , Figures 24B-1 to 24B-3 , Figures 24C-1 to 24C-6 and Figure 24D-1 Figure 24D-6 shows the lifting tables T 2402, 2404, 2406, and 2408. When K... bmax When K = 22, the lifting table T1 2402 in Figure 24A can be used for coding rates 1 / 3 ≤ R ≤ 8 / 9 and information lengths 640 ≤ K ≤ 8192. Indices i = 0, ..., 7 identify the allowed Zs. When K bmax When the value is 16, the lifting table T2 2404 in Figure 24B can be used for coding rates of 1 / 5 ≤ R ≤ 2 / 3 and information lengths of 40 ≤ K ≤ 2560. Indices i = 0, ..., 7 identify the allowed Zs. Figures 24A-1 to 24A-6 and Figure 24B-1 to Figure 24B-3 Show the lifting table for the first code. Figures 24C-1 to 24C-6 and Figures 24D-1 to 24D-6 The lifting tables 2406 and 2408 for the second code are shown.

[0091] Figure 25A and Figure 25C The performance of the decoders used to apply boost tables T1 and T2 and for different coding rates R is shown. Figure 25B and Figure 25D The diagram shows the relevant graphs when the implementation of the present disclosure is not carried out. According to... Figure 25A and Figure 25B as well as Figure 25C and Figure 25D As can be seen from the comparison, the implementation of this disclosure shows smooth curves. In particular, no peaks or sharps are visible in these smooth curves, thus demonstrating excellent performance of using the codes of tables T1 and T2 for a wide range of information lengths K.

[0092] Figure 26This is a block diagram illustrating an implementation of an LDPC encoder 2600. The LDPC encoder 2600 includes: a read-only memory 2602 storing a base PCM 2606 and one or more lift tables T 2608, 2610, 2612; an I / O memory 2614; and an odd / even bit processor / generator 2616. The encoder 2600 receives a K-bit input source word and generates an N-bit output codeword. The I / O memory 2614 stores the input K-bit information word and is used by the encoder 2600 to generate a K-bit output. The read-only memory 2602 stores the base code lift shift values ​​and the lift tables 2608, 2610, 2612. In this implementation, the lift function is implemented in hardware and not stored in memory. The lift tables 2608, 2610, 2612 may include... Figures 4A to 4C or Figure 6A To one of the lifting tables shown in Figure 6B. The odd / even bit processor / generator 2616 uses a subPCM (or a generator matrix corresponding to the subPCM) generated on-fly according to one of the base PCMs 2606 to generate an N-bit output codeword from a K-bit input using a suitable LDPC encoding method. This subPCM generation is accomplished by selecting one of a lifting size offset value and / or an allowable lifting size, and using that lifting size offset and one or a set of lifting functions corresponding to the selected index for a given size K of the input from lifting tables 2608, 2610, 2612, to generate the subcode offset value for each non-zero cycle of the base PCM 2606. The N-bit output is then stored in I / O memory 2614.

[0093] Figure 27This is a block diagram illustrating an implementation of the LDPC decoder 2700. The LDPC decoder 2700 includes: a read-only memory (ROM) 2702 for storing a base PCM 2706; one or more lifting tables T 2708, 2710, 2712; an I / O memory 2714; and a check node processor 2716. The decoder 2700 receives an input sequence of log likelihood ratios (LLRs) of length N and generates a K-bit output. The ROM 2702 stores the lift shift values ​​of the base PCM 2706 and the lifting tables 2708, 2710, 2712. The lifting tables 2708, 2710, 2712 include indices for lift size offsets and / or permissible cycle sizes, as well as indices corresponding to the lift functions. The I / O memory 2714 stores an input vector of length N LLR values ​​and is used by the check node processor 2716 to generate a K-bit output. The K-bit output is then stored in I / O memory 2714. The check node processor 2716 uses a sub-PCM generated at runtime according to one of the base PCMs 2706 to generate a K-bit output information bit sequence based on the received N-component input. This sub-PCM is generated by selecting one of a cyclic offset value and / or an allowable cyclic size, and applying one or more lifting functions corresponding to the selected index in one of the lifting tables 2708, 2710, and 2712 to it, for each non-zero cycle of the base PCM 2706, generating a sub-code shift value based on the base code shift value.

[0094] Figure 28 This is a flowchart illustrating an implementation of a method 2800 for encoding data using LDPC, an explained lifting table, and an explained lifting function. Method 2800 includes: in a first step, receiving a K-bit source word at step 2802; in a next step, at step 2804, encoding the source word by an LDPC encoder to generate an N-bit codeword using the explained lifting table and lifting function; and in a subsequent step, at step 2806, then transmitting the N-bit codeword by an encoder.

[0095] Figure 29This is a flowchart illustrating an implementation of a method 2900 for decoding data using LDPC, an explanatory lifting table T, and an explanatory lifting function. Method 2900 includes: in a first step, receiving a K-bit source word at 2902. In a next step, at step 2904, an LDPC encoding device decodes an N-bit codeword to generate a K-bit source word using the explanatory lifting table T and the lifting function. In a subsequent step, at step 2906, a decoder then stores the K-bit source word. The decoder uses redundancy in the received information sequence during the decoding operation performed by the decoder to correct errors in the received information sequence and generate a decoded information sequence. The decoded information sequence is an estimate of the encoded information sequence from which an information sequence (estimated) can be extracted.

[0096] Figure 30 A block diagram of a processing system 3000, which can be installed in a host device to perform the methods described herein, is shown. As shown, the processing system 3000 includes a processor 3004, a memory 3006, and interfaces 3010-3014, which can (or cannot) be configured to... Figure 30 The arrangement is shown in the diagram. Processor 3004 may be any component or collection of components adapted to perform computation and / or other processing-related tasks, and memory 3006 may be any component or collection of components adapted to store programs and / or instructions executed by processor 3004. In this embodiment, memory 3006 includes a non-transitory computer-readable medium. Interfaces 3010, 3012, and 3014 may be any component or collection of components that allow processing system 3000 to communicate with other devices / components and / or users. For example, one or more of interfaces 3010, 3012, and 3014 may be adapted to communicate data, control, or management messages from processor 3004 to applications installed on host devices and / or remote devices. As another example, one or more of interfaces 3010, 3012, and 3014 may be adapted to allow a user or user device (e.g., a personal computer (PC) etc.) to interact / communicate with processing system 3000. Processing system 3000 may include... Figure 30 Additional components not described herein, such as long-term storage devices (e.g., non-volatile memory, etc.).

[0097] In some embodiments, the processing system 3000 is included in a network device accessing a remote communication network or a portion thereof. In one example, the processing system 3000 is in a network-side device in a wireless or wired remote communication network, such as a base station, relay station, scheduler, controller, gateway, router, application server, or any other device in the remote communication network. In other embodiments, the processing system 3000 is in a user-side device accessing a wireless or wired remote communication network, such as a mobile station, user equipment (UE), personal computer (PC), tablet, wearable communication device (e.g., smartwatch), or any other device suitable for accessing the remote communication network.

[0098] In some implementations, one or more of interfaces 3010, 3012, and 3014 connect the processing system 3000 to a transceiver suitable for sending and receiving signals over a remote communication network.

[0099] Figure 31 A block diagram of a transceiver 3100 suitable for transmitting and receiving signals over a remote communication network is shown. The transceiver 3100 can be installed in a host device. As shown, the transceiver 3100 includes a network-side interface 3102, a coupler 3104, a transmitter 3106, a receiver 3108, a signal processor 3110, and a device-side interface 3112. The network-side interface 3102 may include any component or set of components suitable for transmitting or receiving signals over a wireless or wired remote communication network. The coupler 3104 may include any component or set of components suitable for facilitating bidirectional communication over the network-side interface 3102. The transmitter 3106 may include any component or set of components suitable for converting a baseband signal into a modulated carrier signal suitable for transmission over the network-side interface 3102 (e.g., an up-converter, a power amplifier, etc.). The receiver 3108 may include any component or set of components suitable for converting a carrier signal received over the network-side interface 3102 into a baseband signal (e.g., a down-converter, a low-noise amplifier, etc.). The signal processor 3110 may include any components and a collection of components adapted to convert baseband signals into data signals suitable for communication via the device-side interface 3112, or to convert data signals suitable for communication via the device-side interface 3112 into baseband signals. The device-side interface 3112 may include any components and a collection of components adapted to transmit data signals between the signal processor 3110 and components within the host device (e.g., processing system 800, local area network (LAN) port, etc.).

[0100] Transceiver 3100 can transmit and receive signals via any type of communication medium. In some embodiments, transceiver 3100 transmits and receives signals via a wireless medium. For example, transceiver 3100 may be a wireless transceiver adapted to communicate according to a wireless telematics protocol—e.g., cellular protocols (e.g., Long-Term Evolution, LTE, etc.), wireless local area network (WLAN) protocols (e.g., Wi-Fi, etc.) or any other type of wireless protocol (e.g., Bluetooth, Near Field Communication, NFC, etc.). In such embodiments, network-side interface 3102 includes one or more antennas / radiating elements. For example, network-side interface 3102 may include: a single antenna; multiple individual antennas; or a multi-antenna array configured for multi-layer communication—e.g., single-input multiple-output (SIMO), multiple-input single-output (MISO), multiple-input multiple-output (MIMO, etc.). In other embodiments, transceiver 3100 transmits and receives signals via a wired medium—e.g., twisted-pair cable, coaxial cable, optical fiber, etc. A particular processing system and / or transceiver may utilize all or only a subset of the components shown, and the level of integration may vary depending on the device.

[0101] Figure 32 A network 3200 is illustrated in which the disclosed methods and systems for transmitting data can be implemented. Network 3200 includes multiple network components. Network components may include access points (APs), stations (STAs) (e.g., wireless devices or user equipment (UEs) such as wireless telephones), or any other wireless receiving point. In this embodiment, network 3200 includes an access point (AP) 3210 having a coverage area 3212, multiple STAs 3220, and a backhaul network 3230. In this embodiment, the AP may be implemented as... Figure 31 The transceiver 3100 shown is an example. In an embodiment, the STA 3220 can be implemented as, for example... Figure 30The processing system 3000 shown herein. As used herein, the term AP may also be referred to as a transmission point (TP), and the two terms are used interchangeably in this disclosure. In various embodiments, AP 3210 may be a base station (BS), also referred to as a base transceiver station (BTS). Examples of BS include eNode B (eNB), gNB, etc. In embodiments, AP 3210 may be a wireless router. Therefore, AP 3210 may include any component capable of providing wireless access by establishing an uplink (dashed line) and / or downlink (dotted line) particularly with STA 3220. STA 3220 may include any component capable of establishing a wireless connection with AP 3210. Examples of STA 3220 include mobile phones, tablets, and laptops. Backhaul network 3230 may be any component or collection of components that allows data to be exchanged between AP 3210 and a remote end (not shown). In some implementations, network 3200 may include various other wireless devices, such as relays, femtocells, etc.

[0102] It should be understood that one or more steps of the implementation methods provided herein can be performed by corresponding units or modules. For example, a signal can be transmitted by a transmitting unit or transmitting module. A signal can be received by a receiving unit or receiving module. A signal can be processed by a processing unit or processing module. Other steps can be performed by iteration units / modules, difference units / modules, adjustment units / modules, generation units / modules, calculation units / modules, allocation units / modules, increment units / modules, decrement units / modules, and / or setting units / modules. Each unit / module can be hardware, software, or a combination thereof. For example, one or more of the units / modules can be integrated circuits, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

[0103] In one implementation, a method for raising a subcode from a base code for encoding and decoding data includes determining a single combination of a cycle size, a raising function, and a labeled base matrix (PCM) based on the information length and coding rate using data stored in a raising table. The raising table is defined during the code generation phase. The method also includes calculating multiple shifts for the subcode. Each shift is calculated by applying the raising function to the labeled base matrix (PCM) using an index defined with the cycle size. The method further includes using the resulting subPCM to encode or decode data. The method also includes obtaining the subPCM based on a single combination of the cycle size, the raising function, and the labeled PCM, and based on one of the multiple shifts for the subcode. The method further includes using the resulting subPCM to encode or decode data.

[0104] Implementations of this disclosure provide a method for generating codes. The method includes determining a subset of permissible boost sizes Z for each coding rate R and each information length K. The method also includes determining at least one boost function f for each coding rate R and each permissible Z. i The method also includes determining a set of base PCMs describing a single prototype graph. The base PCMs are based on the coding rate R and the allowable Z. S The method also includes selecting the lifting size Z and the lifting function f. i and PCM t The method also includes storing the cycle size offset and / or cycle size index, lifting function index, and basecode index corresponding to each individual combination for each information length and each coding rate.

[0105] Embodiments of this disclosure provide a method for operating a device on the transmitting side. The method includes encoding information bits into codewords at an encoder. The method also includes transmitting a signal to a receiving side at a transmitter. The signal includes the codewords. The information bits are encoded using multiple tag-based PCMs. The tag-based PCMs are derived from a single base PCM describing a single prototype diagram.

[0106] Embodiments of this disclosure provide a method for operating a device on a receiving side. The method includes receiving a signal from a transmitting side at a receiver. The signal includes codewords. The method further includes decoding the codewords at a decoder by applying extracted information bits. The information bits are decoded using multiple tag-based PCMs. The tag-based PCMs are derived from a single base PCM describing a single prototype diagram.

[0107] In one implementation, the encoder or decoder includes a processor and a computer-readable storage medium storing a program executed by the processor. The program includes instructions to determine a single combination of a cycle size, a lifting function, and a tag PCM based on the information length and the coding rate, using data stored in a lifting table defined during the code generation phase. The program also includes instructions to compute multiple shifts for the subcode, wherein each shift is computed by applying the lifting function to the tag PCM using an index defined with the cycle size. The program further includes instructions to obtain a subPCM based on the single combination of the cycle size, the lifting function, and the tag PCM, and based on one of the multiple shifts for the subcode. The program also includes instructions to encode or decode data using the obtained subPCM.

[0108] In one or more aspects of this disclosure, the shift of a nonzero cycle at a predefined position remains unchanged.

[0109] In one or more aspects of this disclosure, the PCM marker is derived from the base code, and wherein the base code is derived from... Figure 5A and Figures 5B-1 to 5B-2 The PCM representation is shown in the figure.

[0110] In one or more aspects of this disclosure, the lifting function is selected from a single lifting function.

[0111] In one or more aspects of this disclosure, multiple lifting functions are selected.

[0112] In one or more aspects of this disclosure, the label base matrix PCM is obtained directly from the cycle size.

[0113] In one or more aspects of this disclosure, the loop size is Z, where Z = a * 2^s.

[0114] In one or more aspects of this disclosure, the lifting function provides a code shift value.

[0115] In one implementation, the method for generating codes for encoding or decoding data includes determining a subset of permissible boost sizes Z for each coding rate R and each information length K. The method further includes determining at least one boost function f for each Z within the subset of permissible boost sizes Z and for each coding rate R. i The method also includes determining a set of labeled PCMs describing a single prototype graph. The labeled PCMs are based on a subset of the coding rate R and the permissible boost size Z. The method also includes selecting a single combination of boost size Z, boost function f, and labeled PCMt. The method further includes storing, for each information length and each coding rate, a cycle size offset and / or cycle size index, boost function index, and labeled PCM index corresponding to the single combination.

[0116] In one or more aspects of this disclosure, a set of markers describing a single prototype diagram (PCM) is based on Figure 5A and Figures 5B-1 to 5B-2 The PCM is shown in the figure.

[0117] In one or more aspects of this disclosure, the lifting function is selected from a single lifting function.

[0118] In one implementation, the method for operating the device on the transmitting side includes encoding information bits into codewords at an encoder. The method also includes transmitting a signal to the receiving side at a transmitter. The signal includes the codewords. The information bits are encoded using multiple tag-based PCMs. The tag-based PCMs are derived from a single base PCM describing a single prototype diagram.

[0119] In one or more aspects of this disclosure, the information bits have different bit lengths and are encoded at different coding rates.

[0120] In one or more aspects of this disclosure, the tag base PCM is selected based on the coding rate.

[0121] In one or more aspects of this disclosure, encoding includes switching from a first-label PCM to a second-label PCM when the encoding rate changes from a first encoding rate to a second encoding rate.

[0122] In one or more aspects of this disclosure, the encoding includes switching from a first-mark PCM to a second-mark PCM when the boost size changes from a first boost size to a second boost size, wherein the first boost size and the second boost size depend on different information bit lengths.

[0123] In one or more aspects of this disclosure, encoding information bits into codewords includes according to Figure 6A The lifting table shown encodes information bits into codewords, where index a represents the tag base PCM, Z represents the lifting size, and Z depends on the information bit length.

[0124] In one or more aspects of this disclosure, encoding information bits into codewords includes encoding information bits into codewords according to a boosting table shown in FIG6B, wherein index a represents the tag base PCM, and wherein Z represents the boosting size.

[0125] In one implementation, the method for operating the device on the receiving side includes receiving a signal from the transmitting side at the receiver side, the signal including codewords. The method further includes decoding the codewords at a decoder by applying extracted information bits. The information bits are decoded using multiple tag-based PCMs. The tag-based PCMs are derived from a single base PCM describing a single prototype diagram.

[0126] In one or more aspects of this disclosure, the information bits have different bit lengths and are decoded at different coding rates.

[0127] In one or more aspects of this disclosure, the tag base PCM is selected based on the coding rate.

[0128] In one or more aspects of this disclosure, decoding includes switching from a first-label PCM to a second-label PCM when the coding rate changes from a first coding rate to a second coding rate.

[0129] In one or more aspects of this disclosure, decoding includes switching from a first-mark PCM to a second-mark PCM when the boost size changes from a first boost size to a second boost size, wherein the first boost size and the second boost size depend on different information bit lengths.

[0130] In one or more aspects of this disclosure, decoding codewords into information bits includes according to Figure 6A The lifting table shown decodes codewords into information bits, where index a represents the tag base PCM, Z represents the lifting size, and Z depends on the information bit length.

[0131] In one implementation, the encoder or decoder includes a processor and a computer-readable storage medium storing a program executed by the processor. The program includes instructions to determine a single combination of a cycle size, a lifting function, and a tag PCM based on the information length and coding rate, using data stored in a lifting table defined during the code generation phase. The program also includes instructions to compute multiple shifts for the subcode, wherein each shift is computed by applying the lifting function to the tag PCM using an index defined with the cycle size. The program further includes instructions to encode or decode data using the resulting subPCM.

[0132] The following references are incorporated into this article by way of citation, as if they were copied in their entirety:

[0133] Provisional application No. 62 / 454,416 (HW 85338016 US01), entitled “OFFSET LIFTING METHOD”, filed on February 3, 2017.

[0134] U.S. Patent Application No. 15 / 887,148 (HW 85338016 US02), entitled “OFFSET LIFTING METHOD”, filed on February 2, 2018.

[0135] Although this disclosure has been described with reference to illustrative embodiments, this description is not intended to be construed as limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of this disclosure, will be apparent to those skilled in the art when referring to this description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for encoding data, characterized by, The method includes: The sub-PCM is obtained based on a single combination of the cycle size, the lifting function, and the label base matrix PCM, and based on one of a plurality of shifts for the subcode, wherein the plurality of shifts are obtained by applying the lifting function to the label base matrix PCM using an index defined by the cycle size, and the single combination of the cycle size, the lifting function, and the label base matrix PCM is related to the information length and the coding rate; Use the obtained sub-PCM to encode the data; Output the encoded data.

2. The method according to claim 1, characterized in that, The shift of a non-zero cycle at a predefined position remains unchanged.

3. The method according to claim 1 or 2, characterized in that, The label base matrix PCM is obtained based on the cycle size.

4. The method according to claim 1 or 2, characterized in that, The loop size is Z, where Z = a * 2^s, a is a positive integer, and s is a non-negative integer.

5. The method according to claim 1 or 2, characterized in that, The lifting function provides the code shift value.

6. A communication device, characterized in that, include: A module for obtaining a subPCM based on a single combination of a cycle size, a lifting function, and a label base matrix PCM, and based on one of a plurality of shifts for the subcode, wherein the plurality of shifts are obtained by applying the lifting function to the label base matrix PCM using an index defined by the cycle size, and the single combination of the cycle size, the lifting function, and the label base matrix PCM is related to the information length and the coding rate; A module used to encode data using the resulting sub-PCM; This module is used to output the encoded data.

7. The communication device according to claim 6, characterized in that, The shift of a non-zero cycle at a predefined position remains unchanged.

8. The communication device according to claim 6 or 7, characterized in that, The label base matrix PCM is obtained based on the cycle size.

9. The communication device according to claim 6 or 7, characterized in that, The loop size is Z, where Z = a * 2^s, a is a positive integer, and s is a non-negative integer.

10. The communication device according to claim 6 or 7, characterized in that, The lifting function provides the code shift value.

11. A communication method, characterized in that, include: The sub-PCM is obtained based on a single combination of the cycle size, the lifting function, and the label base matrix PCM, and based on one of a plurality of shifts for the subcode, wherein the plurality of shifts are obtained by applying the lifting function to the label base matrix PCM using an index defined by the cycle size, and the single combination of the cycle size, the lifting function, and the label base matrix PCM is related to the information length and the coding rate; Based on the sub-PCM decoded data.

12. The method according to claim 11, characterized in that, The shift of a non-zero cycle at a predefined position remains unchanged.

13. The method according to claim 11 or 12, characterized in that, The label base matrix PCM is obtained based on the cycle size.

14. The method according to claim 11 or 12, characterized in that, The loop size is Z, where Z = a * 2^s, a is a positive integer, and s is a non-negative integer.

15. The method according to claim 11 or 12, characterized in that, The lifting function provides the code shift value.

16. A communication device, characterized in that, include: A module for obtaining a subPCM based on a single combination of a cycle size, a lifting function, and a label base matrix PCM, and based on one of a plurality of shifts for the subcode, wherein the plurality of shifts are obtained by applying the lifting function to the label base matrix PCM using an index defined by the cycle size, and the single combination of the cycle size, the lifting function, and the label base matrix PCM is related to the information length and the coding rate; Module for decoding data based on the sub-PCM.

17. The communication device according to claim 16, characterized in that, The shift of a non-zero cycle at a predefined position remains unchanged.

18. The communication device according to claim 16 or 17, characterized in that, The label base matrix PCM is obtained based on the cycle size.

19. The communication device according to claim 16 or 17, characterized in that, The loop size is Z, where Z = a * 2^s, a is a positive integer, and s is a non-negative integer.

20. The communication device according to claim 16 or 17, characterized in that, The lifting function provides the code shift value.

21. A communication system, characterized in that, It includes the communication device according to any one of claims 6-10 and the communication device according to any one of claims 16-20.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a computer, cause the computer to perform the method of any one of claims 1-5, or cause the computer to perform the method of any one of claims 11-15.

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