Instruction prefetching method, instruction prefetching device, processor and electronic equipment

Abstract

An instruction prefetch method, an instruction prefetch device, a processor, and an electronic device. The instruction prefetch method includes: in response to a target instruction missing a target cache, writing a target access request for the target instruction into a loss status processing queue, the loss status processing queue including multiple access requests, the target access request being one of the multiple access requests, the loss status processing queue being configured to sequentially send the multiple access requests to a next-level cache of the target cache; in response to a target instruction prediction error, sending a cancel request for the target instruction to the loss status processing queue; and in response to the cancel request, releasing the queue space occupied by the access request following the target access request in the loss status processing queue. This instruction prefetch method can improve prefetch accuracy, increase the utilization of the loss status processing queue, and contribute to improving overall performance.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an instruction prefetch method, an instruction prefetch device, a processor, and an electronic device. Background Art

[0002] Throughout the development of computer technology, low-cost, high-capacity storage often suffers from high latency, preventing it from delivering data to processors in a timely manner. Low-latency, small-capacity storage, acting as a buffer between the processor and large-capacity storage, effectively mitigates the impact of high data transmission latency on processor performance. One such low-latency, small-capacity storage technology is caching.

[0003] To balance capacity and latency, caches are organized into multiple levels. Caches with lower level numbers have lower capacity and lower latency; caches with higher level numbers have the opposite. Common processors typically have three levels of cache, with capacity increasing from level 1 to level 3. The capacity of the first-level cache (L1 cache) is typically tens of KB, the second-level cache (L2 cache) is a few MB, and the third-level cache (L3 cache) is several hundred MB. Because the code itself and the data it retrieves typically occupy separate storage spaces, to improve processor efficiency, the first-level cache is typically further divided into a first-level instruction cache and a first-level data cache.

[0004] As the code size of programs running on servers grows, the instruction cache's capacity gradually becomes insufficient to keep up with the code's caching needs. Because increasing the instruction cache increases its latency, simply increasing the instruction cache to meet the increasing code size's need for more cache space is difficult. Code that can't be cached in the instruction cache results in an increase in instruction cache misses, forcing the required code to be retrieved from the higher-latency L2 cache, L3 cache, or even memory. The increased latency associated with accessing large-capacity storage can degrade processor performance.

[0005] Because not all code in the instruction cache will be used by the processor in the near future, processor designers have room for optimization. If the code that the processor will soon use can be predicted, it can be used to replace the code in the instruction cache that will not be used for the time being. This reduces the probability of the processor accessing high-latency memory, reduces data transmission latency, and thus improves processor performance. This technology is called instruction prefetching. Summary of the Invention

[0006] At least one embodiment of the present disclosure provides an instruction prefetch method, comprising: in response to a target instruction missing in a target cache, writing a target access request for the target instruction into a loss status processing queue, wherein the loss status processing queue includes multiple access requests, the target access request is one of the multiple access requests, and the loss status processing queue is configured to send the multiple access requests in sequence to a next-level cache of the target cache; in response to a prediction error of the target instruction, sending a cancel request for the target instruction to the loss status processing queue; in response to the cancel request, releasing the queue space occupied by the access request located after the target access request in the loss status processing queue.

[0007] For example, in the method provided in an embodiment of the present disclosure, at least one access request among the access requests subsequent to the target access request has been sent to the next-level cache.

[0008] For example, in the method provided by an embodiment of the present disclosure, the access request following the target access request is an access request sent to the loss status processing queue later than the target access request.

[0009] For example, the method provided by an embodiment of the present disclosure further includes: the loss status processing queue sends the multiple access requests to the next-level cache in sequence, and the next-level cache responds to each access request in sequence.

[0010] For example, the method provided by an embodiment of the present disclosure also includes: comparing the first preset information in the data returned by the next-level cache with the second preset information stored in the queue space corresponding to the access request corresponding to the data in the loss status processing queue; in response to the first preset information matching the second preset information, sending the data to the target cache and releasing the queue space corresponding to the access request corresponding to the data in the loss status processing queue, wherein the data includes the target instruction; in response to the first preset information not matching the second preset information, sending a consistency maintenance request to the next-level cache.

[0011] For example, the method provided by an embodiment of the present disclosure further includes: in response to the consistency maintenance request, the next-level cache discards the data.

[0012] For example, the method provided by an embodiment of the present disclosure further includes: in response to the coherence maintenance request, the next-level cache updates the flag information in the entry corresponding to the data to an invalid state.

[0013] For example, in the method provided in one embodiment of the present disclosure, the first preset information includes the address information of the data; the second preset information includes the address information of the access request corresponding to the data stored in the queue space corresponding to the lost state processing queue and / or the flag information indicating the idle state.

[0014] For example, in a method provided in an embodiment of the present disclosure, the target cache includes a first-level instruction cache, and the next-level cache includes a second-level cache.

[0015] For example, in the method provided in one embodiment of the present disclosure, the queue space occupied by the access request located after the target access request in the lost status processing queue is released, including: clearing the content of the queue space occupied by the access request located after the target access request in the lost status processing queue; or updating the status identifier of the queue space occupied by the access request located after the target access request in the lost status processing queue to an idle state.

[0016] For example, the method provided by an embodiment of the present disclosure also includes: selecting a cache way in the target cache; updating the most recently accessed information of the selected cache way before the next-level cache returns data; and storing the target instruction contained in the data in the selected cache way when the next-level cache returns data.

[0017] For example, the method provided by an embodiment of the present disclosure also includes: selecting a cache way in the target cache; when the next-level cache returns data, storing the target instruction contained in the data in the selected cache way, and updating the most recent access information of the selected cache way.

[0018] For example, in a method provided in an embodiment of the present disclosure, selecting a cache way in the target cache includes: selecting the cache way that has not been used the longest according to the most recent access information of each cache way in the target cache.

[0019] At least one embodiment of the present disclosure also provides an instruction prefetch device, comprising: a request write unit, configured to write a target access request for the target instruction into a loss status processing queue in response to a target instruction miss in a target cache, wherein the loss status processing queue includes multiple access requests, the target access request is one of the multiple access requests, and the loss status processing queue is configured to send the multiple access requests in sequence to a next-level cache of the target cache; a request cancel unit, configured to send a cancel request for the target instruction to the loss status processing queue in response to a prediction error of the target instruction; and a request processing unit, configured to release the queue space occupied by the access request located after the target access request in the loss status processing queue in response to the cancel request.

[0020] At least one embodiment of the present disclosure also provides a processor, comprising a target cache, a next-level cache of the target cache, and a loss status processing queue; wherein the loss status processing queue is configured to receive a target access request for the target instruction in response to a target instruction miss in the target cache, and to send multiple access requests in sequence to the next-level cache; the loss status processing queue includes the multiple access requests, and the target access request is one of the multiple access requests; the loss status processing queue is also configured to receive a cancellation request for the target instruction in response to a prediction error of the target instruction, and in response to the cancellation request, release the queue space occupied by the access request located after the target access request.

[0021] At least one embodiment of the present disclosure further provides an electronic device, comprising the instruction prefetching device provided by any embodiment of the present disclosure.

[0022] At least one embodiment of the present disclosure further provides an electronic device, comprising the processor provided by any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] Figure 1 A schematic diagram of a cache architecture;

[0025] Figures 2A-2C A schematic diagram of the instruction prefetch process;

[0026] Figure 3 Schematic diagram of processing mispredicted requests in the queue to clear the loss state;

[0027] Figure 4A flowchart of an instruction prefetching method provided in some embodiments of the present disclosure;

[0028] Figure 5 A schematic diagram of clearing mispredicted requests in a loss status processing queue in an instruction prefetch method provided by some embodiments of the present disclosure;

[0029] Figure 6 A flowchart of another instruction prefetching method provided in some embodiments of the present disclosure;

[0030] Figure 7 A flowchart of another instruction prefetching method provided in some embodiments of the present disclosure;

[0031] Figure 8 A flowchart of another instruction prefetching method provided in some embodiments of the present disclosure;

[0032] Figure 9 A schematic block diagram of an instruction prefetching device provided in some embodiments of the present disclosure;

[0033] Figure 10 A schematic block diagram of a processor provided for some embodiments of the present disclosure;

[0034] Figure 11 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure; and

[0035] Figure 12 A schematic block diagram of another electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0037] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0038] In instruction prefetching, the main factors affecting its effectiveness include timeliness, coverage, and accuracy. Timeliness measures whether the code is provided exactly when the processor needs it. Providing it too late results in performance penalties, while providing it too early takes up cache space. Coverage measures whether the prefetched code is sufficient to cover as many potential instruction cache misses as possible. Accuracy measures the probability that the prefetched code is used before it is evicted from the instruction cache.

[0039] Instruction prefetching is based on speculative execution. Incorrect speculation can reduce the effectiveness of instruction prefetching. Speculative execution predicts the execution results of some instructions, allowing subsequent instructions to enter the processor in advance to gain performance advantages. These predicted instructions are called branch instructions. Branch instructions are like two forks in a road, with only one correct path. Before a branch instruction is executed, the processor does not know which path to take. For example, the processor can wait for the branch instruction to complete execution, thus determining its correct branch direction, before continuing execution. However, waiting means increased program execution time. Alternatively, the processor can use a mechanism to predict the direction of the branch instruction and take a branch path in advance. If the prediction is correct, program execution time is reduced. If the prediction is incorrect, the processor can return to the fork and take another path. This branch instruction prediction mechanism is a form of speculative execution. If the predicted result of an instruction matches the executed result of the instruction, the instructions that were preempted can improve processor performance. If the predicted result of an instruction is incorrect, the incorrect instruction that was preempted is canceled, and execution restarts with the correct instruction following the branch instruction to ensure correct program execution.

[0040] If the instruction prefetch has already sent an access request to the L2 cache, even if this access request happens to be on a mispredicted path, the request will not be canceled and will definitely be filled back into the instruction cache. After a mispredicted branch instruction, the instruction entering the processor can be canceled, but the access request that has already been sent to the L2 cache for that instruction will not be canceled. The erroneous instruction is no longer executed, but its data is filled back into the instruction cache. Therefore, this misfetched data is likely to remain unused by the program for some time. This will reduce the accuracy of instruction prefetching and increase instruction cache misses, thus affecting processor performance.

[0041] Figure 1 FIG. 1 is a schematic diagram of a cache architecture, for example, a 4-way cache with 256 entries. Figure 1 The address in the address is the memory address. The index is from 3 to 10 bits of the memory address, corresponding to Figure 1 The tag takes bits 11 to 32 of the memory address, corresponding to Figure 1 Memory addresses 31 to 10. Memory addresses 1 to 0 indicate that the minimum unit of cache access is 4 bytes.

[0042] When a processor accesses a cache, it first uses the index to find the corresponding "group." Within that group, it compares the tag stored in each "way" of data with the tag stored in that group. If the tag matches, it's a cache hit; otherwise, it's a cache miss.

[0043] Assume there is only one L1 cache, and the memory holds all the required data. When the processor begins running, the cache is empty. When the processor accesses the cache, a cache miss occurs. The processor then needs to make further access requests to the memory and backfill the data into the cache. During backfilling, the index is first calculated. Data with the same index can only be backfilled into the same "group." If there is a vacant slot within the group, a slot is selected for the backfilled data. If there is no vacant slot, a mechanism is used to identify data to be "evicted," such as the least recently used data. When all ways in a particular group in the cache are occupied by valid content, a new request to fill the way replaces or discards the existing valid content. This process is called "evicting" or "evicting." For example, the least recently used way is marked as 0, with a larger number indicating the most recent use. Each time a hit is found in a way, the most recently accessed data for that way is marked as the highest value, while the most recently accessed data for the remaining ways is decremented by 1 until it reaches 0.

[0044] Under the first mode (e.g., also known as the "update first" mode), if a cache miss occurs, the most recently accessed information of the "group" can be accessed immediately, the number of the "way" to be "kicked out" can be selected and saved, and the most recently accessed information of the "way" can be updated (subsequent most recently accessed information all refers to the most recently accessed information of the "way"). When the memory backfills data to the cache, it is directly backfilled into the "way" that was once selected, and there is no need to update the most recently accessed information. Under the second mode (e.g., also known as the "update later" mode), if a cache miss occurs, the number of the "way" to be "kicked out" can be not immediately selected. When the data is backfilled, the "way" to be "kicked out" can be selected again and the most recently accessed information can be updated. The advantage of the first mode is that the time required for data backfilling is shorter. However, if the access request is canceled (i.e., no access request has been sent to the secondary cache), the most recently accessed information "updated first" is incorrect. If this error occurs a large number of times, it may have a negative impact on processor performance.

[0045] Figures 2A-2C Schematic diagram of the instruction prefetch process. For example, the access request from the primary instruction cache 100 and the instruction prefetcher 105 to the secondary cache 115 is issued through the loss status processing queue 110. When an instruction or prefetched instruction has a cache loss, the primary instruction cache 100 or the instruction prefetcher 105 will further issue an access request to the secondary cache 115 or a larger storage capacity. This access request will first be written into the loss status processing queue 110 and occupy a position, such as Figure 2A Process ① (Each striped rectangle in the figure represents an access request written into the lost status processing queue 110. The further to the right, the earlier it was written). The most recently accessed information is updated, for example, using the "update first" method. The information in the write lost status processing queue 110 includes the memory address and the "way" information to be backfilled into the L1 instruction cache 100.

[0046] When the secondary cache 115 is capable of receiving a new access request, the access request stored in the lost state processing queue 110 is sent to the secondary cache 115, such as Figure 2B Process ② (each dot-filled rectangle in the figure represents an access request that has been sent). Before the data is obtained, the access request will not be released in the lost state processing queue 110. When the secondary cache 115 prepares the data and prepares to backfill, it will first query the backfill "way" information of the access request (dot-filled rectangle) still stored in the lost state processing queue 110, such as Figure 2C Through this location information, the secondary cache 115 backfills the data to the corresponding location of the primary instruction cache 100, such as Figure 2C ③ in the process, and release the corresponding access request in the lost state processing queue 110 (such as Figure 2CThe position of the blank rectangle on the far right of the lost state processing queue 110).

[0047] If the processor finds an incorrectly predicted instruction, the processor will send a cancel error access request to the loss status processing queue 110, such as Figure 3 As shown, the closer an access request is to the right, the earlier it was written into the miss status processing queue 110 (rectangles filled with dots represent access requests that have been sent to the L2 cache, rectangles filled with stripes represent access requests that have not yet been sent to the L2 cache, and the area marked with an X indicates where a misprediction occurred). Canceling an erroneous access request only cancels requests that have not been sent to the L2 cache (the area filled with stripes) and that were written later than the misprediction instruction (the area to the left of the X).

[0048] In this instruction prefetching method, requests already sent to the L2 cache are not canceled. Even if the prediction is incorrect, data backfilling still occurs. This results in low prefetch accuracy and low utilization of the miss state processing queue. Furthermore, it can cause errors in updating the most recently accessed information in the L1 instruction cache.

[0049] At least one embodiment of the present disclosure provides an instruction prefetching method, an instruction prefetching device, a processor, and an electronic device. The instruction prefetching method can improve prefetching accuracy, increase the utilization rate of the loss state processing queue, and help improve overall performance.

[0050] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements described above.

[0051] At least one embodiment of the present disclosure provides an instruction prefetch method. The instruction prefetch method includes: in response to a target instruction missing in a target cache, writing a target access request for the target instruction into a loss status processing queue, the loss status processing queue including multiple access requests, the target access request being one of the multiple access requests, the loss status processing queue being configured to sequentially send the multiple access requests to a next-level cache of the target cache; in response to a target instruction prediction error, sending a cancel request for the target instruction to the loss status processing queue; and in response to the cancel request, releasing queue space occupied by access requests located after the target access request in the loss status processing queue.

[0052] Figure 4 A flowchart of an instruction prefetching method provided in some embodiments of the present disclosure. Figure 4 As shown, in some embodiments, the instruction prefetching method includes the following operations.

[0053] Step S11: in response to a target instruction not hitting a target cache, writing a target access request for the target instruction into a loss status processing queue, wherein the loss status processing queue includes a plurality of access requests, the target access request is one of the plurality of access requests, and the loss status processing queue is configured to sequentially send the plurality of access requests to a next-level cache of the target cache;

[0054] Step S12: In response to the target instruction prediction error, sending a cancel request for the target instruction to the loss status processing queue;

[0055] Step S13: In response to the cancellation request, the queue space occupied by the access request subsequent to the target access request in the lost state processing queue is released.

[0056] For example, in step S11, if the target instruction does not hit in the target cache, the target access request for the target instruction is written into the miss status processing queue, that is, Figure 2A The process of ① is similar to that of . For example, the loss status processing queue includes multiple access requests, and the target access request is one of the multiple access requests. The loss status processing queue is configured to send multiple access requests to the next level cache of the target cache in sequence to request instructions. For example, the target instruction can be a currently predicted instruction, that is, an instruction that needs to be prefetched. For example, in some examples, the target cache is a first-level cache, and its next-level cache is a second-level cache, and the loss status processing queue is configured to send multiple access requests to the second-level cache in sequence. For example, the process of the loss status processing queue sending access requests to the second-level cache is similar to Figure 2B The process of ② is similar. The Miss Status Handling Queue, also known as the MSHQ, is a component that stores the missing address and other information after a cache miss occurs and processes access requests to the next level of cache.

[0057] For example, in some examples, the target cache may be a first-level instruction cache (e.g., the instruction cache in the aforementioned first-level cache), and the next-level cache may be a second-level cache (e.g., the aforementioned second-level cache). Of course, the embodiments of the present disclosure are not limited thereto, and the target cache and its next-level cache may be caches of any level, for example, a second-level cache and a third-level cache, respectively, as long as they are adjacent two-level caches, which can be determined according to actual needs.

[0058] For example, in step S12, if the target instruction is mispredicted, a cancel request for the target instruction is sent to the lost state processing queue. For example, a target instruction misprediction may refer to an error in the prediction of a branch instruction, that is, the current target instruction is not the instruction to be executed next. Therefore, in order to cancel the target access request corresponding to the target instruction in the lost state processing queue, a cancel request for the target instruction needs to be sent to the lost state processing queue.

[0059] For example, in step S13, upon receiving a cancellation request, the lost state processing queue releases the queue space occupied by the access requests that follow the target access request, that is, cancels all access requests that follow the target access request. At this point, there is no need to determine whether these requests have been sent to the next level cache. As long as they follow the target access request, they are all canceled. For example, in an embodiment of the present disclosure, even if the requests in the lost state processing queue have been sent to the next level cache, as long as these requests come from erroneous predictions, the positions of these requests in the lost state processing queue will be canceled.

[0060] For example, releasing the queue space occupied by the access request following the target access request in the lost status processing queue may include: clearing the queue space occupied by the access request following the target access request in the lost status processing queue; or updating the status indicator of the queue space occupied by the access request following the target access request in the lost status processing queue to an idle state. Thus, the space can be released so that a new access request can be written.

[0061] For example, in some examples, at least one of the access requests following the target access request has been sent to the next level cache. Figure 5 As shown in the figure, in some examples, the X is the location where the misprediction occurred, the rectangle filled with dots represents the access request that has been sent to the next level cache, and the rectangle filled with stripes represents the access request that has not yet been sent to the next level cache. When the loss status processing queue receives a cancellation request, it cancels all access requests to the left of the location where the misprediction occurred. Among these canceled access requests, there are both access requests that have not yet been sent to the next level cache and access requests that have already been sent to the next level cache. Figure 3 Compared with the situation shown in FIG, in this embodiment, one more access request is deleted. The access request that is deleted is the access request that has been sent to the next level cache. The number of requests that the embodiment of the present disclosure abandons backfilling the misprediction is less than Figure 3 There are many more situations shown.

[0062] For example, an access request that follows a target access request is one that was sent to the lost status processing queue later than the target access request. For example, "following the target access request" does not describe a physical location, but rather a temporal order, indicating the order in which the access requests were sent to the lost status processing queue. This is consistent with the meaning of order in queues in common computer technology.

[0063] Through the above method, all requests corresponding to instructions with incorrect predictions can be canceled, thereby avoiding prefetching incorrect instructions and improving prefetching accuracy. In addition, more positions in the lost state processing queue are vacant, and the queue space released after cancellation can be used to store new access requests, allowing more new valid access requests to be written to the lost state processing queue in advance, thereby improving the utilization rate of the lost state processing queue and avoiding requests corresponding to instructions with incorrect predictions occupying the queue space of the lost state processing queue. The instruction prefetching method provided by the embodiment of the present disclosure provides a strategy that can improve the accuracy of instruction prefetching, which helps to improve the overall performance of the system.

[0064] Figure 6 A flow chart of another instruction prefetching method provided in some embodiments of the present disclosure. Figure 6 As shown, in some examples, the instruction prefetching method may further include the following operations.

[0065] Step S14: the loss status processing queue sends multiple access requests to the next level cache in sequence, and the next level cache responds to each access request in sequence;

[0066] Step S15: comparing the first preset information in the data returned by the next-level cache with the second preset information stored in the queue space corresponding to the access request corresponding to the data in the lost state processing queue;

[0067] Step S16: in response to the first preset information matching the second preset information, sending the data to the target cache and releasing the queue space corresponding to the access request corresponding to the data in the lost state processing queue, wherein the data includes the target instruction;

[0068] Step S17: In response to the first preset information not matching the second preset information, sending a consistency maintenance request to the next level cache;

[0069] Step S18: In response to the consistency maintenance request, the next level cache discards the data;

[0070] Step S19: In response to the consistency maintenance request, the next-level cache updates the flag information in the entry corresponding to the data to an invalid state.

[0071] For example, in step S14, the loss status processing queue sends multiple access requests therein to the next level cache in sequence, and the next level cache responds to each access request in sequence, for example, providing data corresponding to each access request in sequence, for example, these data include instructions corresponding to each access request.

[0072] For example, in step S15, the first preset information in the data returned by the next level cache is compared with the second preset information stored in the queue space corresponding to the access request corresponding to the data in the lost state processing queue. In the aforementioned step S13, if there is a prediction error, the lost state processing queue will receive a cancellation request and release the queue space occupied by the access request located after the target access request in response to the cancellation request, that is, all access requests located after the target access request will be canceled. Among these canceled access requests, there may be access requests that have already been sent to the next level cache. Therefore, in this step S15, it is necessary to compare and judge the data returned by each access request to prevent the data corresponding to the canceled access request from still being backfilled into the target cache.

[0073] For example, the first preset information may include the address information of the data. For example, the second preset information may include the address information stored in the queue space corresponding to the access request corresponding to the data in the lost state processing queue, and / or include flag information indicating an idle state. That is, in the case where the queue space corresponding to the access request corresponding to the data in the lost state processing queue has not been released, the second preset information may be the address information stored in the corresponding queue space; in the case where the queue space corresponding to the access request corresponding to the data in the lost state processing queue has been released, the second preset information may be flag information indicating an idle state. By comparing the first preset information with the second preset information, it can be determined whether the access request corresponding to the data has been canceled.

[0074] For example, in step S16, if the first preset information matches the second preset information, that is, the address represented by the first preset information is the same as the address represented by the second preset information, then the corresponding access request has not been canceled, and therefore the corresponding data needs to be backfilled into the target cache. For example, the data to be backfilled includes the target instruction. After the data is stored in the target cache, the queue space corresponding to the access request corresponding to the data in the lost state processing queue is released, that is, the corresponding access request is deleted. Thus, instruction prefetching can be completed in the above manner.

[0075] For example, if the "update first" approach is used, storing data in the target cache may include: based on the location information stored in the queue space corresponding to the access request corresponding to the data in the lost state processing queue, sending the data to the target cache and storing it in the corresponding cache way of the target cache. For example, the location information indicates the cache way of the target cache where the corresponding data should be stored. For example, if the "update last" approach is used, there is no need to obtain the location information from the lost state processing queue.

[0076] For example, in step S17, if the first preset information does not match the second preset information, that is, the first preset information represents an address and the second preset information is flag information indicating an idle state, or the address represented by the first preset information is different from the address represented by the second preset information, then it means that the corresponding access request has been canceled, so there is no need to backfill the corresponding data into the target cache. At this time, in order to maintain cache consistency, it is necessary to send a consistency maintenance request to the next level of cache. For example, when different processor cores or threads have their own caches, ensuring that the content modification of a certain address by one core or thread can be "seen" by other cores or threads to ensure the correct execution of the program is called cache consistency.

[0077] It should be noted that the mismatch between the first preset information and the second preset information may refer to different values between the first preset information and the second preset information, or different types between the first preset information and the second preset information, or may refer to other situations. As long as the first preset information and the second preset information are different, they can be considered mismatched. The first preset information is not limited to address information, and the second preset information is not limited to address information or flag information indicating an idle state. The first preset information and the second preset information can be of any type as long as they can achieve the purpose of confirming the status of the access request (confirming whether the access request has been canceled). The embodiments of the present disclosure are not limited to this.

[0078] For example, in some examples, if the corresponding access request in the lost state processing queue is canceled and the corresponding queue space has not been written with a new request, then at this time, flag information indicating an idle state can be stored in the queue space, that is, the second preset information is flag information indicating an idle state. The first preset information is address information, so the first preset information and the second preset information are of different types and do not match. For example, in other examples, if the corresponding access request in the lost state processing queue is canceled and the corresponding queue space is written with a new request, then at this time, the second preset information stored in the queue space is the address corresponding to the new request, so the first preset information and the second preset information have different values (different specific addresses), and do not match. Of course, there may be other situations, which are not listed here one by one.

[0079] For example, in step S18, in response to the consistency maintenance request, the next level cache discards the data. In order to maintain cache consistency, since the data does not need to be backfilled to the target cache, the data can be discarded.

[0080] For example, in step S19, in response to the consistency maintenance request, the next-level cache updates the flag information in the entry corresponding to the data to an invalid state. In order to maintain cache consistency, since the data does not need to be backfilled to the target cache, the next-level cache updates the flag information in the entry corresponding to the data to an invalid state, thereby invalidating the data. For example, a flag information can be added to each entry in the next-level cache, and the flag information indicates whether the data at the address is stored in the target cache. For example, if the data at the address is stored in the target cache, the flag information is in a valid state; if the data at the address is not stored in the target cache, the flag information is in an invalid state.

[0081] It should be noted that the above steps S18 and S19 provide two different ways to maintain cache consistency. However, the embodiments of the present disclosure are not limited thereto, and other ways can also be used to maintain cache consistency, which can be determined according to actual needs.

[0082] In the above manner, when the next-level cache has prepared the data and is ready to backfill, it will first query the previous position of the corresponding access request in the lost state processing queue and perform an address comparison. If the position is not occupied by a new access request, or the address of the newly written access request does not match the backfill address, the data from the next-level cache will not be backfilled to the target cache, and an operation to maintain cache consistency will be performed. If the access request address and the backfill address at the position match, the data from the next-level cache will be backfilled to the target cache. Thus, a step of verifying the address is added before data backfilling, so that correct data backfill can be achieved when the prediction is correct, and cache consistency can be maintained when the prediction is wrong.

[0083] Figure 7 A flowchart of another instruction prefetching method provided in some embodiments of the present disclosure. Figure 7 As shown, in some examples, the instruction prefetching method may further include the following operations.

[0084] Step S21: selecting a cache way in the target cache;

[0085] Step S22: before the next level cache returns data, update the most recently accessed information of the selected cache way;

[0086] Step S23: When the next level cache returns data, the target instruction contained in the data is stored in the selected cache way.

[0087] For example, the above steps S21-S23 may be the aforementioned “update first” method, that is, first updating the most recently accessed information, and then pre-fetching and backfilling the data.

[0088] For example, step S21 may include: based on the recent access information of each cache way in the target cache, the cache way that has not been used for the longest time (Least Recently Used) is selected as the cache way. For example, in step S22, after the cache way is selected, before the next level cache returns the data, the recent access information of the selected cache way is updated, for example, the recent access information of the "way" is marked as the maximum value, and at the same time, the recent access information numbers of the remaining "ways" are reduced by 1 until they are minimized to 0. For example, in step S23, when the next level cache returns the data, the target instruction contained in the data is stored in the selected cache way. In this way, the "update first" method is implemented.

[0089] Figure 8 A flowchart of another instruction prefetching method provided in some embodiments of the present disclosure. Figure 8 As shown, in some examples, the instruction prefetching method may further include the following operations.

[0090] Step S24: selecting a cache way in the target cache;

[0091] Step S25: When the next-level cache returns data, the target instruction contained in the data is stored in the selected cache way, and the most recently accessed information of the selected cache way is updated.

[0092] For example, the above steps S24-S25 may be the aforementioned "post-update" method, that is, updating the most recently accessed information while backfilling the data.

[0093] For example, step S24 may include: based on the most recently accessed information of each cache way in the target cache, the cache way that has not been used for the longest time (Least Recently Used) is selected as the cache way. For example, in step S25, when the next-level cache returns data, the target instruction contained in the data is stored in the selected cache way, and the most recently accessed information of the selected cache way is updated, that is, the most recently accessed information is updated while the data is backfilled. In this way, a "post-update" method is implemented. In this way, update errors of the most recently accessed information of the target cache can be avoided, for example, update errors of the most recently accessed information of the first-level instruction cache can be avoided.

[0094] It should be noted that, in the embodiments of the present disclosure, the method of maintaining cache consistency is not limited to the two methods described above in combination with steps S18 and S19, but can also be any other applicable method, which can be determined according to actual needs, and the embodiments of the present disclosure do not limit this.

[0095] It should be noted that the instruction prefetching method provided by the embodiment of the present disclosure is not limited to the steps and sequence described above, and may also include more or fewer steps. The execution order of each step may be determined according to actual needs, and the embodiment of the present disclosure does not limit this. The instruction prefetching method can be used for Figure 1 The cache architecture shown can also be used for any other applicable cache architecture, and the embodiments of the present disclosure are not limited to this.

[0096] At least one embodiment of the present disclosure further provides an instruction prefetching device that can improve prefetching accuracy, increase the utilization rate of the loss state processing queue, and help improve overall performance.

[0097] Figure 9 This is a schematic block diagram of an instruction prefetching device provided in some embodiments of the present disclosure. Figure 9 As shown, the instruction prefetch device 10 includes a request writing unit 11 , a request canceling unit 12 , and a request processing unit 13 .

[0098] The request writing unit 11 is configured to write a target access request for a target instruction into a loss status processing queue in response to a target instruction not being hit in the target cache. For example, the loss status processing queue includes multiple access requests, and the target access request is one of the multiple access requests. The loss status processing queue is configured to sequentially send the multiple access requests to the next level cache of the target cache. For example, the request writing unit 11 may execute Figure 4 Step S11 in the instruction prefetch method shown.

[0099] The request cancellation unit 12 is configured to send a cancellation request for the target instruction to the loss status processing queue in response to the target instruction prediction error. For example, the request cancellation unit 12 may execute Figure 4 Step S12 in the instruction prefetch method shown.

[0100] The request processing unit 13 is configured to release the queue space occupied by the access request that follows the target access request in the lost state processing queue in response to the cancellation request. For example, the request processing unit 13 may execute Figure 4 Step S13 in the instruction prefetch method shown.

[0101] For example, in some examples, at least one of the access requests that follows the target access request has already been sent to the next-level cache. For example, an access request that follows the target access request is an access request that was sent to the lost status processing queue later than the target access request. For example, "following the target access request" is not a description of a physical location, but rather a description of a temporal sequence, used to indicate the temporal sequence in which the access requests were sent to the lost status processing queue. This is consistent with the meaning of a sequence in a queue in common computer technology.

[0102] Through the above method, all requests corresponding to instructions with incorrect predictions can be canceled, thereby avoiding prefetching incorrect instructions and improving prefetching accuracy. In addition, more positions in the lost state processing queue are vacant, and the queue space released after cancellation can be used to store new access requests, allowing more new valid access requests to be written to the lost state processing queue in advance, thereby improving the utilization rate of the lost state processing queue and avoiding requests corresponding to instructions with incorrect predictions occupying the queue space of the lost state processing queue. The instruction prefetching device provided by the embodiment of the present disclosure provides a strategy that can improve the accuracy of instruction prefetching, which helps to improve the overall performance of the system.

[0103] For example, the miss status processing queue sends a plurality of access requests to the next level cache in sequence, and the next level cache responds to each access request in sequence.

[0104] For example, the instruction prefetch device 10 may further include a comparison unit, a backfill unit, and a consistency processing unit. For example, the instruction prefetch device 10 may further include a first processing unit or a second processing unit.

[0105] The comparison unit is configured to compare the first preset information in the data returned by the next level cache with the second preset information stored in the queue space corresponding to the access request corresponding to the data in the lost state processing queue. The backfill unit is configured to send the data to the target cache in response to the first preset information matching the second preset information, and release the queue space corresponding to the access request corresponding to the data in the lost state processing queue. For example, the data includes the target instruction. The consistency processing unit is configured to send a consistency maintenance request to the next level cache in response to the first preset information not matching the second preset information.

[0106] The first processing unit is configured to, in response to the coherence maintenance request, enable the next level cache to discard the data. The second processing unit is configured to, in response to the coherence maintenance request, enable the next level cache to update the flag information in the entry corresponding to the data to an invalid state.

[0107] For example, the first preset information includes address information of the data. The second preset information includes address information of the access request corresponding to the data stored in the queue space corresponding to the lost state processing queue and / or flag information indicating an idle state.

[0108] For example, the target cache includes a first-level instruction cache, and the next-level cache includes a second-level cache.

[0109] For example, the request processing unit 13 may include a first subunit or a second subunit. The first subunit is configured to clear the contents of the queue space occupied by the access request located after the target access request in the lost status processing queue. The second subunit is configured to update the state indicator of the queue space occupied by the access request located after the target access request in the lost status processing queue to an idle state.

[0110] For example, in some examples, the instruction prefetch device 10 may further include a selection unit, an update unit, and a return unit. The selection unit is configured to select a cache way in the target cache. The update unit is configured to update the most recently accessed information of the selected cache way before the next-level cache returns the data. The return unit is configured to store the target instruction contained in the data in the selected cache way when the next-level cache returns the data.

[0111] For example, in other examples, the instruction prefetch device 10 may further include a selection unit and an update return unit. The selection unit is configured to select a cache way in the target cache. The update return unit is configured to store the target instruction contained in the data in the selected cache way when the next-level cache returns data, and update the recently accessed information of the selected cache way.

[0112] For example, the selection unit includes a selection subunit, and the selection subunit is configured to select a cache way that has not been used for the longest time as the selected cache way based on the most recent access information of each cache way in the target cache.

[0113] For example, each of the above-mentioned units and sub-units may be hardware, software, firmware, or any feasible combination thereof. For example, each of the above-mentioned units and sub-units may be a dedicated or general-purpose circuit, chip, or device, or may be a combination of a processor and memory. The embodiments of the present disclosure do not limit the specific implementation of each of the above-mentioned units and sub-units.

[0114] It should be noted that in the embodiment of the present disclosure, the various units of the instruction prefetch device 10 correspond to the various steps of the aforementioned instruction prefetch method. For the specific functions and technical effects of the instruction prefetch device 10, please refer to the relevant description of the instruction prefetch method above, which will not be repeated here. Figure 9The components and structures of the instruction prefetch device 10 shown are merely exemplary and non-limiting. The instruction prefetch device 10 may further include other components and structures as needed.

[0115] At least one embodiment of the present disclosure further provides a processor that can improve prefetch accuracy, increase utilization of a loss state processing queue, and contribute to improving overall performance.

[0116] Figure 10 This is a schematic block diagram of a processor provided in some embodiments of the present disclosure. Figure 10 As shown, the processor 20 includes a target cache 21 , a next-level cache 22 of the target cache, and a miss status processing queue 23 .

[0117] The loss status processing queue 23 is configured to receive a target access request for the target instruction in response to a target instruction miss in the target cache, and to send multiple access requests in sequence to the next level cache. For example, the loss status processing queue 23 includes multiple access requests, and the target access request is one of the multiple access requests. The loss status processing queue 23 is also configured to receive a cancel request for the target instruction in response to a target instruction prediction error, and in response to the cancel request, release the queue space occupied by the access request after the target access request. The processor 20 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be an X86 or ARM architecture, etc. The processor 20 can be a general-purpose processor or a dedicated processor.

[0118] It should be noted that in the embodiment of the present disclosure, the working mode of the processor 20 corresponds to the various steps of the aforementioned instruction prefetch method. For the specific functions and technical effects of the processor 20, please refer to the relevant description of the instruction prefetch method above, which will not be repeated here. Figure 10 The components and structures of the processor 20 shown are merely exemplary and non-limiting. The processor 20 may further include other components and structures as needed.

[0119] At least one embodiment of the present disclosure further provides an electronic device comprising the instruction prefetching apparatus provided by any embodiment of the present disclosure. The electronic device can improve prefetching accuracy, increase the utilization rate of the loss state processing queue, and help improve overall performance.

[0120] Figure 11 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 11 As shown, the electronic device 30 includes an instruction prefetching device 31, which can be Figure 9The instruction prefetch device 10 shown. For example, the electronic device 30 can be any device with data processing capabilities and / or program execution capabilities, and the embodiments of the present disclosure are not limited thereto. For the specific functions and technical effects of the electronic device 30, please refer to the relevant description of the instruction prefetch device 10 above, and will not be repeated here.

[0121] At least one embodiment of the present disclosure further provides an electronic device comprising the processor provided by any embodiment of the present disclosure. The electronic device can improve prefetching accuracy, increase the utilization rate of the loss state processing queue, and help improve overall performance.

[0122] Figure 12 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. Figure 12 As shown, the electronic device 40 includes a processor 41, which can be Figure 10 The processor 20 shown. For example, the electronic device 40 can be any device with data processing capabilities and / or program execution capabilities, and the embodiments of the present disclosure are not limited thereto. For the specific functions and technical effects of the electronic device 40, please refer to the relevant description of the processor 20 above, and will not be repeated here.

[0123] There are a few points to note:

[0124] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0125] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0126] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for prefetching instructions, comprising: In response to a target instruction missing in a target cache, writing a target access request for the target instruction into a miss status processing queue, wherein the miss status processing queue includes a plurality of access requests, the target access request is one of the plurality of access requests, and the miss status processing queue is configured to sequentially send the plurality of access requests to a next-level cache of the target cache; In response to the target instruction misprediction, sending a cancel request for the target instruction to the loss status processing queue; In response to the cancellation request, releasing the queue space occupied by the access request located after the target access request in the lost state processing queue; The method further comprises: The loss status processing queue sends the multiple access requests to the next level cache in sequence, and the next level cache responds to each access request in sequence; Comparing first preset information in the data returned by the next-level cache with second preset information stored in the queue space corresponding to the access request corresponding to the data in the lost state processing queue; In response to a match between the first preset information and the second preset information, sending the data to the target cache and releasing a queue space corresponding to an access request corresponding to the data in the lost state processing queue, wherein the data includes the target instruction; In response to the first preset information not matching the second preset information, sending a consistency maintenance request to the next-level cache.

2. The method according to claim 1, wherein At least one access request among the access requests subsequent to the target access request has been sent to the next-level cache.

3. The method according to claim 2, wherein: The access request following the target access request is an access request sent to the lost status processing queue later than the target access request.

4. The method according to claim 1, further comprising: In response to the coherency maintenance request, the next level cache discards the data.

5. The method according to claim 1, further comprising: In response to the coherence maintenance request, the next-level cache updates flag information in the entry corresponding to the data to an invalid state.

6. The method according to claim 1, wherein The first preset information includes address information of the data; The second preset information includes address information of an access request corresponding to the data stored in a queue space corresponding to the lost state processing queue and / or flag information indicating an idle state.

7. The method according to claim 1, wherein The target cache includes a first-level instruction cache, and the next-level cache includes a second-level cache.

8. The method according to claim 1, wherein Releasing the queue space occupied by the access request located after the target access request in the lost state processing queue, comprising: Clearing the queue space occupied by the access request following the target access request in the lost state processing queue; or The state identifier of the queue space occupied by the access request located after the target access request in the lost state processing queue is updated to an idle state.

9. The method according to claim 1, further comprising: Selecting a cache way in the target cache; Before the next level cache returns data, updating the most recently accessed information of the selected cache way; When the next-level cache returns data, the target instruction contained in the data is stored in the selected cache way.

10. The method according to claim 1, further comprising: Selecting a cache way in the target cache; When the next-level cache returns data, the target instruction contained in the data is stored in the selected cache way, and the most recently accessed information of the selected cache way is updated.

11. The method according to claim 9 or 10, wherein: Selecting a cache way in the target cache includes: According to the most recent access information of each cache way in the target cache, the cache way that has not been used for the longest time is selected as the cache way.

12. An instruction prefetch device, comprising: a request writing unit configured to, in response to a target instruction missing in a target cache, write a target access request for the target instruction into a loss status processing queue, wherein the loss status processing queue includes a plurality of access requests, the target access request is one of the plurality of access requests, the loss status processing queue is configured to sequentially send the plurality of access requests to a next-level cache of the target cache, and the next-level cache responds to each access request in sequence; a request cancellation unit configured to send a cancellation request for the target instruction to the loss status processing queue in response to a prediction error of the target instruction; a request processing unit configured to release, in response to the cancellation request, queue space occupied by the access request subsequent to the target access request in the lost state processing queue; Wherein, the device further includes: a comparing unit configured to compare first preset information in the data returned by the next-level cache with second preset information stored in a queue space corresponding to an access request corresponding to the data in the lost state processing queue; a backfill unit configured to, in response to a match between the first preset information and the second preset information, send the data to the target cache and release a queue space corresponding to an access request corresponding to the data in the lost state processing queue, wherein the data includes the target instruction; The consistency processing unit is configured to send a consistency maintenance request to the next-level cache in response to the first preset information not matching the second preset information.

13. A processor comprising a target cache, a next-level cache of the target cache, and a miss status processing queue; wherein: The miss status processing queue is configured to receive a target access request for a target instruction in response to a target instruction missing in a target cache, and to sequentially send a plurality of access requests to the next level cache; The next level cache is configured to respond to each access request in sequence; the loss status processing queue includes the multiple access requests, and the target access request is one of the multiple access requests; The loss status processing queue is further configured to receive a cancel request for the target instruction in response to the target instruction misprediction, and release queue space occupied by an access request subsequent to the target access request in response to the cancel request; The processor is further configured to compare first preset information in the data returned by the next-level cache with second preset information stored in the queue space corresponding to the access request corresponding to the data in the lost state processing queue; In response to the first preset information matching the second preset information, the data is sent to the target cache, and the queue space corresponding to the access request corresponding to the data in the loss state processing queue is released, wherein the data includes the target instruction; in response to the first preset information not matching the second preset information, a consistency maintenance request is sent to the next level cache.

14. An electronic device comprising the instruction prefetching device according to claim 12.

15. An electronic device comprising the processor according to claim 13.

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