A FPGA acceleration board and market data processing method thereof

Abstract

The present application provides an FPGA acceleration board, including: a network interface for receiving exchange market data; a CAM table for storing the mapping relationship between securities codes and market storage addresses; a RISC‑V processor connected to both the network interface and the message buffer, and including a built-in quantitative trading algorithm, for parsing exchange market data, obtaining market information, transaction information, and entrustment information including securities codes; when a transaction is detected, querying the entrustment price according to the entrustment information record number in the entrustment information; and calculating the latest market information according to the entrustment price and the market storage address, and outputting the latest market information. The application utilizes the low latency characteristics of FPGA and the open source and extensible instruction set characteristics of RISC‑V to improve the reconstruction efficiency of financial transaction market conditions. The present application also provides a market data processing method, which has the above-mentioned beneficial effects, which will not be repeated here.

Description

Technical Field

[0001] The present application relates to the field of server hardware, and in particular to an FPGA acceleration board and a market data processing method thereof. Background Art

[0002] At present, traditional software is usually used for data statistical analysis of financial market conditions, or software-based hardware and software acceleration technology cannot meet the current real-time response requirements. Taking the Shenzhen Stock Exchange Level-2 market conditions as an example, it contains two types of data: transaction-by-transaction and transaction-by-transaction. Therefore, the receiver can use the transaction-by-transaction data and trading rules to reconstruct the market conditions by itself. At present, the mainstream solution is still software reconstruction, but the processing capacity is far from meeting the current market real-time data requirements, and its market reconstruction efficiency is relatively low. Summary of the invention

[0003] The purpose of this application is to provide an FPGA acceleration board and a market data processing method thereof, which can achieve high-performance reconstruction of market conditions.

[0004] In order to solve the above technical problems, this application provides an FPGA acceleration board, and the specific technical solution is as follows:

[0005] Network interface, used to receive exchange market data;

[0006] CAM table, used to store the mapping relationship between securities codes and market information storage addresses;

[0007] A RISC-V processor connected to the network interface and the message buffer and including a built-in quantitative trading algorithm is used to parse the exchange market data to obtain market information, transaction information and entrustment information including the securities code; when a transaction is detected, the entrustment price is queried according to the entrustment information record number in the entrustment information; and the latest market information is calculated according to the entrustment price and the market storage address, and the latest market information is output;

[0008] The message buffer connected to the CAM table is used to store the market information storage address and the market information.

[0009] Optionally, also include:

[0010] A FIFO queue connected to both the CAM table and the message buffer, used for caching the market storage address, the entrustment information and the transaction information.

[0011] Optionally, also include:

[0012] A configurable register connected to the CAM table and used to configure key information; the key information includes the IP address of the FPGA acceleration board and the exchange IP address of the exchange market data.

[0013] Optionally, also include:

[0014] The off-chip memory connected to the FIFO queue is used to store the delegation information.

[0015] Optionally, also include:

[0016] The MAC interface and / or PCIE interface connected to the RISC-V processor is used to transmit the latest market information.

[0017] The present application also provides a market data processing method, based on the FPGA acceleration board described above, comprising:

[0018] Get exchange market data;

[0019] Parsing the exchange market data to obtain market information, transaction information and entrustment information; the entrustment information includes an entrustment information record number and a securities code;

[0020] Query the entrustment price according to the entrustment information record number, and retrieve the CAM table according to the securities code to determine the corresponding market information storage address;

[0021] The entrustment price and the market information storage address are sent to the RISC-V processor so that the RISC-V processor can use the built-in quantitative trading algorithm to perform market information calculation on the entrustment price and the market information storage address to obtain the latest market information.

[0022] Optionally, after parsing the exchange market data to obtain market information, transaction information and entrustment information, the method further includes:

[0023] storing the delegation information in an off-chip memory;

[0024] When transaction information is detected, the entrustment information in the off-chip memory is read.

[0025] Optionally, also include:

[0026] Configure the exchange IP address for exchange market data;

[0027] The acquisition of exchange market data also includes:

[0028] Determine whether the IP address corresponding to the exchange market data belongs to the exchange IP address;

[0029] If not, refuse to receive the exchange market data.

[0030] Optionally, when transaction information is detected, it also includes:

[0031] Determine whether the market information queue in the message buffer contains the entrustment price corresponding to the transaction and the market information storage address;

[0032] If so, the position of the entrustment price in the quotation queue and the corresponding quotation information are fed back;

[0033] If not, the corresponding market information is inserted into the market queue according to the commission price.

[0034] Optionally, after obtaining the latest market information, it also includes:

[0035] Get the encapsulation format requirements of the target device;

[0036] The current market queue is encapsulated according to the encapsulation format included in the encapsulation format requirement, and transmitted to the target device through the MAC interface or the PCIE interface.

[0037] The present application provides an FPGA acceleration board, comprising: a network interface for receiving exchange market data; a CAM table for storing a mapping relationship between a securities code and a market storage address; a RISC-V processor connected to both the network interface and the message buffer and including a built-in quantitative trading algorithm, for parsing the exchange market data to obtain market information, transaction information and entrustment information including the securities code; when a transaction is detected, querying the entrustment price according to the entrustment information record number in the entrustment information; and calculating the latest market market information according to the entrustment price and the market storage address, and outputting the latest market market information; the message buffer connected to the CAM table is used to store the market storage address and the market information.

[0038] This application uses the CAM table to store the mapping relationship between securities codes and market storage addresses. During trading, the RISC-V processor with a built-in quantitative trading algorithm directly reconstructs the trading market. By utilizing the low-latency characteristics of FPGA and the open source and scalable instruction set characteristics of RISC-V, a high-performance, low-latency, flexible and scalable financial acceleration processing device is constructed, thereby improving the efficiency of reconstructing financial trading market conditions.

[0039] The present application also provides a market data processing method, which has the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0041] Figure 1 A schematic diagram of the structure of an FPGA acceleration board provided in an embodiment of the present application;

[0042] Figure 2 A flowchart of a market data processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] Figure 1 A schematic diagram of the structure of an FPGA acceleration board provided in an embodiment of the present application, the board includes:

[0045] Network interface, used to receive exchange market data;

[0046] CAM table, used to store the mapping relationship between securities codes and market information storage addresses;

[0047] A RISC-V processor connected to the network interface and the message buffer and including a built-in quantitative trading algorithm is used to parse the exchange market data to obtain market information, transaction information and entrustment information including the securities code; when a transaction is detected, the entrustment price is queried according to the entrustment information record number in the entrustment information; and the latest market information is calculated according to the entrustment price and the market storage address, and the latest market information is output;

[0048] The message buffer connected to the CAM table is used to store the market information storage address and the market information.

[0049] The network interface is not specifically limited here, and a MAC interface can be used, and of course other interfaces can also be used, which is used to receive exchange market data. Taking the MAC interface as an example, after receiving the exchange market data, the exchange market data can be converted into corresponding MAC frames. For exchange market data of different protocol types, such as the exchange market data of the Shenzhen Stock Exchange and the Shanghai Stock Exchange, the corresponding MAC frame header data is different, based on which the exchange market data corresponding to the protocol type can be distinguished.

[0050] The CAM table is used to store the mapping relationship between the securities code and the market storage address. The corresponding market storage address can be queried according to the securities code in the entrustment information or transaction information. For the market information obtained by parsing the exchange market data, a corresponding market queue needs to be established in the message buffer.

[0051] like Figure 1 As shown, the board may also include a FIFO queue connected to both the CAM table and the message buffer for caching the market storage address, the entrustment information and the transaction information. The FIFO queue may be used to cache data. The parsed entrustment information may be stored in an off-chip memory connected to the FIFO queue.

[0052] When a transaction comes, the corresponding entrustment information is obtained through the off-chip memory.

[0053] Furthermore, the board may also include a configurable register connected to the CAM table for configuring key information. The key information includes the IP address of the FPGA accelerator board and the exchange IP address of the exchange market data. That is, the IP address of the FPGA accelerator board itself is configured, and the source IP address of the exchange market data that can be processed by the FPGA accelerator board can also be limited to limit the protocol type of the exchange market data that can be processed. In addition, the configurable register can also store different types of securities information.

[0054] like Figure 1 As shown, the FPGA acceleration board can also include a MAC interface and / or PCIE interface connected to the RISC-V processor for transmitting the latest market information. Of course, any one of the MAC interface and the PCIE interface can be selected, or both interfaces can be supported at the same time to realize the output of the latest market information for different types of devices.

[0055] See also Figure 2 , Figure 2 This is a flow chart of a market data processing method provided by an embodiment of the present application. The present application also provides a market data processing method, which is implemented based on the FPGA acceleration board described above, and the method includes:

[0056] S101: Obtain exchange market data;

[0057] This step aims to obtain the exchange market data through the network interface. Before obtaining the exchange market data, the IP of the exchange market data can be restricted by the configurable module to ensure that the received exchange market data is data that can be accelerated by the FPGA acceleration board.

[0058] If the exchange IP address of the exchange market data is configured, when executing this step, you can determine whether the IP address corresponding to the exchange market data belongs to the exchange IP address. If it does not belong to the exchange IP address, you can refuse to receive the exchange market data.

[0059] Of course, there is no need to impose IP restrictions on exchange market data. The processable protocols can be parsed and processed by the RISC-V processor, while the securities Binary / Step protocol or the Shanghai Futures Exchange futures protocol can be processed by the existing protocol parsing IP. That is, other input financial protocol messages can be processed using standard instruction sets.

[0060] S102: parsing the exchange market data to obtain market information, transaction information and entrustment information;

[0061] This step requires parsing the exchange market data to obtain market information, transaction information and entrustment information; and the entrustment information includes the entrustment information record number and the stock code. It should be noted that the transaction information and entrustment information usually contain several transactions and entrustments. Taking the Shenzhen Stock Exchange Level-2 market data as an example, after parsing, it contains four types of data: entrustment by entrustment, transaction by transaction, index market data and market data. The index market data and market conditions correspond to the market information in this step.

[0062] The parsed market information can be stored in the message buffer to form a market queue. As for the entrustment information, since it is only used during trading, it can be stored in the off-chip memory. However, in order to improve the data reading efficiency of the entrustment information during trading, the cache memory can be configured to be connected to the off-chip memory, so as to quickly read the entrustment information in the off-chip memory.

[0063] S103: querying the entrustment price according to the entrustment information record number, and searching the CAM table according to the securities code to determine the corresponding market information storage address;

[0064] S104: Send the entrustment price and the market information storage address to the RISC-V processor, so that the RISC-V processor applies a built-in quantitative trading algorithm to perform market information calculation on the entrustment price and the market information storage address to obtain the latest market information.

[0065] This step requires determining the entrustment price and the market storage address. When the transaction information arrives, it is necessary to query the entrustment price according to the entrustment message record number, and obtain the market storage address through the CAM table according to the securities code, and finally send the entrustment price and market storage address to the RISC-V processor.

[0066] RISC-V processors can have built-in quantitative trading algorithms. There is no specific limitation on what kind of built-in quantitative trading algorithms are used, including but not limited to programmed T+0 strategies, Alpha strategies, and futures-to-spot arbitrage. It is easy to understand that in order to improve processing efficiency, multiple quantitative trading algorithms can be configured at the same time. It is also possible to design special custom extension instructions for RISC-V processors, cooperate with financial acceleration units, quickly complete the reconstruction of thousands of market conditions, and complete the implementation of quantitative trading algorithms on this basis.

[0067] When transaction information is detected, it can be determined whether the market information queue in the message buffer contains the entrustment price and market information storage address corresponding to the transaction. If the market information already exists in the market information queue, the position of the entrustment price in the market information queue and the corresponding market information are fed back. On the contrary, if the market information queue does not contain the market information, the corresponding market information is inserted into the market information queue according to the entrustment price. Usually sorted by entrustment price.

[0068] As can be seen from the FPGA architecture diagram, all market information is stored in the message buffer. The external FPGA module can obtain the offset address of this queue in the buffer by querying the CAM table according to the securities code, and then search in the existing market queue according to the entrustment price. If the search is successful, the position of the entrustment price in the existing market queue and the corresponding market information will be fed back; if there is no such entrustment price, the insertion position will be fed back.

[0069] After obtaining the latest market information, the encapsulation format requirements of the target device can also be obtained, so as to encapsulate the current market queue according to the encapsulation format contained in the encapsulation format requirements, and transmit it to the target device through the MAC interface or PCIE interface. It should be noted that when encapsulating, all market queues can be encapsulated, or part of the market queues can be encapsulated. It can be seen that through this embodiment, the market queue in the message buffer can be updated in real time according to the entrustment and transaction, and the market reconstruction can be realized.

[0070] The embodiment of the present application utilizes a CAM table to store the mapping relationship between security codes and market information storage addresses. During trading, a RISC-V processor with a built-in quantitative trading algorithm is used to reconstruct trading information. The low-latency characteristics of FPGA and the open source and extensible instruction set characteristics of RISC-V are utilized to build a high-performance, low-latency, flexible and extensible financial acceleration processing device, thereby improving the efficiency of reconstructing financial trading information.

[0071] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the system provided in the embodiment, since it corresponds to the method provided in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0072] Specific examples are used herein to illustrate the principles and implementation methods of the present application, and the description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0073] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. An FPGA acceleration board, characterized in that: include: Network interface, used to receive exchange market data; CAM table, used to store the mapping relationship between securities codes and market information storage addresses; The RISC-V processor is connected to the network interface and the message buffer, and includes a plurality of built-in quantitative trading algorithms, and is used to parse the exchange market data to obtain market information, transaction information and entrustment information including the security code; wherein the quantitative trading algorithm includes: programmed T+0 strategy, Alpha strategy, and futures-spot arbitrage; the market information obtained by parsing is stored in the message buffer to form a market queue, and the entrustment information obtained by parsing is stored in an off-chip memory; When a transaction is detected, the entrustment information in the off-chip memory is read; the entrustment price is queried according to the entrustment information record number in the entrustment information; and the latest market information is calculated according to the entrustment price and the market storage address, and the latest market information is output; wherein the calculation of the latest market information according to the entrustment price and the market storage address includes: querying the corresponding market storage address according to the securities code in the entrustment information or the transaction information; judging whether the market queue in the message buffer contains the entrustment price and the market storage address corresponding to the transaction; if so, feeding back the position of the entrustment price in the market queue and the corresponding market information; if not, inserting the corresponding market information into the market queue according to the entrustment price; The message buffer connected to the CAM table is used to store the market information storage address and the market information; A FIFO queue connected to the CAM table and the message buffer, used for caching the market storage address, the entrustment information and the transaction information; an off-chip memory connected to the FIFO queue, for storing the delegation information; a high-speed cache memory connected to the off-chip memory, used for reading the delegation information in the off-chip memory; A configurable register connected to the CAM table and used to configure key information; the key information includes the IP address of the FPGA acceleration board and the exchange IP address of the exchange market data, and is used to determine whether the IP address corresponding to the exchange market data belongs to the exchange IP address when acquiring the exchange market data; if not, refuse to receive the exchange market data; A MAC interface and / or PCIE interface connected to the RISC-V processor is used to transmit the latest market information to the target device; wherein the latest market information is a current market queue encapsulated in an encapsulation format according to the encapsulation format requirement corresponding to the target device, and is transmitted to the target device through a MAC interface or a PCIE interface.

2. A market data processing method, based on the FPGA acceleration board according to claim 1, characterized in that: include: Get exchange market data; Parsing the exchange market data to obtain market information, transaction information and entrustment information; The entrustment information includes the entrustment information record number and the securities code; The market information obtained by parsing is stored in the message buffer to form a market queue, and the entrustment information obtained by parsing is stored in the off-chip memory; Query the entrustment price according to the entrustment information record number, and retrieve the CAM table according to the securities code to determine the corresponding market information storage address; The entrustment price and the market storage address are sent to the RISC-V processor, so that the RISC-V processor applies a plurality of built-in quantitative trading algorithms to perform market calculations on the entrustment price and the market storage address to obtain the latest market information; wherein the quantitative trading algorithms include: programmed T+0 strategy, Alpha strategy, and futures-spot arbitrage; When transaction information is detected, the method further includes: Reading the delegation information in the off-chip memory; Query the corresponding market information storage address according to the securities code in the entrustment information or transaction information; Determine whether the market information queue in the message buffer contains the entrustment price corresponding to the transaction and the market information storage address; If so, the position of the entrustment price in the quotation queue and the corresponding quotation information are fed back; If not, insert the corresponding market information into the market queue according to the commission price; The method further comprises: Configure the exchange IP address for exchange market data; The acquisition of exchange market data also includes: Determine whether the IP address corresponding to the exchange market data belongs to the exchange IP address; If not, refuse to receive the exchange market data; After obtaining the latest market information, the method further includes: Get the encapsulation format requirements of the target device; The current market queue is encapsulated according to the encapsulation format included in the encapsulation format requirement, and transmitted to the target device through the MAC interface or the PCIE interface.

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