AHB bus data transmission method and device

Abstract

The present application provides a data transmission method and device for an AHB bus. Each time an AHB master device transmits data to a slave end, the AHB master device performs an authentication operation on the slave end. The AHB master device pre-reconstructs an AHB master device space mapping table to perform the authentication operation on the slave end using information in the AHB master device space mapping table. Upon determining that authentication is successful, the AHB master device transmits data to the slave end. The present application's solution, by reconstructing the AHB master device space mapping table of the AHB master device and adding corresponding logic control for performing the authentication operation on the slave end using information in the AHB master device space mapping table, implements the authentication operation on the slave end on the AHB master device without requiring the integration of a separate security authentication module, thereby reducing the workload during integration and avoiding additional power and area consumption.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a data transmission method and device for an AHB bus. Background Art

[0002] As the scale of integrated circuit chips continues to increase, and their functionality and complexity increase, the number of slave controllers generated within SOC (system-on-chip) chips to interact with other devices is increasing. In particular, the number of slaves based on the AHB bus configuration port is increasing. Considering the security requirements and chip robustness requirements in SOC chip design, additional security authentication logic and bus anti-hang logic are usually added in addition to the AHB bus. To address this, existing technologies add corresponding logic controls based on the specific characteristics of each slave. However, the security authentication and bus anti-hang modules are relatively complex to implement, resulting in additional power and area consumption. Furthermore, integrating these two components separately based on demand also adds additional workload. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a data transmission method and device for an AHB bus, so as to solve the problem that the prior art adds corresponding logic control according to the specific characteristics of each slave, which will bring additional power consumption and area consumption, and for integration, separately integrating these two types of components according to needs will also increase additional workload.

[0004] An embodiment of the present application provides a data transmission method of an AHB bus, comprising:

[0005] Each time before the AHB master device transmits data to the slave end, the AHB master device performs the authentication operation on the slave end. The AHB master device pre-reconstructs the AHB master device space mapping table to perform the authentication operation on the slave end based on the information in the AHB master device space mapping table.

[0006] If the authentication is successful, the AHB master device transmits data to the Slave end.

[0007] In the above technical solution, by reconstructing the AHB master device space mapping table of the AHB master device and adding corresponding logic control of the authentication operation of the slave side based on the information of the AHB master device space mapping table, the authentication operation of the slave side is realized in the AHB master device, without the need for additional separate integration of a security authentication module, reducing the workload during integration and avoiding additional power consumption and area consumption.

[0008] In some optional implementations, the authentication operation performed by the AHB master device includes: authentication of the address range of the slave, authentication of the security state of the slave, and authentication of the clock / reset state of the slave;

[0009] Determining that the authentication is passed includes: determining that the authentication is passed when the address range authentication of the slave, the security state authentication of the slave, and the clock / reset state authentication of the slave are all passed.

[0010] In the above technical solution, the authentication operation performed by the AHB master device includes authentication of the slave's address range, the slave's security status, and the slave's clock / reset status. That is, the AHB master device has some security authentication logic and bus anti-hang logic when the slave is turned off or in an inaccessible state such as reset. Only when the slave's address range authentication, the slave's security status authentication, and the slave's clock / reset status authentication are all passed can it be determined that the authentication is successful.

[0011] In some optional implementations, the Slave address range authentication includes:

[0012] Determine whether the access address of the AHB master device is within the address range of the corresponding Slave. If so, the Slave address range authentication passes; otherwise, the Slave address range authentication fails.

[0013] In some optional implementations, the Slave security status authentication includes:

[0014] Determine whether the current access of the AHB master device meets the security permissions of the slave. If the security permissions of the AHB master device are not lower than the security permissions of the slave, the security status authentication of the slave passes; otherwise, the security status authentication of the slave fails.

[0015] In some optional implementations, the clock / reset state authentication of the slave includes:

[0016] Determine whether the slave currently accessed by the AHB master device is in the clock-off or reset state. If the slave is neither in the clock-off state nor in the reset state, the slave's clock / reset state authentication passes.

[0017] In some optional embodiments, the AHB master device space mapping table pre-reconstructed by the AHB master device includes: the name of each slave end, the size of each slave end space, the starting address of each slave end space range, the end address of each slave end space range, the name / address bit width and data bit width of the AHB bus to be generated, and the corresponding slave end range.

[0018] In the above technical solution, the AHB master device pre-reconstructs the AHB master device space mapping table, which contains the name of each slave terminal, the size of each slave terminal space, the starting address of each slave terminal space range, the ending address of each slave terminal space range, the name / address bit width and data bit width of the AHB bus to be generated, and the corresponding slave terminal range. This information is used to achieve secure authentication of the slave terminal.

[0019] In some optional implementations, the authentication operation of the slave end is implemented through the information of the AHB master device space mapping table, and anti-hanging logic is also added.

[0020] In the above technical solution, in addition to implementing authentication operations based on some security authentication logic, the information of the AHB master device space mapping table of the AHB master device is used to implement the anti-hang function based on the bus anti-hang logic when the slave is shut down or in an inaccessible state such as reset.

[0021] In some optional implementations, the information of the AHB master device space mapping table is further verified, wherein the verification content includes:

[0022] Check whether the difference between the end address and the start address of the slave end space range is consistent with the size of the corresponding space;

[0023] Whether the starting address of the slave's space range is aligned with its own space size;

[0024] Parse the minimum and maximum addresses contained in the AHB bus, calculate the total address space size, and verify whether the starting address of the AHB bus is aligned with its own total address space range.

[0025] In the above technical solution, the newly added information in the reconstructed AHB master space mapping table is first verified. This includes at least three aspects: first, whether the difference between the end address and the start address of the slave-side space range is consistent with the corresponding space size; second, whether the start address of the slave-side space range is aligned with the size of the slave space range; and third, the minimum and maximum addresses contained in the AHB bus are parsed to calculate the total address space size, and whether the start address of the AHB bus is aligned with the total address space range. These verification steps avoid generating incorrect table information when reconstructing the AHB master space mapping table, ensuring the correct implementation of subsequent security authentication and other operations.

[0026] An embodiment of the present application provides an AHB bus device, including:

[0027] AHB bus master device interface, used to transmit data to the Slave end;

[0028] An access authentication unit is configured to implement an authentication operation on the slave end before each data transmission from the AHB master device to the slave end; wherein the AHB master device pre-reconstructs the space mapping table of the AHB master device to implement the authentication operation on the slave end based on the information in the space mapping table;

[0029] The authentication error feedback module is used to feedback a response to the Slave end when authentication fails.

[0030] In the above technical solution, the AHB bus master interface is used to transmit data to the slave end. The access authentication unit reconstructs the AHB master space mapping table of the AHB master device and adds corresponding information based on the AHB master space mapping table to implement logical control of the slave end's authentication operation. This enables the slave end's authentication operation to be performed on the AHB master device. If the authentication fails, the authentication error feedback module feeds back a response to the slave end. Therefore, the AHB bus device of the embodiment of the present application does not need to separately integrate a security authentication module, reducing the workload during integration and avoiding additional power and area consumption.

[0031] In some optional implementations, the access authentication unit includes:

[0032] The slave address interval authentication module is used to determine whether the access address of the AHB master device is within the corresponding slave address interval. If so, the slave address interval authentication passes; otherwise, the slave address interval authentication fails.

[0033] The slave's security status authentication module is used to determine whether the current access of the AHB master device meets the slave's security permissions. If the AHB master's security permissions are not lower than the slave's security permissions, the slave's security status authentication passes; otherwise, the slave's security status authentication fails.

[0034] The slave's clock / reset status authentication module is used to determine whether the slave currently accessed by the AHB master device is in the clock-off or reset state. If the slave is neither in the clock-off state nor in the reset state, the slave's clock / reset status authentication passes.

[0035] In the above technical solution, the security authentication and anti-hangup of the AHB master device are achieved through some security authentication logic of the slave's address range authentication module and the slave's security status authentication module, as well as the bus anti-hangup logic of the slave's clock / reset status authentication module when the slave is turned off or in an inaccessible state such as reset. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 AHB bus structure diagram based on the AHB protocol;

[0038] Figure 2 A flowchart of a data transmission method for an AHB bus provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of an AHB master device space mapping table provided in an embodiment of the present application;

[0040] Figure 4 A functional module diagram of an AHB bus device provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of the working process of an AHB bus device provided in an embodiment of the present application.

[0042] Icons: 1-AHB bus master device interface, 2-access authentication unit, 3-authentication error feedback module. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0044] Considering the security requirements and chip robustness requirements in SOC chip design, some additional security authentication logic and bus anti-hang logic are usually added in addition to the AHB bus when the slave is turned off or in an inaccessible state such as reset. To this end, the existing technology adds corresponding logic control according to the specific characteristics of each slave, such as Figure 1 As shown in the figure, if security authentication and bus hang prevention are required for data transmission from slave 0, and security authentication is required for data transmission from slave 1, then security authentication and bus hang prevention are integrated for slave 0, and security authentication is integrated for slave 1. However, the implementation of security authentication and bus hang prevention modules is relatively complex, resulting in additional power and area consumption. Furthermore, integrating these two components separately based on requirements also adds additional workload.

[0045] Therefore, an AHB bus data transmission method and device according to an embodiment of the present application implements the authentication operation of the slave end in the AHB master device, and no longer separately integrates the security authentication function module in the SOC system, thereby reducing the workload during integration and avoiding additional power consumption and area consumption.

[0046] Please refer to Figure 2 , Figure 2 A flowchart of a data transmission method for an AHB bus provided in an embodiment of the present application includes:

[0047] Step 100: Each time before the AHB master device transmits data to the slave end, the AHB master device performs an authentication operation on the slave end; wherein the AHB master device pre-reconstructs the AHB master device space mapping table to perform the authentication operation on the slave end based on the information in the AHB master device space mapping table;

[0048] Step 200: If the authentication is successful, the AHB master device transmits data to the slave end.

[0049] In the embodiment of the present application, by reconstructing the AHB master device space mapping table of the AHB master device and adding corresponding logic control of the authentication operation of the slave side based on the information of the AHB master device space mapping table, the authentication operation of the slave side is implemented in the AHB master device without the need for an additional separate integration of a security authentication module, thereby reducing the workload during integration and avoiding additional power consumption and area consumption.

[0050] In some optional implementations, the authentication operation performed by the AHB master device includes: authentication of the address range of the slave, authentication of the security status of the slave, and authentication of the clock / reset status of the slave.

[0051] Correspondingly, determining that the authentication is passed includes: determining that the authentication is passed when the address range authentication of the slave, the security state authentication of the slave, and the clock / reset state authentication of the slave are all passed.

[0052] In the embodiment of the present application, the authentication operation performed by the AHB master device includes authentication of the address range of the slave, authentication of the security status of the slave, and authentication of the clock / reset status of the slave. That is, the AHB master device has some security authentication logic and bus anti-hang logic when the slave is turned off or in an inaccessible state such as reset. Only when the address range authentication of the slave, the security status authentication of the slave, and the clock / reset status authentication of the slave are all passed, can it be determined that the authentication is passed.

[0053] In some optional implementations, the Slave address interval authentication includes: determining whether the access address of the AHB master device is within the address interval of the corresponding Slave; if so, the Slave address interval authentication passes; otherwise, the Slave address interval authentication fails.

[0054] In some optional implementations, the Slave's security status authentication includes: determining whether the AHB master's current access complies with the slave's security permissions. If the AHB master's security permissions are not lower than the slave's security permissions, the Slave's security status authentication passes; otherwise, the Slave's security status authentication fails. The details are shown in Table 1 below:

[0055] Table 1. Slave security status authentication

[0056]

[0057] In some optional implementations, the Slave clock / reset status authentication includes: determining whether the slave currently accessed by the AHB master device is in a clock-off or reset state; if the slave is neither in a clock-off state nor in a reset state, the Slave clock / reset status authentication passes.

[0058] In some optional implementations, the AHB master device space mapping table pre-reconstructed by the AHB master device includes: the name of each slave end, the size of each slave end space, the starting address of each slave end space range, the ending address of each slave end space range, the name / address bit width and data bit width of the AHB bus to be generated, and the range of the corresponding slave end. For example, the settings of the AHB master device space mapping table in the embodiment of the present application are as follows: Figure 3 As shown, the H / J / K columns are necessary conditions for generating the AHB bus, and the G column can be used to do some illegal information verification. The following is a detailed introduction:

[0059] Column B: This column lists the names of each slave. The name must be a continuous string of letters and underscores, that is, the string format supported by the Verilog language. There must be no spaces in the string.

[0060] Column G: The size of each slave space. The unit supports GB / MB / KB / B, which are the four commonly used space sizes.

[0061] Column H: The starting address of each slave space range, in hexadecimal format, starting with '0x' as a hexadecimal data mark.

[0062] Column J: The end address of each slave space range. The format is the same as column H. It is hexadecimal data and starts with '0x0' as the hexadecimal data mark.

[0063] Column K: The name / address bit width and data bit width of the AHB bus that needs to be generated, as well as the range of slaves included in the AHB bus.

[0064] The keyword 'ahbdec' indicates a type of AHB bus. It supports prefixes and suffixes, such as 'flash_top' for prefixes and '2' for suffixes. The brackets after the name define the address and data bit widths of the decoder. For example, this defines an AHB bus with a 28-bit address width and a 32-bit data width.

[0065] The slave range is determined by the upper and lower boundaries of the merged cell where the name is located. For example, falsh_apbdec_2 is a merged cell in Excel. The upper boundary of the merged cell is in row 03, and the lower boundary is in row 09. Therefore, the slave range included in the AHB bus is the slave pointed to by the name in column B in rows 3 to 9 of the formula.

[0066] In the embodiment of the present application, the AHB master device pre-reconstructed AHB master device space mapping table should contain the name of each slave end, the size of each slave end space, the starting address of each slave end space range, the end address of each slave end space range, the name / address bit width and data bit width of the AHB bus to be generated, and the corresponding slave end range. Therefore, based on this information, the security authentication of the slave end is implemented, specifically including: writing a script, parsing the content in the Excel table, and adding some anti-hanging information and security authentication information for various scenarios through the script input command line. The following is a detailed description:

[0067] The command line defines the Excel file path and table page name. The script finds the corresponding sheet based on the defined Excel file path and the specified table page name in Excel. If the sheet is not defined, the first sheet in the table is used by default.

[0068] The command line defines whether to support anti-hang logic. The script determines whether the final generated RTL contains anti-hang logic based on the input anti-hang enable information.

[0069] The command line defines whether security authentication logic is supported. The script determines whether the final generated RTL logic includes security authentication logic based on the input security authentication enable information.

[0070] The command line defines the AHB bus name. The script finds the corresponding AHB bus based on the input name, parses the final logical address and data bit width of the AHB bus based on the content in parentheses after the AHB bus name, and parses the range of slaves included based on the upper and lower tables of the merged cells occupied. If the AHB bus name is not defined, all AHB buses are generated by default.

[0071] Based on the upper and lower boundaries of the slave range, the script further parses the slave name of each row from column B, the starting address of the slave in column H, and the ending address of the slave in column J. Column G parses the size of the slave space in the row and verifies the correctness of the addresses in columns H and J based on this size.

[0072] The script can generate the expected security authentication logic and anti-hanging logic based on the information parsed above.

[0073] Therefore, the embodiments of the present application restructure the existing AHB bus structure, integrating logic such as security authentication and bus deadlock prevention into the AHB bus with minimal logic overhead, resulting in a compact, simple, and low-power AHB bus solution. Furthermore, the present application utilizes the existing AHB master device space mapping table in existing projects, slightly restructures the table to add information such as the name, address, and data bit width of the desired AHB bus. The table is then parsed using a scripting language to quickly and accurately generate the desired logic, significantly improving design efficiency and accuracy in large-scale SOC chip design.

[0074] In some optional implementations, the information of the AHB master device space mapping table is further verified, wherein the verification content includes: whether the difference between the end address and the start address of the slave-side space range is consistent with the corresponding space size; whether the start address of the slave-side space range is aligned with its own space size; parsing the minimum address and maximum address contained in the AHB bus, calculating the total address space size, and verifying whether the start address of the AHB bus is aligned with its own total address space range.

[0075] In the embodiment of the present application, the following are checked: first, whether the size of column G is consistent with the difference between H / J; second, whether the starting address of column H is aligned with its own space size; third, the minimum and maximum addresses contained in the AHB bus are parsed, the total address space size of the AHB bus is calculated, and at the same time, whether the starting address of the AHB bus is aligned with its own total address space range is verified.

[0076] In the embodiment of the present application, the newly added information in the reconstructed AHB master space mapping table is first verified, including at least three aspects: first, whether the difference between the end address and the start address of the slave-side space range is consistent with the corresponding space size; second, whether the start address of the slave-side space range is aligned with the size of its own space; and third, the minimum and maximum addresses contained in the AHB bus are parsed, the total address space size is calculated, and whether the start address of the AHB bus is aligned with its own total address space range. Through these verification steps, the generation of incorrect table information when reconstructing the AHB master space mapping table is avoided, thereby ensuring the correct implementation of subsequent security authentication and other operations.

[0077] Please refer to Figure 4 , Figure 4 A functional module diagram of an AHB bus device provided in an embodiment of the present application includes an AHB bus master device interface 1, an access authentication unit 2 and an authentication error feedback module 3.

[0078] The AHB bus master interface 1 is used to transmit data to a slave. An access authentication unit 2 is used to perform slave authentication before each data transmission from the AHB master to the slave. The AHB master pre-reconstructs the AHB master space mapping table to perform slave authentication based on the information in the space mapping table. An authentication error feedback module 3 is used to provide a response to the slave if authentication fails.

[0079] In the embodiment of the present application, the AHB bus master interface 1 is used to transmit data to the slave end. The access authentication unit 2 reconstructs the AHB master space mapping table of the AHB master device and adds corresponding information based on the AHB master space mapping table to implement the logic control of the slave end authentication operation. This enables the slave end authentication operation to be performed on the AHB master device. If the authentication fails, the authentication error feedback module 3 feeds back a response to the slave end. Therefore, the AHB bus device of the embodiment of the present application does not need to separately integrate a security authentication module, which reduces the workload during integration and avoids additional power consumption and area consumption.

[0080] In some optional implementations, the access authentication unit 2 includes:

[0081] Among them, the Slave address interval authentication module is used to determine whether the access address of the AHB master device is within the address interval of the corresponding Slave. If so, the Slave address interval authentication passes; otherwise, the Slave address interval authentication fails. The Slave security status authentication module is used to determine whether the current access of the AHB master device complies with the slave's security authority. If the security authority of the AHB master device is not lower than the security authority of the slave, the Slave security status authentication passes; otherwise, the Slave security status authentication fails. The Slave clock / reset status authentication module is used to determine whether the slave currently accessed by the AHB master device is in the clock-off or reset state. If the slave is neither in the clock-off state nor in the reset state, the Slave clock / reset status authentication passes.

[0082] In the embodiment of the present application, the security authentication and anti-hanging of the AHB master device are achieved through some security authentication logic of the slave's address range authentication module and the slave's security status authentication module, as well as the bus anti-hanging logic of the slave's clock / reset status authentication module when the slave is turned off or in an inaccessible state such as reset.

[0083] In some optional real-time modes, the AHB bus device also includes a multiplexer, a multiplexer, etc., wherein the function of the multiplexer module is to distribute the forward control signal of the AHB master device to the hit slave end according to the selection signal output by the access authentication unit, and the function of the multiplexer module is to output the reverse return signal of the hit slave end to the AHB master device according to the selection signal output by the access authentication unit.

[0084] Please refer to Figure 5 , Figure 5 A schematic diagram of the workflow of an AHB bus device provided in an embodiment of the present application. Before the AHB master device transmits data to the Slave end, the AHB master device implements the authentication operation of the Slave end. First, the Slave's address interval authentication module is used to determine whether the Slave's address interval authentication passes. If it passes, the Slave's security status authentication module is used to determine whether the Slave's security status authentication passes. If it still passes, the Slave's clock / reset status authentication module is used to determine whether the Slave's clock / reset status authentication passes. If both pass, the AHB master device transmits data to the Slave end. If one step fails, the authentication misalignment feedback module is used to feedback a response to the Slave end.

[0085] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0086] In addition, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0087] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0088] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0089] The above description is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. For those skilled in the art, various modifications and variations of the present application are possible. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A data transmission method of an AHB bus, characterized in that: include: Each time an AHB master device transmits data to a slave end, the AHB master device performs an authentication operation on the slave end. The AHB master device pre-reconstructs a space mapping table of the AHB master device to perform the authentication operation on the slave end using information in the space mapping table. Performing the authentication operation on the slave end using information in the space mapping table includes: writing a script to parse the contents of the space mapping table, inputting command lines in the script to add anti-hanging information and security authentication information for various scenarios, and generating expected security authentication logic and anti-hanging logic to perform the authentication operation on the slave end. If the authentication is successful, the AHB master device transmits data to the Slave end; Among them, the authentication operation performed by the AHB master device includes: authentication of the slave's address range, authentication of the slave's security status, and authentication of the slave's clock / reset status; Determining that the authentication is passed includes: determining that the authentication is passed when the address range authentication of the slave, the security state authentication of the slave, and the clock / reset state authentication of the slave are all passed; The space mapping table pre-reconstructed by the AHB master device includes: the name of each slave end, the size of each slave end space, the starting address of each slave end space range, the end address of each slave end space range, the name of the AHB bus to be generated, the address bit width of the AHB bus to be generated, the data bit width of the AHB bus to be generated, and the range of the corresponding slave end; It also includes verification of the information in the spatial mapping table, wherein the verification content includes: Check whether the difference between the end address and the start address of the slave end space range is consistent with the size of the corresponding space; Whether the starting address of the slave's space range is aligned with its own space size; Parse the minimum and maximum addresses contained in the AHB bus, calculate the total address space size, and verify whether the starting address of the AHB bus is aligned with its own total address space range.

2. The method according to claim 1, wherein in, The Slave address range authentication includes: Determine whether the access address of the AHB master device is within the address range of the corresponding Slave. If so, the Slave address range authentication passes; otherwise, the Slave address range authentication fails.

3. The method according to claim 1, wherein in, The Slave security status authentication includes: Determine whether the current access of the AHB master device meets the security permissions of the slave. If the security permissions of the AHB master device are not lower than the security permissions of the slave, the security status authentication of the slave passes; otherwise, the security status authentication of the slave fails.

4. The method according to claim 1, wherein in, The clock / reset state authentication of the slave includes: Determine whether the slave currently accessed by the AHB master device is in the clock-off or reset state. If the slave is neither in the clock-off state nor in the reset state, the clock / reset state authentication of the slave passes.

5. An AHB bus device, characterized in that: include: AHB bus master device interface, used to transmit data to the Slave end; An access authentication unit is configured to implement a slave authentication operation before each AHB master device transmits data to a slave device. The AHB master device pre-reconstructs a space mapping table of the AHB master device to implement the slave authentication operation using information in the space mapping table. Implementing the slave authentication operation using information in the space mapping table includes: writing a script to parse the contents of the space mapping table, inputting command lines in the script to add anti-hanging information and security authentication information for various scenarios, and generating the expected security authentication logic and anti-hanging logic to implement the slave authentication operation. If the authentication is successful, the AHB master device transmits data to the Slave end; Among them, the authentication operation performed by the AHB master device includes: authentication of the slave's address range, authentication of the slave's security status, and authentication of the slave's clock / reset status; Determining that the authentication is passed includes: determining that the authentication is passed when the address range authentication of the slave, the security state authentication of the slave, and the clock / reset state authentication of the slave are all passed; The space mapping table pre-reconstructed by the AHB master device includes: the name of each slave end, the size of each slave end space, the starting address of each slave end space range, the end address of each slave end space range, the name of the AHB bus to be generated, the address bit width of the AHB bus to be generated, the data bit width of the AHB bus to be generated, and the range of the corresponding slave end; It also includes verification of the information in the spatial mapping table, wherein the verification content includes: Check whether the difference between the end address and the start address of the slave end space range is consistent with the size of the corresponding space; Whether the starting address of the slave's space range is aligned with its own space size; Parse the minimum and maximum addresses contained in the AHB bus, calculate the total address space size, and verify whether the starting address of the AHB bus is aligned with its own total address space range; The authentication error feedback module is used to feedback a response to the Slave end when the authentication fails.

6. The device according to claim 5, characterized in that The access authentication unit includes: The slave address interval authentication module is used to determine whether the access address of the AHB master device is within the corresponding slave address interval. If so, the slave address interval authentication passes; otherwise, the slave address interval authentication fails. The Slave's security status authentication module is used to determine whether the current access of the AHB master device meets the Slave's security permissions. If the AHB master's security permissions are not lower than the Slave's security permissions, the Slave's security status authentication passes; otherwise, the Slave's security status authentication fails. The slave's clock / reset status authentication module is used to determine whether the slave currently accessed by the AHB master device is in the clock-off or reset state. If the slave is neither in the clock-off state nor in the reset state, the slave's clock / reset status authentication passes.

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