Method for reading, writing and copying between memory array blocks, and memory chip

Abstract

A method for reading page data from a memory is disclosed. The method includes enabling a bit line sense amplifier between a first memory block and a second memory block adjacent to the first memory block to latch signals / data represented in voltage form loaded to a plurality of bit lines of the memory array, so that the plurality of latched data is propagated to a plurality of bit lines in the second memory block. Voltage signals are sequentially propagated from one memory block to a subsequent adjacent memory block in this manner until a target memory block location is reached. Data can also be written into the memory chip in this manner by sequentially propagating voltage signals from one memory block to another adjacent memory block until a target memory block location is reached, and finally activating a word line at the target location to write data into a memory cell at the target location.

Description

Technical Field

[0001] The present invention relates to memory management, and more particularly to a page data copy method utilizing low power and wide data access and a bit line sense amplifier structure between memory blocks for enhancing the prefetch function in a memory module. Background Art

[0002] Maximizing high-bandwidth data access is a key design consideration for memory devices like dynamic random access memory (DRAM). However, existing data access methods can present challenges. For example, a trade-off may need to be made between the number of prefetches and the size of the memory bank. Furthermore, conventional cell array architectures in DRAM chips may have reached a limit on the number of prefetches that can be achieved without significantly increasing the memory cell array area. Therefore, a new data access architecture and method are needed to address this issue. Summary of the Invention

[0003] An embodiment of the present invention provides a method for reading page data of a memory, wherein the memory includes multiple memory banks, each memory bank includes multiple memory blocks, each memory block includes multiple memory cells coupled via word lines, each memory cell is coupled to different bit lines, and the different bit lines are substantially perpendicular to the word lines. Each bit line is coupled to or selectively coupled to a bit line in an adjacent memory block via a bit line sense amplifier (whose main circuit part is the same as a latch). The method includes activating a word line in a first memory block of the memory bank to load multiple data present in multiple memory cells of the first memory block into multiple bit lines of the first memory block in the form of a first voltage signal, using multiple bit lines between the first memory block and the second memory block. Bit line sense amplifiers are used to latch the data loaded into the bit lines of the first portion, so that the data are propagated to the bit lines of the second portion in a second voltage signal pattern. The second memory block is adjacent to the first memory block. Bit line sense amplifiers are used between the second memory block and a third memory block to latch the data propagated into the bit lines of the second memory block, so that the data are propagated to the bit lines of the third portion in a third voltage signal pattern. The third memory block (different from the first memory block) is adjacent to the second memory block. The previous voltage signals are sequentially propagated from one memory block to a subsequent adjacent memory block until the bit lines at the end of the memory bank are reached.

[0004] Embodiments of the present application provide a memory page data writing method. The memory includes a plurality of memory banks, each of which includes a plurality of memory blocks, each of which includes a plurality of memory cells coupled by word lines, each of which is coupled to a different bit line, which is substantially perpendicular to the word line. Each bit line is coupled to or selectively coupled to a bit line in an adjacent portion by a bit line sense amplifier. The method includes writing a plurality of data to a plurality of bit lines in a first voltage signal pattern, latching the data written to the bit lines using a plurality of bit line sense amplifiers between a first memory block and a second memory block, to cause the data to propagate to a plurality of bit lines in the second memory block in a plurality of second voltage patterns, the second memory block being adjacent to the first memory block, latching the data propagated to the bit lines in the second memory block using a plurality of bit line sense amplifiers between the second memory block and a third memory block, to cause the plurality of data to propagate to a plurality of bit lines in the third memory block in a plurality of third voltage patterns, the third memory block being different from the first memory block and adjacent to the second memory block, continuing to sequentially propagate a plurality of previous voltage signals from a memory block to a subsequent adjacent memory block until a plurality of bit lines of a target memory block is reached, and after reaching the target memory block, activating a word line included in a memory bank portion of the target memory block to write the plurality of data propagated to the target memory block to a plurality of memory cells of the target memory block in a voltage pattern.

[0005] Embodiments of the present application provide a memory chip. The memory chip includes a plurality of memory banks, each of which includes a plurality of memory blocks, each of which includes a plurality of memory cells having a 1T1C architecture coupled by word lines, a group of memory cells being coupled to a first bit line, the first bit line being coupled to a first bit line sense amplifier outside each memory cell, another group of memory cells in the memory block being coupled to a second bit line, the second bit line being coupled to a second bit line sense amplifier outside each memory cell, the first bit line sense amplifier being coupled to a first bit line or a second bit line of memory cells of a first adjacent memory block, the second bit line sense amplifier being coupled to a first bit line or a second bit line of memory cells of a second adjacent memory block, the second adjacent memory block being different from the first adjacent memory block and located on another adjacent side.

[0006] Embodiments of the present application provide another memory chip. The memory chip includes a plurality of memory banks, each of which includes a plurality of memory blocks, each of which includes a plurality of memory cells having a 2T2C architecture coupled by word lines, each of which is coupled to a pair of bit lines, which are combined or shorted by an electrical link to become a bit line, a first bit line sense amplifier being coupled to a bit line of memory cells of a first adjacent memory block, a second bit line sense amplifier being coupled to a bit line of memory cells of a second adjacent memory block, the second adjacent memory block being different from the first adjacent memory block and located on another adjacent side.

[0007] An embodiment of the present invention provides another memory chip, comprising a plurality of memory blocks and a latch module. Each memory block includes a plurality of memory cells, which are coupled to word lines, and each memory cell is respectively coupled to a different bit line substantially perpendicular to the word line. The latch module is respectively coupled between each bit line in the memory portion and the corresponding bit line in the adjacent memory portion. The latch module includes four transistors, a first bit line in the memory block, a second bit line in the memory portion, and a bit line sense amplifier. Each transistor has a first end, a second end, and a control end. The first bit line in the memory block is connected in series with the first end of the first transistor, the second end of the first transistor, the first node, the first end of the second transistor, the second end of the second transistor, and the first bit line in the adjacent memory block. The second bit line in the memory block is connected in series with the first end of the third transistor, the second end of the third transistor, the second node, the first end of the fourth transistor, the second end of the fourth transistor, and the second bit line in the adjacent memory block. The bit line sense amplifier is coupled to the first node and the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 4 is a schematic diagram of an apparatus for enhancing data access in a memory module according to an embodiment of the present invention. Figure 2 A schematic diagram showing an alternate arrangement of multiple memory blocks and multiple bit line sense amplifiers (BLSA) according to an embodiment of the present invention.

[0009] Figure 3 for Figure 1 Schematic diagram of the 1T1C memory unit in the memory module.

[0010] Figure 4 for Figure 1 Schematic diagram of the bit line sense amplifier in the memory module.

[0011] Figure 5A and 5B The embodiment of the present invention shows a method for copying page data between memory blocks (inter-sectional).

[0012] Figure 6A To implement data replication between memory blocks in a 1T1C memory cell and an open bit line array architecture, Figure 6B The present invention is an embodiment of data replication between memory blocks in a 2T2C memory cell array architecture.

[0013] Figure 7A Shows data replication in 1T1C memory cells and open bit line array architecture. Figure 7B Shows another example of data replication in a 1T1C memory cell and open bitline array architecture.

[0014] Figure 8 The operation embodiments show data replication in the open bit line array using inter-sectional movement of page data.

[0015] Figure 9 The schematic diagram shows applying array data access mode to peripheral devices.

[0016] Wherein, the reference signs are explained as follows:

[0017] 100: memory module

[0018] 101: memory bank

[0019] 102: semiconductor chip

[0020] 110: word line decoder

[0021] 120: memory cell array

[0022] 130: page buffer

[0023] 150: peripheral circuit

[0024] 152: access circuit

[0025] 1-4: page data replication

[0026] 2T2C: two transistors and two capacitors

[0027] A, P, Z: data

[0028] BL, BL(1)-BL(N), BL_0-BL_4, BLF: bit line

[0029] BLSA, BLSA_0-BLSA_3, BLSA0-BLSA3: bit line sense amplifier

[0030] CA: memory

[0031] Cap: capacitor

[0032] L1, L2: electrical link

[0033] SEN, bit line sense amplifier (BLSA) enable driving signal

[0034] tRCD: row address to column address input delay period

[0035] WL, WL(1)-WL(M): word line DETAILED DESCRIPTION

[0036] Figure 1 FIG2 is a schematic diagram of an apparatus for enhancing data access (e.g., read / write / move) in a memory module 100 (e.g., a DRAM) according to an embodiment of the present invention. The apparatus may include at least a portion (e.g., a portion or all) of the memory module 100. For example, the apparatus may include a portion of the memory architecture of the memory module 100. In another embodiment, the apparatus may include a combination of the portion of the memory architecture and associated control mechanisms. In another embodiment, the apparatus may include the entire memory module 100.

[0037] like Figure 1 As shown, the memory module 100 may include a memory bank 101 and a semiconductor chip 102. The memory bank 101 may include a word line decoder 110 and a memory cell array 120. The memory cell array 120 includes a plurality of memory cells, for example, (M*N) memory cells, where M and N may be represented by positive integers. The plurality of memory cells are respectively coupled to a plurality of bit lines and a plurality of word lines of the memory cell array 120, for example, N bit lines {BL(1), BL(2), ..., BL(N)} and M word lines {WL(1), WL(2), ..., WL(M)} coupled to the (M*N) memory cells, but the present invention is not limited thereto. In some embodiments, in addition to the word line drivers, the word line decoder 110 may be at least partially implemented in the semiconductor chip 102. For example, a word line decoder pre-stage circuit of the word line decoder 110 may be implemented on the semiconductor chip 102 , and a word line decoder final stage circuit (which may include a word line driver) of the word line decoder 110 may be implemented on the memory bank 101 .

[0038] The memory bank 101 may further include a plurality of bit-line sense amplifiers (BLSAs) and a plurality of main data lines. The BLSAs are each coupled to the memory cell array 120 via a plurality of bit lines. For example, the page buffer 130 may include N BLSAs, and the plurality of main data lines are coupled to the N BLSAs of the page buffer 130. The main data lines may serve as an off-chip data interface for the memory bank 101. For example, the semiconductor chip 102 may be electrically connected to the memory bank 101 via direct face-to-face attachment, but the present invention is not limited thereto. Furthermore, the semiconductor chip 102 may include access-related peripheral circuits 150, and the access-related peripheral circuits 150 may include access circuits 152. For example, the semiconductor chip 102 may include a plurality of secondary amplifiers within the access circuits 152.

[0039] The memory cell array 120 can store data, and the memory module 100 can be installed in a host system. Examples of the host system may include a multi-function mobile phone, a tablet computer, and a personal computer such as a desktop computer and a laptop computer. A plurality of bit lines, such as N bit lines {BL(1), BL(2), ..., BL(N)} and a plurality of word lines, such as M word lines {WL(1), WL(2), ..., WL(M)} can access and control the memory cell array 120. According to this embodiment, a plurality of BLSAs can respectively sense a plurality of bit line signals read from (M*N) memory cells and convert the bit line signals into a plurality of amplified signals.

[0040] Some implementation details regarding access control for the memory cell array 120 are described below. In some embodiments, the word line decoder 110 may decode an access control signal (e.g., a row select signal) to determine whether to select (e.g., activate) a row of memory cells corresponding to a word line WL(m) (where the index value "m" may represent an integer within the interval [1, M]). Word line decoder 110 may provide a row decoder function for access control of the memory cell array 120.

[0041] about Figure 1 In the architecture shown in FIG, the device may include a memory bank 101 located in a memory module 100, but the present invention is not limited thereto. For example, the device may further include a semiconductor chip 102. According to some embodiments, in addition to the memory bank 101, the memory module 100 may include at least a portion (e.g., a portion or all) of the semiconductor chip 102. For example, one or more other circuits having any external functions of the memory module 100 may be integrated into the semiconductor chip 102.

[0042] In some embodiments, Figure 1 The structure shown in FIG is variable. For example, the memory cell array 120 may be divided into a plurality of memory cell array (CA) blocks according to predetermined bit line lengths to improve access speed, and a plurality of BLSAs (e.g., N BLSAs in the page buffer 130) may be divided into a plurality of BLSA portions corresponding to the cell array portions for performing related sensing operations.

[0043] Figure 2 A schematic diagram showing an alternate arrangement of a plurality of memory blocks and a plurality of bit line amplifier (BLSA) blocks according to an embodiment of the present invention. Figure 2 The memory blocks and the bit line amplifier blocks of the structure in the embodiment of the present invention are shown. In addition, any two memory blocks can be the same or similar to each other, and any two bit line amplifier blocks can be the same or similar to each other.

[0044] Figure 3 show Figure 1The illustrated memory module 100 includes a 1T1C (one transistor and one capacitor) memory cell (e.g., in the form of a DRAM cell). The memory cell may be an embodiment of any memory cell (e.g., each memory cell) among the plurality of memory cells in the memory cell array 120. Figure 3 As shown, the memory cell may include a switch and a capacitor Cap. The switch may be, for example, a metal oxide semiconductor field effect transistor (MOSFET). The memory cell may be coupled to a word line (e.g., word line WL(m)) among a plurality of word lines and a bit line (e.g., bit line BL(n)) among a plurality of bit lines. The capacitor Cap may store memory charge, and different states of the charge may represent one bit of information (e.g., 0 or 1), but the present invention is not limited thereto. In some embodiments, a 2T2C (two transistors and two capacitors) memory cell may also be used to increase reliability. Those skilled in the art are aware of the general structure and function of a 2T2C memory cell.

[0045] Figure 4 for Figure 1 Schematic diagram of the BLSA of the memory module 100. Figure 4 As shown, the BLSA can be a bit line sense amplifier and includes two cross-connected inverters. Specifically, the two cross-connected inverters can each be coupled to two bit lines (labeled "BL_0" and "BL_1") of the plurality of bit lines. The two bit lines can be coupled to different memory cells in different memory blocks (e.g., two memory blocks, each adjacent to a bit line amplifier block) and can be used in embodiments of any of the bit pairs. Each of the inverters can be driven by two drive signals SENf and SEN from a set of drive signals.

[0046] The bit line amplifier can operate according to two drive signals SENf and SEN to obtain respective bit information (voltages). Memory module 100 (e.g., memory bank 101) can select one of a plurality of memory cells according to an access control signal from word line decoder 110. For example, during the first phase of a read phase, the bit line amplifier can obtain the bit information of the memory cell via BL_0. For example, the bit information of the first memory cell can be obtained by amplifying a signal carrying the bit information of the first memory cell.

[0047] The bitline amplifiers are controlled by drive signals SENf and SEN. Because the application is focused on moving data one page at a time, where a page is defined as the data contained in all memory cells activated by the same wordline, no row select or data lines are required, saving cost, chip area, and circuit complexity. By sequentially activating adjacent BLSA sections, data present in the first BLSA is copied to the next BLSA in sequence. In this embodiment, a data page can be propagated from a source location to a destination location in any direction perpendicular to the wordlines.

[0048] For example, by enabling the BLSA between a first memory block and a second memory block adjacent to the first memory block, multiple voltages applied to multiple bit lines in the first memory block are latched, allowing the multiple latched voltages to propagate to multiple bit lines in the second memory block. Multiple bit line sense amplifiers between the second memory block and a third memory block are used to latch the multiple voltages propagated to the bit lines in the second memory block, allowing the multiple latched voltages to propagate to multiple bit lines in a third memory block (which is different from the first memory block and adjacent to the second memory block). Using the sequential BLSA activation method described in this embodiment, voltages can be propagated from one memory block to subsequent adjacent memory blocks until they reach the target location.

[0049] Therefore, a read operation activates the word line at the source location, applying multiple voltages from the memory cells at the source location to the corresponding bit lines, which are then latched by activating adjacent BLSAs. Subsequently, whether the target location is the data access circuit 152 or another memory block (when moving data), the voltages can sequentially propagate from one memory block to another adjacent memory block until reaching the target location.

[0050] Figure 5A and 5B The embodiment of the present invention shows a method for copying page data between memory blocks (inter-sectional). Figure 5A This is a functional diagram of a portion of the memory bank in the embodiment. The memory cell array blocks are represented by dotted lines and are numbered 0-4. Each memory cell array block includes a word line. Figure 5A Only the word line WL of one memory cell array block is shown. BLSA portions BLSA_0-BLSA_3 are provided between each memory cell array block, and each BLSA is connected to an adjacent memory cell array block via a bit line, shown as BL_0-BL_3.

[0051] like Figure 5BAs shown, after BLSA_0 is enabled (i.e., SENf–0v, SEN–VDD), the page data is read from the memory cell of the enabled wordline and loaded into the bitline BL_0. At the same time, the page data is copied from the bitline BL_0 of the memory block 0 to the bitline BL_1 of the memory block 1 (in Figure 5B Then, after BLSA_1 is enabled, the page data is copied from the bit line BL_1 of the memory block 1 to the bit line BL_2 of the memory block 2 (in Figure 5B Then, after BLSA_2 is enabled, the page data is copied from the bit line BL_2 of the memory block 2 to the bit line BL_3 of the memory block 3 (in Figure 5B Finally, after BLSA_3 is enabled, the page data is copied from the bit line BL_3 of the memory block 3 to the bit line BL_4 of the memory block 4 (in Figure 5B In this way, the page data of memory block 0 is propagated to memory block 4 in sequence.

[0052] Figure 6A In the conventional open bit line array shown, since the open bit line structure cannot always copy data, the disclosed data copy method cannot be continuously transferred beyond the two memory blocks (for example, from Figure 6A To solve this problem, Figure 6B A structural modification of an open bitline array is shown, forming an electrical link connecting the first bitline and the second bitline in each memory cell. For example, electrical link L1 is formed between bitline BL and bitline BLF in memory block 1, and electrical link L2 is formed between bitline BL and bitline BLF in memory block 2. Since data is always present on bitline BLF or BL, Figure 6B The modification ensures that no matter whether the data exists on the bit line BLF or BL, the subsequent BLSA in the memory can continue to use the data of the previous BLSA. In memory block 2, the subsequent BLSA of memory block 2 can continue to use the data of the previous BLSA of memory block 2 through the electrical link L2, thus solving the problem of Figure 6A The problem in .

[0053] Figure 7A Shows the copying of data in the open bit line array of the previous memory section, Figure 7B Shows data replication in an open bit line array of an embodiment memory portion. Figure 6A Similar to the previous embodiment, in the disclosed conventional open bit line array, since the open bit line structure cannot always copy data, the disclosed data copy method cannot be continuously transferred beyond the two memory blocks (for example, from Figure 7ATo solve this problem, Figure 7B Another possible structural modification of the open bitline array is shown. Figure 7B As shown, each BLSA is connected to a plurality of transistors ( Figure 7B In the embodiment, there are four transistors), each transistor having a first terminal, a second terminal and a control terminal. Figure 7B The first bit line in the display memory portion is sequentially connected in series to the first end of the first transistor, the second end of the first transistor, the first node, the first end of the second transistor, the second end of the second transistor, and the first bit line in the adjacent memory portion. For example, the bit line BLF in memory block 2 is sequentially connected in series to the first end of the first transistor T1, the second end of the first transistor T1, the first node N1, the first end of the second transistor T2, the second end of the second transistor T2, and the bit line BLF in memory block 3. Figure 7B Also shown is a second bit line in a memory section, sequentially connected in series to the first end of a third transistor, the second end of the third transistor, the second node, the first end of a fourth transistor, the second end of the fourth transistor, and the second bit line in an adjacent memory section. BLSA is coupled to the first and second nodes. For example, bit line BL in memory block 2 is connected in series to the first end of a third transistor T3, the second end of the third transistor T3, the second node N2, the first end of a fourth transistor T4, the second end of the fourth transistor T4, and bit line BL in memory block 3. BLSA2 is coupled to the first node N1 and the second node N2. Each of the four transistors can be controlled to electrically connect BLSA to bit lines BLF and BL in adjacent memory blocks, ensuring propagation of the desired data voltage.

[0054] Figure 8 The embodiment of the present invention shows an operation embodiment of data replication in the open bit line array, so that page data can be moved between memory blocks (inter-sectional). Figure 8 In , time increases from the top to the bottom of the graph, and data is replicated from left to right as time passes. Figure 8 In FIG, before the data copy operation begins, memory blocks 0 to 7 are precharged (marked as "P"). After the word line of memory block 2 is activated, data is read and amplified from the memory cells of memory block 2 and the data (marked as "A" in the figure) is latched in the appropriate BLSA. Figure 8 As shown, the word line can then be turned off. When the subsequent BLSA is activated, data "A" will be copied from the current BLSA to the subsequent BLSA. The BLSA activation process continues, propagating data "A" from one BLSA to the next BLSA until it reaches the target location.

[0055] Some benefits of this page duplication method include:

[0056] The maximum data prefetch provided by the DRAM array can be collected;

[0057] The data line sense amplifier can be omitted to save power consumption of unnecessary column select decoders.

[0058] Power can be saved due to the inherent half-voltage transition of the bit lines BL and BLF (because they are precharged to half voltage before each data read); and

[0059] Comply with the BL-before-WL page data writing method to achieve very fast and low-power data writing.

[0060] Figure 9 The application of array data access method in chip peripheral devices is described to achieve long-distance, wide bus and high-performance data movement.

[0061] Apart from Figure 9 Displays the voltage value propagating on the BLSA, Figure 9 In symbols Figure 8 Since the BLSA amplifies the read value and converts it into a digital signal, and since the circuit precharges the BLSA to 1 / 2VDD, the maximum amplitude of the propagated voltage is 1 / 2VDD.

[0062] Compared to CMOS operations that copy / move data to the edge of the chip using a VDD voltage swing, the disclosed function has the advantage of low power consumption. Compared to conventional small voltage swing interfaces, the analog fully differential amplifier receiver for small voltage swing signals in the embodiments of the present invention does not consume the DC current that a conventional analog fully differential amplifier receiver would consume. In addition, the embodiments of the present invention do not require the reference voltage (Vref or 1 / 2V) required by the fully differential amplifier. IF ).

[0063] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for reading page data from a memory, characterized in that: The memory includes a plurality of memory banks, each memory bank includes a plurality of memory blocks, each memory block includes a plurality of memory cells coupled via word lines, each memory cell is coupled to a different bit line, the different bit lines are substantially perpendicular to the word line, each bit line is coupled to or selectively coupled to a bit line in an adjacent memory block via a bit line sense amplifier, and the method includes: activating a word line in a first memory block of a memory bank to load a plurality of data in a plurality of memory cells of the first memory block to a plurality of bit lines of the first memory block at a first voltage type; Using a plurality of bit line sense amplifiers between the first memory block and a second memory block to amplify and latch a plurality of first voltages applied to the bit lines of a first portion, so that the plurality of data are propagated to a plurality of bit lines in a second memory block adjacent to the first memory block in a plurality of second voltage patterns; Latching a plurality of second voltages propagated to the bit lines in a second portion using a plurality of bit line sense amplifiers between the second memory block and a third memory block so that the plurality of data are propagated to the plurality of bit lines in the third memory block in the form of a plurality of third voltages, wherein the third memory block is different from the first memory block and is adjacent to the second memory block at another end; Continue to propagate the plurality of previous data in the voltage form from the memory block to the subsequent adjacent memory block in sequence until reaching the plurality of bit lines at the end of the memory bank; and The plurality of data sequentially propagated are read from the bit lines at the end of the memory bank.

2. The method according to claim 1, wherein Also includes: Each bit line is precharged before activating the word line in the first memory block of the memory.

3. The method according to claim 1, wherein Also includes: The bit line sense amplifiers invert the previous voltages between each memory block before propagating the previous voltage signals to the next memory block.

4. A method for writing page data into a memory, characterized in that: The memory includes a plurality of memory banks, each memory bank includes a plurality of memory blocks, each memory block includes a plurality of memory cells coupled via word lines, each memory cell is coupled to a different bit line, the different bit lines are substantially perpendicular to the word line, each bit line is coupled to or selectively coupled to a bit line in an adjacent memory block via a bit line sense amplifier, and the method includes: Writing a plurality of data to a plurality of bit lines respectively at a first voltage type; amplifying and latching a plurality of first voltage signals written to the bit lines using a plurality of bit line sense amplifiers between the first memory block and a second memory block adjacent to the first memory block, so as to propagate a plurality of second voltages to a plurality of bit lines in the second memory block; amplifying and latching a plurality of second voltage signals propagated to the bit lines in the second memory block using a plurality of bit line sense amplifiers between the second memory block and a third memory block, so as to propagate a plurality of third voltage signals to a plurality of bit lines in the third memory block, the third memory block being different from the first memory block and adjacent to the second memory block at another end; Continue to propagate multiple previous voltage signals from the memory block to the subsequent adjacent memory blocks in sequence, until a plurality of bit lines of the target memory block are reached; and After reaching the target memory block, a word line in the memory bank portion including the target portion is activated to write the target voltage signals propagated to the target memory block into the memory cells of the target memory block.

5. The method according to claim 4, wherein Also includes: The bit line sense amplifiers invert the previous voltage signals between each memory block before propagating the previous voltages to the next memory block.

6. The method according to claim 1 or 4, wherein: The method also includes sequentially activating the bit line sense amplifiers between the memory blocks.

7. A memory chip, characterized in that: include: a plurality of memory banks, each memory bank including a plurality of memory blocks, each memory block including a plurality of memory cells having a 1T1C (one transistor and one capacitor) or 2T2C (two transistors and two capacitors) architecture coupled via word lines, each memory cell being coupled to a first bit line or a second bit line of a group of bit lines; a first bit line sense amplifier disposed outside each memory cell and coupled to the first bit line of the group of bit lines and the first bit line or the second bit line of the group of bit lines of the first adjacent memory block, the first bit line sense amplifier being configured to amplify and latch a first voltage applied to the first bit line or the second bit line of the group of bit lines of the first adjacent memory block to propagate a second voltage to the first bit line of the group of bit lines; a second bit line sense amplifier, coupled to the outside of each memory cell and coupled to the second bit line of the group of bit lines and the first bit line or the second bit line of the group of bit lines of the second adjacent memory block, the second bit line sense amplifier being configured to amplify and latch a second voltage applied to the second bit line of the group of bit lines to propagate a third voltage to the first bit line or the second bit line of the group of bit lines of the second adjacent memory block; a transistor circuit for selectively connecting the first bit line and the second bit line of the set of bit lines of the first adjacent memory block to the first bit line sense amplifier; and Another transistor circuit is used for selectively connecting the first bit line and the second bit line in the group of bit lines of the second adjacent memory block to the second bit line sense amplifier.

8. The memory chip according to claim 7, wherein: Each bit line sense amplifier includes cross-connected inverters.

9. The memory chip according to claim 7, wherein: The transistor circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor, each transistor having a first terminal, a second terminal and a control terminal; The first bit line in the memory block is sequentially connected in series to the first end of the first transistor, the second end of the first transistor, the first node, the first end of the second transistor, the second end of the second transistor, and the first bit line in the adjacent memory block; The second bit line in the memory block is serially connected to the first end of the third transistor, the second end of the third transistor, the second node, the first end of the fourth transistor, the second end of the fourth transistor, and the second bit line in the adjacent memory block in sequence; and The first bit line sense amplifier is coupled to the first node and the second node.

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