Virtual SRAM device

Abstract

The present invention provides a virtual static random access memory device, comprising a plurality of memories, an arbitrator and a controller. The memories respectively generate a plurality of self-refresh request signals. Each self-refresh request signal indicates a time interval for each corresponding memory to perform a self-refresh action. The arbitrator receives the self-refresh request signal and generates a delay synchronization flag according to the self-refresh request signal when the memory is enabled. The controller determines the access delay time of the memory under the access operation according to the delay synchronization flag.

Description

Technical Field

[0001] The present invention relates to a virtual static random access memory device, in particular to a virtual static random access memory device capable of dynamically adjusting access time delay. Background Art

[0002] In electronic devices that need to use static memory, the required static memory capacity is getting larger and larger, so a virtual static random access memory device constructed using dynamic random access memory is proposed. Especially in IoT devices, the virtual static random access memory device is a popular option.

[0003] Since the DRAM needs to perform a self-refresh operation, when the virtual SRAM device performs an access operation and the DRAM is performing a self-refresh operation, the DRAM needs to provide access data after a certain access latency time. In order to cope with this problem, a mechanism of adjustable access latency time is proposed.

[0004] However, the above-mentioned adjustable access delay time mechanism can only be applied to the architecture of a single dynamic random access memory. In order to improve the data width and storage density of the virtual static random access memory device, the virtual static random access memory device often needs to be equipped with multiple dynamic random access memories. Since the time for each dynamic random access memory to perform a self-refresh action is different, the above-mentioned adjustable access delay time mechanism cannot be applied. Therefore, the prior art sets a fixed and sufficiently long access delay time to perform access operations for a virtual static random access memory device with multiple dynamic random access memories. As a result, the access rate of the virtual static random access memory device is subject to certain limitations. Summary of the invention

[0005] The present invention is directed to a virtual static random access memory device, which can dynamically adjust the access delay time of the memory to improve the use performance.

[0006] According to an embodiment of the present invention, a virtual static random access memory device includes a plurality of memories, an arbitrator, and a controller. The memories generate a plurality of self-refresh request signals respectively. Each self-refresh request signal indicates a time interval for each corresponding memory to perform a self-refresh action. The arbitrator receives the self-refresh request signal and generates a delay synchronization flag according to the self-refresh request signal when the memory is enabled. The controller is coupled to the memory and the arbitrator. The controller determines the access delay time of the access memory under the access operation according to the delay synchronization flag.

[0007] Based on the above, the embodiment of the present invention determines whether at least one of the memories generates a collision phenomenon of self-refresh action during access operation, and dynamically adjusts the access delay time of the memory according to the determination result, thereby effectively improving the access performance of the virtual static random access memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0009] Figure 1 A schematic diagram of a virtual static random access memory device according to an embodiment of the present invention;

[0010] Figure 2A as well as Figure 2B are waveform diagrams of read actions of different implementations of a virtual static random access memory device according to an embodiment of the present invention;

[0011] Figure 2C as well as Figure 2D 1. The waveform diagrams of write actions of different implementations of the virtual static random access memory device according to the embodiment of the present invention;

[0012] Figure 3 A schematic diagram of an implementation of an arbitrator according to an embodiment of the present invention;

[0013] Figure 4 A schematic diagram of an implementation of a partial circuit of a memory according to an embodiment of the present invention;

[0014] Figure 5 FIG. 4 is a schematic diagram of another circuit implementation of a memory according to an embodiment of the present invention.

[0015] Description of Figure Numbers

[0016] 100: virtual static random access memory device;

[0017] 111~11N, 400, 500: memory;

[0018] 120: arbitrator;

[0019] 130: controller;

[0020] 300: arbitrator;

[0021] 310: Logic circuit;

[0022] 320: Latch;

[0023] 330: feedback circuit;

[0024] 410: timer;

[0025] 420: Delay device;

[0026] 510: Multitasker;

[0027] A1, A2: signal;

[0028] CK#: reverse frequency signal;

[0029] CK, CK1: frequency signal;

[0030] CS#: chip enable signal;

[0031] DQA1~DQAN, DQSA1[7:0], DQSA2[7:0]: data signal;

[0032] FF1: Flip-flop;

[0033] IV1: inverter;

[0034] LAT11, LAT12: delay time;

[0035] LSF: delayed synchronization flag;

[0036] ND1, ND2: NAND gates;

[0037] OPR: operation result;

[0038] RR1~RRN: self-refresh request signal;

[0039] RWDS, RWDS1, RWDS2: access delay indication signals;

[0040] SR1: Latch;

[0041] TPS: start time interval;

[0042] tS: start time point;

[0043] VH, VL: voltage;

[0044] WDATA1: write data. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0046] Please refer to Figure 1 , Figure 1Schematic diagram of a virtual static random access memory device according to an embodiment of the present invention. The virtual static random access memory device 100 includes memories 111-11N, an arbiter 120 and a controller 130. The memories 111-11N are dynamic random access memories. The memories 111-11N respectively generate a plurality of self-refresh request signals RR1-RRN, each of which indicates a time interval in which each corresponding memory 111-11N performs a self-refresh action. The self-refresh request signals RR1-RRN are provided to the arbiter 120. The arbiter 120 also receives a chip enable signal CS#, and the arbiter 120 generates a delayed synchronization flag LSF according to the self-refresh request signals RR1-RRN at a start time point in a start time interval according to the chip enable signal CS#. According to the chip enable signal CS# which is not enabled, the arbiter 120 can obtain the time interval in which each memory 111-11N performs a self-refresh action through the self-refresh request signals RR1-RRN during the standby time interval in which the memory 111-11N bits are enabled for access. At the time point when the chip enable signal CS# turns to enable (i.e., the start time point of the start time interval), the arbiter 120 can determine whether any of the memories 111-11N is still performing a self-refresh action according to the self-refresh request signals RR1-RRN. If the determination result is yes, an enabled delay synchronization flag LSF is generated; if the determination result is no, a disabled delay synchronization flag LSF is generated.

[0047] The arbiter 120 can transmit the delay synchronization flag LSF to the memories 111-11N, and make the memories 111-11N generate the access delay indication signal RWDS according to the delay synchronization flag LSF. Please note that the endpoints of the memories 111-11N generating the access delay indication signal RWDS are coupled to the same transmission wire, that is, the memories 111-11N generate the same access delay indication signal RWDS.

[0048] The controller 130 is coupled to the memories 111 ˜ 11N, and receives the access delay indication signal RWDS, the chip enable signal CS#, the clock signal CK, and the reverse clock signal CK# generated by the memories 111 ˜ 11N. The controller 130 also receives the data signals DQA1 ˜DQAN respectively provided by the memories 111 ˜ 11N during the access operation.

[0049] In addition, in the access operation, the controller 130 can set the access delay time according to the access delay indication signal RWDS provided by the memories 111-11N, and obtain the data signals DQA1-DQAN according to the set access delay time. The access operation in this embodiment can be a data read operation or a data write operation.

[0050] It is not difficult to know from the above description that the arbiter 120 in the embodiment of the present invention can determine whether there is a conflict between the self-refresh operation performed by the memories 111-11N and the time interval during which the memories 111-11N are enabled. The virtual static random access memory device 100 in the present embodiment can dynamically adjust the access delay time of the access operation through the access delay indication signal RWDS generated by the memories 111-11N according to the judgment result of the arbiter 120, thereby improving the working performance of the virtual static random access memory device 100.

[0051] Incidentally, the arbiter 120 can be set in the memory 111~11N, or can also be set outside the memory 111~11N, without specific restrictions. The memory 111~11N can be implemented by multiple dynamic random access memory chips respectively. In addition, the controller 130 of the embodiment of the present invention can be a processor with computing capabilities. Alternatively, the controller 130 can be designed by hardware description language (Hardware Description Language, HDL) or any other digital circuit design method known to those with ordinary knowledge in the field, and implemented as a hardware circuit by field programmable gate array (Field Programmable Gate Array, FPGA), complex programmable logic device (Complex Programmable Logic Device, CPLD) or application-specific integrated circuit (Application-specific Integrated Circuit, ASIC).

[0052] Please refer to the following Figure 2A as well as Figure 2B , Figure 2A as well as Figure 2B 1 is a waveform diagram of read operation of different implementations of the virtual static random access memory device of the embodiment of the present invention. Figure 2A In the embodiment, a virtual static random access memory device includes a first memory and a second memory. The first memory and the second memory share a chip enable signal CS#, wherein the chip enable signal CS# is a low logic level enable signal (low active). When the chip enable signal CS# is at a logic high level, multiple memories in the virtual static random access memory device are in a standby time interval.

[0053] During the standby time period, the first memory and the second memory in the virtual static random access memory device need to periodically perform a self-refresh action, and generate a plurality of self-refresh request signals respectively according to the time period during which the self-refresh action occurs.

[0054] When the chip enable signal CS# changes to a logic low level, all memories in the virtual static random access memory device are enabled and enter the start time interval TPS. At this time, the arbiter in the virtual static random access memory device can generate an access delay indication signal RWDS according to the self-refresh request signal. In detail, at the start time point tS of the start time interval TPS, if the arbiter determines that the self-refresh action of at least one of the first memory and the second memory in the virtual static random access memory device is still being executed, the arbiter can determine that the self-refresh action of the memory and its access operation may collide, and thereby enable the delay synchronization flag.

[0055] Furthermore, the first memory and the second memory can generate access delay indication signals RWDS1 and RWDS2 of logic high level respectively according to the enabled delay synchronization flag. In this embodiment, the access delay indication signals RWDS1 and RWDS2 can be transmitted to the same transmission wire and are the same signal.

[0056] On the other hand, in the start time interval TPS, the first memory can receive the data signal DQSA1[7:0] to obtain the command and address CMDADD1, and the second memory can receive the data signal DQSA2[7:0] to obtain the command and address CMDADD2. When it is determined that the data read operation is to be performed on the first memory and the second memory according to the command and address CMDADD1 and CMDADD2, the controller can set the access delay time of the first memory = delay time LAT11 + delay time LAT12 according to the access delay indication signal RWDS1 of the logic high level, and set the access delay time of the second memory = delay time LAT11 + delay time LAT12 according to the access delay indication signal RWDS2 of the logic high level. And obtain the access data RDOUT1 transmitted from the first memory and the access data RDOUT2 transmitted from the second memory after the access delay time. Among them, in the embodiment of the present invention, the controller can perform the data read operation according to a setting bit in the command and address CMDADD1 and a setting bit in the command and address CMDADD2.

[0057] In this embodiment, the delay times LAT11 and LAT12 may be the same.

[0058] Incidentally, the start-up time interval TPS ends when the chip enable signal CS# changes to a logic high level. The operation of this embodiment can be performed based on the clock signal CK and the reverse clock signal CK# which are differential signals.

[0059] exist Figure 2B In, with Figure 2AIn a different implementation, the arbiter determines at the start time point tS that neither the first memory nor the second memory has performed a self-refresh operation, and accordingly sets the delay synchronization flag to a disabled state. Under such conditions, the first memory and the second memory respectively generate access delay indication signals RWDS1 and RWDS2 of a logic low level according to the disabled delay synchronization flag. The controller can set the access delay time of the first memory and the second memory = time delay LAT11 according to the access delay indication signals RWDS1 and RWDS2 of a logic low level during the access operation. In other words, when there is no collision between the self-refresh operation of the memory and its access operation, the controller can reduce the access delay time of the first memory and the second memory.

[0060] Incidentally, in this embodiment, by setting the first memory and the second memory in the virtual static random access memory, the width of the data signal to be accessed can be expanded to N times that of a single memory, thereby improving the performance, where N is an integer greater than or equal to 2.

[0061] Please refer to the following Figure 2C as well as Figure 2D , Figure 2C as well as Figure 2D 1 is a waveform diagram of write operations of different implementations of a virtual static random access memory device according to an embodiment of the present invention.

[0062] exist Figure 2C In the embodiment, when the chip enable signal CS# changes to a logic low level, all memories in the virtual static random access memory device are enabled and enter the start time interval TPS. At this time, the arbiter in the virtual static random access memory device can generate an access delay indication signal RWDS according to the self-refresh request signal. In detail, at the start time point tS of the start time interval TPS, if the arbiter determines that the self-refresh action of any memory (such as the first memory) in the virtual static random access memory device is still being executed, the arbiter can determine that the self-refresh action of the memory and its access operation may collide, and thereby enable the delay synchronization flag.

[0063] Furthermore, the first memory can generate a logic high access delay indication signal RWDS1 according to the enabled delay synchronization flag. In this embodiment, the access delay indication signal RWDS1 can be transmitted to a transmission line, and the access delay indication signals of other memories are equal to the access delay indication signal RWDS1.

[0064] On the other hand, in the start time interval TPS, the first memory can receive the data signal DQSA1[7:0] to obtain the command and address CMDADD1. When it is determined that a data write operation is to be performed on the first memory according to the command and address CMDADD1, the controller can set the access delay time of the first memory = delay time LAT11 + delay time LAT12 according to the access delay indication signal RWDS1 of the logic high level. And perform a write operation of writing data WDATA1 to the first memory after the access delay time. Among them, in the embodiment of the present invention, the controller can perform a data write operation according to a setting bit in the command and address CMDADD1.

[0065] On the other hand, in Figure 2D In the example, at the start time point tS, the arbiter determines that the first memory and other memories have not performed a self-refresh action, and accordingly sets the delay synchronization flag to a disabled state. Under such conditions, the first memory generates a logic low level access delay indication signal RWDS1 according to the disabled delay synchronization flag. The controller can set the access delay time of the first memory = time delay LAT11 according to the logic low level access delay indication signal RWDS1 during the access operation. In other words, when the self-refresh action of the memory does not conflict with its access operation, the controller can reduce the access delay time of the first memory.

[0066] Please refer to Figure 3 , Figure 3 Schematic diagram of an implementation of an arbiter according to an embodiment of the present invention. The arbiter 300 includes a logic circuit 310, a latch 320, and a feedback circuit 330. The logic circuit 310 receives self-refresh request signals RR1-RRN respectively generated by a plurality of memories, performs a logic operation on the self-refresh request signals, and generates an operation result OPR.

[0067] In this embodiment, the self-refresh request signals RR1-RRN may be pulse signals, and are used to reflect the time interval during which the memory performs a self-refresh action. Taking the self-refresh request signal RR1 as an example, when the self-refresh request signal RR1 is pulled high to a logic high level, it indicates that the corresponding memory is performing a self-refresh action. The positive pulse length of the self-refresh request signal RR1 indicates the time length during which the self-refresh action is maintained. When the self-refresh request signal RR1 is pulled low to a logic low level, it indicates that the self-refresh action of the corresponding memory is completed.

[0068] In this embodiment, the logic circuit 310 may be an OR gate and is used to perform a logical OR operation. The logic circuit 310 generates an operation result OPR of a logic high level when at least one of the self-refresh request signals RR1-RRN is at a logic high level. That is, when the operation result OPR is at a logic high level, at least one of the multiple memories in the virtual static random access memory device is performing a self-refresh operation.

[0069] The latch 320 receives the operation result OPR, latches the operation result OPR, and provides the latched operation result OPR to generate the delayed synchronization flag LSF according to the transition time point of the chip enable signal CS#, wherein the transition time point of the chip enable signal CS# is the start time point of the start time interval when the memory is enabled.

[0070] The feedback circuit 330 receives the delayed synchronization flag LSF and the chip enable signal CS#. When the delayed synchronization flag LSF and the chip enable signal CS# are both at a logic high level, the feedback circuit 330 provides a reset signal to clear the data latched by the latch 320. In this embodiment, the feedback circuit 330 can be an AND gate or a NAND gate. The reset signal received by the latch 320 can be a high level enable or a low level enable.

[0071] Please refer to the following Figure 4 , Figure 4 Schematic diagram of the implementation of a partial circuit of a memory according to an embodiment of the present invention. In the embodiment of the present invention, the memory 400 in the virtual static random access memory device includes a timer 410 and a delay 420. The timer 410 performs a timing action according to the clock signal CK1, and after the timing action overflows, the corresponding self-refresh request signal is enabled to a logic high level. The delay 420 is used to control the length of time the self-refresh request signal RR is enabled, and is disabled (transitioned to a logic low level) after the self-refresh request signal RR is maintained at a logic high level for a preset time.

[0072] In this embodiment, the timer 410 is coupled to the flip-flop FF1. The flip-flop FF1 can generate a signal A1 equal to a logic high level according to the voltage VH after the timing action of the timer 410 overflows. The latch SR1 receives the signal A1 and the signal A2, and outputs a self-refresh request signal RR1. The signal A2 is generated by the delayer 420 by delaying the self-refresh request signal RR1 for a default time and passing through the inverter IV1. The latch SR1 can be composed of NAND gates ND1 and ND2, and is a set-reset type latch (SR-latch).

[0073] The signal A2 is further provided to a reset terminal of the flip-flop FF1 , and when the signal A2 is at a logic low level, the flip-flop FF1 can reset the signal A2 to a logic low level.

[0074] Please refer to the following Figure 5 , Figure 5 Schematic diagram of another implementation of a circuit of a memory according to an embodiment of the present invention. The memory 500 in the virtual static random access memory device includes a multiplexer 510. The multiplexer 510 receives voltages VH and VL, wherein the voltage VH can be a logic high level and the voltage VL can be a logic low level. The multiplexer 510 also receives a delay synchronization flag LSF, and selects an output voltage VH or a voltage VL according to the delay synchronization flag LSF to generate an access delay indication signal RWDS.

[0075] In the present embodiment, when the delay synchronization flag LSF is enabled (a collision between a self-refresh action and an access operation occurs), the multiplexer 510 may select a voltage VH to generate an access delay indication signal RWDS. Conversely, when the delay synchronization flag LSF is disabled (a collision between a self-refresh action and an access operation does not occur), the multiplexer 510 may select a voltage VL to generate an access delay indication signal RWDS.

[0076] In summary, the virtual static random access memory device of the present invention provides an arbitration mechanism to determine the collision status between the self-refresh actions of multiple memories in the virtual static random access memory device and the access operation of the virtual static random access memory device, and thereby dynamically adjust the access delay time. In this way, in a virtual static random access memory device with multiple memories, dynamic read latency can still be effectively implemented, and the performance of the virtual static random access memory device can be improved.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A virtual static random access memory device, characterized in that: include: A plurality of memories, each generating a plurality of self-refresh demand signals, each of the self-refresh demand signals indicating a time interval for each corresponding memory to perform a self-refresh action; An arbiter receives the plurality of self-refresh request signals and generates a delay synchronization flag according to the plurality of self-refresh request signals when the plurality of memories are enabled; as well as The controller is coupled to the multiple memories and the arbiter, and determines access delay times of accessing the multiple memories in an access operation according to the delay synchronization flag.

2. The virtual static random access memory device according to claim 1, characterized in that: During the time interval of executing the self-refresh action, each of the memories makes the corresponding self-refresh request signals be at the first logic level.

3. The virtual static random access memory device according to claim 2, wherein: The arbiter performs logic operations on the self-refresh request signals to generate operation results in a standby time interval before the start time interval, and outputs the operation results at the start time point of the start time interval when the memories are enabled to generate the delay synchronization flag.

4. The virtual static random access memory device according to claim 3, characterized in that: When the first logic level is a logic high level, the logic operation is a logic OR operation.

5. The virtual static random access memory device according to claim 3, characterized in that: The arbiter latches the operation result at the start time point to generate the delay synchronization flag.

6. The virtual static random access memory device according to claim 3, characterized in that: The arbitrator comprises: a logic circuit, receiving the plurality of self-refresh requirement signals, and performing the logic operation on the plurality of self-refresh requirement signals to generate the operation result; and The latch is coupled to the logic circuit, latches the operation result at the start time point according to a chip enable signal, and outputs the delay synchronization flag according to the operation result.

7. The virtual static random access memory device according to claim 6, characterized in that: The arbitrator also includes: The feedback circuit is coupled to the latch and is used for clearing the operation result according to the delayed synchronization flag and the chip enable signal during the standby time interval.

8. The virtual static random access memory device according to claim 6, wherein: The plurality of memories receive the chip enable signal together.

9. The virtual static random access memory device according to claim 1, wherein: The multiple memories respectively generate the same multiple access delay indication signals according to the delay synchronization flags, and the controller determines the access delay time in the access operation according to the multiple access delay indication signals.

10. The virtual static random access memory device according to claim 9, characterized in that: Each of the memories comprises: A multiplexer selects a first voltage or a second voltage according to the delay synchronization flag to generate the access delay indication signal, The first voltage is different from the second voltage.

11. The virtual static random access memory device according to claim 10, characterized in that: When the access delay indication signal is the first voltage, the access delay time is a first length, and when the access delay indication signal is the second voltage, the access delay time is a second length, wherein the second length is N times the first length, and N is an integer greater than or equal to 2.

12. The virtual static random access memory device according to claim 1, wherein: Each of the memories comprises: A timer, performing a timing action according to a frequency signal, and enabling each of the corresponding self-refresh request signals after the timing action overflows; and The delayer enables each corresponding self-refresh request signal to be disabled after being enabled for a predetermined time.

13. The virtual static random access memory device according to claim 1, wherein: The multiple memories are dynamic random access memories.

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