Semiconductor structure and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof, which comprises a semiconductor substrate; N layers of metal interconnection lines which are arranged at intervals, N being a positive integer greater than or equal to 3; the N layers of metal interconnection lines at least comprise a first interconnection line, a second interconnection line and a third interconnection line; the first interconnection line and the third interconnection line are connected through a via contact piece which penetrates the second interconnection line. By forming one via through the multi-layer metal interconnection lines, a specific metal interconnection line in the lower part can be connected, so that the process is simplified, in addition, unnecessary metal interconnection line forming areas and unnecessary via occupation spaces are reduced, process defects are improved, the integration of the device is improved, and the size of the device is greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] In semiconductor manufacturing, patterning is an important task. In order to form a fine pattern, photolithography and etching are needed to form a basic pattern. In the process, multiple film deposition and removal are needed. Patterning is also the main process for forming a via hole for multi-layer metal interconnection. Currently, multi-layer metal interconnection lines 11' are mostly interconnected by via holes 12' as shown in the figure. As a result, the patterning process of the via hole is relatively complex, and the multi-layer metal interconnection structure formed is relatively complex, with low structural integration, which cannot meet the requirement of continuously reducing the feature size of semiconductor elements. Figure 1 SUMMARY

[0003] The present application at least partially solves the above technical problems in the related art. To this end, the present application provides a semiconductor structure and a preparation method thereof to solve the problem of low device integration.

[0004] To achieve the above-mentioned purpose, the first aspect of the present application provides a semiconductor structure, comprising:

[0005] a semiconductor substrate;

[0006] N layers of metal interconnection lines are arranged at intervals, and N is a positive integer greater than or equal to 3;

[0007] The N layers of metal interconnection lines at least include a first interconnection line, a second interconnection line and a third interconnection line; the first interconnection line and the third interconnection line are connected by a via hole contact; and the via hole contact penetrates the second interconnection line.

[0008] The second aspect of the present application provides a preparation method of a semiconductor structure, comprising the following steps:

[0009] providing a semiconductor substrate;

[0010] stacking at least a first interconnection line and a second interconnection line on the semiconductor substrate from bottom to top;

[0011] patterning and etching the second interconnection line to expose the top surface of the first interconnection line to form a via hole;

[0012] gap filling the via hole to form a via hole contact;

[0013] forming a third interconnection line in contact with the top end of the via hole contact. BRIEF DESCRIPTION OF DRAWINGS​

[0014] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a better understanding of the preferred embodiments, and are not intended to be a limitation on the scope of the present application. Furthermore, in the accompanying drawings, the same reference numerals are used in different drawings to designate the same elements. In the drawings:

[0015] Figure 1 A schematic diagram of a structure of a multi-layer metal interconnect line in the prior art is shown;

[0016] Figure 2 A schematic diagram of a structure of a multi-layer metal interconnect line in one embodiment of the present application is shown;

[0017] Figure 3 A schematic diagram of a structure of a multi-layer metal interconnect line in another embodiment of the present application is shown;

[0018] Figure 4 A schematic diagram of a structure of depositing a 3-layer metal interconnect line in one embodiment of the present application is shown;

[0019] Figure 5 A schematic diagram of a structure of etching a 3-layer metal interconnect line in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present disclosure, and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known functions and constructions are omitted to avoid obscuring the concept of the present disclosure in unnecessary detail.

[0021] Various schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the diagrams are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art as needed.

[0022] In the context of the present disclosure, when a layer / element is said to be "on" another layer / element, the layer / element can be directly on the other layer / element, or an intervening layer / element can be present therebetween. Also, if a layer / element is "on" another layer / element in one orientation, it can be "under" the other layer / element when the orientation is reversed.

[0023] Reference will now be made to Figure 2The first aspect of the present application provides a semiconductor structure 100, comprising: a semiconductor substrate (not shown in the figure), 4 layers of intermetal dielectric (IMD) layers, 4 layers of metal interconnection lines 10 and 1 via contact 11 formed on the semiconductor substrate from bottom to top.

[0024] It should be noted that the present embodiment is described with N being 4, the 4 layers of intermetal dielectric (IMD) layers include a first IMD layer, a second IMD layer, a third IMD layer and a fourth IMD layer, and the 4 layers of metal interconnection lines 10 include a first interconnection line 101, a second interconnection line 102, a third interconnection line 103 and a fourth interconnection line 104.

[0025] The semiconductor substrate can include a semiconductor material such as silicon, germanium, silicon-germanium, etc., or a III-V semiconductor compound such as GaP, GaAs, GaSb, etc. In some embodiments, the semiconductor substrate can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0026] In addition, although not shown, the semiconductor substrate can include a conductive pattern. The conductive pattern can be a metal line, a contact, a conductive pad, etc., and can be a gate electrode of a transistor, a source / drain of a transistor, or a diode, but embodiments are not limited thereto.

[0027] It should be noted that the IMD layer can include a low-k material having a dielectric constant lower than that of silicon oxide (SiO2). For example, silicon oxide can have a dielectric constant of about 3.9 to about 4.5. The IMD layer can have a dielectric constant of 3.5 or less. For example, the IMD layer can have a dielectric constant of about 2.0 to about 3.5. In an example embodiment, the IMD layer can include silicon oxide containing carbon and hydrogen (SiCOH). For example, the IMD layer can include about 10% to about 50% carbon. In some example embodiments, the IMD layer can include fluorine-doped silicon oxide (F-SiO2), porous silicon oxide, etc.

[0028] The 4 layers of metal interconnection lines 10 are respectively arranged in the 4 layers of IMD layers, the 4 layers of metal interconnection lines 10 are arranged at intervals from each other, and the 4 layers of metal interconnection lines 10 have overlapping areas therebetween. Specifically, metal interconnection line grooves are formed in the IMD layers, the metal interconnection lines 10 are filled in the metal interconnection line grooves, and the top surfaces of the metal interconnection lines 10 and the top surfaces of the IMD layers are located on the same horizontal plane.

[0029] The via contact 11 penetrates the second interconnection line 102 and the third interconnection line 103, and the top end of the via contact 11 is in contact with the bottom surface of the fourth interconnection line 104, and the bottom end of the via contact 11 is in contact with the top surface of the first interconnection line 101, so as to realize the interconnection of the first interconnection line 101 and the fourth interconnection line 104.

[0030] Specifically, the connection part of the via contact 11 and the second interconnection line 102 and the third interconnection line 103 is provided with an insulating layer 12, and the unconnected part of the via contact 11 and the second interconnection line 102 and the third interconnection line 103 is provided with a first barrier layer 13. Wherein, the thickness of the insulating layer 12 and the first barrier layer 13 is the same, and the insulating layer 12 and the first barrier layer 13 are connected end to end, the via contact 11 can include tungsten (W) or copper, and the first barrier layer 13 can include tungsten nitride, Ti / TiNy, W, Ta / TaN, etc.

[0031] It is worth mentioning that the material of the insulating layer 12 can be selected from silicon oxide, silicon nitride or SiCN. Using an insulating film with a buffering effect at the connection part of the via contact 11 and the second interconnection line 102 and the third interconnection line 103 can improve the interference between patterns and the pattern margin.

[0032] The materials of the first interconnection line 101, the second interconnection line 102, the third interconnection line 103 and the fourth interconnection line 104 can be the same, and each can include a filling layer and a second barrier layer formed on the side and bottom surface of the filling layer. Specifically, the filling layer can include a first metal having a first resistance, and the second barrier layer can include, for example, titanium, titanium nitride, tantalum and tantalum nitride, etc. The first metal can include one of aluminum and copper. In an example embodiment, the first metal can include copper.

[0033] It should be noted that in other embodiments of the present application, there can be a case as shown in Figure 3 The semiconductor structure 100 can include 4 layers of metal interconnection lines 10, wherein the first interconnection line 101 and the second interconnection line 102 have been interconnected by a traditional damascene process, and only the second interconnection line 102 and the fourth interconnection line 104 need to be interconnected, in which case the via contact 11 needs to pass through the second interconnection line 102 and the third interconnection line 103 to connect the second interconnection line 102 and the fourth interconnection line 104.

[0034] It is worth mentioning that the present embodiment only exemplifies the value of N in the above two cases, but the present application should not be limited thereto, and those skilled in the art can flexibly select the value of N as needed to connect the top metal interconnection line and the lower specific metal interconnection line through the via contact.

[0035] The preparation method of the semiconductor structure 100 in the embodiment of the present application is described below.

[0036] The present application provides a preparation method of a semiconductor structure 100, comprising the following steps:

[0037] A semiconductor substrate is provided and placed in a reaction chamber. In this embodiment, the semiconductor substrate may include semiconductor materials such as silicon, germanium, silicon-germanium, or III-V semiconductor compounds such as GaP, GaAs, and GaSb. In some embodiments, the semiconductor substrate may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0038] When the semiconductor substrate is a silicon-based semiconductor substrate, it may include, for example, dangling bonded silicon atoms that are not bonded to oxygen ions. The operating characteristics of the transistor can be stabilized using a hydrogen annealing process, in which hydrogen atoms bond to the dangling bonded silicon atoms of the semiconductor substrate. In this case, hydrogen atoms can easily separate from silicon atoms, but boron can increase the binding energy between silicon and hydrogen atoms. Therefore, the variable hold time or charge hold time of the capacitor can be improved.

[0039] Next, as Figure 4 As shown, the first IMD layer can be formed by depositing a low-k material with a dielectric constant lower than that of silicon oxide (SiO2). In an example embodiment, the first IMD layer may be a silicon oxide (SiCOH) comprising carbon and hydrogen. For example, the first IMD layer may comprise about 10% to about 50% carbon. In some example embodiments, the first IMD layer may comprise fluorine-doped silicon oxide (F-SiO2) or porous silicon oxide.

[0040] Next, a first IMD layer is etched using a first etch mask (not shown) to form metal interconnect trenches within the first IMD layer. In an example embodiment, a first interconnect 101 is formed within the metal wiring trenches using a conventional damascene process;

[0041] Next, a first etch stop layer (not shown in the figure) is formed on the first IMD layer and the first interconnect 101. The first etch stop layer can be a material with a high selectivity in selective etching. Furthermore, since the first etch stop layer directly contacts the first IMD layer, it can include a material that can easily contact the first IMD layer. The first etch stop layer can include SiCN or SiN and other materials suitable for use as etch stop layers. Next, a second IMD layer is formed on the first etch stop layer. The second IMD layer can include a low-k material with a dielectric constant lower than that of silicon oxide (SiO2). In an example embodiment, the second IMD layer can include the same material as the first IMD layer.

[0042] Next, the same process described above is used to form metal wiring trenches in the second IMD layer, and then the second interconnect 102 is filled in.

[0043] Next, a second etch stop layer is formed on the second IMD layer and the second interconnect 102 using the same process described above. The second etch stop layer is made of the same material as the second etch stop layer.

[0044] Continue to refer to Figure 4 Repeat the above process until the third IMD layer, the third interconnect 103, and the third etch stop layer are formed;

[0045] It is worth mentioning that, while forming interconnects in each layer, through-hole interconnect structures (not shown in the figure) can be formed between adjacent interconnects using the traditional damascus mosaic process. This embodiment will not be elaborated on here.

[0046] Next, as Figure 5 As shown, the overlapping area of ​​the third interconnect 103, the second interconnect 102, and the first interconnect 101 is patterned. Specifically, the patterned etching removes the etch stop layer of the overlapping area to form a via 14. Specifically, the appropriate etching depth is adjusted according to the metal interconnects to be connected. In this embodiment, the third interconnect 103, the second interconnect 102, and the first interconnect 101 are etched using a second etch mask (not shown).

[0047] Next, continue to refer to Figure 2 An insulating layer 12 is formed at the via penetration of the third interconnect 103 and the second interconnect 102. It is worth mentioning that the insulating layer 12 can be formed not only by deposition, but also by self-alignment, such as by depositing an insulating layer precursor material and then annealing it to form the insulating layer 12, or by directly forming the insulating layer through interface oxidation.

[0048] Next, a first barrier layer 13 is formed in the uncovered area of ​​the via 14. The insulating layer 12 and the first barrier layer 13 do not completely fill the via 14, and the via contact 11 is filled in the via 14.

[0049] Next, continue to refer to Figure 2 A fourth IMD layer is deposited above the via contact 11, and then the via 14 is repaired by a repair process to improve the product defects caused by poor contact. A through hole corresponding to the via 14 is formed on the fourth IMD layer, and then a fourth metal interconnect is filled in the through hole to electrically connect the first metal interconnect to the fourth metal interconnect.

[0050] It should be noted that, after forming the via 14, the via 14 may not be filled immediately. Instead, a fourth IMD layer may be formed above the via 14, and a metal wiring trench communicating with the via 14 may be formed in the fourth IMD layer. Then, the via contact 11 and the fourth metal interconnect 104 may be formed simultaneously in the via 14 and the metal wiring trench using a conventional damascus inlay process. This application does not limit the above process, as long as it can achieve the spaced interconnection of the metal interconnects.

[0051] It should be noted that this embodiment only describes the connection method between the first metal interconnect and the fourth interconnect 104. Of course, the above method is also applicable to some other situations. For example, if the first interconnect 101 and the second interconnect 102 have already been connected using a conventional single-insertion process, this method can be used to connect the second interconnect 102 and the fourth interconnect 104. In addition, the method of this embodiment is also applicable to the interconnection of other multilayer metal wiring, and this embodiment does not limit it here.

[0052] It is worth noting that this embodiment can connect a specific layer of metal interconnects by forming a single via through multiple layers of metal interconnects, avoiding the formation of unnecessary vias and metal wiring, thus simplifying the process. In addition, it reduces the area of ​​unnecessary metal interconnect formation and the space occupied by unnecessary vias, improves process defects and increases the integration of the device, and greatly reduces the size of the device.

[0053] The semiconductor structure in this embodiment can be a volatile memory device such as a DRAM device or an SRAM device, or a non-volatile memory device such as a flash memory device, a PRAM device, an MRAM device, or an RRAM device.

[0054] Furthermore, the semiconductor structure in this embodiment can be used in various chips.

[0055] Furthermore, chips with the aforementioned semiconductor structure can be used in various electronic devices, specifically smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, power banks, etc.

[0056] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0057] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Semiconductor substrate; N layers of metal interconnects spaced apart, where N is a positive integer ≥ 3; The N-layer metal interconnect includes at least a first interconnect, a second interconnect, and a third interconnect; the first interconnect and the third interconnect are connected by a via contact, and the via contact passes through the second interconnect; An insulating layer is provided at the connection portion between the via contact and the second interconnect line; A barrier layer is provided at the unconnected portion of the via contact and the second interconnect line; Furthermore, the insulating layer (12) is connected end to end with the first barrier layer (13).

2. The semiconductor structure according to claim 1, characterized in that, The insulating layer and the barrier layer have the same thickness.

3. The semiconductor structure according to claim 1, characterized in that, The insulating layer is made of silicon oxide, silicon nitride, or SiCN.

4. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide semiconductor substrates; At least a first interconnect and a second interconnect are formed by stacking them from bottom to top on the semiconductor substrate; The second interconnect is patterned and etched to expose the top surface of the first interconnect to form a via; An insulating layer is formed at the connection between the via contact and the second interconnect; A barrier layer is formed at the unconnected portion between the via contact and the second interconnect; The via is filled to form a via contact; A third interconnect line is formed that contacts the top of the via contact.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The following steps are included before patterning and etching the second interconnect: An etch stop layer is deposited on the surface of each interconnect layer.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, The steps of patterning and etching the second interconnect include: The second interconnect is patterned and etched using a mask.

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