Electromigration test structure

Abstract

The present application relates to the technical field of semiconductor, and particularly relates to an electromigration test structure, including 13 structures of I-V lead hole through layer type, single-side lead voltage test pad and current source hole through layer type, cross layer type for double-side lead voltage test pad. The I-V lead hole through layer type is a structure, which comprises four structural elements, namely, a metallization test line, other metal interconnection lines, a hole interconnection structure and a large-area metallization test pad. The structure comprises two metal layers, wherein the metallization test line is located on the first layer, and the current source, the voltage lead and the other metal interconnection lines are connected to the second layer through the hole interconnection, forming a cross layer structure. The present application provides an electromigration test structure for evaluating the electromigration reliability problem caused in the semiconductor device manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an electromigration test structure. Background Technology

[0002] Electromigration refers to the migration of metal ions within a metallic conductor material due to the movement of a large number of electrons.

[0003] Electromigration is a phenomenon that occurs under certain conditions, macroscopically manifested as the movement of metallic substances. This effect is particularly pronounced when a large current flows through a metallic conductor. Since the successful commercialization of integrated circuits, electromigration has become a key focus mechanism in the field of semiconductor reliability. A test characterization vehicle (TCV) is a wafer-level or package-level structure used to evaluate the reliability of semiconductor devices. Its purpose is to identify reliability defects, take measures to resolve them, and ensure good reliability of the device throughout its product lifespan. Test characterization vehicles can measure physical parameters, process parameters, device parameters, or circuit parameters.

[0004] The test structure design for electromigration is generally a metal wire test structure, consisting of metal wires in each layer of the CMOS process and VIA vias connecting different layers. Electromigration tests are simulated by applying specific electrical and thermal stresses to the test structure, and the reliability of the tested process is evaluated through the test data. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an electromigration test structure for evaluating electromigration reliability issues arising during semiconductor device manufacturing.

[0006] This invention is achieved through the following technical solution:

[0007] An electromigration test structure is a cross-layer type with IV lead-out vias, comprising four structural elements: metallized test lines, other metal interconnects, via interconnects, and a large-area metallized test pad; it includes two metal layers, wherein the metallized test lines are located in the first layer, and the current source, voltage lead-out, and other metal interconnects are interconnected to the second layer through vias, forming a cross-layer structure.

[0008] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0009] This invention also provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad and current source. It includes five structural elements: a metallized test line, a monitoring line structure, other metal interconnects, a through-hole interconnect structure, and a large-area metallized test pad. It includes two metal layers, wherein the metallized test line, other metal interconnects on one side, the monitoring line structure, current source 1, and voltage test pad 1 are located in the first layer, and the other metal interconnects on the other side, current source 2, and voltage test pad 2 are located in the second layer through the through-hole interconnect structure, forming a cross-layer structure.

[0010] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0011] The present invention also provides an electromigration test structure, which is a cross-layer type with double-sided voltage test pads. It is characterized by comprising four structural elements, namely, metallized test lines, other metal interconnects, through-hole interconnects, and large-area metallized test pads; and comprising two metal layers, wherein the metallized test lines and metal interconnects are located in the first layer, and the double-sided voltage detection lines and voltage test pads are located in the second layer through a single through-hole interconnect, forming a cross-layer structure.

[0012] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0013] The present invention also provides an electromigration test structure, which is a through-hole cross-layer type with three-sided voltage test pads and current sources. It includes four structural elements: metallized test lines, other metal interconnects, through-hole interconnect structure, and large-area metallized test pads. It includes two metal layers, wherein the metallized test lines, metal interconnects, and current source 1 are located in the first layer, and the dual-sided voltage detection lines, current source 2, and voltage test pads are located in the second layer through a single through-hole interconnect structure, forming a cross-layer structure.

[0014] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0015] The present invention also provides an electromigration test structure, which is a cross-layer type with IV lead-out vias and a ring monitoring line. It includes five structural elements: a metallized test line, other metal interconnects, a via interconnect structure, a monitoring line structure, and a large-area metallized test pad. It includes two metal layers, wherein the metallized test line and the monitoring line structure are located in the first layer, and the current source, voltage lead-out, and other metal interconnects are interconnected in the second layer through vias to form a cross-layer structure.

[0016] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0017] Preferably, the monitoring structure is a metal ring monitoring line surrounding the test line, connected on one side via a cross-layer via structure, and connected to a leakage current detection pad via a cross-layer interconnect; the effective length of the ring monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the ring monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line; the spacing between the ring monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0018] This invention also provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad and a ring monitoring line. It includes five structural elements: a metallized test line, a monitoring line structure, other metal interconnects, a through-hole interconnect structure, and a large-area metallized test pad. It includes two metal layers, wherein the metallized test line, other metal interconnects on one side, the monitoring line structure, current source 1, and voltage test pad 1 are located in the first layer, and other metal interconnects on the other side, current source 2, and voltage test pad 2 are located in the second layer through the through-hole interconnect structure, forming a cross-layer structure.

[0019] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0020] Preferably, the monitoring structure is a metal ring monitoring line surrounding the test line, connected on one side via a cross-layer via structure, and connected to a leakage current detection pad via a cross-layer interconnect; the effective length of the ring monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the ring monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line; the spacing between the ring monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0021] This invention also provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad and a ring monitoring line. It includes five structural elements: a metallized test line, a monitoring line structure, other metal interconnects, a through-hole interconnect structure, and a large-area metallized test pad. It includes two metal layers, wherein the metallized test line, metal interconnects, monitoring line structure, current source, and voltage test pad 2 are located in the first layer, and the voltage detection line and voltage test pad are located in the second layer through the through-hole interconnect structure, forming a cross-layer structure.

[0022] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0023] Preferably, the monitoring structure is a metal ring monitoring line surrounding the test line, connected on one side via a cross-layer via structure, and connected to a leakage current detection pad via a cross-layer interconnect; the effective length of the ring monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the ring monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line; the spacing between the ring monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0024] This invention also provides an electromigration test structure, which is a through-hole cross-layer type with three-sided voltage test pads and current sources connected by a ring monitoring line. It includes five structural elements: a metallized test line, a monitoring line structure, other metal interconnects, a through-hole interconnect structure, and a large-area metallized test pad. It includes two metal layers, wherein the metallized test line, metal interconnects, monitoring line structure, and current source 1 are located in the first layer, and the double-sided voltage detection line, current source 2, and voltage test pad are located in the second layer through a single through-hole interconnect structure, forming a cross-layer structure.

[0025] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0026] Preferably, the monitoring structure is a metal ring monitoring line surrounding the test line, connected on one side via a cross-layer via structure, and connected to a leakage current detection pad via a cross-layer interconnect; the effective length of the ring monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the ring monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line; the spacing between the ring monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0027] This invention also provides an electromigration test structure, which is a cross-layer type with a double-sided lead-out voltage test pad with a monitoring structure. It includes five structural elements: a metallized test line, a monitoring line structure, other metal interconnects, a via interconnect structure, and a large-area metallized test pad. It includes two metal layers, wherein the metallized test line, metal interconnects, double-sided current source, and monitoring line structure are located in the first layer, and the double-sided voltage detection line and voltage lead-out terminal are interconnected to the second layer through vias to form a cross-layer structure.

[0028] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0029] Preferably, the monitoring line structure consists of two metal lines parallel to the metal test line, connected to two leakage current detection pads via interconnects; or a ring-shaped metal line encircling the test line, connected via a cross-layer via structure, and connected to a leakage current detection pad via interconnects; the effective length of the monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the evaluated and verified product process line design rules; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line; the spacing between the monitoring line and the metallized test line also follows the minimum spacing determined by the evaluated and verified product process line design rules.

[0030] The present invention also provides an electromigration test structure, which is a cross-layer type with IV lead-out vias and parallel monitoring lines. It includes five structural elements: metallized test lines, monitoring line structures, other metal interconnects, via interconnect structures, and a large area metallized test pad. It includes two metal layers, wherein the metallized test lines and monitoring line structures are located in the first layer, and the current source, voltage lead-out, and other metal interconnects are interconnected in the second layer through vias to form a cross-layer structure.

[0031] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0032] Preferably, the monitoring line structure consists of two metal lines parallel to the metal test line, connected to two leakage current detection pads via interconnects; the effective length of the monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line; the spacing between the monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0033] The present invention also provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad and a current source with parallel monitoring lines. It includes five structural elements, namely, metallized test lines, monitoring line structure, other metal interconnects, through-hole interconnect structure and large-area metallized test pad; it includes two metal layers, wherein the metallized test lines, other metal interconnects on one side, monitoring line structure, current source 1 and voltage test pad 1 are located in the first layer, and other metal interconnects on the other side, current source 2 and voltage test pad 2 are located in the second layer through the through-hole interconnect structure, forming a cross-layer structure.

[0034] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0035] Preferably, the monitoring line structure consists of two metal lines parallel to the metal test line, connected to two leakage current detection pads via interconnects; the effective length of the monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line; the spacing between the monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0036] This invention also provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad and parallel monitoring lines. It includes five structural elements: a metallized test line, a monitoring line structure, other metal interconnects, a through-hole interconnect structure, and a large-area metallized test pad. It contains two metal layers, wherein the metallized test line, metal interconnects, monitoring line structure, current source, and voltage test pad 2 are located in the first layer, and the voltage detection line and voltage test pad are located in the second layer through the through-hole interconnect structure, forming a cross-layer structure.

[0037] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0038] Preferably, the monitoring line structure consists of two metal lines parallel to the metal test line, connected to two leakage current detection pads via interconnects; the effective length of the monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line; the spacing between the monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0039] This invention also provides an electromigration test structure, which is a through-hole cross-layer type with three-sided voltage test pads and current sources with parallel monitoring lines. It includes five structural elements: metallized test lines, monitoring line structure, other metal interconnects, through-hole interconnect structure, and large-area metallized test pads. It includes two metal layers, wherein the metallized test lines, metal interconnects, and current source 1 are located in the first layer, and the dual-sided voltage detection lines, current source 2, and voltage test pads are located in the second layer through a single through-hole interconnect structure, forming a cross-layer structure.

[0040] Preferably, the number of through holes is 1 to 10. When there is more than 1, an even number is selected and arranged in a 2×N array.

[0041] Preferably, the monitoring line structure consists of two metal lines parallel to the metal test line, connected to two leakage current detection pads via interconnects; the effective length of the monitoring line should not be less than the length of the uniform linewidth of the metallized test line; the width of the monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line; the spacing between the monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

[0042] The beneficial effects of this invention are as follows:

[0043] This invention is used to characterize the reliability of electromigration effects on metallized test leads and vias in a test process. During testing, a current is applied across a current source, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance.

[0044] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the planar structure in Embodiment 1 of the present invention.

[0047] Figure 2-(a) is a schematic diagram of the voltage terminal cross-layer structure in Embodiment 1 of the present invention.

[0048] Figure 2-(b) is a partial enlarged view of the voltage terminal cross-layer structure in Embodiment 1 of the present invention.

[0049] Figure 2-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 2-(b) in Embodiment 1 of the present invention.

[0050] Figure 2-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 2-(b) in Embodiment 1 of the present invention.

[0051] Figure 3 This is a diagram of the interconnection structure in Embodiment 1 of the present invention.

[0052] Figure 4 This is a schematic diagram of the interconnect via array in Embodiment 1 of the present invention.

[0053] Figure 5 This is a schematic diagram of the planar structure in Embodiment 2 of the present invention.

[0054] Figure 6-(a) is a schematic diagram of the cross-layer structure in Embodiment 2 of the present invention.

[0055] Figure 6-(b) is a partial enlarged view of the cross-layer structure in Embodiment 2 of the present invention.

[0056] Figure 6-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 6-(b) in Embodiment 2 of the present invention.

[0057] Figure 6-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 6-(b) in Embodiment 2 of the present invention.

[0058] Figure 7 This is a schematic diagram of the interconnect via array in Embodiment 2 of the present invention.

[0059] Figure 8 This is a schematic diagram of the planar structure in Embodiment 3 of the present invention.

[0060] Figure 9-(a) is a schematic diagram of the cross-layer structure in Embodiment 3 of the present invention.

[0061] Figure 9-(b) is a partial enlarged view of the cross-layer structure in Embodiment 3 of the present invention.

[0062] Figure 9-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 9-(b) in Embodiment 3 of the present invention.

[0063] Figure 9-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 9-(b) in Embodiment 3 of the present invention.

[0064] Figure 10 This is a diagram of the interconnection structure in Embodiment 3 of the present invention.

[0065] Figure 11 This is a schematic diagram of the interconnect via array in Embodiment 3 of the present invention.

[0066] Figure 12 This is a schematic diagram of the planar structure in Embodiment 4 of the present invention.

[0067] Figure 13-(a) is a schematic diagram of the cross-layer structure in Embodiment 4 of the present invention.

[0068] Figure 13-(b) is a partial magnification of the cross-layer structure in Embodiment 4 of the present invention. Figure 1 .

[0069] Figure 13-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 13-(b) in Embodiment 4 of the present invention.

[0070] Figure 13-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 13-(b) in Embodiment 4 of the present invention.

[0071] Figure 13-(e) is a partial enlarged view of the cross-layer structure in Embodiment 4 of the present invention.

[0072] Figure 13-(f) is a longitudinal cross-sectional view along the X-X' direction of Figure 13-(e) in Embodiment 4 of the present invention.

[0073] Figure 13-(g) is a longitudinal cross-sectional view along the Y-Y' direction in Figure 13-(e) of Embodiment 4 of the present invention.

[0074] Figure 14 This is a diagram of the interconnection structure in Embodiment 4 of the present invention.

[0075] Figure 15 This is a schematic diagram of the interconnect via array in Embodiment 4 of the present invention.

[0076] Figure 16 This is a schematic diagram of the planar structure in Embodiment 5 of the present invention.

[0077] Figure 17-(a) is a schematic diagram of the voltage terminal cross-layer structure in Embodiment 5 of the present invention.

[0078] Figure 17-(b) is a partial enlarged view of the cross-layer structure in Embodiment 5 of the present invention.

[0079] Figure 17-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 17-(b) in Embodiment 5 of the present invention.

[0080] Figure 17-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 17-(b) in Embodiment 5 of the present invention.

[0081] Figure 18 This is a diagram of the interconnection structure in Embodiment 5 of the present invention.

[0082] Figure 19 This is a schematic diagram of the interconnect via array in Embodiment 5 of the present invention.

[0083] Figure 20 This is a schematic diagram of the planar structure in Embodiment 6 of the present invention.

[0084] Figure 21-(a) is a schematic diagram of the cross-layer structure in Embodiment 6 of the present invention.

[0085] Figure 21-(b) is a partial enlarged view of the cross-layer structure in Embodiment 6 of the present invention.

[0086] Figure 21-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 21-(b) in Embodiment 6 of the present invention.

[0087] Figure 21-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 21-(b) in Embodiment 6 of the present invention.

[0088] Figure 22 This is a schematic diagram of the interconnect via array in Embodiment 6 of the present invention.

[0089] Figure 23 This is a schematic diagram of the planar structure in Embodiment 7 of the present invention.

[0090] Figure 24-(a) is a schematic diagram of the cross-layer structure in Embodiment 7 of the present invention.

[0091] Figure 24-(b) is a partial enlarged view of the cross-layer structure in Embodiment 7 of the present invention.

[0092] Figure 24-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 24-(b) in Embodiment 7 of the present invention.

[0093] Figure 24-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 24-(b) in Embodiment 7 of the present invention.

[0094] Figure 25 This is a diagram of the interconnection structure in Embodiment 7 of the present invention.

[0095] Figure 26 This is a schematic diagram of the interconnect via array in Embodiment 7 of the present invention.

[0096] Figure 27 This is a schematic diagram of the planar structure in Embodiment 8 of the present invention.

[0097] Figure 28-(a) is a schematic diagram of the cross-layer structure in Embodiment 8 of the present invention.

[0098] Figure 28-(b) is a partial magnification of the cross-layer structure in Embodiment 8 of the present invention. Figure 1 .

[0099] Figure 28-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 28-(b) in Embodiment 8 of the present invention.

[0100] Figure 28-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 28-(b) in Embodiment 8 of the present invention.

[0101] Figure 28-(e) is a partial enlarged view of the cross-layer structure in Embodiment 8 of the present invention.

[0102] Figure 28-(f) is a longitudinal cross-sectional view along the X-X' direction of Figure 28-(e) in Embodiment 8 of the present invention.

[0103] Figure 28-(g) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 28-(e) in Embodiment 8 of the present invention.

[0104] Figure 29 This is a diagram of the interconnection structure in Embodiment 8 of the present invention.

[0105] Figure 30 This is a schematic diagram of the interconnect via array in Embodiment 8 of the present invention.

[0106] Figure 31 This is a schematic diagram of the planar structure (parallel line monitoring structure) in Embodiment 9 of the present invention.

[0107] Figure 32-(a) is a schematic diagram of the voltage terminal cross-layer structure in Embodiment 9 of the present invention.

[0108] Figure 32-(b) is a partial enlarged view of the cross-layer structure in Embodiment 9 of the present invention.

[0109] Figure 32-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 32-(b) in Embodiment 9 of the present invention.

[0110] Figure 32-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 32-(b) in Embodiment 9 of the present invention.

[0111] Figure 33 This is a schematic diagram of the planar structure (ring-shaped monitoring structure) in Embodiment 9 of the present invention.

[0112] Figure 34 This is a diagram of the interconnection structure in Embodiment 9 of the present invention.

[0113] Figure 35 This is a schematic diagram of the interconnect via array in Embodiment 9 of the present invention.

[0114] Figure 36 This is a schematic diagram of the planar structure in Embodiment 10 of the present invention.

[0115] Figure 37-(a) is a schematic diagram of the voltage terminal cross-layer structure in Embodiment 10 of the present invention.

[0116] Figure 37-(b) is a partial enlarged view of the cross-layer structure in Embodiment 10 of the present invention.

[0117] Figure 37-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 37-(b) in Embodiment 10 of the present invention.

[0118] Figure 37-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 37-(b) in Embodiment 10 of the present invention.

[0119] Figure 38 This is a diagram of the interconnection structure in Embodiment 10 of the present invention.

[0120] Figure 39 This is a schematic diagram of the interconnect via array in Embodiment 10 of the present invention.

[0121] Figure 40 This is a schematic diagram of the planar structure in Embodiment 11 of the present invention.

[0122] Figure 41-(a) is a schematic diagram of the cross-layer structure in Embodiment 11 of the present invention.

[0123] Figure 41-(b) is a partial enlarged view of the cross-layer structure in Embodiment 11 of the present invention.

[0124] Figure 41-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 41-(b) in Embodiment 11 of the present invention.

[0125] Figure 41-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 41-(b) in Embodiment 11 of the present invention.

[0126] Figure 42 This is a schematic diagram of the interconnect via array in Embodiment 11 of the present invention.

[0127] Figure 43 This is a schematic diagram of the planar structure in Embodiment 12 of the present invention.

[0128] Figure 44-(a) is a schematic diagram of the cross-layer structure in Embodiment 12 of the present invention.

[0129] Figure 44-(b) is a partial enlarged view of the cross-layer structure in Embodiment 12 of the present invention.

[0130] Figure 44-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 44-(b) in Embodiment 12 of the present invention.

[0131] Figure 44-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 44-(b) in Embodiment 12 of the present invention.

[0132] Figure 45 This is a diagram of the interconnection structure in Embodiment 12 of the present invention.

[0133] Figure 46 This is a schematic diagram of the interconnect via array in Embodiment 12 of the present invention.

[0134] Figure 47 This is a schematic diagram of the planar structure in Embodiment 13 of the present invention.

[0135] Figure 48-(a) is a schematic diagram of the cross-layer structure in Embodiment 13 of the present invention.

[0136] Figure 48-(b) is a partial magnification of the cross-layer structure in Embodiment 13 of the present invention. Figure 1 .

[0137] Figure 48-(c) is a longitudinal cross-sectional view along the X-X' direction of Figure 48-(b) in Embodiment 13 of the present invention.

[0138] Figure 48-(d) is a longitudinal cross-sectional view along the Y-Y' direction of Figure 48-(b) in Embodiment 13 of the present invention.

[0139] Figure 48-(e) is a partial enlarged view of the cross-layer structure in Embodiment 13 of the present invention.

[0140] Figure 48-(f) is a longitudinal cross-sectional view along the X-X' direction of Figure 48-(e) in Embodiment 13 of the present invention.

[0141] Figure 48-(g) is a longitudinal cross-sectional view along the Y-Y' direction in Figure 48-(e) of Embodiment 13 of the present invention.

[0142] Figure 49 This is a diagram of the interconnection structure in Embodiment 13 of the present invention.

[0143] Figure 50 This is a schematic diagram of the interconnect via array in Embodiment 13 of the present invention.

[0144] In the diagram: 1-Metallized test line, 2-Monitoring line structure, 3-Metallic interconnect, 4-Through-hole interconnect structure, 5-Current source, 6-Voltage test pad, 7-Voltage detection line lead-out, 8-Voltage detection line, 9-Leakage current detection pad. Detailed Implementation

[0145] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1:

[0146] Please see Figures 1-4As shown: This invention provides an electromigration test structure, which is a multi-layer via-hole type with IV leads. It can be decomposed into four structural elements: a metallized test line 1, other metal interconnects 3, a via interconnect structure 4, and a large-area metallized test pad. The metallized test line 1 is used for testing electromigration effects; the other metal interconnects 3 are used for interconnection and detection; the via interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input and voltage reading. Figure 1 As shown.

[0147] This invention comprises two metal layers, wherein the metallized test line 1 is located in the first layer, and the current source 5, voltage lead, and other metal interconnects 3 are interconnected to the second layer through vias, forming a cross-layer structure, as shown below. Figure 1 , Figures 2-(a) to 2-(d) As shown;

[0148] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0149] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0150] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0151] Other metal interconnects 3 used for interconnection and detection include metallized interconnects and voltage sensing lines 8, such as Figure 3 As shown.

[0152] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0153] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0154] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0155] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 4 As shown.

[0156] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0157] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0158] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0159] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0160] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 2:

[0161] Please see Figures 5-7 As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad 6 and a current source 5. It can be decomposed into four structural elements: a metallized test line 1, other metal interconnects 3, a through-hole interconnect structure 4, and a large-area metallized test pad. The metallized test line 1 is used for testing electromigration effects; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 5 As shown.

[0162] This invention comprises two metal layers. The metallized test line 1, other metal interconnects 3 on one side, current sources 1-5, and voltage test pad 61 are located in the first layer. The other metal interconnects 3, current sources 2-5, and voltage test pad 62 on the other side are located in the second layer via a via interconnect structure 4, forming a cross-layer structure. Figures 6-(a) to 6-(d) As shown.

[0163] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0164] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0165] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0166] Other metal interconnects 3 used for interconnection and detection include metal interconnects 3 and voltage detection lines 8, as shown in Figure 6-(a).

[0167] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0168] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0169] In this invention, the metallized through-hole interconnect structure 4 is a single-sided through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0170] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 7 As shown.

[0171] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0172] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0173] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0174] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0175] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 3:

[0176] Please see Figures 8-11 As shown: This invention provides an electromigration test structure, a cross-layer type with double-sided voltage test pads 6, which can be decomposed into four structural elements: metallized test lines 1, other metal interconnects 3, through-hole interconnect structures 4, and a large-area metallized test pad. The metallized test lines 1 are used for testing electromigration effects; the other metal interconnects 3 are used for interconnection and monitoring; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input and voltage reading. Figure 8 As shown.

[0177] This invention relates to a two-layer metal structure, wherein the metallized test line 1 and the metal interconnect line 3 are located in the first layer, and the double-sided voltage detection line 8 and the voltage test pad 6 are located in the second layer through a single via interconnect structure 4, forming a cross-layer structure, as shown below. Figures 9-(a) to 9-(d) As shown.

[0178] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0179] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0180] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0181] Other metal interconnects 3 used for interconnection and monitoring include test line interconnect segments, metal interconnects 3, and voltage detection lines 8, such as Figure 10 As shown.

[0182] The width of the interconnect segment of the test line is twice the length of the metallized test line 1. The length must meet the requirement that the ratio of the length of the metallized test line 1 to the length of the metallized test line 1 plus the interconnect segments of the test lines at both ends is greater than or equal to 95% and less than or equal to 8μm.

[0183] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0184] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0185] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0186] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 11 As shown.

[0187] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0188] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0189] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0190] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0191] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 4:

[0192] Please see Figures 12-15 As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with three-sided voltage test pads 6 and current sources 5. It can be decomposed into four structural elements: a metallized test line 1, a detection line structure, other metal interconnects 3, a through-hole interconnect structure 4, and a large-area metallized test pad. The metallized test line 1 is used for testing electromigration effects; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input and voltage reading. Figure 12 As shown.

[0193] This invention relates to a two-layer metal structure, wherein the metallized test line 1, the metal interconnect line 3, and the current source 1-5 are located in the first layer, and the dual-sided voltage detection line 8, the current source 2-5, and the voltage test pad 6 are located in the second layer through a single via interconnect structure 4, forming a cross-layer structure, as shown below. Figures 13-(a) to 13-(g) As shown.

[0194] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0195] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0196] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0197] Other metal interconnects 3 used for interconnection and detection include test line interconnect segments, metal interconnects 3, and voltage detection lines 8, such as Figure 14 As shown.

[0198] The width of the interconnect segment of the test line is twice the length of the metallized test line 1. The length must meet the requirement that the ratio of the length of the metallized test line 1 to the length of the metallized test line 1 plus the interconnect segments of the test lines at both ends is greater than or equal to 95% and less than or equal to 8μm.

[0199] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0200] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0201] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0202] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 15 As shown.

[0203] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0204] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0205] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0206] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0207] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 5:

[0208] Please see Figures 16-19As shown: This invention provides an electromigration test structure, which is a multi-layer type with an IV lead via and a ring-shaped monitoring line. It can be decomposed into five structural elements: a metallized test line 1, other metal interconnects 3, a via interconnect structure 4, a monitoring line structure 2, and a large-area metallized test pad. The metallized test line 1 is used for testing electromigration effects; the other metal interconnects 3 are used for interconnection and detection; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the via interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input and voltage reading. Figure 16 As shown.

[0209] This invention comprises two metal layers, wherein the metallized test line 1 and the monitoring line structure 2 are located in the first layer, and the current source 5, the voltage lead-out terminal, and other metal interconnects 3 are interconnected to the second layer through vias, forming a cross-layer structure, such as... Figure 16 , Figures 17-(a) to 17-(d) As shown.

[0210] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0211] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0212] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0213] The monitoring structure is a ring-shaped metal wire that surrounds the test line. One side is connected through a cross-layer via structure and is connected to a leakage current detection pad 9 through a cross-layer interconnect. The purpose is to monitor whether there is leakage current or even short circuit between interconnects due to the accumulation of metal atoms in the interconnects causing the interconnects to grow tendrils laterally.

[0214] The effective length of the ring monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the ring monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line. The spacing between the ring monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0215] Other metal interconnects 3 used for interconnection and detection include metallized interconnects and voltage sensing lines 8, such as Figure 18 As shown.

[0216] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0217] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0218] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0219] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 19 As shown.

[0220] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0221] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0222] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0223] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0224] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 6:

[0225] Please see Figures 20-22As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad 6 and a ring-shaped monitoring line. It can be decomposed into five structural elements: a metallized test line 1, a monitoring line structure 2, other metal interconnects 3, a through-hole interconnect structure 4, and a large-area metallized test pad. Specifically, the metallized test line 1 is used for testing electromigration effects; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 20 As shown.

[0226] This invention comprises two metal layers. The metallized test line 1, other metal interconnects 3 on one side, the monitoring line structure 2, current sources 1-5, and voltage test pad 61 are located in the first layer. The other metal interconnects 3, current sources 2-5, and voltage test pad 62 on the other side are interconnected via a via structure 4 in the second layer, forming a cross-layer structure. Figures 21-(a) to 21-(d) As shown.

[0227] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0228] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0229] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0230] The monitoring structure is a ring-shaped metal wire that surrounds the test line. One side is connected through a cross-layer via structure and is connected to a leakage current detection pad 9 through a cross-layer interconnect. The purpose is to monitor whether there is leakage current or even short circuit between interconnects due to the accumulation of metal atoms in the interconnects causing the interconnects to grow tendrils laterally.

[0231] The effective length of the ring monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the ring monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line. The spacing between the ring monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0232] Other metal interconnects 3 used for interconnection and detection include metal interconnects 3 and voltage detection lines 8, as shown in Figure 21-(a).

[0233] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0234] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0235] In this invention, the metallized through-hole interconnect structure 4 is a single-sided through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0236] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 22 As shown.

[0237] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0238] The design rules for the cross-layer through holes in the ring monitoring line structure 2 follow the rules mentioned above.

[0239] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0240] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0241] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0242] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 7:

[0243] Please see Figures 23-26 As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad 6 and a ring monitoring line. It can be decomposed into five structural elements: a metallized test line 1, a monitoring line structure 2, other metal interconnects 3, a through-hole interconnect structure 4, and a large-area metallized test pad. Specifically, the metallized test line 1 is used for testing electromigration effects; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 23 As shown.

[0244] This invention comprises two metal layers. The metallized test line 1, other metal interconnects 3 on one side, the monitoring line structure 2, current sources 1-5, and voltage test pad 61 are located in the first layer. The other metal interconnects 3, current sources 2-5, and voltage test pad 62 on the other side are interconnected via a via structure 4 in the second layer, forming a cross-layer structure. Figures 24-(a) to 24-(d) As shown.

[0245] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0246] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0247] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0248] The monitoring structure is a ring-shaped metal wire that surrounds the test line. One side is connected through a cross-layer via structure and is connected to a leakage current detection pad 9 through a cross-layer interconnect. The purpose is to monitor whether there is leakage current or even short circuit between interconnects due to the accumulation of metal atoms in the interconnects causing the interconnects to grow tendrils laterally.

[0249] The effective length of the ring monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the ring monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line. The spacing between the ring monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0250] Other metal interconnects 3 used for interconnection and detection include metal interconnects 3 and voltage detection lines 8, as shown in Figure 24-(a).

[0251] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0252] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0253] In this invention, the metallized through-hole interconnect structure 4 is a single-sided through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0254] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 26 As shown.

[0255] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0256] The design rules for the cross-layer through holes in the ring monitoring line structure 2 follow the rules mentioned above.

[0257] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0258] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0259] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0260] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 8:

[0261] Please see Figures 27-30 As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with three-sided voltage test pads 6 and current sources 5 connected by a ring monitoring line. It can be decomposed into five structural elements: a metallized test line 1, a monitoring line structure 2, other metal interconnects 3, a through-hole interconnect structure 4, and a large-area metallized test pad. Specifically, the metallized test line 1 is used for testing electromigration effects; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 27 As shown.

[0262] This invention relates to a two-layer metal structure, wherein the metallized test line 1, metal interconnect line 3, monitoring line structure 2, and current source 1-5 are located in the first layer, and the dual-sided voltage detection line 8, current source 2-5, and voltage test pad 6 are located in the second layer through a single via interconnect structure 4, forming a cross-layer structure, as shown below. Figures 28-(a) to 28-(g) As shown.

[0263] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0264] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0265] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0266] The monitoring structure is a ring-shaped metal wire that surrounds the test line. One side is connected through a cross-layer via structure and is connected to a leakage current detection pad 9 through a cross-layer interconnect. The purpose is to monitor whether there is leakage current or even short circuit between interconnects due to the accumulation of metal atoms in the interconnects causing the interconnects to grow tendrils laterally.

[0267] The effective length of the ring monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the ring monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the ring monitoring line should not be less than the width of the ring monitoring line. The spacing between the ring monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0268] Other metal interconnects 3 used for interconnection and detection include test line interconnect segments, metal interconnects 3, and voltage detection lines 8, such as Figure 29 As shown.

[0269] The width of the interconnect segment of the test line is twice the length of the metallized test line 1. The length must meet the requirement that the ratio of the length of the metallized test line 1 to the length of the metallized test line 1 plus the interconnect segments of the test lines at both ends is greater than or equal to 95% and less than or equal to 8μm.

[0270] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0271] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0272] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0273] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 30 As shown.

[0274] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0275] The design rules for the cross-layer through holes in the ring monitoring line structure 2 follow the rules mentioned above.

[0276] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0277] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0278] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0279] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 9:

[0280] Please see Figures 31-35 As shown: This invention provides an electromigration test structure, which is a cross-layer type with double-sided voltage test pads 6 and a monitoring structure. It can be decomposed into five structural elements: a metallized test line 1, a monitoring line structure 2, other metal interconnects 3, a via interconnect structure 4, and a large-area metallized test pad. The metallized test line 1 is used for testing electromigration effects; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the other metal interconnects 3 are used for interconnection and detection; the via interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 31 As shown.

[0281] This invention relates to a two-layer metal structure, wherein the metallized test line 1, the metal interconnect line 3, the dual-sided current source 5, and the monitoring line structure 2 are located in the first layer, and the dual-sided voltage detection line 8 and the voltage lead are interconnected to the second layer through vias, forming a cross-layer structure, as shown below. Figure 31 , Figures 32-(a) to 32-(d) As shown.

[0282] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0283] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0284] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0285] The monitoring structure consists of two metal lines parallel to the metal test line, connected to two leakage current detection pads 9 via interconnects; or a ring-shaped metal line encircling the test line, connected via a cross-layer via structure, and connected to a leakage current detection pad 9 via interconnects, as shown below. Figure 31 , Figure 33 As shown. The purpose is to monitor whether the accumulation of metal atoms in the interconnects causes lateral growth of tendrils, which in turn leads to leakage current or even short circuits between the interconnects.

[0286] The effective length of the monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line. The spacing between the monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0287] Other metal interconnects 3 used for interconnection and detection include test line interconnect segments, metal interconnects 3, and voltage detection lines 8, such as Figure 34 As shown.

[0288] The width of the interconnect segment of the test line is twice the length of the metallized test line 1. The length must meet the requirement that the ratio of the length of the metallized test line 1 to the length of the metallized test line 1 plus the interconnect segments of the test lines at both ends is greater than or equal to 95% and less than or equal to 8μm.

[0289] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0290] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0291] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0292] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 35 As shown.

[0293] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0294] The design rules for the cross-layer through holes in the ring monitoring line structure 2 follow the rules mentioned above.

[0295] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0296] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0297] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0298] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 10:

[0299] Please see Figures 36-39As shown: This invention provides an electromigration test structure, which is a multi-layer type with IV leads and parallel monitoring lines. It can be decomposed into four structural elements: a metallized test line 1, other metal interconnects 3, a via interconnect structure 4, and a large-area metallized test pad. The metallized test line 1 is used for testing electromigration effects; the other metal interconnects 3 are used for interconnection and detection; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the via interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input and voltage reading. Figure 36 As shown.

[0300] This invention comprises two metal layers, wherein the metallized test line 1 and the monitoring line structure 2 are located in the first layer, and the current source 5, the voltage lead, and other metal interconnects 3 are interconnected to the second layer through vias, forming a cross-layer structure, such as... Figure 36 , Figures 37-(a) to 37-(d) As shown.

[0301] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0302] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0303] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0304] The monitoring structure consists of two metal lines parallel to the metal test lines, connected to two leakage current detection pads 9 via interconnects, such as... Figure 36 As shown. The purpose is to monitor whether the accumulation of metal atoms in the interconnects causes lateral growth of tendrils, which in turn leads to leakage current or even short circuits between the interconnects.

[0305] The effective length of the monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line. The spacing between the monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0306] Other metal interconnects 3 used for interconnection and detection include metallized interconnects and voltage sensing lines 8, such as Figure 38 As shown.

[0307] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0308] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0309] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0310] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 39 As shown.

[0311] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0312] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0313] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0314] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0315] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 11:

[0316] Please see Figures 40-42As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad 6 and a current source 5 with parallel monitoring lines. It can be decomposed into five structural elements: a metallized test line 1, a monitoring line structure 2, other metal interconnects 3, a through-hole interconnect structure 4, and a large-area metallized test pad. Specifically, the metallized test line 1 is used for testing electromigration effects; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 40 As shown.

[0317] This invention comprises two metal layers. The metallized test line 1, other metal interconnects 3 on one side, the monitoring line structure 2, current sources 1-5, and voltage test pads 61 are located in the first layer. The other metal interconnects 3, current sources 2-5, and voltage test pads 62 on the other side are connected via vias 4 in the second layer, forming a cross-layer structure. Figures 41-(a) to 41-(d) As shown.

[0318] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0319] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0320] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0321] The monitoring structure consists of two metal lines parallel to the metal test lines, connected to two leakage current detection pads 9 via interconnects, such as... Figure 40 As shown. The purpose is to monitor whether the accumulation of metal atoms in the interconnects causes lateral growth of tendrils, which in turn leads to leakage current or even short circuits between the interconnects.

[0322] The effective length of the monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line. The spacing between the monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0323] Other metal interconnects 3 used for interconnection and detection include metal interconnects 3 and voltage detection lines 8, as shown in Figure 41-(a).

[0324] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0325] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0326] In this invention, the metallized through-hole interconnect structure 4 is a single-sided through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0327] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 42 As shown.

[0328] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0329] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0330] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0331] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0332] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 12:

[0333] Please see Figures 43-46 As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with a single-sided voltage test pad 6 and parallel monitoring lines. It can be decomposed into five structural elements: a metallized test line 1, a monitoring line structure 2, other metal interconnects 3, a through-hole interconnect structure 4, and a large-area metallized test pad. Specifically, the metallized test line 1 is used for testing electromigration effects; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 43 As shown.

[0334] This invention comprises two metal layers. The metallized test line 1, other metal interconnects 3 on one side, the monitoring line structure 2, current sources 1-5, and voltage test pads 61 are located in the first layer. The other metal interconnects 3, current sources 2-5, and voltage test pads 62 on the other side are connected via vias 4 in the second layer, forming a cross-layer structure. Figures 44-(a) to 44-(d) As shown.

[0335] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0336] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0337] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0338] The monitoring structure consists of two metal lines parallel to the metal test lines, connected to two leakage current detection pads 9 via interconnects, such as... Figure 43 As shown. The purpose is to monitor whether the accumulation of metal atoms in the interconnects causes lateral growth of tendrils, which in turn leads to leakage current or even short circuits between the interconnects.

[0339] The effective length of the monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line. The spacing between the monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0340] Other metal interconnects 3 used for interconnection and detection include metal interconnects 3 and voltage detection lines 8, as shown in Figure 44-(a).

[0341] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0342] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0343] In this invention, the metallized through-hole interconnect structure 4 is a single-sided through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0344] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 46 As shown.

[0345] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0346] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0347] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0348] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0349] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other. Example 13:

[0350] Please see Figures 47-50 As shown: This invention provides an electromigration test structure, which is a through-hole cross-layer type with three-sided voltage test pads 6 and current sources 5 with parallel monitoring lines. It can be decomposed into five structural elements: metallized test lines 1, monitoring line structure 2, other metal interconnects 3, through-hole interconnect structure 4, and a large-area metallized test pad. Specifically, the metallized test lines 1 are used for testing electromigration effects; the monitoring line structure 2 is used for monitoring leakage current or short circuits; the other metal interconnects 3 are used for interconnection and detection; the through-hole interconnect structure 4 is used for interconnection between different layer structures; and the large-area metallized test pad is used for current input, voltage reading, and monitoring of leakage current or short circuits. Figure 47 As shown.

[0351] This invention relates to a two-layer metal structure, wherein the metallized test line 1, the metal interconnect line 3, and the current source 1-5 are located in the first layer, and the dual-sided voltage detection line 8, the current source 2-5, and the voltage test pad 6 are located in the second layer through a single via interconnect structure 4, forming a cross-layer structure, as shown below. Figures 48-(a) to 48-(g) As shown.

[0352] Metallized test line 1 is a long metallized resistor strip designed on the oxide layer. The cross-sectional area of ​​the resistor strip needs to be kept uniform in order to ensure that the test line has a nearly uniform temperature before obvious voids are formed.

[0353] Metallization test line 1 typically requires two linewidth designs: a fixed linewidth of 2 μm and a minimum linewidth conforming to the product's process line design rules, determined by the rules being evaluated and validated. It is also important to note that the linewidth should be greater than the average size of the metal grains in metallization test line 1.

[0354] The length of the metallization test line 1 must be greater than or equal to 800 μm. This is to better characterize the metallization electromigration effect, avoid the short-line effect and thermal interference between the two current pads, and ensure that the metallization test line 1 has an approximately uniform temperature distribution before obvious voids are formed.

[0355] The monitoring structure consists of two metal lines parallel to the metal test lines, connected to two leakage current detection pads 9 via interconnects, such as... Figure 47 As shown. The purpose is to monitor whether the accumulation of metal atoms in the interconnects causes lateral growth of tendrils, which in turn leads to leakage current or even short circuits between the interconnects.

[0356] The effective length of the monitoring line should not be less than the length of the uniform linewidth of metallization test line 1; the width of the monitoring line should be equal to the linewidth of metallization test line 1, using the minimum linewidth determined by the product process line design rules being evaluated and verified; the width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line. The spacing between the monitoring line and metallization test line 1 should also follow the minimum spacing determined by the product process line design rules being evaluated and verified.

[0357] Other metal interconnects 3 used for interconnection and detection include test line interconnect segments, metal interconnects 3, and voltage detection lines 8, such as Figure 49 As shown.

[0358] The width of the interconnect segment of the test line is twice the length of the metallized test line 1. The length must meet the requirement that the ratio of the length of the metallized test line 1 to the length of the metallized test line 1 plus the interconnect segments of the test lines at both ends is greater than or equal to 95% and less than or equal to 8μm.

[0359] The width of the metallized interconnect is twice the length of the metallized test line 1, and the length is greater than or equal to 80 μm.

[0360] The voltage detection line 8 has a line width less than or equal to the metallized test line 1, and a length greater than or equal to 80μm.

[0361] In this invention, the metallized through-hole interconnect structure 4 is a through-hole interconnect structure 4, and the voltage detection line 8 is led out from the middle position of the through hole.

[0362] The number of through holes is generally 1 to 10. When there is more than 1, an even number is usually chosen, and they are arranged in a 2×N array, such as... Figure 50 As shown.

[0363] The size of a single via is the minimum allowed by the design rules. The edge distance between the via and Metal 1 layer is the minimum allowed by the design rules. The edge distance between the via and Metal 2 layer is the minimum allowed by the design rules. The spacing between vias is the minimum allowed by the design rules.

[0364] To reduce the impact of the metallization layer of the current source pad and voltage pad on the electromigration of the metallized interconnect, the length and width of the metallized pad should be designed to be at least 5 times the width of the interconnect.

[0365] To facilitate probe contact or bonding, it is recommended that the design size of the current source 5 pad and the voltage test pad 6 be greater than or equal to 90μm × 90μm.

[0366] This invention is used to characterize the reliability of electromigration effects on the metallized test lead 1 and via of the tested process. During testing, current is applied across the current source 5, and the voltage across the metal lead is measured using an independent voltage loop to observe the change in resistance of the metal lead.

[0367] Directly measuring the voltage between PADs introduces unnecessary parasitic parameters. Voltage measurement also requires a current loop, but the current is extremely small, while the current in electromigration testing is much larger. Combining the voltage measurement loop with the current stress loop—that is, measuring voltage with a large current—would affect the accuracy of the voltage measurement. If the current is interrupted during the test before voltage measurement, the continuity of stress will be disrupted, leading to inaccurate test results. Therefore, the current loop and voltage loop in the electromigration testing process must be independent of each other.

[0368] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electromigration test structure, comprising a via-type multi-layer structure with three-sided voltage test pads and a current source connected by parallel monitoring lines, characterized in that, It contains five structural elements: metallized test lines, monitoring line structure, other metal interconnects, through-hole interconnect structure, and large-area metallized test pads; it contains two metal layers, in which the metallized test lines, metal interconnects, and current source 1 are located in the first layer, and the dual-sided voltage detection lines, current source 2, and voltage test pads are located in the second layer through a single through-hole interconnect structure, forming a cross-layer structure; The number of through holes is 1 to 10. When there is more than 1, an even number is used and they are arranged in a 2×N array. The monitoring line structure consists of two metal lines parallel to the metal test line, connected to two leakage current detection pads via interconnects. The effective length of the monitoring line should not be less than the length of the uniform linewidth of the metallized test line. The width of the monitoring line should be equal to the linewidth of the metallized test line, using the minimum linewidth determined by the product process line design rules being evaluated and verified. The width of the lead-out line of the monitoring line should not be less than the width of the parallel monitoring line. The spacing between the monitoring line and the metallized test line also follows the minimum spacing determined by the product process line design rules being evaluated and verified.

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