Three-dimensional memory devices and methods for forming the same

Abstract

A 3D memory device includes a memory stack having alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel in the second portion of the channel structure.

Description

[0001] This application is a divisional application of Chinese patent application No. 202080003907.7, filed on November 13, 2020. Background Technology

[0002] This disclosure relates to three-dimensional (3D) storage devices and methods for manufacturing the same.

[0003] Improvements in process technology, circuit design, programming algorithms, and manufacturing processes have enabled planar memory cells to be shrunk to even smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar fabrication and manufacturing technologies become more difficult and costly. Therefore, the storage density of planar memory cells is approaching its upper limit.

[0004] 3D memory architecture can overcome the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals traveling to and from the memory array. Summary of the Invention

[0005] This article discloses embodiments of 3D storage devices and methods for forming the same.

[0006] In one example, a 3D memory device includes a memory stack having alternating stacked conductive and dielectric layers, a semiconductor layer, and a channel structure extending perpendicularly through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel within the first portion of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel within the second portion of the channel structure.

[0007] In another example, a 3D memory device includes a semiconductor structure comprising a memory stack having alternating stacked conductive and dielectric layers, a semiconductor layer, and a channel structure extending perpendicularly through the memory stack into the semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The doping concentration of the semiconductor channel is greater at locations toward the source than at locations away from the source.

[0008] In another example, a method for forming a 3D memory device is disclosed. A semiconductor layer is formed on a substrate, and a stacked structure is formed on the semiconductor layer. A channel structure extending vertically through the stacked structure and the semiconductor layer is formed. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel located in a first portion of the channel structure (facing the semiconductor layer) is greater than a second doping concentration of a portion of the semiconductor channel located in a second portion of the channel structure (facing the stacked structure). The substrate and the portion of the memory film located in the first portion of the channel structure are removed, thereby exposing the portion of the semiconductor channel located in the first portion of the channel structure. A conductive layer is formed in contact with the semiconductor layer and the exposed portion of the semiconductor channel located in the first portion of the channel structure. Attached Figure Description

[0009] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0010] Figure 1A A side view of a cross-section of an exemplary 3D storage device according to some embodiments of the present disclosure is shown.

[0011] Figure 1B A side view of a cross section of another exemplary 3D storage device according to some embodiments of the present disclosure is shown.

[0012] Figure 2 An enlarged side view of cross-sections of various exemplary channel structures in a 3D storage device according to various embodiments of the present disclosure is shown.

[0013] Figure 3A-3L The present disclosure illustrates a fabrication process for forming an exemplary 3D storage device according to some embodiments thereof.

[0014] Figure 4 A flowchart illustrating an exemplary method for forming a 3D storage device according to some embodiments of the present disclosure is shown.

[0015] Figure 5 A flowchart is shown of an exemplary method for forming a channel structure in a 3D storage device according to some embodiments of the present disclosure.

[0016] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0017] Although specific configurations and arrangements have been discussed, it should be understood that the discussion is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure can be used in a wide variety of other applications.

[0018] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," and "some embodiments" in the specification indicates that the described embodiment may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0019] Generally, terms should be understood at least partly by their use in context. For example, the word "one or more" can be used, at least partly according to context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the words "a," "one," or "the" can be understood to convey either a singular or a plural usage, at least partly depending on the context. Furthermore, the word "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the existence of other factors that are not necessarily explicitly stated, again at least partly depending on the context.

[0020] It should be readily understood that the terms “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest terms. “On” means not only being directly on something, but also being contained on something with an intermediate feature or layer in between. “Above” or “on top of” means not only being contained above or on something, but also being above or on something without an intermediate feature or layer in between (i.e., being directly on something).

[0021] Furthermore, for ease of explanation, spatially relative terms such as "below," "below," "under," "above," and "above" may be used to describe the relationship of one element or feature to other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0022] The term "substrate" as used in this text refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be formed from non-conductive materials, such as glass, plastic, or sapphire wafers.

[0023] As used herein, the term "layer" can refer to a portion of material comprising a region of a certain thickness. A layer may extend over the entire underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located above, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor layers and contact layers (forming interconnect lines and / or vertical interconnect channel (via) contacts therein) and one or more dielectric layers.

[0024] As used herein, the term "nominal / nominally" refers to the expected or target value of a feature or parameter of a component or process operation set during the design phase of a product or process, along with a range of values ​​higher and / or lower than said expected value. This range may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term "around" means that a given value can vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, "around" can indicate that a given value can vary within, for example, 10-30% of that value (e.g., ±10%, ±20%, or 30% of that value).

[0025] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," e.g., NAND memory strings) situated on a laterally oriented substrate, such that the memory strings extend vertically relative to the substrate. The term "vertically" as used herein refers to a lateral surface nominally perpendicular to the substrate.

[0026] In some 3D memory devices (e.g., 3D NAND memory devices), semiconductor plugs are selectively grown to surround the sidewalls of the channel structure; this is known as sidewall selective epitaxial growth (SEG). Compared to another type of semiconductor plug formed at the bottom of the channel structure (e.g., bottom SEG), the formation of sidewall SEG avoids etching of the memory film and semiconductor channel at the bottom surface of the channel via (also known as SONO vias), thereby increasing the process window, especially when fabricating 3D NAND memory devices using advanced techniques, for example, when there are 90 or more levels for a multi-level architecture.

[0027] However, because intrinsic (pure, undoped) semiconductor materials (e.g., intrinsic polysilicon) are used to form the semiconductor channel, a relatively high barrier exists between the semiconductor channel and the sidewall SEG or the conductive layer in contact with the semiconductor channel, thereby introducing high contact resistance. The electrical performance of 3D memory devices can be affected by high contact resistance.

[0028] Various embodiments of the present disclosure provide 3D memory devices with reduced contact resistance and sheet resistance having semiconductor channels. In some embodiments, the semiconductor channel is locally in-situ doped such that the portion of the semiconductor channel forming the source contacts is highly doped to reduce barrier properties, while another portion of the semiconductor channel forming the memory cells remains undoped or lightly doped. In some embodiments, the portion of the channel structure not forming memory cells includes an additional extended structure (with highly doped polysilicon or silicon oxide) that acts as a dopant source, thereby in-situ doping the portion of the semiconductor channel in contact with the dopant source during the thermal process of fabricating the 3D memory device. In some embodiments, one end of each channel structure is opened from the back side to expose the doped portion of the corresponding semiconductor channel, and the 3D memory device further includes a conductive layer electrically connecting the exposed doped portions of the semiconductor channel to further reduce contact resistance and sheet resistance. Therefore, the electrical performance of the 3D memory device can be improved.

[0029] Figure 1A A side view of a cross-section of an exemplary 3D memory device 100 according to some embodiments of the present disclosure is shown. In some embodiments, the 3D memory device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are connected at a bonding interface 106 therebetween. Figure 1AAs shown, the first semiconductor structure 102 may include a substrate 101, which may include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), SOI, or any other suitable material.

[0030] The first semiconductor structure 102 of the 3D memory device 100 may include peripheral circuitry 108 on a substrate 101. It should be noted that, in Figure 1A The inclusion of x-axis and y-axis is to further illustrate the spatial relationships of components in a 3D memory device 100 having substrate 101. Substrate 101 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally along the x-direction (i.e., the lateral direction). As used herein, when the substrate is located in the lowest plane of the semiconductor device in the y-direction, whether a component (e.g., a layer or device) of the semiconductor device (e.g., 3D memory device 100) is "above," "above," or "below" another component (e.g., a layer or device) is determined along the y-direction (i.e., the vertical direction) relative to the substrate (e.g., substrate 101) of the semiconductor device. The same concepts will be used throughout this disclosure to describe spatial relationships.

[0031] In some embodiments, peripheral circuitry 108 is configured to control and sense the 3D memory device 100. Peripheral circuitry 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the 3D memory device 100, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of said circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 108 may include transistors formed "on" substrate 101, wherein all or part of the transistors are formed within semiconductor layer 101 (e.g., below the top surface of substrate 101) and / or directly on substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of transistors) may also be formed within substrate 101. According to some embodiments, transistors are high-speed thanks to advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). It should be understood that in some embodiments, peripheral circuitry 108 may further include any other circuitry compatible with advanced logic processes, including logic circuitry such as processors and programmable logic devices (PLDs) or memory circuitry such as static random access memory (SRAM) and dynamic RAM (DRAM).

[0032] In some embodiments, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuitry 108 to transmit electrical signals to and from the peripheral circuitry 108. The interconnect layer may include multiple interconnects (also referred to herein as contacts) including lateral interconnects and vertical interconnect access (via) contacts. As used herein, the term “interconnect” may broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-process (BEOL) interconnects. The interconnect layer may further include one or more interlayer dielectric (ILD) layers (also referred to as intermetallic dielectric (IMD) layers) within which the interconnects and via contacts may be formed. That is, the interconnect layer may include interconnects and via contacts within multiple ILD layers. The interconnects and via contacts within the interconnect layer may be encapsulated in a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof.

[0033] like Figure 1A As shown, the first semiconductor structure 102 of the 3D memory device 100 may further include a bonding layer 110 located at the bonding interface 106 and above the interconnect layer and peripheral circuitry 108. The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric material electrically isolating the bonding contacts 111. The bonding contacts 111 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 110 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 111 in the bonding layer 110 and the surrounding dielectric material may be used for hybrid bonding.

[0034] Similarly, such as Figure 1A As shown, the second semiconductor structure 104 of the 3D memory device 100 may further include a bonding layer 112 located at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 may include a plurality of bonding contacts 113 and a dielectric material electrically isolating the bonding contacts 113. The bonding contacts 113 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining regions of the bonding layer 112 may be formed using a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 113 in the bonding layer 112 and the surrounding dielectric material may be used for mixed bonding. According to some embodiments, the bonding contacts 113 are in contact with the bonding contacts 111 at the bonding interface 106.

[0035] As detailed below, the second semiconductor structure 104 can be bonded to the top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 110 and 112 as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where the bonding layers 112 and 110 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness comprising the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0036] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 to transmit electrical signals. This interconnect layer may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may further include one or more ILD layers, within which interconnect lines and via contacts may be formed. The interconnect lines and via contacts within the interconnect layer may be encapsulated in a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0037] In some embodiments, the 3D memory device 100 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings. Figure 1A As shown, the second semiconductor structure 104 of the 3D memory device 100 may include an array of channel structures 124 that function as an array of NAND memory strings. Figure 1AAs shown, each channel structure 124 extends vertically through multiple pairs, each pair comprising a stacked conductive layer 116 and a stacked dielectric layer 118. Alternating stacked conductive layers 116 and stacked dielectric layers 118 form part of a storage stack 114. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 within the storage stack 114 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D storage device 100. It should be understood that in some embodiments, the storage stack 114 may have a multi-level architecture (not shown) comprising multiple storage levels stacked one on top of the other. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 within each storage level may be the same or different.

[0038] The memory stack 114 may include a plurality of alternating stacked conductive layers 116 and stacked dielectric layers 118. The stacked conductive layers 116 and stacked dielectric layers 118 in the memory stack 114 may alternate in the vertical direction. In other words, except for the layers located at the top or bottom of the memory stack 114, each stacked conductive layer 116 may be adjacent to two stacked dielectric layers 118 on both sides, and each stacked dielectric layer 118 may be adjacent to two stacked conductive layers 116 on both sides. The stacked conductive layers 116 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each stacked conductive layer 116 may include a gate electrode (gate line) surrounded by a binder / barrier layer and a gate dielectric layer. The gate electrode of the stacked conductive layer 116 may extend laterally as a word line, terminating at one or more stepped structures of the memory stack 114. The stacked dielectric layers 118 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0039] like Figure 1A As shown, the second semiconductor structure 104 of the 3D memory device 100 may further include a semiconductor layer 120 above the memory stack 114. The semiconductor layer 120 may include a semiconductor material, such as silicon. In some embodiments, the semiconductor layer 120 includes polycrystalline silicon formed by a deposition technique, as detailed below. In some embodiments, the semiconductor layer 120 is doped to a desired doping concentration to reduce its sheet resistance. The semiconductor layer 120 may be doped with any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and improve the conductivity of the intrinsic semiconductor. For example, the semiconductor layer 120 may include N-type doped polycrystalline silicon.

[0040] In some embodiments, each channel structure 124 includes a channel via filled with a semiconductor layer (e.g., as a semiconductor channel 128) and a composite dielectric layer (e.g., as a storage film 126). In some embodiments, the semiconductor channel 128 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the storage film 126 is a composite layer including a tunnel layer, a reservoir layer (also referred to as a "charge trapping layer"), and a barrier layer. The remaining space of the channel structure 124 may be partially or entirely filled with a capping layer 160 including a dielectric material (e.g., silicon oxide) and / or air gaps. The channel structure 124 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the capping layer 160, the semiconductor channel 128, and the tunnel layer, reservoir layer, and barrier layer of the storage film 126 are arranged radially from the center of the column to the outer surface of the column in this order. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The reservoir layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the storage film 126 may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0041] In some embodiments, the channel structure 124 further includes a channel plug 151 located in the bottom portion of the channel structure 124 (e.g., at the lower end). As used herein, when the substrate 101 is placed in the lowest plane of the 3D memory device 100, the “upper end” of the component (e.g., the channel structure 124) is the end farther from the substrate 101 in the y-direction, and the “lower end” of the component (e.g., the channel structure 124) is the end closer to the substrate 101 in the y-direction. The channel plug 151 may include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 151 functions as the drain of a NAND flash memory string.

[0042] like Figure 1A As shown, each channel structure 124 can extend vertically through the alternating stacked conductive layers 116 and stacked dielectric layers 118 of the memory stack 114 into the semiconductor layer 120. The upper end of each channel structure 124 can be below the top surface of the semiconductor layer 120. That is, according to some embodiments, the channel structure 124 does not extend beyond the top surface of the semiconductor layer 120. Although in Figure 1A Not shown in the side view, but it should be understood that the semiconductor layer 120 may be a laterally extending continuous layer, and each channel structure 124 may be surrounded by the semiconductor layer 120 in the plan view. In some embodiments, the upper end of the storage film 126 is below the upper end of the semiconductor channel 128 within the channel structure 124 and below the top surface of the semiconductor layer 120, such as... Figure 1A As shown.

[0043] Also refer to Figure 2Enlarged side view of various examples of the channel structure 124, which may include two parts: one facing the semiconductor layer 120 (e.g., as shown in the image). Figure 1A The first part 124-1 (as shown) and the part facing the storage stack (e.g., as shown) Figure 1A The second portion 124-2 (shown in the diagram). For example, the first portion 124-1 of the channel structure 124 may be surrounded by the semiconductor layer 120 (e.g., vertically between the top and bottom surfaces of the semiconductor layer 120). In some embodiments, in the channel structure 124, the lateral dimension (e.g., diameter) of the first portion 124-1 is larger than the lateral dimension (e.g., diameter) of the second portion 124-2 of the channel structure 124. For example, the shape of the channel structure 124 can be considered as two concentric cylinders (pillars) connected together with different diameters. In some embodiments, the first portion 124-1 of the channel structure 124 further includes an enlarged structure 127 in contact with the semiconductor channel 128. For example, in the first portion 124-1 of the channel structure 124, the enlarged structure 127 may be laterally sandwiched between the semiconductor channel 128 and the cap layer 160. According to some embodiments, the lateral dimension of the first portion 124-1 becomes larger than the lateral dimension of the second portion 124-2 because an enlargement structure 127 exists in the first portion 124-1 of the channel structure 124 but not in the second portion 124-2.

[0044] As detailed in the fabrication process below, the enlarged structure 127 can function as a dopant source for local in-situ doping of the semiconductor channel 128 during the fabrication process of the 3D memory device 100. According to the scope of this disclosure, the material and / or shape of the enlarged structure 127 can vary, as long as the dopant can diffuse from the enlarged structure 127 to the semiconductor channel 128 during the fabrication process. In one embodiment, for example, the enlarged structure 127 may comprise the same material as the semiconductor channel 128, such as polysilicon (e.g., ...). Figure 2 (127A and 127B in the example). In another embodiment, for example, a material different from semiconductor channel 128 may be included, such as silicon oxide (e.g., ...). Figure 2 (e.g., 127C, 127D, and 127E). For example, the enlarged structure 127 may also contain seams or other defects therein (e.g., Figure 2 127A and 127D in the above), or both the enlarged structure 127 and the cap layer 160 may contain seams or other defects therein (e.g., Figure 2(127B and 127E in the example). It should be understood that in examples where the extended structure 127 and the semiconductor channel 128 have the same material (e.g., polycrystalline silicon), the interface and boundary between the extended structure 127 and the semiconductor channel 128 may become indistinguishable and thus unrecognizable in the final product of the 3D memory device 100.

[0045] According to some embodiments, portions of the semiconductor channel 128 are doped with dopant from a doping source (i.e., the expanded structure 127 in the first portion 124-1 of the channel structure 124) due to local in-situ doping from the doping source. As the dopant diffuses from the expanded structure 127 to the portions of the semiconductor channel 128 that contact the expanded structure 127 in the first portion 124-1 of the channel structure 124 (and may further diffuse to the portions of the semiconductor channel 128 in the second portion 124-2 of the channel structure 124), the doping concentration distribution in the semiconductor channel 128 may exhibit a difference in doping concentration between the first portion 124-1 and the second portion 124-2 of the channel structure 124. In some embodiments, the doping concentration of the portion of the semiconductor channel 128 in the first portion 124-1 of the channel structure 124 is greater than the doping concentration of the portion of the semiconductor channel 128 in the second portion 124-2 of the channel structure 124. In one embodiment, the doping concentration may be nominally uniform within the portion of the semiconductor channel 128 located within the first portion 124-1 of the channel structure 124. In another embodiment, the doping concentration may vary gradually within the portion of the semiconductor channel 128 located within the first portion 124-1 of the channel structure 124. It should be understood that in some examples, the diffusion of the dopant may be confined to the first portion 124-1 of the channel structure 124, so that the portion of the semiconductor channel 128 located within the second portion 124-2 of the channel structure 124 may still comprise intrinsic semiconductor, such as intrinsic polysilicon (i.e., with a nominal doping concentration of zero). In other examples, the portion of the semiconductor channel 128 located within the second portion 124-2 of the channel structure 124 and close to the first portion 124-1 is also doped (i.e., at a lower doping concentration than in the first portion 124-1), while the remaining portion of the semiconductor channel 128 within the second portion 124-2 (e.g., the portion forming the memory cells of a NAND memory string) can still comprise intrinsic semiconductor, such as intrinsic polysilicon. However, a decrease in doping concentration in the semiconductor channel 128 can be observed in the second portion 124-2 compared to the first portion 124-1 of the channel structure 124.

[0046] In some embodiments, the doped portion of the semiconductor channel 128 within the first portion 124-1 of the channel structure 124 comprises N-type doped polysilicon. The dopant can be any suitable N-type dopant, such as P, Ar, or Sb. In some embodiments, the doping concentration of the doped portion of the semiconductor channel 128 within the first portion 124-1 of the channel structure 124 is approximately 10. 19 cm -3 and about 10 21 cm -3 Between, for example, at 10 19 cm -3 and 10 21 cm -3 Between (e.g., 10) 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 8×10 19 cm -3 9×10 19 cm -3 10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 5×10 20 cm -3 6×10 20 cm -3 7×10 20 cm -3 8×10 20 cm -3 9×10 20 cm -3 10 21 cm -3The doping concentration of the expanded structure 127 (in the final product of the 3D memory device 100 after diffusion) is equal to or greater than the doping concentration of the doped portion of the semiconductor channel 128 located in the first portion 124-1 of the channel structure 124. That is, according to some embodiments, the doping concentration of the expanded structure 127 is not less than the doping concentration of the doped portion of the semiconductor channel 128 located in the first portion 124-1 of the channel structure 124. Accordingly, according to some embodiments, the doping concentration of the expanded structure 127 is greater than the doping concentration of the portion of the semiconductor channel 128 located in the second portion 124-2 of the channel structure 124. In other words, in some embodiments, the doping concentration of the semiconductor channel 128 is higher towards the source (e.g., the source corresponding to a NAND memory string) than away from the source. The doping concentration distribution described above can reduce the barrier, contact resistance, and sheet resistance at the doped portion of the semiconductor channel 128 located in the first portion 124-1 of the channel structure 124 (which realizes the electrical connection for the source of the NAND memory string) without changing the intrinsic properties of the other portion of the semiconductor channel 128 that forms the memory cell of the NAND memory string.

[0047] like Figure 1A As shown, in some embodiments, the second semiconductor structure 104 of the 3D memory device 100 may further include a conductive layer 122, which is located above and in contact with the semiconductor layer 120, and is located above and in contact with the doped portion of the semiconductor channel 128 in the first portion 124-1 of the channel structure 124. The conductive layer 122 may electrically connect multiple channel structures 124. Although Figure 1A Not shown in the side view, but it should be understood that the conductive layer 122 may be a continuous conductive layer in contact with the plurality of channel structures 124 and the semiconductor layer 120. Therefore, the conductive layer 122 and the semiconductor layer 120 may together provide electrical connections between the sources of an array of NAND memory strings in the same block, i.e., provide an array common source (ACS). In some embodiments, the conductive layer 122 includes two portions laterally: a first portion on the semiconductor layer 120 (outside the region of the channel structure 124) and a second portion (within the region of the channel structure 124) in contact with a doped portion of the semiconductor channel 128 located in the first portion 124-1 of the channel structure 124. That is, according to some embodiments, at least a portion (i.e., the first portion) of the conductive layer 122 is on the semiconductor layer 120. According to some embodiments, the remaining portion (i.e., the second portion) of the conductive layer 122 surrounding the first portion 124-1 of each channel structure 124 extending into the semiconductor layer 120 is in contact with the doped portion of the semiconductor channel 128.

[0048] In some embodiments, the conductive layer 122 comprises a plurality of layers in the vertical direction, including a metal silicide layer 121 and a metal layer 123 situated above and in contact with the metal silicide layer 121. Each of the metal silicide layer 121 and the metal layer 123 may be a continuous film. The metal silicide layer 121 may be situated above and in contact with the semiconductor layer 120 (within a first portion of the conductive layer 122) and may be situated above and in contact with a first portion 124-1 of the channel structure 124 (within a second portion of the conductive layer 122). In some embodiments, a portion of the metal silicide layer 121 surrounds and contacts a doped portion of the semiconductor channel 128 within the first portion 124-1 of the channel structure 124, thereby establishing an electrical connection with the plurality of channel structures 124. The metal silicide layer 121 may include metal silicides such as copper silicide, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, silver silicide, aluminum silicide, gold silicide, platinum silicide, any other suitable metal silicide, or any combination thereof. In some embodiments where the semiconductor channel 128 comprises polysilicon, contact between the metal silicide layer 121 and a doped portion of the semiconductor channel 128 may further reduce the contact resistance therebetween. According to some embodiments, a metal layer 123 is positioned above and in contact with the metal silicide layer 121. The metal layer 123 may include metals such as W, Co, Cu, Al, nickel (Ni), titanium (Ti), any other suitable metal, or any combination thereof. It should be understood that the metal in the metal layer 123 may also broadly comprise any suitable conductive metal compound and metal alloy, such as titanium nitride (TiN) and tantalum nitride (TaN), for example, as a binder / barrier layer therein. The metal layer 123 may further reduce the total resistance of the conductive layer 122.

[0049] Compared to known solutions that use only sidewall SEG-generated source contacts, forming a conductive layer 122 that contacts the doped portion of the semiconductor channel 128, in addition to the doped portion of the semiconductor channel 128, can further reduce (i.e., at the ACS of the NAND memory string in the same block) the resistance (e.g., contact resistance and sheet resistance) between the channel structures 124, thereby improving the electrical performance of the 3D memory device 100. Therefore, in order to maintain the same conductance / resistance between the channel structures 124, the thickness of the semiconductor layer 120 can be reduced, for example, to less than about 50 nm, for example, less than 50 nm. In some embodiments, the thickness of the semiconductor layer 120 is between approximately 10 nm and approximately 30 nm, for example, between 10 nm and 30 nm (e.g., 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, any range defined by the lower end and any of these values, or any range defined by any two of these values). The semiconductor layer 120, combined with the conductive layer 122 surrounding the first portion 124-1 of the channel structure 124, enables gate-induced drain leakage (GIDL) auxiliary body bias to facilitate operation of the 3D memory device 100. The GIDL surrounding the source-select gate of the NAND memory string generates hole currents flowing into the NAND memory string to increase the body potential for erase operations. In other words, according to some embodiments, the 3D storage device 100 is configured to generate a GIDL auxiliary body bias when performing an erase operation.

[0050] In some embodiments, the second semiconductor structure 104 further includes barrier structures 129, each of which surrounds a corresponding portion of the second portion 124-2 of the channel structure 124. As described in detail below, the barrier structure 129 may be the remainder of a barrier structure used during fabrication to define the lateral boundary of the first portion 124-1 of the channel structure 124. Therefore, the lateral dimension (e.g., inner diameter) of the barrier structure 129 may be nominally the same as the lateral dimension (e.g., diameter) of the first portion 124-1 of the channel structure 124. In some embodiments, the barrier structure 129 comprises silicon oxide.

[0051] like Figure 1A As shown, the second semiconductor structure 104 of the 3D memory device 100 may further include an insulating structure 130, each of which extends vertically through the alternating stacked conductive layers 116 and stacked dielectric layers 118 of the memory stack 114. The insulating structure 130 may further extend into the semiconductor layer 120, such as... Figure 1AAs shown in the diagram. It should be understood that in some embodiments, the insulating structure 130 may not extend into the semiconductor layer 120, i.e., its top surface may be flush with the bottom surface of the semiconductor layer 120. Each insulating structure 130 may also extend laterally, thereby dividing the memory stack 114 into multiple blocks. That is, the memory stack 114 may be divided into multiple memory blocks by the insulating structure 130, so that the array of channel structures 124 can be assigned to each memory block. Unlike the slit structures in some known 3D NAND memory devices that include front-side source contacts, according to some embodiments, the insulating structure 130 does not contain any contacts therein (i.e., does not function as source contacts), and therefore does not introduce parasitic capacitance and leakage current together with the stacked conductive layer 116 (including word lines). In some embodiments, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, silicon oxide may be used to fill each insulating structure 130.

[0052] The 3D storage device 100 will no longer have a front source contact, but may instead include a back source contact 132 located above the storage stack 114 and in contact with the conductive layer 122, such as... Figure 1A As shown. Source contacts 132 and storage stack 114 (and insulating structure 130 therethrough) can be disposed on opposite sides of semiconductor layer 120 and are thus considered “back” source contacts. In some embodiments, source contacts 132 are electrically connected to semiconductor channel 128 of channel structure 124 via conductive layer 122. It should be understood that in some examples, second semiconductor structure 104 may not include conductive layer 122, and source contacts 132 may be in direct contact with a doped portion of semiconductor channel 128 within a first portion 124-1 of channel structure 124, for example, when the doping concentration of this doped portion of semiconductor channel 128 is sufficiently high. It should also be understood that, although Figure 1A Each source contact 132 is laterally aligned with each channel structure 124, but the presence of a conductive layer 122 (e.g., a continuous conductive layer) allows the source contacts 132 to contact any portion of the conductive layer 122 without being laterally aligned with the channel structure 124. The source contacts 132 can include any suitable type of contact. In some embodiments, the source contacts 132 include VIA contacts. In some embodiments, the source contacts 132 include laterally extending wall-like contacts. The source contacts 132 can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive / barrier layer (e.g., TiN).

[0053] like Figure 1AAs shown, the 3D memory device 100 may further include a BEOL interconnect layer 133 located above and electrically connected to the source contact 132 to enable pad take-off, for example, thereby transmitting electrical signals between the 3D memory device 100 and external circuitry. In some embodiments, the interconnect layer 133 includes one or more ILD layers 134 on a conductive layer 122 (or a semiconductor layer 120 in the absence of a conductive layer 122) and a redistribution layer 136 on the ILD layers 134. According to some embodiments, the upper end of the source contact 132 is flush with the top surface of the ILD layer 134 and the bottom surface of the redistribution layer 136. The ILD layer 134 in the interconnect layer 133 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 in the interconnect layer 133 may contain a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the redistribution layer 136 may include Al. In some embodiments, interconnect layer 133 further includes a passivation layer 138 as the outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 may be exposed from the passivation layer 138 to form contact pads 140. That is, interconnect layer 133 of the 3D memory device 100 may also include contact pads 140 for wire bonding and / or bonding with interposers.

[0054] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 extending through the ILD layer 134. In some embodiments, contact 142 extends through the ILD layer 134 to contact the redistribution layer 136, such that contact 142 is electrically connected to the semiconductor channel 128 of the channel structure 124 via the redistribution layer 136, source contact 132, and conductive layer 122. In some embodiments, contact 144 extends through the ILD layer 134 to contact contact pad 140. Each of contacts 142 and 144 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0055] In some embodiments, the 3D memory device 100 further includes peripheral contacts 146 and 148, each extending vertically outside the memory stack 114. Each peripheral contact 146 or 148 may have a depth greater than the depth of the memory stack 114, extending vertically from the bonding layer 112 through the semiconductor layer 120 in a peripheral region outside the memory stack 114. In some embodiments, peripheral contact 146 is below and in contact with contact 142, such that the source of the NAND memory string is electrically connected to peripheral circuitry 108 within the first semiconductor structure 102 at least through conductive layer 122, source contact 132, interconnect layer 133, contact 142, and peripheral contact 146. In some embodiments, peripheral contact 148 is below and in contact with contact 144, such that peripheral circuitry 108 within the first semiconductor structure 102 is electrically connected to contact pad 140 at least through contact 144 and peripheral contact 148 to enable pad take-off. Each of the peripheral contacts 146 and 148 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive / barrier layer (e.g., TiN). In some embodiments, the conductive layer 122 is located within the region of the storage stack 114, i.e., it does not extend laterally into the peripheral region, so that contacts 142 and 144 do not extend perpendicularly through the conductive layer 122 to contact peripheral contacts 148 and 144, respectively. In some embodiments, peripheral contacts 146 and 148 extend through a spacer structure 149 in the semiconductor layer 120 to electrically isolate them from the surrounding semiconductor layer 120. As described in the fabrication process below, the spacer structure 149 and the barrier structure 129 may be formed through the semiconductor layer 120 in the same process and comprise the same material, such as silicon oxide.

[0056] like Figure 1AAs shown, the 3D memory device 100 also includes various local contacts (also referred to as "C1") as part of an interconnect structure that directly contact structures within the memory stack 114. In some embodiments, these local contacts include channel local contacts 150, each channel local contact being below and contacting the lower end of a corresponding channel structure 124. Each channel local contact 150 may be electrically connected to bit line contacts (not shown) to implement bit line fan-out. In some embodiments, these local contacts further include word line local contacts 152, each word line local contact being below and contacting a corresponding stacked conductive layer 116 (including word lines) at a stepped structure of the memory stack 114 to implement word line fan-out. The local contacts (such as channel local contacts 150 and word line local contacts 152) may be electrically connected to the peripheral circuitry 108 of the first semiconductor structure 102 at least via bonding layers 112 and 110. Each of the local contacts (such as channel local contact 150 and word line local contact 152) may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu or Al) or a silicide layer surrounded by an adhesive / barrier layer (e.g., TiN).

[0057] Figure 1B A side view of a cross-section of another exemplary 3D storage device 103 according to some embodiments of the present disclosure is shown. (As described above) Figure 1A Similar to the 3D memory device 100, the 3D memory device 103 represents an example of a bonded 3D memory device, wherein a first semiconductor structure 102 including peripheral circuitry 108 and a second semiconductor structure 104 including a memory stack 114 and a channel structure 124 are separately formed and bonded face-to-face at a bonding interface 106. Figure 1A In the 3D memory device 100, the semiconductor structure 102, including the peripheral circuitry 108, is located below the second semiconductor structure 104, which includes the memory stack 114 and the channel structure 124. In contrast, Figure 1B The 3D memory device 103 includes a second semiconductor structure 104 disposed above the first semiconductor structure 102. It should be understood that, for ease of description, details of other identical structures in both 3D memory devices 103 and 100 may not be repeated.

[0058] like Figure 1B As shown, according to some embodiments, the second semiconductor structure 104 includes a memory stack 114, which includes alternating stacked conductive layers 116 and stacked dielectric layers 118. In some embodiments, the second semiconductor structure 104 further includes a semiconductor layer 120 located below and in contact with the memory stack 114. The semiconductor layer 120 may include N-type doped polysilicon to reduce its resistance. Figure 1BAs shown, the second semiconductor structure 104 of the 3D memory device 103 may further include channel structures 124, each channel structure 124 extending vertically through the memory stack 114 into the semiconductor layer 120. The channel structure 124 may include a memory film 126 and a semiconductor channel 128. In some embodiments, the lateral dimension of a first portion 124-1 of the channel structure 124 facing the semiconductor layer 120 is greater than the lateral dimension of a second portion 124-2 of the channel structure 124 facing the memory stack 114. The first portion 124-1 of the channel structure 124 may include an enlarged structure 127 in contact with the semiconductor channel 128. In some embodiments, the doping concentration of the portion of the semiconductor channel 128 located in the first portion 124-1 of the channel structure 124 is greater than the doping concentration of the portion of the semiconductor channel 128 located in the second portion 124-2 of the channel structure 124.

[0059] like Figure 1B As shown, the second semiconductor structure 104 may further include a conductive layer 122 located below and in contact with the semiconductor layer 120, and located below and in contact with the doped portion of the semiconductor channel 128 in the first portion 124-1 of the channel structure 124. In some embodiments, the conductive layer 122 includes a metal silicide layer 121 located below and in contact with the semiconductor layer 120 and the doped portion of the semiconductor channel 128, and a metal layer 123 located below and in contact with the metal silicide layer 121. In some embodiments, the second semiconductor structure 104 may further include an insulating structure 130 extending vertically through the memory stack 114 into the semiconductor layer 120.

[0060] like Figure 1B As shown, according to some embodiments, the back source contact 132 in the 3D memory device 100 is replaced by a front source contact 147 in the 3D memory device 103. The source contact 147 may be located above and in contact with the semiconductor layer 120, and the source contact 147 and the insulating structure 130 may be disposed on the same surface of the semiconductor layer 120, for example, on the front side. In some embodiments, the semiconductor layer 120 comprises N-type doped polysilicon to reduce its resistance. Therefore, the front source contact 147 can be electrically connected to the source of the NAND flash memory string, for example, the doped portion of the semiconductor channel 128 in the first portion 124-1 of the channel structure 124, through the semiconductor layer 120 and the conductive layer 122.

[0061] like Figure 1BAs shown, the first semiconductor structure 102 of the 3D memory device 103 may include peripheral circuitry 108 above the memory stack 114 in the second semiconductor structure 104, and a semiconductor layer 135 (e.g., a thinned substrate) above the peripheral circuitry 108. In some embodiments, the first semiconductor structure 102 may also include an ILD layer 137 on the semiconductor layer 135 and a passivation layer 139 on the ILD layer 137 for insulation and protection. The first semiconductor structure 102 may further include contact pads 141 above the semiconductor layer 135 and the ILD layer 137 for pad take-off, for example, for transmitting electrical signals between the 3D memory device 103 and external circuitry. In some embodiments, the first semiconductor structure 102 may further include contacts 145 (e.g., over-substrate contacts (TSCs)) that penetrate the semiconductor layer 135 and the ILD layer 137 and contact the contact pads 141.

[0062] although Figure 1A and Figure 1B Two exemplary 3D memory devices 100 and 103 are shown, but it should be understood that any other suitable architecture of the 3D memory device may be applied in this disclosure by changing the relative positions of the first semiconductor structure 102 and the second semiconductor structure 104, the use of the front source contact 147 or the back source contact 132, and the pad lead-out position (e.g., through the first semiconductor structure 102 and / or the second semiconductor structure 104), which will not be further elaborated here.

[0063] Figure 3A-3L The present disclosure illustrates a fabrication process for forming an exemplary 3D storage device according to some embodiments thereof. Figure 4 A flowchart of a method 400 for forming an exemplary 3D storage device according to some embodiments of the present disclosure is shown. Figure 3A-3L as well as Figure 4 Examples of 3D storage devices shown include Figure 1A The 3D storage device 100 shown is intended for... Figure 3A-3L as well as Figure 4 Described together. It should be understood that the operations shown in method 400 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a sequence different from the operations described. Figure 4 The execution is performed in the order shown.

[0064] refer to Figure 4 Method 400 begins with operation 402, in which a peripheral circuit is formed on a first substrate. The first substrate may be a silicon substrate. Figure 3IAs shown, multiple transistors are formed on a silicon substrate 350 using various processes, including but not limited to photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed within the silicon substrate 350 by ion implantation and / or thermal diffusion, serving as source and / or drain regions of transistors, for example. In some embodiments, isolation regions (e.g., STI) are also formed within the silicon substrate 350 by wet etching and / or dry etching, as well as thin film deposition. The transistors are capable of forming peripheral circuitry 352 on the silicon substrate 350.

[0065] like Figure 3I As shown, a bonding layer 348 is formed above the peripheral circuit 352. The bonding layer 348 may include bonding contacts electrically connected to the peripheral circuit 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; bonding contacts through the ILD layer are formed using wet etching and / or dry etching (e.g., reactive ion etching (RIE)) and subsequent one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0066] Method 400 proceeds to operation 404, such as Figure 4 As shown, in this operation, a semiconductor layer is formed above a second substrate, and a stacked structure is formed above the semiconductor layer. The semiconductor layer and the stacked structure can be formed on the front side of the second substrate on which a semiconductor device can be formed. The second substrate can be a silicon substrate. It should be understood that, since the second substrate may be removed from the final product, it can be a portion of a pseudo-wafer (e.g., a carrier substrate) made of any suitable material to reduce the cost of the second substrate; for example, the material can be glass, sapphire, plastic, silicon, and only a few examples are given here. According to some embodiments, the substrate is a carrier substrate. In some embodiments, the semiconductor layer comprises N-type doped polysilicon, and the stacked structure comprises a dielectric stack having alternating stacked dielectric layers and stacked sacrificial layers. It should be understood that, in some examples, the stacked structure can comprise a memory stack having alternating stacked dielectric layers (e.g., silicon oxide layers) and stacked conductive layers (e.g., polysilicon layers).

[0067] In some embodiments, a first isolation layer is formed between the second substrate and the semiconductor layer, and a second isolation layer is formed between the semiconductor layer and the stacked structure. That is, the semiconductor layer may be sandwiched between the first and second isolation layers. The first and second isolation layers may comprise silicon oxynitride or silicon nitride. In some embodiments, a barrier structure extending vertically through the second isolation layer and the semiconductor layer is formed. In some embodiments, a sacrificial layer is formed between the second substrate and the first isolation layer. The sacrificial layer may comprise two pad oxide layers (also referred to as buffer layers) and a stop layer sandwiched between the two pad oxide layers. In some embodiments, the stop layer comprises silicon oxynitride or silicon nitride, and each of the two pad oxide layers comprises silicon oxide.

[0068] like Figure 3A As shown, a sacrificial layer 303 is formed on a carrier substrate 302, a first isolation layer 305 is formed on the sacrificial layer 303, an N-type doped semiconductor layer 306 is formed on the first isolation layer 305, and a second isolation layer 307 is formed on the N-type doped semiconductor layer 306. The N-type doped semiconductor layer 306 may comprise a polysilicon layer doped with an N-type dopant such as P, As, or Sb. The sacrificial layer 303 may comprise any suitable sacrificial material that can be selectively removed later, and may be different from the material of the carrier substrate 302. In some embodiments, the sacrificial layer 303 is a composite dielectric layer having a stop layer 304 sandwiched between two pad oxide layers. As described in detail below, the stop layer 304 may act as a CMP / etch stop layer when the carrier substrate 302 is removed from the back side, and may therefore comprise any suitable material other than the material of the carrier substrate 302, such as silicon nitride or silicon oxynitride. When etching the channel via from the front, the isolation layers 305 and 307 sandwiching the N-type doped semiconductor layer 306 can act as etch stop layers, and therefore can include any suitable material with high etch selectivity (e.g., greater than about 5) relative to polysilicon (the material of the N-type doped semiconductor layer 306), such as silicon nitride or silicon oxynitride. It should be understood that in some examples, pad oxide layers (e.g., silicon oxide layers) can be formed between the carrier substrate 302 and the stop layer 304, and between the stop layer 304 and the first isolation layer 305, to relax stress between the different layers and avoid peeling.

[0069] According to some embodiments, to form the sacrificial layer 303, silicon oxide, silicon nitride, or silicon oxynitride and silicon oxide are sequentially deposited on the carrier substrate 302 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. According to some embodiments, to form the first isolation layer 305, silicon nitride or silicon oxynitride is deposited on the sacrificial layer 303 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, to form the N-type doped semiconductor layer 306, polysilicon is deposited on the first isolation layer 305 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, followed by doping the deposited polysilicon with an N-type dopant (such as P, As, or Sb) using ion implantation and / or thermal diffusion. In some embodiments, to form the N-type doped semiconductor layer 306, in-situ doping of N-type dopant such as P, As, or Sb is performed when polysilicon is deposited on the first isolation layer 305. According to some embodiments, in order to form the second isolation layer 307, silicon nitride or silicon oxynitride is deposited on the N-type doped semiconductor layer 306 using one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof.

[0070] like Figure 3B As shown, a barrier structure 309 is formed that extends vertically through the second isolation layer 307 and the N-type doped semiconductor layer 306. In some embodiments, the barrier structure 309 further extends into or through the first isolation layer 305. To form the barrier structure 309, a barrier opening (not shown) is first patterned using photolithography and etched through the second isolation layer 307 and the N-type doped semiconductor layer 306 using wet etching and / or dry etching (e.g., deep RIE (DRIE)). Subsequently, a dielectric layer (e.g., silicon oxide) is deposited using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to fill the barrier opening. A CMP process can be performed to remove excess dielectric layer on the second isolation layer 307, thereby planarizing the barrier structure 309. In some embodiments, a spacer structure 311 is formed in the same process used to form the barrier structure 309. The barrier structure 309 can be patterned and formed in the core array region that forms the channel structure, and the spacer structure 311 can be patterned and formed in the peripheral region that forms the peripheral contacts.

[0071] like Figure 3CAs shown, a dielectric stack 308 comprising multiple pairs of first dielectric layers (hereinafter referred to as "stacked sacrificial layers" 312) and second dielectric layers (hereinafter referred to as "stacked dielectric layers" 310, and together with the former referred to as "dielectric layer pairs") is formed on a second isolation layer 307 above an N-type doped semiconductor layer 306. According to some embodiments, the dielectric stack 308 comprises alternating stacked sacrificial layers 312 and stacked dielectric layers 310. The stacked dielectric layers 310 and stacked sacrificial layers 312 may be alternately deposited on the second isolation layer 307 to form the dielectric stack 308. In some embodiments, each stacked dielectric layer 310 comprises a layer of silicon oxide, and each stacked sacrificial layer 312 comprises a layer of silicon nitride. The dielectric stack 308 may be formed using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 3C As shown, a stepped structure can be formed on the edge of the dielectric stack 308. This stepped structure can be formed by performing multiple so-called "trimming-etching" cycles on the dielectric layer pairs of the dielectric stack 308 toward the carrier substrate 302. Due to the repeated trimming-etching cycles applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more sloping edges and a top dielectric layer pair shorter than the bottom dielectric layer pair, as shown. Figure 3C As shown.

[0072] Method 400 proceeds to operation 406, such as Figure 4 As shown, in this operation, a channel structure is formed that extends vertically through the stacked structure and the semiconductor layer. The channel structure may include a storage film and a semiconductor channel. In some embodiments, a first doping concentration of the portion of the semiconductor channel located in a first portion of the channel structure (facing the semiconductor layer) is greater than a second doping concentration of the portion of the semiconductor channel located in a second portion of the channel structure (facing the stacked structure). For example, Figure 5 A flowchart of an exemplary method 500 for forming a channel structure in a 3D memory device according to some embodiments of the present disclosure is shown. In operation 502, a channel hole extending vertically through the stacked structure, the second isolation layer, and the semiconductor layer is formed, the channel hole ending at the first isolation layer. In some embodiments, a first lateral dimension of the channel hole facing a first portion of the semiconductor layer is greater than a second lateral dimension of the channel hole facing a second portion of the stacked structure and the second isolation layer. According to some embodiments, to form the channel hole, an etching process is performed to create a channel hole extending vertically through the stacked structure, the second isolation layer, and the semiconductor layer and ending at the first isolation layer, and the etching of the first portion of the channel hole is stopped laterally by a barrier structure.

[0073] like Figure 3DAs shown, the channel via 313 is an opening that extends vertically through the dielectric stack 308, the second isolation layer 307, and the N-type doped semiconductor layer 306 and terminates at the first isolation layer 305. In some embodiments, a plurality of openings are formed such that each opening becomes a location for growing an individual channel structure 314 in a subsequent process. Each channel via may be laterally aligned with a corresponding barrier structure 309 and may include a first portion 313-1 facing the N-type doped semiconductor layer 306 and a second portion 313-2 facing the second isolation layer 307 and the dielectric stack 308. Figure 3D As shown, the dimensions of the first portion 313-1 of the channel hole 313 can be vertically defined by the first isolation layer 305 and the second isolation layer 307 (which stop the etching of the N-type doped semiconductor layer 306 in the vertical direction) and laterally defined by the barrier structure 309 (which stops the etching of the N-type doped semiconductor layer 306 in the lateral direction). In some embodiments, the lateral dimension (e.g., inner diameter) of the barrier structure 309 is larger than the lateral dimension of the second portion 313-2 of the channel hole 313, and thus the lateral dimension (e.g., diameter) of the first portion 313-1 is larger than the lateral dimension (e.g., diameter) of the second portion 313-2 of the channel hole 313.

[0074] In some embodiments, the fabrication process for forming the via 313 includes wet etching and / or dry etching, such as DRIE. According to some embodiments, etching of the via continues until the first isolation layer 305 is reached. In some embodiments, etching conditions, such as etching rate and time, can be controlled to ensure that each via 313 has reached and stopped at the first isolation layer 305, thereby minimizing the variability in the vias between the vias 313. In some embodiments, a second etching process is applied to laterally extend and enlarge the first portion 313-1 of the via 313 facing the N-type doped semiconductor layer 306. For example, a wet etchant comprising tetramethylammonium hydroxide (TMAH) can be applied through the via 313, thereby selectively etching the N-type doped semiconductor layer 306 (e.g., comprising polysilicon) using a wet etching process without damaging the first isolation layer 305 and the second isolation layer 307, which comprise materials different from those of the N-type doped semiconductor layer 306. The wet etching of the N-type doped semiconductor layer 306 can be laterally stopped by a barrier structure 309 (e.g., comprising silicon oxide). It should be understood that in some examples, the barrier structure 309 may not be formed, and the second etching process may be controlled (e.g., by controlling the etching time and / or etching rate) to enlarge and expand the first portion 313-1 of the channel hole 313 to the desired extent. However, according to some embodiments, after these etching processes, the channel hole 313 comprises two portions 313-1 and 313-2 with different lateral dimensions.

[0075] refer to Figure 5 In operation 504, a memory film and a semiconductor channel are sequentially formed along the sidewalls and bottom surface of the channel via. In some embodiments, to sequentially form the memory film and the semiconductor channel, layers composed of silicon oxide, silicon nitride, silicon oxide, and intrinsic polysilicon are sequentially deposited.

[0076] like Figure 3E As shown, a memory film comprising a barrier layer 317, a reservoir layer 316, and a tunnel layer 315, and a semiconductor channel 318 are subsequently formed along the sidewalls and bottom surface of the channel via 313 in the listed order. In some embodiments, the barrier layer 317, the reservoir layer 316, and the tunnel layer 315 may be deposited along the sidewalls and bottom surface of the channel via 313 in the listed order using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof to form the memory film. Subsequently, the semiconductor channel 318 may be formed by depositing a semiconductor material such as intrinsic polycrystalline silicon (e.g., pure undoped polycrystalline silicon) over the tunnel layer 315 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are deposited sequentially to form a barrier layer 317, a reservoir layer 316, a tunnel layer 315, and a semiconductor channel 318 of the storage film.

[0077] refer to Figure 5 In operation 506, a doped expansion structure is formed on a portion of the semiconductor channel located within a first portion of the channel via. In some embodiments, to form the doped expansion structure, a layer of polysilicon or silicon oxide is deposited on the semiconductor channel within the channel via, the polysilicon or silicon oxide layer is in-situ doped with a dopant, and the portion of the polysilicon or silicon oxide layer above the semiconductor channel within a second portion of the channel via is etched away. In some embodiments, the dopant is an N-type dopant, and the doping concentration of the doped expansion structure is approximately 10. 21 cm -3 and about 10 22 cm -3 between.

[0078] like Figure 3E As shown, a layer 351 made of polysilicon or silicon oxide is deposited over a semiconductor channel 318 within a channel via 313 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Figure 3E As shown, the deposition of layer 351 can be controlled, thereby in the first portion 313-1 of the channel via 313 in the semiconductor channel 318 (e.g., Figure 3DA layer 351 is deposited on the portion within the channel 313, and a second portion 313-2 of the channel 313 is deposited thereon (e.g., Figure 3D The layer 351 above the sidewall of the channel 313 does not seal the channel via 313. Layer 351 can be doped with an N-type dopant such as P, As, or Sb using ion implantation and / or thermal diffusion. In some embodiments, to form the doped layer 351, in-situ doping with an N-type dopant such as P, As, or Sb is performed when the layer 351, made of polysilicon or silicon oxide, is deposited (e.g., CVD) over the semiconductor channel 318 within the channel via 313. In some embodiments, the doping concentration of layer 351 (i.e., the initial doping concentration) is approximately 10. 21 cm -3 and about 10 22 cm -3 Between, for example, at 10 21 cm -3 and 10 22 cm -3 Between (e.g., 10) 21 cm -3 2×10 21 cm -3 3×10 21 cm -3 4×10 21 cm -3 5×10 21 cm -3 6×10 21 cm -3 7×10 21 cm -3 8×10 21 cm -3 9×10 21 cm -3 10 22 cm -3 The lower end is within any range defined by any of these values, or within any range defined by any two of these values.

[0079] like Figure 3FAs shown, a portion of layer 351 along the sidewall of the channel hole 313 (e.g., in the second portion 313-2) is removed, for example, by using wet etching or dry etching. In some embodiments, a wet etchant containing TMAH can be applied through the channel hole 313, thereby selectively removing this portion of layer 351 made of polysilicon using a wet etching process, or a wet etchant containing hydrofluoric acid can be applied through the channel hole 313, thereby selectively removing this portion of layer 351 made of silicon oxide using a wet etching process. It should be understood that the etching can also remove the portion of layer 351 located within the first portion 313-1 of the channel hole 313. However, according to some embodiments, after etching, the remaining portion of layer 351 in contact with the portion of semiconductor channel 318 located within the first portion 313-1 of the channel hole 313 becomes a doped expanded structure 319, such as... Figure 3F As shown. The initial doping concentration of the doped expansion structure 319 can be the same as the initial doping concentration of the doped layer 351.

[0080] refer to Figure 5 In operation 508, the dopant is diffused from the doped expansion structure into the semiconductor channel such that the first doping concentration of the portion of the semiconductor channel located within the first portion of the channel hole is greater than the second doping concentration of the portion of the semiconductor channel located within the second portion of the channel hole.

[0081] During any thermal process following the formation of the doped expansion structure 319, a dopant (e.g., P, As, or Sb) can diffuse from the doped expansion structure 319 to the semiconductor channel 318, thereby locally in-situ doping the semiconductor channel 318 (e.g., including polysilicon) with the same dopant as in the doped expansion structure 319. In some embodiments, since the doped expansion structure 319 contacts only the portion of the semiconductor channel 318 within the first portion 313-1 of the channel via 313, and not the other portion of the semiconductor channel 318 within the second portion 313-2 of the channel via 313, the doping concentration of the portion of the semiconductor channel 318 within the first portion 313-1 of the channel via 313 is greater than the doping concentration of the portion of the semiconductor channel 318 within the second portion 313-2 of the channel via 313. It should be understood that the post-diffusion doping concentration distribution can vary in different examples depending on the initial doping concentration of the doped expansion structure 319, the conditions of the thermal process, the structure of the semiconductor channel 318 and the doped expansion structure 319, etc. However, the intrinsic polysilicon within the first portion 313-1 of the channel via 313 in the semiconductor channel 318 can be replaced with doped polysilicon (e.g., as shown in the image). Figure 3G As shown in the figure, for example, it (after diffusion) has a value of approximately 10 19 cm -3 and about 10 21cm -3 Between, for example, at 10 19 cm -3 and 10 21 cm -3 The doping concentration varies between these values. Meanwhile, according to some embodiments, this localized in-situ doping of the semiconductor channel 318 does not alter the intrinsic properties of another portion of the semiconductor channel 318 located within the second portion 313-2 of the channel via 313, which will be formed as a portion of the memory cell. The doping concentration of the doped expansion structure 319 can decrease from its initial doping concentration after diffusion, but may still be higher than the doping concentration of the portion of the semiconductor channel 318 located within the second portion 313-2 of the channel via 313 due to residual dopant in the doped expansion structure 319.

[0082] It should be understood that no additional thermal process needs to be added to the fabrication process flow to allow the dopant to diffuse from the doped expansion structure 319 to the semiconductor channel 318. Instead, any existing process in the existing fabrication process flow that occurs after the formation of the doped expansion structure 319 can cause the dopant to diffuse, such as the various processes described above for illustrative purposes only.

[0083] like Figure 3G As shown, a capping layer 320 is formed within the channel via 313 and over the semiconductor channel 318 and the doped expansion structure 319 to completely or partially fill the channel via 313 (e.g., with or without air gaps). The capping layer 320 can then be formed by depositing a dielectric material such as silicon oxide using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Subsequently, a capping layer can be deposited on the top portion of the channel via 313 (e.g., as shown). Figure 3FA channel plug 321 is formed in the (shown) portion. In some embodiments, portions of the storage film, semiconductor channel 318, and capping layer 320 on the top surface of the dielectric stack 308 are removed and planarized by CMP, wet etching, and / or dry etching. A recess (not shown) is then formed in the upper end of the channel hole 313 by wet etching and / or dry etching of portions of the capping layer 320. A semiconductor material such as polysilicon can then be deposited using one or more thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof, thereby forming the channel plug 321. According to some embodiments, this forms a channel structure 314 that extends through the dielectric stack 308 and the second isolation layer 307 into the N-type doped semiconductor layer 306. The channel structure 314 may include a first portion (corresponding to the first portion 313-1 of the channel hole 313) facing the N-type doped semiconductor layer 306 and a second portion (corresponding to the second portion 313-2 of the channel hole 313) facing the dielectric stack 308 and the second isolation layer 307. The lateral dimension of the first portion of the channel structure 314 may be larger than the lateral dimension of its second portion.

[0084] Method 400 proceeds to operation 408, such as Figure 4 As shown, an insulating structure is formed during this process. In some embodiments, an opening is formed perpendicularly through the stacked structure, and the stacked structure is replaced through the opening with a memory stack comprising alternating stacked conductive layers and stacked dielectric layers, for example, using a so-called "gate replacement" process. The insulating structure may be formed within the opening. In some embodiments, to form the insulating structure, one or more dielectric materials are deposited into the opening after the memory stack is formed to fill the opening. It should be understood that in some examples where the stacked structure is a memory stack, the gate replacement process may be skipped.

[0085] like Figure 3H As shown, an insulating structure 336 is formed that extends vertically through the memory stack 330 and into the N-type doped semiconductor layer 306. In some embodiments, to form the insulating structure 336, a slit (not shown) is first formed, which is an opening extending vertically through the dielectric stack 308 and the second isolation layer 307. In some embodiments, the fabrication process for forming the slit includes wet etching and / or dry etching, such as DRIE.

[0086] Subsequently, a gate replacement process can be performed through this slit to replace the dielectric stack 08 with the memory stack 330. In some embodiments, the stack sacrificial layer 312 is first removed through this slit (e.g., Figure 3G(as shown in the diagram), thereby forming a lateral recess (not shown). In some embodiments, the lateral recesses are created by removing the stacked sacrificial layer 312 by applying an etchant through the slit, thereby creating alternating lateral recesses between the stacked dielectric layers 310. The etchant may include any suitable etchant that selectively etches the stacked sacrificial layer 312 relative to the stacked dielectric layer 310. In some embodiments where the second isolation layer 307 and the stacked sacrificial layer 312 comprise the same material (e.g., silicon nitride), at least a portion of the second isolation layer 307 is also removed to form the lateral recess. Subsequently, a stacked conductive layer (including a gate electrode and a binder layer) may be deposited into the lateral recess through the slit. In some embodiments, a gate dielectric layer is deposited into the lateral recess prior to the stacked conductive layer 328, thereby depositing the stacked conductive layer 328 on the gate dielectric layer. The stacked conductive layer 328, such as a metal layer, may be deposited using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, a gate dielectric layer, such as a high-k dielectric layer, is also formed along the sidewalls and bottom surface of the slit. According to some embodiments, this forms a memory stack 330 comprising alternating stacked conductive layers 328 and stacked dielectric layers 310, thereby replacing the dielectric stack 308 (e.g., as shown in the original text). Figure 3G (As shown in the diagram). It should be understood that in some examples, a stacked conductive layer 328 may be used instead of at least a portion of the second isolation layer 307 to form part of the storage stack 330.

[0087] Subsequently, one or more dielectric materials (e.g., silicon oxide) can be deposited into the slit using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to completely or partially fill the slit (with or without air gaps), thereby forming the insulating structure 336. In some embodiments, the insulating structure 336 includes a gate dielectric layer (e.g., including a high-k dielectric) and a dielectric capping layer (e.g., including silicon oxide).

[0088] like Figure 3HAs shown, after forming the insulating structure 336, local contacts including channel local contacts 334 and word line local contacts 342, as well as peripheral contacts 338 and 340, are formed. A local dielectric layer can be formed on the memory stack 330 by depositing a dielectric material (such as silicon oxide or silicon nitride) on top of the memory stack 330 using one or more thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. Contact openings (not shown) through the local dielectric layer (and any other ILD layer) can be etched using wet etching and / or dry etching (e.g., RIE), followed by filling the contact openings with a conductive material using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, thereby forming the channel local contacts 344, word line local contacts 342, and peripheral contacts 338 and 340. In some embodiments where the spacer structure 311 is formed by the same process used to form the barrier structure 309, the peripheral contacts 338 and 340 are patterned to align with the spacer structure 311 such that each of the peripheral contacts 338 and 340 extends perpendicularly through the spacer structure 311 to electrically isolate it from the surrounding N-type doped semiconductor layer 306.

[0089] Although not shown, it should be understood that in some examples, the front source contact can be formed in the same process used to form the word line local contact 342 (e.g., Figure 1B (147 in the text). The front source contact can contact the N-type doped semiconductor layer 306.

[0090] like Figure 3H As shown, a bonding layer 346 is formed above the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes bonding contacts electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts through the ILD layer are formed using wet etching and / or dry etching (e.g., RIE) and subsequent one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0091] Method 400 proceeds to operation 410, such as Figure 4 As shown, in this operation, the first and second substrates are bonded face-to-face. The bonding includes hybrid bonding. (As illustrated...) Figure 3IAs shown, the carrier substrate 302 and components formed thereon (e.g., the memory stack 330 and the channel structure 314 formed therethrough) are flipped upside down. According to some embodiments, the downward-facing bonding layer 346 is bonded to the upward-facing bonding layer 348, i.e., face-to-face, thereby forming a bonding interface 354 between the carrier substrate 302 and the silicon substrate 350. In some embodiments, a processing step, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surfaces prior to bonding. After bonding, the bonding contacts in the bonding layers 346 and 348 are aligned and contacted to electrically connect the memory stack 330 and the channel structure 314 formed therethrough to the peripheral circuitry 352.

[0092] Method 400 proceeds to operation 412, such as Figure 4 As shown, in this operation, portions of the second substrate and the storage film located within the first portion of the channel structure are removed, thereby exposing portions of the semiconductor channel located within the first portion of the channel structure. This removal can be performed from the back side of the second substrate. In some embodiments, the removal of the second substrate is stopped by a sacrificial layer.

[0093] like Figure 3J As shown, the carrier substrate 302 (and the pad oxide layer between the carrier substrate 302 and the stop layer 304) are mounted from the back side. Figure 3I The carrier substrate 302 is completely removed until it is stopped by a stop layer 304 (e.g., a silicon nitride layer). CMP, polishing, dry etching, and / or wet etching can be used to completely remove the carrier substrate 302. In some embodiments, the carrier substrate 302 is stripped. In some embodiments where the carrier substrate 302 comprises silicon and the stop layer 304 comprises silicon nitride, the carrier substrate 302 is removed using silicon CMP, which is automatically stopped upon reaching a stop layer 304 containing a material other than silicon (e.g., acting as a back-side CMP stop layer). In some embodiments, the substrate 302 (silicon substrate) is removed using wet etching via TMAH, which is automatically stopped upon reaching a stop layer 304 containing a material other than silicon (e.g., acting as a back-side etching stop layer). The stop layer 304 can ensure complete removal of the carrier substrate 302 without concern for thickness uniformity after thinning.

[0094] like Figure 3J As shown, the remaining portion of the sacrificial layer 303 (e.g., the stop layer 304 and another pad oxide layer between the stop layer 304 and the first isolation layer 305) is then completely removed using wet etching with appropriate etchants (such as phosphoric acid and hydrofluoric acid). Figure 3IAs shown in the diagram, the etching process continues until it is stopped by the first isolation layer 305. In some embodiments, at least a portion of the first isolation layer 305 (e.g., the portion covering the channel structure 314 and the N-type doped semiconductor layer 306 within the core array region) can also be removed using wet etching. Thus, a first portion of the channel structure 314 and at least a portion of the N-type doped semiconductor layer 306 can be exposed from the back side. In some embodiments, a portion of the first isolation layer 305 (e.g., the portion covering the peripheral contacts 340 and 338 in the peripheral region) remains intact after this etching.

[0095] like Figure 3K As shown, a portion of the storage film located within the first part of the channel structure 314 (facing the N-type doped semiconductor layer 306) can be removed (e.g., Figure 3J (as shown in the diagram), thereby exposing the portion of the semiconductor channel 318 within the first portion of the channel structure 314. In some embodiments, portions of the reservoir layer 316, the barrier layer 317, and the tunnel layer 315 within the first portion of the channel structure 314 are removed to form a recess (not shown) surrounding the portion of the semiconductor channel 318 within the first portion of the channel structure 314. In some embodiments, two wet etching processes are performed sequentially. For example, the reservoir layer 316, comprising silicon nitride, can be selectively removed by wet etching using a suitable etchant such as phosphoric acid, without etching the N-type doped semiconductor layer 306, comprising polysilicon. Subsequently, the barrier layer 317 and the tunnel layer 315, comprising silicon oxide, can be selectively removed by wet etching using a suitable etchant such as hydrofluoric acid, without etching the N-type doped semiconductor layer 306, comprising polysilicon, and the semiconductor channel 318. The etching of the reservoir layer 316, barrier layer 317, and tunnel layer 315 can be controlled by adjusting the etching time and / or etching rate so that the etching does not further affect the remaining portions of the reservoir layer 316, barrier layer 317, and tunnel layer 315 within the second portion of the channel structure 314 (facing the memory stack 330). It should be understood that in some examples where the barrier structure 309 is present and has the same material as the barrier layer 317 and tunnel layer 315 (e.g., silicon oxide), etching of the barrier layer 317 and tunnel layer 315 can also remove the portion of the barrier structure 309 surrounding the first portion of the channel structure 314, leaving the remaining portion of the barrier structure 309 surrounding the second portion of the channel structure 314. However, the doped portion of the semiconductor channel 318 within the first portion of the channel structure 314 may be exposed after such etching.

[0096] Method 400 proceeds to operation 414, such as Figure 4As shown, in this operation, a conductive layer is formed that contacts the exposed portion of the semiconductor layer and the semiconductor channel within the first portion of the channel structure. In some embodiments, to form the conductive layer, a metal silicide layer is formed on the exposed portion of the semiconductor layer and the semiconductor channel within the first portion of the channel structure, and a metal layer is formed on the metal silicide layer.

[0097] like Figure 3K As shown, a conductive layer 359 is formed within a recess above the doped portion of the semiconductor channel 318 within the first portion of the channel structure 314 and on the N-type doped semiconductor layer 306 outside the recess. In some embodiments, to form the conductive layer 359, a metal silicide layer 360 is formed within the recess that will contact the doped portion of the semiconductor channel 318 within the first portion of the channel structure 314 and outside the recess that will contact the N-type doped semiconductor layer 306, and a metal layer 362 is formed on the metal silicide layer 360. In one example, a metal film (e.g., Co, Ni, or Ti) can be deposited on the sidewalls and bottom surfaces of the recess and on the N-type doped semiconductor layer 306 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. This metal film can contact the polysilicon of the N-type doped semiconductor layer 306 and the doped portion of the semiconductor channel 318 within the first portion of the channel structure 314. Subsequently, a silicide process is performed on the metal film and polysilicon by heat treatment (e.g., annealing, sintering, or any other suitable process) to form a metal silicide layer 360 along the sidewalls and bottom surface of the recess and on the N-type doped semiconductor layer 306. Then, a metal layer 362 can be formed on the metal silicide layer 360 by depositing another metal film (e.g., W, Al, Ti, TiN, Co, and / or Ni) on the metal silicide layer 360 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In another example, instead of depositing two metal films separately, a single metal film (e.g., Co, Ni, or Ti) can be deposited into the recess and on the N-type doped semiconductor layer 306 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Subsequently, a silicide process can be performed on the metal film and polysilicon by heat treatment (e.g., annealing, sintering, or any other suitable process), such that a portion of the metal film forms a metal silicide layer 360 along the sidewalls and bottom surface of the recess and on the N-type doped semiconductor layer 306, while the remaining portion of the metal film becomes a metal layer 362 on the metal silicide layer 360. In some embodiments, the conductive layer 359 is patterned and etched such that it does not cover the remaining portion of the first isolation layer 305 in the peripheral region.

[0098] Method 400 proceeds to operation 416, such as Figure 4 As shown, in this operation, a source contact is formed that contacts the conductive layer. Figure 3L As shown, one or more ILD layers 356 are formed on the conductive layer 359 (and the remainder of the first isolation layer 305). The ILD layer 356 can be formed by depositing a dielectric material on the top surface of the conductive layer 359 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. Source contact openings (not shown) can be formed through the ILD layer 356 to reach the conductive layer 359. In some embodiments, the source contact openings are formed using wet etching and / or dry etching (e.g., RIE). Figure 3L As shown, a source contact 364 is formed in a source contact opening on the back side of the N-type doped semiconductor layer 306. According to some embodiments, the source contact 364 is positioned above the memory stack 330 and in contact with the conductive layer 359. In some embodiments, one or more conductive materials are deposited into the source contact opening using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof, thereby filling the source contact opening with a binder layer (e.g., TiN) and a conductor layer (e.g., W). A planarization process, such as CMP, can then be performed to remove excess conductive material, such that the top surface of the source contact 364 is flush with the top surface of the ILD layer 356.

[0099] Method 400 proceeds to operation 418, such as Figure 4 As shown, in this operation, an interconnect layer is formed above and in contact with the source contact. For example... Figure 3L As shown, a redistribution layer 370 is formed above and in contact with the source contact 364. In some embodiments, the redistribution layer 370 is formed by depositing a conductive material (e.g., Al) on the top surface of the ILD layer 356 and the source contact 364 using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A passivation layer 372 may be formed on the redistribution layer 370. In some embodiments, the passivation layer 372 is formed by depositing a dielectric material such as silicon nitride using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. According to some embodiments, an interconnect layer 376 comprising the ILD layer 356, the redistribution layer 370, and the passivation layer 372 is thus formed.

[0100] like Figure 3LAs shown, contacts 366 and 368 are formed on the back side of the N-type doped semiconductor layer 306. According to some embodiments, contacts 366 and 368 extend vertically through the remaining portion of the ILD layer 356 and the first isolation layer 305. Contacts 366 and 368, as well as source contact 364, can be formed using the same deposition process, thereby reducing the number of deposition processes. In some embodiments, contacts 366 and 368 are also laterally aligned and in contact with peripheral contacts 338 and 340, respectively. Figure 3L As shown, a contact pad 374 is formed on and in contact with the contact 368. In some embodiments, the passivation layer 372, except for the portion covering the contact 368, is removed by wet etching and / or dry etching, thereby exposing a portion of the underlying redistribution layer 370 to form the contact pad 374. Therefore, the contact pad 374 for pad routing can be electrically connected to the peripheral circuitry 352 via the contact 368, the peripheral contact 340, and the bonding layers 346 and 348.

[0101] According to one aspect of this disclosure, a 3D memory device includes a memory stack having alternating stacked conductive and dielectric layers, a semiconductor layer, and a channel structure extending perpendicularly through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel located within the first portion of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel located within the second portion of the channel structure.

[0102] In some embodiments, the first doping concentration is approximately 10. 19 cm -3 and about 10 21 cm -3 between.

[0103] In some embodiments, the portion of the semiconductor channel located within the first part of the channel structure comprises N-type doped polysilicon.

[0104] In some embodiments, the semiconductor layer comprises N-type doped polycrystalline silicon.

[0105] In some embodiments, the 3D memory device further includes a conductive layer in contact with the semiconductor layer and a portion of the semiconductor channel located within a first portion of the channel structure.

[0106] In some embodiments, the conductive layer includes a metal silicide layer in contact with the portion of the semiconductor channel and a metal layer in contact with the metal silicide layer.

[0107] In some embodiments, the 3D storage device further includes a source contact that is in contact with the conductive layer.

[0108] In some embodiments, the 3D memory device further includes a source contact that contacts the semiconductor layer.

[0109] In some embodiments, the first portion of the channel structure further includes an enlarged structure in contact with the semiconductor channel, and the third doping concentration of the enlarged structure is equal to or greater than the first doping concentration.

[0110] In some embodiments, the enlarged structure comprises polycrystalline silicon or silicon oxide.

[0111] In some embodiments, the 3D storage device further includes an insulating structure that extends vertically through the storage stack and laterally, thereby dividing the storage stack into multiple blocks.

[0112] In some embodiments, the 3D storage device further includes a barrier structure surrounding a second portion of the channel structure.

[0113] According to another aspect of this disclosure, a 3D memory device includes a semiconductor structure comprising a memory stack having alternating stacked conductive layers and stacked dielectric layers, a semiconductor layer, and a channel structure extending perpendicularly through the memory stack into the semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The doping concentration of the semiconductor channel is greater at locations toward the source than at locations away from the source.

[0114] In some embodiments, the first doping concentration of the portion of the semiconductor channel located in the first part of the channel structure (facing the semiconductor layer) is greater than the second doping concentration of the portion of the semiconductor channel located in the second part of the channel structure (facing the memory stack).

[0115] In some embodiments, the first lateral dimension of the first portion of the channel structure is greater than the second lateral dimension of the second portion of the channel structure.

[0116] In some embodiments, the first portion of the channel structure further includes an enlarged structure in contact with the semiconductor channel, and the third doping concentration of the enlarged structure is equal to or greater than the first doping concentration.

[0117] In some embodiments, the enlarged structure comprises polycrystalline silicon or silicon oxide.

[0118] In some embodiments, the first doping concentration is approximately 10. 19 cm -3 and about 10 21 cm -3between.

[0119] In some embodiments, the portion of the semiconductor channel located within the first part of the channel structure comprises N-type doped polysilicon.

[0120] In some embodiments, the semiconductor layer comprises N-type doped polycrystalline silicon.

[0121] In some embodiments, the second semiconductor structure further includes a conductive layer that contacts the semiconductor layer and a portion of the semiconductor channel located within the first portion of the channel structure.

[0122] In some embodiments, the conductive layer includes a metal silicide layer in contact with the portion of the semiconductor channel and a metal layer in contact with the metal silicide layer.

[0123] In some embodiments, the second semiconductor structure further includes a source contact that is in contact with the conductive layer.

[0124] In some embodiments, the second semiconductor structure further includes a source contact that is in contact with the semiconductor layer.

[0125] In some embodiments, the second semiconductor structure further includes an insulating structure that extends vertically through the memory stack and laterally, thereby dividing the memory stack into multiple blocks.

[0126] In some embodiments, the second semiconductor structure further includes a barrier structure surrounding a portion of the second part of the channel structure.

[0127] In some embodiments, the 3D memory device further includes another semiconductor structure having peripheral circuitry and a bonding interface between the semiconductor structure and the other semiconductor structure.

[0128] According to another aspect of this disclosure, a method for forming a 3D memory device is disclosed. A semiconductor layer is formed above a substrate, and a stacked structure is formed above the semiconductor layer. A channel structure extending vertically through the stacked structure and the semiconductor layer is formed. The channel structure includes a memory film and a semiconductor channel. A first doping concentration of a portion of the semiconductor channel located in a first portion of the channel structure (facing the semiconductor layer) is greater than a second doping concentration of a portion of the semiconductor channel located in a second portion of the channel structure (facing the stacked structure). The substrate and portions of the memory film located in the first portion of the channel structure are removed, thereby exposing portions of the semiconductor channel located in the first portion of the channel structure. A conductive layer is formed in contact with the semiconductor layer and the exposed portions of the semiconductor channel located in the first portion of the channel structure.

[0129] In some embodiments, a first isolation layer is formed between the substrate and the semiconductor layer, and a second isolation layer is formed between the semiconductor layer and the stacked structure.

[0130] In some embodiments, to form the channel structure, a channel via is formed that extends vertically through the stacked structure, the second isolation layer, and the semiconductor layer, ending at the first isolation layer. A first lateral dimension of the channel via facing a first portion of the semiconductor layer is greater than a second lateral dimension of the channel via facing a second portion of the stacked structure and the second isolation layer. In some embodiments, to form the channel structure, a storage film and a semiconductor channel are sequentially formed along the sidewalls and bottom surface of the channel structure, and a doped expansion structure is formed over a portion of the semiconductor channel located within the first portion of the channel via. In some embodiments, to form the channel structure, a dopant diffuses from the doped expansion structure into the semiconductor channel such that a first doping concentration in the portion of the semiconductor channel within the first portion of the channel via is greater than a second doping concentration in the portion of the semiconductor channel within the second portion of the channel via.

[0131] In some embodiments, a barrier structure is formed that extends vertically through the second isolation layer and the semiconductor layer. In some embodiments, to form the via, a via extending vertically through the stacked structure, the second isolation layer, and the semiconductor layer is etched, and the via stops at the first isolation layer. In some embodiments, the etching of a first portion of the via is laterally stopped by the barrier structure.

[0132] In some embodiments, in order to form a doped expansion structure, a layer of polysilicon or silicon oxide is deposited on the semiconductor channel within the channel hole, the polysilicon or silicon oxide layer is in situ doped with a dopant, and the portion of the polysilicon or silicon oxide layer above the semiconductor channel within the second portion of the channel hole is etched away.

[0133] In some embodiments, the dopant is an N-type dopant, and the doping concentration of the doped extended structure is approximately 10⁻⁶ before diffusion. 21 cm -3 and about 10 22 cm -3 between.

[0134] In some embodiments, in order to sequentially form a storage film and a semiconductor channel, layers consisting of silicon oxide, silicon nitride, silicon oxide, and intrinsic polysilicon are sequentially deposited.

[0135] In some embodiments, in order to form the conductive layer, a metal silicide layer is formed on the exposed portion of the semiconductor layer and the semiconductor channel within the first portion of the channel structure, and a metal layer is formed on the metal silicide layer.

[0136] In some embodiments, source contacts are formed in contact with the conductive layer after the substrate is removed.

[0137] In some embodiments, source contacts that are in contact with the semiconductor layer are formed before the substrate is removed.

[0138] In some embodiments, the semiconductor layer comprises N-type doped polycrystalline silicon.

[0139] In some embodiments, before removing the substrate, an opening is formed perpendicularly through the stacked structure, and the stacked structure is replaced through the opening with a storage stack comprising alternating stacked conductive layers and stacked dielectric layers, and an insulating structure is formed within the opening.

[0140] The foregoing description of specific embodiments thus reveals the general essence of this disclosure. Those skilled in the art, with their knowledge and skills, can readily modify and / or adjust such specific embodiments for various applications without departing from the general principles of this disclosure, without requiring extensive experimentation. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed embodiments and their equivalents. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and those skilled in the art should interpret the terminology or terminology in this specification in accordance with the teachings and guidance provided.

[0141] The foregoing description of embodiments of this disclosure uses functional building blocks to illustrate implementations of the specified functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined. Alternative boundaries may be defined, provided that the specified functions and their relationships are appropriately performed.

[0142] The summary and abstract sections may set forth one or more exemplary embodiments of the present disclosure as conceived by the inventors, but not all of them, and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0143] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the following claims and their equivalents.

Claims

1. A three-dimensional storage device, comprising: A memory stack comprising alternating stacked conductive layers and stacked dielectric layers; Semiconductor layer; Source contacts located above the storage stack; A channel structure extending vertically through the memory stack into the semiconductor layer; as well as A first conductive layer, wherein at least a portion of the first conductive layer is located on the side of the semiconductor layer away from the memory stack, wherein The first lateral dimension along the first direction of the first portion of the channel structure located in the semiconductor layer is greater than the second lateral dimension along the first direction of the second portion of the channel structure located in the memory stack. The channel structure includes a storage film and a semiconductor channel; Another portion of the first conductive layer is located between the source contact and the semiconductor channel; The first doping concentration of the portion of the semiconductor channel located in the first part of the channel structure is greater than the second doping concentration of the portion of the semiconductor channel located in the second part of the channel structure; and The source contact contacts another portion of the first conductive layer, and the other portion of the first conductive layer contacts the portion of the semiconductor channel located within the first portion of the channel structure. The first portion of the channel structure within the semiconductor layer includes an enlarged structure in contact with the semiconductor channel.

2. The three-dimensional storage device according to claim 1, wherein, The first doping concentration is 10 19 cm -3 and 10 21 cm -3 between.

3. The three-dimensional storage device according to claim 1 or 2, wherein, The portion of the semiconductor channel located within the first part of the channel structure comprises N-type doped polycrystalline silicon.

4. The three-dimensional storage device according to claim 1 or 2, wherein, The semiconductor layer comprises N-type doped polycrystalline silicon.

5. The three-dimensional storage device according to claim 1, wherein, The first conductive layer includes a metal silicide layer in contact with the portion of the semiconductor channel and a metal layer in contact with the metal silicide layer.

6. The three-dimensional storage device according to claim 1 or 2, wherein, The third doping concentration of the enlarged structure is equal to or greater than the first doping concentration.

7. The three-dimensional storage device according to claim 6, wherein, The enlarged structure includes polycrystalline silicon or silicon oxide.

8. The three-dimensional storage device according to any one of claims 1, 2 or 7, further comprising an insulating structure extending perpendicularly through the storage stack and laterally along a second direction perpendicular to the first direction.

9. The three-dimensional storage device according to any one of claims 1, 2 or 7, further comprising a barrier structure surrounding a portion of the second part of the channel structure.

10. The three-dimensional storage device according to any one of claims 1, 2, or 7, further comprising forming at least two contacts on the back side of the semiconductor layer, wherein, The at least two contacts are respectively laterally aligned with and in contact with the at least two peripheral contacts.

11. The three-dimensional storage device according to claim 8, wherein, The insulation structure includes lateral recesses.

12. A three-dimensional storage device, comprising: Semiconductor structure, comprising: A memory stack comprising alternating stacked conductive layers and stacked dielectric layers; Semiconductor layer; Source contacts located above the storage stack; A channel structure extending vertically through the memory stack into the semiconductor layer, wherein the channel structure includes a memory film and a semiconductor channel, and the doping concentration of the semiconductor channel is greater towards the source than away from the source. A first conductive layer, wherein at least a portion of the first conductive layer is located on the side of the semiconductor layer away from the memory stack, and another portion of the first conductive layer is located between the source contact and the semiconductor channel. The source contact is in contact with another portion of the first conductive layer, and the other portion of the first conductive layer is in contact with the portion of the semiconductor channel facing the source. Wherein, the first doping concentration of the portion of the semiconductor channel located in the first part of the channel structure is greater than the second doping concentration of the portion of the semiconductor channel located in the second part of the channel structure, the first part of the channel structure is located in the semiconductor layer, and the second part of the channel structure is located in the memory stack. Wherein, the other portion of the first conductive layer located between the source contact and the semiconductor channel is in contact with the portion of the semiconductor channel having a first doping concentration.

13. The three-dimensional storage device according to claim 12, wherein, The first lateral dimension of the first part of the channel structure along the first direction is greater than the second lateral dimension of the second part of the channel structure along the first direction.

14. The three-dimensional storage device according to claim 13, wherein, The first portion of the channel structure further includes an enlarged structure in contact with the semiconductor channel, and the third doping concentration of the enlarged structure is equal to or greater than the first doping concentration.

15. The three-dimensional storage device according to claim 14, wherein, The enlarged structure includes polycrystalline silicon or silicon oxide.

16. The three-dimensional storage device according to any one of claims 12-15, wherein, The first doping concentration is 10 19 cm -3 and 10 21 cm -3 between.

17. The three-dimensional storage device according to any one of claims 12-15, wherein, The portion of the semiconductor channel located within the first part of the channel structure comprises N-type doped polycrystalline silicon.

18. The three-dimensional storage device according to any one of claims 12-15, wherein, The semiconductor layer comprises N-type doped polycrystalline silicon.

19. The three-dimensional storage device according to claim 12, wherein, The conductive layer includes a metal silicide layer in contact with the portion of the semiconductor channel and a metal layer in contact with the metal silicide layer.

20. The three-dimensional storage device according to any one of claims 13-15, wherein, The semiconductor structure further includes an insulating structure that extends perpendicularly through the memory stack and laterally along a second direction perpendicular to the first direction.

21. The three-dimensional storage device according to any one of claims 12-15, wherein, The semiconductor structure further includes a barrier structure surrounding a second portion of the channel structure.

22. The three-dimensional storage device according to any one of claims 12-15, further comprising: Another semiconductor structure including peripheral circuitry; as well as A bonding interface located between the semiconductor structure and the other semiconductor structure.

23. The three-dimensional storage device according to any one of claims 12-15, further comprising forming at least two contacts on the back side of the semiconductor layer, wherein, The at least two contacts are respectively laterally aligned with and in contact with the at least two peripheral contacts.

24. The three-dimensional storage device according to claim 20, wherein, The insulation structure includes lateral recesses.

25. A method for forming a three-dimensional storage device, comprising: A semiconductor layer is formed on the substrate and a stacked structure is formed on the semiconductor layer; Source contacts are formed on top of the stacked structure; A channel structure is formed that extends vertically through the stacked structure and the semiconductor layer, wherein the channel structure includes a memory film and a semiconductor channel, and a first doping concentration of a portion of the semiconductor channel located in a first part of the channel structure is greater than a second doping concentration of a portion of the semiconductor channel located in a second part of the channel structure, the first part of the channel structure being located in the semiconductor layer, and the second part of the channel structure being located in the stacked structure; Remove portions of the substrate and the storage film located within the first portion of the channel structure, thereby exposing the portion of the semiconductor channel located within the first portion of the channel structure; and A first conductive layer is formed in contact with the exposed portion of the semiconductor layer and the semiconductor channel within a first portion of the channel structure, wherein at least a portion of the first conductive layer is located on the side of the semiconductor layer away from the stacked structure, and another portion of the first conductive layer is located between the source contact and the semiconductor channel. Wherein, the source contact is in contact with the other portion of the first conductive layer, and Wherein, the other portion of the first conductive layer located between the source contact and the semiconductor channel is in contact with the portion of the semiconductor channel having a first doping concentration.

26. The method of claim 25, further comprising forming a first isolation layer between the substrate and the semiconductor layer and forming a second isolation layer between the semiconductor layer and the stacked structure.

27. The method according to claim 26, wherein, The formation of the channel structure includes: A channel hole is formed that extends vertically through the stacked structure, the second isolation layer, and the semiconductor layer and stops at the first isolation layer, wherein a first lateral dimension of a first portion of the channel hole in the semiconductor layer along a first direction is greater than a second lateral dimension of a second portion of the channel hole in the stacked structure and the second isolation layer along the first direction. A storage film and a semiconductor channel are sequentially formed along the sidewall and bottom surface of the channel hole; A doped expansion structure is formed on the portion of the semiconductor channel located within the first portion of the channel aperture; and The dopant diffuses from the doped expansion structure into the semiconductor channel such that the first doping concentration of the portion of the semiconductor channel located within the first portion of the channel aperture is greater than the second doping concentration of the portion of the semiconductor channel located within the second portion of the channel aperture.

28. The method of claim 27, further comprising forming a barrier structure extending vertically through the second insulating layer and the semiconductor layer. in, Forming the channel hole includes etching the channel hole vertically through the stacked structure, the second isolation layer, and the semiconductor layer, and stopping at the first isolation layer, with the etching of a first portion of the channel hole laterally stopped by the barrier structure.

29. The method according to claim 27 or 28, wherein, Forming the doped extended structure includes: A layer of polysilicon or silicon oxide is deposited inside the channel hole on top of the semiconductor channel; The layer of polycrystalline silicon or silicon oxide is in-situ doped with the aforementioned dopant; and The portion of the polysilicon or silicon oxide layer above the semiconductor channel within the second portion of the channel hole is etched away.

30. The method according to claim 27 or 28, wherein, The dopant is an N-type dopant, and the third doping concentration of the doped extended structure is 10 before diffusion. 21 cm -3 and 10 22 cm -3 between.

31. The method according to claim 27 or 28, wherein, The sequential formation of the memory film and the semiconductor channel includes the sequential deposition of layers composed of silicon oxide, silicon nitride, silicon oxide and intrinsic polysilicon.

32. The method according to any one of claims 25-28, wherein, Forming the conductive layer includes: A metal silicide layer is formed on the exposed portion of the semiconductor layer and the semiconductor channel located within the first portion of the channel structure; and A metal layer is formed on the metal silicide layer.

33. The method according to any one of claims 25-28, wherein, The semiconductor layer comprises N-type doped polycrystalline silicon.

34. The method according to any one of claims 25-28, further comprising, prior to removing the substrate: Forming an opening that extends vertically through the stacked structure; The stacked structure is replaced by a storage stack comprising alternating stacked conductive layers and stacked dielectric layers through the opening; and An insulating structure is formed within the opening.

35. The method according to any one of claims 25-28, further comprising forming at least two contacts on the back side of the semiconductor layer, wherein, The at least two contacts are respectively laterally aligned with and in contact with the at least two peripheral contacts.

36. The method according to claim 34, wherein, The insulation structure includes lateral recesses.

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